Phase change memory cell and method of making the same

Abstract

The application provides a phase change memory cell, which comprises a substrate, a medium layer and a stack structure, the medium layer is located on the substrate, the stack structure is located in the medium layer and comprises a first bottom electrode layer, a second bottom electrode layer, a third bottom electrode layer, a phase change memory layer and a top electrode layer arranged from bottom to top. In the application, the resistivity of the first bottom electrode layer and the third bottom electrode layer is greater than that of the second bottom electrode layer, so the first bottom electrode layer and the third bottom electrode layer are worse in heat conduction and better in heat preservation than the second bottom electrode layer. Since the second bottom electrode layer is sandwiched between the first bottom electrode layer and the third bottom electrode layer, the first bottom electrode layer and the third bottom electrode layer can prevent heat diffusion, improve heating efficiency and reduce power consumption. Accordingly, the application also provides a preparation method of the phase change memory cell.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a phase-change memory cell and its fabrication method. Background Technology

[0002] Phase-change memory (PCM) is a novel type of resistive non-volatile semiconductor memory. It uses chalcogenide compound materials as the storage medium and leverages the different resistance states of nanoscale phase-change materials in their crystalline (low-resistance) and amorphous (high-resistance) states to achieve data storage. PCM offers significant advantages such as non-volatility, high speed, high density, low power consumption, high reliability, and good compatibility with CMOS processes. It has been recognized by the Semiconductor Industry Association (SIA) as the most likely new type of non-volatile memory to replace flash memory as the mainstream product in the future memory market.

[0003] A typical structure of a phase-change memory (PCM) includes a bottom electrode layer, a top electrode layer, and a phase-change storage layer (GST) located between the bottom and top electrode layers. The bottom electrode layer acts as a heater, used to heat a small area of ​​the GST. The heating effect of the bottom electrode layer controls the entire phase-change storage process. Only by improving the heating efficiency of the bottom electrode layer and limiting the diffusion of heat inside the device can devices with lower power consumption and higher performance be obtained. Summary of the Invention

[0004] The purpose of this invention is to provide a phase change memory cell and its preparation method, which can improve the heating efficiency of the bottom electrode layer.

[0005] To achieve the above objectives, the present invention provides a phase-change memory cell, comprising: Substrate; A dielectric layer is located on the substrate; and, The stacked structure, located within the dielectric layer, includes a first bottom electrode layer, a second bottom electrode layer, a third bottom electrode layer, a phase change storage layer, and a top electrode layer arranged sequentially from bottom to top, wherein the resistivity of the first bottom electrode layer and the third bottom electrode layer is greater than the resistivity of the second bottom electrode layer.

[0006] Optionally, the resistivity of the first bottom electrode layer is less than the resistivity of the third bottom electrode layer.

[0007] Optionally, the materials of the first bottom electrode layer and the third bottom electrode layer both include SiC, N-type / P-type doped SiC, or TaN.

[0008] Optionally, the first bottom electrode layer and the third bottom electrode layer completely cover the outer wall of the second bottom electrode layer.

[0009] Optionally, the first bottom electrode layer is U-shaped, the second bottom electrode layer is located inside the opening of the first bottom electrode layer and fills at least a portion of the depth of the opening of the first bottom electrode layer, and the third bottom electrode layer covers the top surfaces of the first bottom electrode layer and the second bottom electrode layer.

[0010] Optionally, the first bottom electrode layer and the second bottom electrode layer are both U-shaped and stacked sequentially, and the third bottom electrode layer fills the opening of the second bottom electrode layer and extends to cover the top surface of the first bottom electrode layer and the second bottom electrode layer.

[0011] Optionally, the first bottom electrode layer, the second bottom electrode layer, and the third bottom electrode layer are all flat and stacked sequentially.

[0012] Optionally, it may also include a thermal insulation layer located within the dielectric layer and at least covering the exposed outer wall of the stacked structure.

[0013] Optionally, the material of the insulation layer includes SiCN or Si3N4.

[0014] Optionally, the dielectric layer includes a first sub-dielectric layer and a second sub-dielectric layer disposed sequentially from bottom to top, and the heat insulation layer is located between the first sub-dielectric layer and the second sub-dielectric layer, and includes a first sub-heat insulation layer and a second sub-heat insulation layer; and, The first sub-insulation layer covers the first sub-dielectric layer and has a perforation therein. The first bottom electrode layer and the second bottom electrode layer fill a portion of the depth of the perforation. The third bottom electrode layer fills at least the remaining depth of the perforation. The second sub-insulation layer covers the first sub-insulation layer and the exposed outer walls of the third bottom electrode layer, the phase change storage layer, and the top electrode layer.

[0015] Optional, also includes: The source and drain regions are located within the substrate; A gate structure is located on a substrate between the source region and the drain region; and, The first pad, the second pad, and the third pad are located on the dielectric layer and are electrically connected to the source region, the gate structure, and the top electrode layer through the first plug, the second plug, and the third plug located in the dielectric layer, respectively. The second bottom electrode layer is electrically connected to the drain region through the first bottom electrode layer and the fourth plug located in the dielectric layer.

[0016] The present invention also provides a method for fabricating a phase-change memory cell, comprising: Provide substrate; A dielectric layer is formed on the substrate; and, A stacked structure is formed within the dielectric layer. The stacked structure includes a first bottom electrode layer, a second bottom electrode layer, a third bottom electrode layer, a phase change storage layer, and a top electrode layer arranged sequentially from bottom to top. The resistivity of the first bottom electrode layer and the third bottom electrode layer is greater than that of the second bottom electrode layer.

[0017] Optionally, the steps of forming the dielectric layer and the stacked structure include: A first sub-dielectric layer and a first sub-thermal insulation layer are sequentially formed on the substrate, wherein the first sub-thermal insulation layer has a perforation; A first bottom electrode layer, a second bottom electrode layer, and a third bottom electrode layer are sequentially formed within the perforation, and a phase change storage layer and a top electrode layer are sequentially formed on the third bottom electrode layer; A second sub-insulation layer is formed on the first sub-insulation layer, and the second sub-insulation layer further covers the exposed outer walls of the third bottom electrode layer, the phase change storage layer, and the top electrode layer; and... A second sub-dielectric layer is formed on the second sub-insulation layer, the first sub-dielectric layer and the second sub-dielectric layer constitute the dielectric layer, and the first sub-insulation layer and the second sub-insulation layer constitute the insulation layer.

[0018] Optionally, the steps of forming the first bottom electrode layer, the second bottom electrode layer, the third bottom electrode layer, the phase change storage layer, and the top electrode layer include: A first bottom electrode layer, a second bottom electrode layer, and a first sub-electrode layer are sequentially formed in at least a portion of the depth of the perforation. The first bottom electrode layer and the second bottom electrode layer are both U-shaped and sequentially cover the inner wall of the perforation. The first sub-electrode layer fills the opening of the second bottom electrode layer. A second sub-electrode layer is formed on the first sub-insulation layer, and the second sub-electrode layer further fills the remaining depth of the perforation; and, The phase change storage layer and the top electrode layer are formed on the second sub-electrode layer, and a portion of the lateral width of the top electrode layer, the phase change storage layer and the second sub-electrode layer are removed simultaneously. The remaining first sub-electrode layer and the second sub-electrode layer constitute the third bottom electrode layer.

[0019] Optionally, the steps of forming the first bottom electrode layer, the second bottom electrode layer, the third bottom electrode layer, the phase change storage layer, and the top electrode layer include: The first bottom electrode layer is formed in at least a portion of the depth of the perforation, the first bottom electrode layer being U-shaped and covering the inner wall of the perforation; A second bottom electrode layer is formed within the opening of the first bottom electrode layer, and the second bottom electrode layer fills at least a portion of the depth of the opening of the first bottom electrode layer; A third bottom electrode layer is formed on the first sub-insulation layer and within the remaining depth of the perforation; and, The phase change storage layer and the top electrode layer are formed on the third bottom electrode layer, and a portion of the lateral width of the top electrode layer, the phase change storage layer and the third bottom electrode layer are removed simultaneously.

[0020] Optionally, the steps of forming the first bottom electrode layer, the second bottom electrode layer, the third bottom electrode layer, the phase change storage layer, and the top electrode layer include: The first bottom electrode layer and the second bottom electrode layer are sequentially formed within at least a portion of the depth of the perforation; A third bottom electrode layer is formed on the first sub-insulation layer and within the remaining depth of the perforation; and, The phase change storage layer and the top electrode layer are formed on the third bottom electrode layer, and a portion of the lateral width of the top electrode layer, the phase change storage layer and the third bottom electrode layer are removed simultaneously.

[0021] Optionally, the substrate has a source region and a drain region. Before forming the first sub-dielectric layer, a gate structure is formed on the substrate between the source region and the drain region. After forming the first sub-dielectric layer, a first sub-plug, a second sub-plug, and a fourth plug are formed in the first sub-dielectric layer, respectively electrically connected to the source region, the gate structure, and the drain region. The through hole is aligned with and exposes the fourth plug. After forming the second sub-dielectric layer, a third sub-plug, a fourth sub-plug, and a third plug, respectively electrically connected to the first sub-plug, the second sub-plug, and the top electrode layer, are formed within the second sub-dielectric layer; and, A first pad, a second pad, and a third pad are formed on the second sub-dielectric layer. The first pad, the second pad, and the third pad are electrically connected to the third sub-plug, the fourth sub-plug, and the third plug, respectively. The first sub-plug and the third sub-plug constitute a first plug, and the second sub-plug and the fourth sub-plug constitute a second plug.

[0022] The phase-change memory cell provided by this invention includes a substrate, a dielectric layer, and a stacked structure. The dielectric layer is located on the substrate, and the stacked structure is located within the dielectric layer. It includes, from bottom to top, a first bottom electrode layer, a second bottom electrode layer, a third bottom electrode layer, a phase-change memory layer, and a top electrode layer. In this invention, the resistivity of the first bottom electrode layer and the third bottom electrode layer is greater than that of the second bottom electrode layer. Therefore, the first bottom electrode layer and the third bottom electrode layer have lower thermal conductivity and better heat retention than the second bottom electrode layer. Since the second bottom electrode layer is sandwiched between the first bottom electrode layer and the third bottom electrode layer, the first bottom electrode layer and the third bottom electrode layer can prevent heat diffusion, improve the overall heating efficiency of the bottom electrode, and reduce power consumption. Accordingly, this invention also provides a method for fabricating the phase-change memory cell. Attached Figure Description

[0023] Figure 1 A flowchart illustrating the fabrication method of the phase-change memory unit provided in Embodiment 1 of the present invention; Figures 2-11 This is a schematic diagram of the structure corresponding to the steps of the preparation method of the phase change memory unit provided in Embodiment 1 of the present invention; Figures 12-20 This is a schematic diagram of the corresponding steps in the preparation method of the phase change memory unit provided in Embodiment 2 of the present invention. Figures 21-29 This is a schematic diagram of the corresponding steps in the preparation method of the phase change memory unit provided in Embodiment 3 of the present invention. The attached figures are labeled as follows: 100 - Substrate; 101 - Source region; 102 - Drain region; 200 - Gate structure; 301 - First sub-dielectric layer; 302 - Second sub-dielectric layer; 401 - First sub-plug; 402 - Second sub-plug; 403 - Fourth plug; 501 - First sub-insulation layer; 501a - Through-hole; 502 - Second sub-insulation layer; 601 - First bottom electrode layer; 602 - Third bottom electrode layer; 612 - First sub-electrode layer; 622 - Second sub-electrode layer; 701 - Second bottom electrode layer; 702 - Top electrode layer; 703 - Phase change memory layer; 801 - Third sub-plug; 802 - Fourth sub-plug; 803 - Third plug; 901 - First pad; 902 - Second pad; 903 - Third pad. Detailed Implementation

[0024] The specific embodiments of the present invention will now be described in more detail with reference to the accompanying drawings. The advantages and features of the present invention will become clearer from the following description. It should be noted that the accompanying drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the present invention.

[0025] Example 1 Figure 11 This is a schematic diagram of the phase-change memory unit provided in this embodiment. Figure 11 As shown, in this embodiment, the phase-change memory cell includes a substrate 100, a dielectric layer, a stacked structure, and a thermal insulation layer. The dielectric layer is located on the substrate 100, and the stacked structure and the thermal insulation layer are both located within the dielectric layer.

[0026] Specifically, the substrate 100 has an active region and a trench isolation structure for isolating the active region. Figure 11 (not shown in the image), the active region includes a source region 101 and a drain region 102.

[0027] The substrate 100 can be made of common substrate materials in the art. For example, the substrate 100 may include, but is not limited to, silicon, germanium, gallium arsenide, silicon carbide, sapphire or diamond.

[0028] Furthermore, a gate structure 200 is formed on the substrate 100, the gate structure 200 is located between the source region 101 and the drain region 102, and the gate structure 200 and the source region 101 and the drain region 102 on both sides constitute a transistor.

[0029] Optionally, the gate structure 200 may be formed by stacking multiple film layers. For example, the gate structure 200 may include a gate oxide layer, a gate conductive layer and a gate insulating layer, wherein the gate oxide layer and the gate conductive layer are stacked sequentially on the substrate 100 from bottom to top, and the gate insulating layer covers the exposed outer walls of the gate oxide layer and the gate conductive layer.

[0030] Please continue reading. Figure 11 The dielectric layer is located on the substrate 100, covering the top surface of the substrate 100 and the gate structure 200. In this embodiment, the dielectric layer includes a first sub-dielectric layer 301 and a second sub-dielectric layer 302, wherein the first sub-dielectric layer 301 covers the top surface of the substrate 100 and the gate structure 200, and the second sub-dielectric layer 302 covers the first sub-dielectric layer 301. Both the first sub-dielectric layer 301 and the second sub-dielectric layer 302 are planarized film layers.

[0031] Optionally, the first sub-dielectric layer 301 and the second sub-dielectric layer 302 can be made of the same material, for example, both can be silicon oxide.

[0032] Furthermore, a first sub-plug 401, a second sub-plug 402, and a fourth plug 403 are formed in the first sub-dielectric layer 301. The first sub-plug 401, the second sub-plug 402, and the fourth plug 403 penetrate the first sub-dielectric layer 301 and are electrically connected to the source region 101, the gate structure 200, and the drain region 102, respectively.

[0033] Please continue reading. Figure 11 The heat insulation layer is located between the first sub-dielectric layer 301 and the second sub-dielectric layer 302. Specifically, the heat insulation layer includes a first sub-heat insulation layer 501 and a second sub-heat insulation layer 502. The first sub-heat insulation layer 501 covers the top surface of the first sub-dielectric layer 301, and has a perforation 501a that aligns with and exposes the fourth plug 403. A portion of the stacked structure is located in the perforation 501a and extends upward above the first sub-heat insulation layer 501, and the stacked structure may also cover a portion of the top surface of the first sub-heat insulation layer 501; the second sub-heat insulation layer 502 covers the remaining top surface of the first sub-heat insulation layer 501 and the exposed outer wall of the stacked structure. In this way, the first sub-heat insulation layer 501 and the second sub-heat insulation layer 502 completely enclose the exposed outer wall of the stacked structure, preventing heat diffusion in the stacked structure.

[0034] Furthermore, the stacked structure includes a first bottom electrode layer 601, a second bottom electrode layer 701, a third bottom electrode layer 602, a phase change storage layer 703, and a top electrode layer 702 arranged sequentially from bottom to top. In this embodiment, the second bottom electrode layer 701 serves as the main heating electrode for heating the phase change storage layer 703. The resistivity of both the first bottom electrode layer 601 and the third bottom electrode layer 602 is greater than that of the second bottom electrode layer 701. Therefore, the first bottom electrode layer 601 and the third bottom electrode layer 602 have lower thermal conductivity and better heat retention than the second bottom electrode layer 701. Moreover, since the second bottom electrode layer 701 is sandwiched between the first bottom electrode layer 601 and the third bottom electrode layer 602, the first bottom electrode layer 601 and the third bottom electrode layer 602 can prevent heat dissipation, thereby improving heating efficiency and reducing power consumption.

[0035] Please continue reading. Figure 11In this embodiment, both the first bottom electrode layer 601 and the second bottom electrode layer 701 are located within the perforation 501a. The second bottom electrode layer 701 is electrically connected to the fourth plug 403 through the first bottom electrode layer 601. Further, the second sub-dielectric layer 302 includes a third sub-plug 801, a fourth sub-plug 802, and a third plug 803. The third sub-plug 801 and the fourth sub-plug 802 penetrate the second sub-dielectric layer 302, the second sub-insulation layer 502, and the first sub-insulation layer 501, and are electrically connected to the first sub-plug 401 and the second sub-plug 402, respectively. The first sub-plug 401 and the third sub-plug 801 constitute a first plug, and the second sub-plug 402 and the fourth sub-plug 802 constitute a second plug. The third plug 803 penetrates the second sub-dielectric layer 302 and the second sub-insulation layer 502 and is electrically connected to the top electrode layer 702.

[0036] Furthermore, a first pad 901, a second pad 902, and a third pad 903 are formed on the second sub-dielectric layer 302. The first pad 901, the second pad 902, and the third pad 903 are electrically connected to the third sub-plug 801, the fourth sub-plug 802, and the third plug 803, respectively. In this way, the first pad 901 is electrically connected to the source region 101 through the first plug, the second pad 902 is electrically connected to the gate structure 200 through the second plug, the third pad 903 is electrically connected to the top electrode layer 702, and the second bottom electrode layer 701 is electrically connected to the drain region 102 through the first bottom electrode layer 601 and the fourth plug 403.

[0037] In this embodiment, the first sub-plug 401, the second sub-plug 402, the fourth plug 403, the third sub-plug 801, the fourth sub-plug 802 and the third plug 803 all include a tungsten pillar and a metal barrier layer wrapped around the side wall and bottom wall of the tungsten pillar. The material of the metal barrier layer can be TiW, TiN and other materials, thereby preventing tungsten migration.

[0038] Please continue reading. Figure 11 In this embodiment, the first bottom electrode layer 601 and the second bottom electrode layer 701 are both U-shaped and stacked sequentially within the perforation 501a; the third bottom electrode layer 602 fills the opening of the second bottom electrode layer 701 and extends to cover the top surfaces of the first bottom electrode layer 601 and the second bottom electrode layer 701. Figure 11As can be seen, the first bottom electrode layer 601 completely covers the bottom surface of the second bottom electrode layer 701, and the third bottom electrode layer 602 completely covers the top surface of the second bottom electrode layer 701. The first bottom electrode layer 601 and the third bottom electrode layer 602 can completely wrap around the outer wall of the second bottom electrode layer 701, thereby effectively preventing heat diffusion from the second bottom electrode layer 701. At the same time, the top surface of the U-shaped second bottom electrode layer 701 has a smaller area, which can achieve better heating efficiency.

[0039] In this embodiment, the first bottom electrode layer 601 and the second bottom electrode layer 701 are located within a portion of the depth of the perforation 501a. The top surfaces of the first bottom electrode layer 601 and the second bottom electrode layer 701 are lower than the top surface of the perforation 501a, thereby preventing material residue of the first bottom electrode layer 601 and / or the second bottom electrode layer 701 from remaining on the first sub-insulation layer 501 during the fabrication of the first bottom electrode layer 601 and the second bottom electrode layer 701, thus avoiding short circuits between them and the third sub-plug 801 and the fourth sub-plug 802. As an optional embodiment, the top surfaces of the first bottom electrode layer 601 and the second bottom electrode layer 701 may also be flush with the top surface of the perforation 501a; this invention is not limited thereto.

[0040] In this embodiment, the third bottom electrode layer 602 fills the remaining depth of the perforation 501a and extends to cover part of the top surface of the first sub-insulation layer 501. However, this should not be a limitation. As an optional embodiment, the third bottom electrode layer 602 may only fill the remaining depth of the perforation 501a without extending to cover part of the top surface of the first sub-insulation layer 501. This invention does not impose any limitations.

[0041] Optionally, the materials of the top electrode layer 702 and the second bottom electrode layer 701 can be metals such as TiW, W, Al, PT, and Ni, which will not be elaborated further here.

[0042] Optionally, the materials of the first bottom electrode layer 601 and the third bottom electrode layer 602 can both be SiC, N-type / P-type doped SiC (doping SiC can improve its resistivity), or TaN. It should be understood that the adhesion between semiconductor materials is better than that between metal and semiconductor materials. Therefore, when the material of the third bottom electrode layer 602 is SiC, the adhesion between the third bottom electrode layer 602 and the phase change storage layer 703 is better, which can prevent delamination.

[0043] Preferably, the resistivity of the first bottom electrode layer 601 can be less than that of the third bottom electrode layer 602. For example, the material of the first bottom electrode layer 601 is TaN, and the material of the third bottom electrode layer 602 is SiC. In this embodiment, SiC, with its slightly higher resistivity, can be used as the interface layer between the phase change storage layer 703 and the second bottom electrode layer 701. This not only increases the interface resistance and the Joule heating after current is applied, but also, since SiC is a tetravalent element, it has good adhesion to the GST material, allowing for better adhesion between the GST and the bottom electrode (third bottom electrode 602), thereby reducing defects at the contact surface between different materials.

[0044] Furthermore, the materials of the first sub-insulation layer 501 and the second sub-insulation layer 502 can be the same or different. For example, the materials of the first sub-insulation layer 501 and the second sub-insulation layer 502 can be SiCN or Si3N4. Since SiCN has better tensile stress than Si3N4, when the material of the second sub-insulation layer 502 is SiCN, the element migration in the phase change storage layer 703 can be reduced.

[0045] Figure 1 This is a flowchart illustrating the fabrication method of the phase-change memory cell provided in this embodiment. Figure 1 As shown, the method for fabricating the phase-change memory cell includes: Step S100: Provide a substrate; Step S200: Forming a dielectric layer on the substrate; and, Step S300: Form a stacked structure within the dielectric layer. The stacked structure includes a first bottom electrode layer, a second bottom electrode layer, a third bottom electrode layer, a phase change storage layer, and a top electrode layer arranged sequentially from bottom to top. The resistivity of the first bottom electrode layer and the third bottom electrode layer is greater than that of the second bottom electrode layer.

[0046] Figures 2-11 This is a schematic diagram of the structure corresponding to the steps of the fabrication method of the phase-change memory cell provided in this embodiment. Next, we will combine... Figures 2-11 The preparation method of the phase change memory unit provided in this embodiment will be described in detail.

[0047] like Figure 2 As shown, in step S100, the substrate 100 is provided, and an active region and a trench isolation structure for isolating the active region are formed in the substrate 100. Figure 2 (not shown in the image), the active region includes a source region 101 and a drain region 102.

[0048] A gate structure 200 is formed on the substrate 100. The gate structure 200 is located between the source region 101 and the drain region 102. The gate structure 200 and the source region 101 and drain region 102 on both sides constitute a transistor unit. The process steps for forming the gate structure 200 can be any existing method, which will not be described in detail here.

[0049] Optionally, the step of forming the active region can be performed before or after forming the gate structure 200.

[0050] Optionally, after forming the gate structure 200, metal silicides may also be formed on the source region 101, the drain region 102 and the top surface of the gate structure 200.

[0051] like Figure 3 As shown, steps S200 and S300 are performed to form a first sub-dielectric layer 301 on the substrate 100. The first sub-dielectric layer 301 covers the substrate 100 and the gate structure 200, and extends upward above the gate structure 200. After the first sub-dielectric layer 301 is formed, it can be polished to make the top of the first sub-dielectric layer 301 flat.

[0052] Furthermore, after forming the first sub-dielectric layer 301, a first sub-plug 401, a second sub-plug 402, and a fourth plug 403 are formed within the first sub-dielectric layer 301. The first sub-plug 401, the second sub-plug 402, and the fourth plug 403 penetrate the first sub-dielectric layer 301 and are electrically connected to the source region 101, the gate structure 200, and the drain region 102, respectively.

[0053] In this embodiment, the first sub-plug 401, the second sub-plug 402, and the fourth plug 403 are formed simultaneously. The process steps for forming the first sub-plug 401, the second sub-plug 402, and the fourth plug 403 may be as follows: etching the first sub-dielectric layer 301 to form a first through-hole, a second through-hole, and a third through-hole penetrating the first sub-dielectric layer 301, respectively exposing the top surfaces of the source region 101, the gate structure 200, and the drain region 102; depositing conductive material on the first sub-dielectric layer 301, covering the top surface of the first sub-dielectric layer 301 and filling the first through-hole, the second through-hole, and the third through-hole; and finally removing the conductive material from the top surface of the first sub-dielectric layer 301, with the conductive material in the first through-hole, the second through-hole, and the third through-hole constituting the first sub-plug 401, the second sub-plug 402, and the fourth plug 403, respectively.

[0054] like Figure 4 As shown, a first sub-insulation layer 501 is formed on the first sub-dielectric layer 301, and the first sub-insulation layer 501 covers the top surface of the first sub-dielectric layer 301. The first sub-insulation layer 501 is etched to form a perforation 501a, which is aligned with and exposes at least a portion of the top surface of the fourth plug 403.

[0055] like Figure 5 As shown, a first bottom electrode layer 601, a second bottom electrode layer 701, and a first sub-electrode layer 612 are formed conformally on the first sub-insulation layer 501 and in the perforation 501a. The first bottom electrode layer 601 and the second bottom electrode layer 701 only cover the inner wall of the perforation 501a, making the first bottom electrode layer 601 and the second bottom electrode layer 701 in the perforation 501a U-shaped, while the first sub-electrode layer 612 also fills the opening of the second bottom electrode layer 701.

[0056] like Figure 6 As shown, grinding is performed to remove the first bottom electrode layer 601, the second bottom electrode layer 701, and the first sub-electrode layer 612 from the first sub-heat insulation layer 501. Then, portions of the first bottom electrode layer 601, the second bottom electrode layer 701, and the first sub-electrode layer 612 in the perforation 501a are etched back. After etching, the top surfaces of the first bottom electrode layer 601, the second bottom electrode layer 701, and the first sub-electrode layer 612 are flush with and lower than the top surface of the first sub-heat insulation layer 501; that is, the first bottom electrode layer 601, the second bottom electrode layer 701, and the first sub-electrode layer 612 are located only within a portion of the depth of the perforation 501a. Furthermore, at this time, the first bottom electrode layer 601 and the second bottom electrode layer 701 still maintain a U-shape, and the first sub-electrode layer 612 fills the opening of the second bottom electrode layer 701.

[0057] Of course, as an optional embodiment, the step of re-etching part of the first bottom electrode layer 601, the second bottom electrode layer 701, and the first sub-electrode layer 612 in the perforation 501a can be omitted. After grinding, the top surfaces of the first bottom electrode layer 601, the second bottom electrode layer 701, and the first sub-electrode layer 612 can be flush with the top surface of the first sub-insulation layer 501, that is, the first bottom electrode layer 601, the second bottom electrode layer 701, and the first sub-electrode layer 612 just fill the perforation 501a.

[0058] like Figure 7As shown, a second sub-electrode layer 622 is formed conformally on the first sub-insulation layer 501 and in the perforation 501a, and the second sub-electrode layer 622 fills the remaining depth of the perforation 501a.

[0059] like Figure 8 As shown, the phase change storage layer 703 and the top electrode layer 702 are sequentially formed on the second sub-electrode layer 622.

[0060] like Figure 9 As shown, etching is performed to remove part of the lateral width of the top electrode layer 702, the phase change storage layer 703, and the second sub-electrode layer 622, leaving only the top electrode layer 702, the phase change storage layer 703, and the second sub-electrode layer 622 above the through hole 501a. The remaining second sub-electrode layer 622 and the first sub-electrode layer 612 constitute the third bottom electrode layer 602.

[0061] like Figure 10 As shown, a second sub-insulation layer 502 is formed on the first sub-insulation layer 501. The second sub-insulation layer 502 also conformally covers the exposed outer wall of the top electrode layer 702, the phase change storage layer 703, and the second sub-electrode layer 622. The first sub-insulation layer 501 and the second sub-insulation layer 502 constitute an insulation layer.

[0062] like Figure 11 As shown, a second sub-dielectric layer 302 is formed on the second sub-insulation layer 502, and the second sub-dielectric layer 302 extends upward above the top electrode layer 702. After the second sub-dielectric layer 302 is formed, it can be polished to make the top of the second sub-dielectric layer 302 flat.

[0063] Further, after forming the second sub-dielectric layer 302, a third sub-plug 801, a fourth sub-plug 802, and a third plug 803 are formed on the second sub-dielectric layer 302. The third sub-plug 801 and the fourth sub-plug 802 are electrically connected to the first sub-plug 401 and the second sub-plug 402, respectively. The first sub-plug 401 and the third sub-plug 801 constitute the first plug, and the second sub-plug 402 and the fourth sub-plug 802 constitute the second plug. The third plug 803 penetrates the second sub-dielectric layer 302 and the second sub-insulation layer 502, and is electrically connected to the top electrode layer 702.

[0064] In this embodiment, the third sub-plug 801, the fourth sub-plug 802, and the third plug 803 can be formed in steps. For example, the third plug 803 can be formed first, and then the third sub-plug 801 and the fourth sub-plug 802 can be formed.

[0065] The process steps for forming the third plug 803 may be as follows: etching the second sub-dielectric layer 302 and the second sub-heat insulation layer 502 to form a fourth through hole penetrating the second sub-dielectric layer 302 and the second sub-heat insulation layer 502, the fourth through hole exposing part of the top surface of the top electrode layer 702; depositing conductive material on the second sub-dielectric layer 302, the conductive material covering the top surface of the second sub-dielectric layer 302 and filling the fourth through hole; and finally removing the conductive material on the top surface of the second sub-dielectric layer 302, the conductive material in the fourth through hole constituting the third plug 803. Similarly, the process steps for forming the third sub-plug 801 and the fourth sub-plug 802 may be as follows: etching the second sub-dielectric layer 302, the second sub-heat insulation layer 502, and the first sub-heat insulation layer 501 to form a fifth through hole and a sixth through hole penetrating the second sub-dielectric layer 302, the second sub-heat insulation layer 502, and the first sub-heat insulation layer 501, respectively, with the fifth through hole and the sixth through hole exposing the top surfaces of the first sub-plug 401 and the second sub-plug 402, respectively; depositing conductive material on the second sub-dielectric layer 302, with the conductive material covering the top surface of the second sub-dielectric layer 302 and filling the fifth through hole and the sixth through hole; and finally removing the conductive material from the top surface of the second sub-dielectric layer 302, with the conductive material in the fifth through hole and the sixth through hole constituting the third sub-plug 801 and the fourth sub-plug 802, respectively.

[0066] Please continue reading. Figure 11 A first pad 901, a second pad 902, and a third pad 903 are formed on the top surface of the second dielectric layer. The first pad 901, the second pad 902, and the third pad 903 are electrically connected to the third sub-plug 801, the fourth sub-plug 802, and the third plug 803, respectively. In this way, the first pad 901, the second pad 902, and the third pad 903 can be electrically connected to the source region 101, the gate structure 200, and the top electrode layer 702, respectively, through the first plug, the second plug, and the third plug 803.

[0067] Example 2 Figure 20 This is a schematic diagram of the phase-change memory unit provided in this embodiment. Figure 20As shown, the difference from Embodiment 1 is that in this embodiment, the first bottom electrode layer 601 is U-shaped and located within the perforation 501a, covering the inner wall of the perforation 501a; the second bottom electrode layer 701 is located within the opening of the first bottom electrode layer 601 and fills a portion of the depth of the opening of the first bottom electrode layer 601; the third bottom electrode layer 602 covers the top surfaces of the first bottom electrode layer 601 and the second bottom electrode layer 701. Figure 20 As can be seen, the first bottom electrode layer 601 completely covers the bottom surface of the second bottom electrode layer 701, and the third bottom electrode layer 602 completely covers the top surface of the second bottom electrode layer 701. The first bottom electrode layer 601 and the third bottom electrode layer 602 can completely wrap around the outer wall of the second bottom electrode layer 701, thereby effectively preventing heat diffusion from the second bottom electrode layer 701.

[0068] In this embodiment, the first bottom electrode layer 601 and the second bottom electrode layer 701 are located within a portion of the depth of the perforation 501a. The top surfaces of the first bottom electrode layer 601 and the second bottom electrode layer 701 are lower than the top surface of the perforation 501a, thereby preventing material residue of the first bottom electrode layer 601 and / or the second bottom electrode layer 701 from remaining on the first sub-insulation layer 501 during the fabrication of the first bottom electrode layer 601 and the second bottom electrode layer 701, thus avoiding short circuits between them and the third sub-plug 801 and the fourth sub-plug 802. As an optional embodiment, the top surfaces of the first bottom electrode layer 601 and the second bottom electrode layer 701 may also be flush with the top surface of the perforation 501a; this invention is not limited thereto.

[0069] In this embodiment, the second bottom electrode layer 701 fills a portion of the depth of the opening of the first bottom electrode layer 601, but this should not be a limitation. As an optional embodiment, the second bottom electrode layer 701 may also completely fill the opening of the first bottom electrode layer 601. This invention does not impose any limitations.

[0070] In this embodiment, the third bottom electrode layer 602 fills the remaining depth of the perforation 501a and extends to cover part of the top surface of the first sub-insulation layer 501. However, this should not be a limitation. As an optional embodiment, the third bottom electrode layer 602 may only fill the remaining depth of the perforation 501a without extending to cover part of the top surface of the first sub-insulation layer 501. This invention does not impose any limitations.

[0071] Figures 12-20 This is a schematic diagram of the structure corresponding to the steps of the fabrication method of the phase-change memory cell provided in this embodiment. Next, we will combine... Figures 12-20The preparation method of the phase change memory unit provided in this embodiment will be described in detail.

[0072] It has been executed in Example 1 Figure 3 Based on the steps, such as Figure 12 As shown, a first bottom electrode layer 601 is formed conformally on the first sub-insulation layer 501 and in the perforation 501a. The first bottom electrode layer 601 only covers the inner wall of the perforation 501a, so that the first bottom electrode layer 601 in the perforation 501a is U-shaped.

[0073] like Figure 13 As shown, etching is performed to remove a portion of the first bottom electrode layer 601 on the first sub-heat insulation layer 501 and in the perforation 501a, leaving only a portion of the first bottom electrode layer 601 in the perforation 501a. After etching, the top surface of the first bottom electrode layer 601 is lower than the top surface of the first sub-heat insulation layer 501, and the first bottom electrode layer 601 still retains a U-shape at this time.

[0074] like Figure 14 As shown, a second bottom electrode layer 701 is formed conformally on the first sub-insulation layer 501 and in the perforation 501a, and the second bottom electrode layer 701 fills the perforation 501a (and also fills the opening of the first bottom electrode layer 601).

[0075] like Figure 15 As shown, etching is performed to remove a portion of the second bottom electrode layer 701 on the first sub-insulation layer 501 and in the perforation 501a, leaving only a portion of the second bottom electrode layer 701 in the opening of the first bottom electrode layer 601.

[0076] like Figure 16 As shown, a third bottom electrode layer 602 is formed conformally on the first sub-insulation layer 501 and in the perforation 501a, the third bottom electrode layer 602 filling the perforation 501a (and also filling the remaining depth of the opening of the first bottom electrode layer 601).

[0077] like Figure 17 As shown, the phase change storage layer 703 and the top electrode layer 702 are sequentially formed on the third bottom electrode layer 602.

[0078] like Figure 18 As shown, etching is performed to remove part of the lateral width of the top electrode layer 702, the phase change storage layer 703, and the third bottom electrode layer 602, leaving only the top electrode layer 702, the phase change storage layer 703, and the third bottom electrode layer 602 above the through hole 501a.

[0079] like Figure 19 As shown, a second sub-insulation layer 502 is formed on the first sub-insulation layer 501, and the second sub-insulation layer 502 also conformally covers the exposed outer walls of the top electrode layer 702, the phase change storage layer 703, and the third bottom electrode layer 602. The first sub-insulation layer 501 and the second sub-insulation layer 502 constitute an insulation layer.

[0080] like Figure 20 As shown, a second sub-dielectric layer 302 is formed on the second sub-insulation layer 502, and the second sub-dielectric layer 302 extends upward above the top electrode layer 702. After the second sub-dielectric layer 302 is formed, it can be polished to make the top of the second sub-dielectric layer 302 flat.

[0081] Further, after forming the second sub-dielectric layer 302, a third sub-plug 801, a fourth sub-plug 802, and a third plug 803 are formed on the second sub-dielectric layer 302. The third sub-plug 801 and the fourth sub-plug 802 are electrically connected to the first sub-plug 401 and the second sub-plug 402, respectively. The first sub-plug 401 and the third sub-plug 801 constitute the first plug, and the second sub-plug 402 and the fourth sub-plug 802 constitute the second plug. The third plug 803 penetrates the second sub-dielectric layer 302 and the second sub-insulation layer 502 and is electrically connected to the top electrode layer 702.

[0082] In this embodiment, the third sub-plug 801, the fourth sub-plug 802, and the third plug 803 can be formed in a distributed manner. For example, the third plug 803 can be formed first, and then the third sub-plug 801 and the fourth sub-plug 802 can be formed.

[0083] The process steps for forming the third sub-plug 801, the fourth sub-plug 802 and the third plug 803 can be the same as in Embodiment 1, and will not be described in detail here.

[0084] Please continue reading. Figure 20 A first pad 901, a second pad 902, and a third pad 903 are formed on the top surface of the second dielectric layer. The first pad 901, the second pad 902, and the third pad 903 are electrically connected to the third sub-plug 801, the fourth sub-plug 802, and the third plug 803, respectively. In this way, the first pad 901, the second pad 902, and the third pad 903 can be electrically connected to the source region 101, the gate structure 200, and the top electrode layer 702, respectively, through the first plug, the second plug, and the third plug 803.

[0085] Example 3 Figure 29 This is a schematic diagram of the phase-change memory unit provided in this embodiment. Figure 29 As shown, the difference from Embodiments 1 and 2 is that in this embodiment, the first bottom electrode layer 601, the second bottom electrode layer 701, and the third bottom electrode layer 602 are all flat and stacked sequentially within the perforation 501a. Specifically, the first bottom electrode layer 601 is located within the perforation 501a and fills a portion of the depth of the perforation 501a; the second bottom electrode layer 701 is located on top of the first bottom electrode layer 601 and fills a portion of the depth of the perforation 501a; and the third bottom electrode layer 602 is located on top of the second bottom electrode layer 701 and fills the remaining depth of the perforation 501a. Figure 28 As can be seen, the first bottom electrode layer 601 covers the bottom surface of the second bottom electrode layer 701, and the third bottom electrode layer 602 covers the top surface of the second bottom electrode layer 701. The first bottom electrode layer 601 and the third bottom electrode layer 602 can at least wrap around the bottom and top surfaces of the second bottom electrode layer 701, which can also prevent heat diffusion to a certain extent, improve heating efficiency and reduce power consumption.

[0086] In this embodiment, the first bottom electrode layer 601 and the second bottom electrode layer 701 are located within a portion of the depth of the perforation 501a. The top surfaces of the first bottom electrode layer 601 and the second bottom electrode layer 701 are lower than the top surface of the perforation 501a, thereby preventing material residue of the first bottom electrode layer 601 and / or the second bottom electrode layer 701 from remaining on the first sub-insulation layer 501 during the fabrication of the first bottom electrode layer 601 and the second bottom electrode layer 701, thus avoiding short circuits between them and the third sub-plug 801 and the fourth sub-plug 802. As an optional embodiment, the top surfaces of the first bottom electrode layer 601 and the second bottom electrode layer 701 may also be flush with the top surface of the perforation 501a; this invention is not limited thereto.

[0087] In this embodiment, the third bottom electrode layer 602 fills the remaining depth of the perforation 501a and extends to cover part of the top surface of the first sub-insulation layer 501. However, this should not be a limitation. As an optional embodiment, the third bottom electrode layer 602 may only fill the remaining depth of the perforation 501a without extending to cover part of the top surface of the first sub-insulation layer 501. This invention does not impose any limitations.

[0088] Figures 21-29 This is a schematic diagram of the structure corresponding to the steps of the fabrication method of the phase-change memory cell provided in this embodiment. Next, we will combine... Figures 21-29 The preparation method of the phase change memory unit provided in this embodiment will be described in detail.

[0089] It has been executed in Example 1 Figure 3 Based on the steps, such as Figure 21 As shown, a first bottom electrode layer 601 is formed conformally on the first sub-insulation layer 501 and in the perforation 501a, and the first bottom electrode layer 601 also fills the perforation 501a.

[0090] like Figure 22 As shown, etching is performed to remove a portion of the first bottom electrode layer 601 on the first sub-heat insulation layer 501 and in the perforation 501a, leaving only a portion of the first bottom electrode layer 601 in the perforation 501a. After etching, the top surface of the first bottom electrode layer 601 is lower than the top surface of the first sub-heat insulation layer 501, and at this time, the first bottom electrode layer 601 fills a portion of the depth of the perforation 501a.

[0091] like Figure 23 As shown, a second bottom electrode layer 701 is formed conformally on the first sub-insulation layer 501 and in the perforation 501a, and the second bottom electrode layer 701 fills the perforation 501a.

[0092] like Figure 24 As shown, etching is performed to remove a portion of the second bottom electrode layer 701 on the first sub-heat insulation layer 501 and in the perforation 501a, leaving only a portion of the second bottom electrode layer 701 in the perforation 501a. After etching, the top surface of the second bottom electrode layer 701 is lower than the top surface of the first sub-heat insulation layer 501, and at this time, the first bottom electrode layer 601 and the second bottom electrode layer 701 together fill a portion of the depth of the perforation 501a.

[0093] like Figure 25 As shown, a third bottom electrode layer 602 is formed conformally on the first sub-insulation layer 501 and in the perforation 501a, and the third bottom electrode layer 602 fills the perforation 501a.

[0094] like Figure 26 As shown, the phase change storage layer 703 and the top electrode layer 702 are sequentially formed on the third bottom electrode layer 602.

[0095] like Figure 27 As shown, etching is performed to remove part of the lateral width of the top electrode layer 702, the phase change storage layer 703, and the third bottom electrode layer 602, leaving only the top electrode layer 702, the phase change storage layer 703, and the third bottom electrode layer 602 above the through hole 501a.

[0096] like Figure 28As shown, a second sub-insulation layer 502 is formed on the first sub-insulation layer 501, and the second sub-insulation layer 502 also conformally covers the exposed outer walls of the top electrode layer 702, the phase change storage layer 703, and the third bottom electrode layer 602. The first sub-insulation layer 501 and the second sub-insulation layer 502 constitute an insulation layer.

[0097] like Figure 29 As shown, a second sub-dielectric layer 302 is formed on the second sub-insulation layer 502, and the second sub-dielectric layer 302 extends upward above the top electrode layer 702. After the second sub-dielectric layer 302 is formed, it can be polished to make the top of the second sub-dielectric layer 302 flat.

[0098] Further, after forming the second sub-dielectric layer 302, a third sub-plug 801, a fourth sub-plug 802, and a third plug 803 are formed on the second sub-dielectric layer 302. The third sub-plug 801 and the fourth sub-plug 802 are electrically connected to the first sub-plug 401 and the second sub-plug 402, respectively. The first sub-plug 401 and the third sub-plug 801 constitute the first plug, and the second sub-plug 402 and the fourth sub-plug 802 constitute the second plug. The third plug 803 penetrates the second sub-dielectric layer 302 and the second sub-insulation layer 502 and is electrically connected to the top electrode layer 702.

[0099] In this embodiment, the third sub-plug 801, the fourth sub-plug 802, and the third plug 803 can be formed in a distributed manner. For example, the third plug 803 can be formed first, and then the third sub-plug 801 and the fourth sub-plug 802 can be formed.

[0100] The process steps for forming the third sub-plug 801, the fourth sub-plug 802 and the third plug 803 can be the same as in Embodiment 1, and will not be described in detail here.

[0101] Please continue reading. Figure 29 A first pad 901, a second pad 902, and a third pad 903 are formed on the top surface of the second dielectric layer. The first pad 901, the second pad 902, and the third pad 903 are electrically connected to the third sub-plug 801, the fourth sub-plug 802, and the third plug 803, respectively. In this way, the first pad 901, the second pad 902, and the third pad 903 can be electrically connected to the source region 101, the gate structure 200, and the top electrode layer 702, respectively, through the first plug, the second plug, and the third plug 803.

[0102] In summary, the phase-change memory cell provided in this embodiment of the invention includes a substrate, a dielectric layer, and a stacked structure. The dielectric layer is located on the substrate, and the stacked structure is located within the dielectric layer. It includes, from bottom to top, a first bottom electrode layer, a second bottom electrode layer, a third bottom electrode layer, a phase-change memory layer, and a top electrode layer. In this invention, the resistivity of both the first and third bottom electrode layers is greater than that of the second bottom electrode layer. Therefore, the first and third bottom electrode layers have lower thermal conductivity and better heat retention than the second bottom electrode layer. Since the second bottom electrode layer is sandwiched between the first and third bottom electrode layers, the first and third bottom electrode layers can prevent heat diffusion, improve the overall heating efficiency of the bottom electrode, and reduce power consumption. Accordingly, this invention also provides a method for fabricating the phase-change memory cell.

[0103] It should be noted that the various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. For the systems disclosed in the embodiments, since they correspond to the methods disclosed in the embodiments, the descriptions are relatively simple, and relevant parts can be referred to the method section.

[0104] It should also be noted that although the present invention has been disclosed above with reference to preferred embodiments, these embodiments are not intended to limit the present invention. For any person skilled in the art, many possible variations and modifications can be made to the technical solutions of the present invention based on the disclosed technical content, or equivalent embodiments can be modified accordingly, without departing from the scope of the present invention. Therefore, any simple modifications, equivalent changes, and modifications made to the above embodiments based on the technical essence of the present invention without departing from the content of the present invention shall still fall within the scope of protection of the present invention.

[0105] It should also be understood that, unless otherwise specified or indicated, the terms “first,” “second,” “third,” etc., in the specification are used only to distinguish the various components, elements, and steps in the specification, and not to indicate the logical or sequential relationships between the various components, elements, and steps.

[0106] Furthermore, it should be recognized that the terminology described herein is used only to describe particular embodiments and not to limit the scope of the invention. It must be noted that the singular forms “a” and “an” used herein and in the appended claims include plural bases unless the context clearly indicates otherwise. For example, a reference to “a step” or “an apparatus” means a reference to one or more steps or apparatuses, and may include secondary steps and secondary apparatuses. All conjunctions used should be understood in the broadest sense. Also, the word “or” should be understood to have the definition of logical “or” rather than logical “exclusive OR”, unless the context clearly indicates otherwise. Furthermore, implementation of the methods and / or devices in embodiments of the invention may include performing selected tasks manually, automatically, or in combination.

Claims

1. A phase-change memory cell, characterized in that, include: Substrate; A dielectric layer is located on the substrate; as well as, The stacked structure, located within the dielectric layer, includes a first bottom electrode layer, a second bottom electrode layer, a third bottom electrode layer, a phase change storage layer, and a top electrode layer arranged sequentially from bottom to top. The resistivity of the first bottom electrode layer and the third bottom electrode layer is greater than that of the second bottom electrode layer, and the thermal conductivity of the first bottom electrode layer and the third bottom electrode layer is worse than that of the second bottom electrode layer.

2. The phase-change memory unit as described in claim 1, characterized in that, The resistivity of the first bottom electrode layer is less than that of the third bottom electrode layer.

3. The phase-change memory unit as described in claim 1 or 2, characterized in that, The materials of the first bottom electrode layer and the third bottom electrode layer both include SiC and N-type / P-type doped SiC.

4. The phase-change memory unit as described in claim 1, characterized in that, The first bottom electrode layer and the third bottom electrode layer completely cover the outer wall of the second bottom electrode layer.

5. The phase-change memory unit as described in claim 4, characterized in that, The first bottom electrode layer is U-shaped, the second bottom electrode layer is located inside the opening of the first bottom electrode layer and fills at least a portion of the depth of the opening of the first bottom electrode layer, and the third bottom electrode layer covers the top surfaces of the first bottom electrode layer and the second bottom electrode layer.

6. The phase-change memory unit as described in claim 4, characterized in that, The first bottom electrode layer and the second bottom electrode layer are both U-shaped and stacked sequentially. The third bottom electrode layer fills the opening of the second bottom electrode layer and extends to cover the top surface of the first bottom electrode layer and the second bottom electrode layer.

7. The phase-change memory unit as described in claim 1, characterized in that, The first bottom electrode layer, the second bottom electrode layer, and the third bottom electrode layer are all flat and stacked sequentially.

8. The phase-change memory cell as described in any one of claims 1, 2, 4, 5, 6, and 7, characterized in that, It also includes a heat insulation layer located within the dielectric layer and at least covering the exposed outer wall of the stacked structure.

9. The phase-change memory unit as described in claim 8, characterized in that, The material of the heat insulation layer includes SiCN or Si3N4.

10. The phase-change memory unit as described in claim 8, characterized in that, The dielectric layer includes a first sub-dielectric layer and a second sub-dielectric layer disposed sequentially from bottom to top; the heat insulation layer is located between the first sub-dielectric layer and the second sub-dielectric layer, and includes a first sub-heat insulation layer and a second sub-heat insulation layer; and, The first sub-insulation layer covers the first sub-dielectric layer and has a perforation therein. The first bottom electrode layer and the second bottom electrode layer fill a portion of the depth of the perforation. The third bottom electrode layer fills at least the remaining depth of the perforation. The second sub-insulation layer covers the first sub-insulation layer and the exposed outer walls of the third bottom electrode layer, the phase change storage layer, and the top electrode layer.

11. The phase-change memory unit as claimed in claim 1, characterized in that, Also includes: The source and drain regions are located within the substrate; A gate structure is located on a substrate between the source region and the drain region; as well as, The first pad, the second pad, and the third pad are located on the dielectric layer and are electrically connected to the source region, the gate structure, and the top electrode layer through the first plug, the second plug, and the third plug located in the dielectric layer, respectively. The second bottom electrode layer is electrically connected to the drain region through the first bottom electrode layer and the fourth plug located in the dielectric layer.

12. A method for fabricating a phase-change memory cell, characterized in that, include: Provide substrate; A dielectric layer is formed on the substrate; as well as, A stacked structure is formed within the dielectric layer. The stacked structure includes a first bottom electrode layer, a second bottom electrode layer, a third bottom electrode layer, a phase change storage layer, and a top electrode layer arranged sequentially from bottom to top. The resistivity of the first bottom electrode layer and the third bottom electrode layer is greater than that of the second bottom electrode layer, and the thermal conductivity of the first bottom electrode layer and the third bottom electrode layer is worse than that of the second bottom electrode layer.

13. The method for preparing a phase-change memory cell as described in claim 12, characterized in that, The steps of forming the dielectric layer and the stacked structure include: A first sub-dielectric layer and a first sub-thermal insulation layer are sequentially formed on the substrate, wherein the first sub-thermal insulation layer has a perforation; A first bottom electrode layer, a second bottom electrode layer, and a third bottom electrode layer are sequentially formed within the perforation, and a phase change storage layer and a top electrode layer are sequentially formed on the third bottom electrode layer; A second sub-insulation layer is formed on the first sub-insulation layer, and the second sub-insulation layer further covers the exposed outer walls of the third bottom electrode layer, the phase change storage layer, and the top electrode layer; and... A second sub-dielectric layer is formed on the second sub-insulation layer, the first sub-dielectric layer and the second sub-dielectric layer constitute the dielectric layer, and the first sub-insulation layer and the second sub-insulation layer constitute the insulation layer.

14. The method for preparing a phase-change memory cell as described in claim 13, characterized in that, The steps of forming the first bottom electrode layer, the second bottom electrode layer, the third bottom electrode layer, the phase change storage layer, and the top electrode layer include: A first bottom electrode layer, a second bottom electrode layer, and a first sub-electrode layer are sequentially formed in at least a portion of the depth of the perforation. The first bottom electrode layer and the second bottom electrode layer are both U-shaped and sequentially cover the inner wall of the perforation. The first sub-electrode layer fills the opening of the second bottom electrode layer. A second sub-electrode layer is formed on the first sub-insulation layer, and the second sub-electrode layer further fills the remaining depth of the perforation; and, The phase change storage layer and the top electrode layer are formed on the second sub-electrode layer, and a portion of the lateral width of the top electrode layer, the phase change storage layer and the second sub-electrode layer are removed simultaneously. The remaining first sub-electrode layer and the second sub-electrode layer constitute the third bottom electrode layer.

15. The method for preparing a phase-change memory cell as described in claim 13, characterized in that, The steps of forming the first bottom electrode layer, the second bottom electrode layer, the third bottom electrode layer, the phase change storage layer, and the top electrode layer include: The first bottom electrode layer is formed in at least a portion of the depth of the perforation, the first bottom electrode layer being U-shaped and covering the inner wall of the perforation; A second bottom electrode layer is formed within the opening of the first bottom electrode layer, and the second bottom electrode layer fills at least a portion of the depth of the opening of the first bottom electrode layer; A third bottom electrode layer is formed on the first sub-insulation layer and within the remaining depth of the perforation; and, The phase change storage layer and the top electrode layer are formed on the third bottom electrode layer, and a portion of the lateral width of the top electrode layer, the phase change storage layer and the third bottom electrode layer are removed simultaneously.

16. The method for preparing a phase-change memory cell as described in claim 13, characterized in that, The steps of forming the first bottom electrode layer, the second bottom electrode layer, the third bottom electrode layer, the phase change storage layer, and the top electrode layer include: The first bottom electrode layer and the second bottom electrode layer are sequentially formed within at least a portion of the depth of the perforation; A third bottom electrode layer is formed on the first sub-insulation layer and within the remaining depth of the perforation; and, The phase change storage layer and the top electrode layer are formed on the third bottom electrode layer, and a portion of the lateral width of the top electrode layer, the phase change storage layer and the third bottom electrode layer are removed simultaneously.

17. The method for preparing a phase-change memory cell as described in any one of claims 13 to 16, characterized in that, The substrate has a source region and a drain region. Before forming the first sub-dielectric layer, a gate structure is formed on the substrate between the source region and the drain region. After forming the first sub-dielectric layer, a first sub-plug, a second sub-plug, and a fourth plug are formed in the first sub-dielectric layer, which are electrically connected to the source region, the gate structure, and the drain region, respectively. The through hole is aligned with and exposes the fourth plug. After forming the second sub-dielectric layer, a third sub-plug, a fourth sub-plug, and a third plug, respectively electrically connected to the first sub-plug, the second sub-plug, and the top electrode layer, are formed within the second sub-dielectric layer; and, A first pad, a second pad, and a third pad are formed on the second sub-dielectric layer. The first pad, the second pad, and the third pad are electrically connected to the third sub-plug, the fourth sub-plug, and the third plug, respectively. The first sub-plug and the third sub-plug constitute a first plug, and the second sub-plug and the fourth sub-plug constitute a second plug.

Images