Wiring substrate and electronic device

Abstract

The application provides a wiring substrate and an electronic device. The wiring substrate comprises a substrate and a shield signal line arranged on the substrate. The substrate comprises a functional area; the functional area is provided with a plurality of pad groups; the plurality of pad groups are respectively arranged in a first direction and a second direction; the second direction intersects the first direction. The shield signal line comprises a first part surrounding all the pad groups and a second part connected with the first part; the second part is located between two adjacent pad groups in the second direction. The electronic device comprises the wiring substrate and an electronic element connected with the pad groups.

Description

Technical Field

[0001] This application relates to the field of display technology, and in particular to a wiring substrate and electronic device. Background Technology

[0002] Miniature light-emitting diodes, such as Mini-LEDs and Micro LEDs, are approximately smaller than 500μm. Due to their smaller size, ultra-high brightness, and long lifespan, their use in the display field is increasing significantly. Summary of the Invention

[0003] A first aspect of this application provides a wiring substrate. The wiring substrate includes a substrate and shielded signal lines disposed on the substrate;

[0004] The substrate includes a functional region; the functional region is provided with a plurality of pad groups; the plurality of pad groups are respectively arrayed along a first direction and a second direction, the second direction intersecting the first direction;

[0005] The shielded signal line includes a first portion that surrounds all pad groups and a second portion that is connected to the first portion, the second portion being located between two adjacent pad groups in the second direction.

[0006] In one embodiment, the wiring substrate further includes a bonding area located on one side of the functional area, and the second part is located between two pad groups that are furthest from the bonding area and adjacent to each other in the second direction among a plurality of pad groups arranged along the first direction.

[0007] In one embodiment, the first part and the second part form an integral structure.

[0008] In one embodiment, the line width of the first part is smaller than the dimension of the second part in the first direction.

[0009] In one embodiment, the wiring substrate further includes an insulating layer located on the side of the shielded signal line away from the substrate, the insulating layer having a plurality of first openings, and a second portion of the orthogonal projection on the substrate covering at least one of the first openings of the orthogonal projection on the substrate.

[0010] In one embodiment, the orthographic projection of one of the second portions on the substrate covers the orthographic projection of at least two first openings on the substrate, and the at least two first openings are spaced apart in the first direction.

[0011] In one embodiment, the pad group includes at least two sub-pads; the insulating layer is further provided with a plurality of second openings, one second opening exposing one of the sub-pads; the total area of ​​each of the first openings corresponding to a second portion is greater than the total area of ​​each of the second openings corresponding to an adjacent pad group.

[0012] In one embodiment, the shielded signal line further includes a third part connected to the first part;

[0013] The third part is located on the side of the pad group at the corner of the functional area that is not adjacent to other pad groups in the second direction.

[0014] In one embodiment, the first part and the third part form an integral structure.

[0015] In one embodiment, the line width of the first part is smaller than the dimension of the third part in the first direction; and / or, the dimension of the third part in the second direction is smaller than the dimension of the second part in the second direction.

[0016] In one embodiment, the wiring substrate further includes an insulating layer located on the side of the shielded signal line away from the substrate, the insulating layer having a plurality of first openings, and the orthographic projection of one of the third portions on the substrate covering the orthographic projection of at least one of the first openings on the substrate.

[0017] In one embodiment, the orthographic projection of one of the third parts onto the substrate covers the orthographic projections of at least two first openings onto the substrate; the at least two first openings are spaced apart in the first direction.

[0018] In one embodiment, the pad group includes at least two sub-pads; the insulating layer is further provided with a plurality of second openings, one of the second openings exposing one of the sub-pads;

[0019] The total area of ​​each first opening corresponding to a third part is greater than the total area of ​​each second opening corresponding to an adjacent pad group.

[0020] In one embodiment, the wiring substrate further includes a bonding area located on one side of the functional area; among the plurality of second openings corresponding to the pad group furthest from the bonding area among the plurality of pad groups arranged along the first direction, the distance from the second opening with the smallest distance from the bonding area to the bonding area is the first distance, the distance from the edge of the second part facing the bonding area to the bonding area to the bonding area is the second distance, and the distance from the edge of the third part facing the bonding area to the bonding area to the bonding area is the third distance;

[0021] The second distance is greater than or equal to the first distance; and / or, the third distance is greater than or equal to the first distance.

[0022] In one embodiment, the insulating layer comprises an inorganic layer.

[0023] In one embodiment, the wiring substrate further includes a reflective material layer located on the side of the insulating layer opposite to the substrate, the reflective material layer covering the first opening.

[0024] In one embodiment, the wiring substrate further includes a plurality of signal lines disposed on the substrate, and the wiring substrate further includes a bonding area located on one side of the functional area;

[0025] Of the plurality of signal lines, at least one signal line is located on the side of the second part facing the bonding area; in the first direction, the distance between the second part and the signal line located on the side of the second part facing the bonding area is greater than or equal to 200 micrometers;

[0026] And / or, of the plurality of signal lines, at least one signal line is located on the side of the third part facing the bonding area; in the first direction, the distance between the third part and the signal line located on the side of the third part facing the bonding area is greater than or equal to 200 micrometers.

[0027] In one embodiment, the pad group includes a plurality of sub-pads, the wiring substrate further includes connecting wires, and at least two sub-pads in the same pad group are connected by the connecting wires; in the second direction, the minimum distance between the second part and the adjacent connecting wire is greater than or equal to 200 micrometers; and / or, in the second direction, the minimum distance between the third part and the adjacent connecting wire is greater than or equal to 200 micrometers.

[0028] In one embodiment, the pad group includes multiple sub-pads, which are disposed on the same layer as the shielded signal line.

[0029] A second aspect of this application provides an electronic device, the electronic device including the wiring substrate described above and electronic components connected to the pad group.

[0030] The wiring substrate and electronic device provided in this application embodiment, by setting a shielded signal line including a second part, the second part being located between two adjacent pad groups in a second direction, can discharge the static charge accumulated on the sub-pads of the adjacent pad group, thereby improving the ability of the shielded signal line to discharge static charge, thereby improving the problem of electrostatic breakdown between adjacent sub-pads and improving the product yield of the wiring substrate. Attached Figure Description

[0031] Figure 1 This is a schematic diagram of the structure of a wiring substrate provided in an exemplary embodiment of this application;

[0032] Figure 2 This is a partial structural schematic diagram of a wiring substrate provided in an exemplary embodiment of this application;

[0033] Figure 3 yes Figure 2 A partial cross-sectional view of the wiring substrate shown along the AA direction;

[0034] Figure 4 This is a partial structural schematic diagram of an electronic device containing a wiring substrate provided in an exemplary embodiment of this application;

[0035] Figure 5 yes Figure 4 The diagram shows a partial cross-sectional view of the wiring substrate of the electronic device along the BB direction. Detailed Implementation

[0036] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numerals in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this application as detailed in the appended claims.

[0037] The terminology used in this application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. The singular forms “a,” “the,” and “the” used in this application and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the term “and / or” as used herein refers to and includes any or all possible combinations of one or more of the associated listed items.

[0038] It should be understood that although the terms first, second, third, etc., may be used in this application to describe various information, such information should not be limited to these terms. These terms are only used to distinguish information of the same type from one another. For example, without departing from the scope of this application, first information may also be referred to as second information, and similarly, second information may also be referred to as first information. Depending on the context, the word "if" as used herein may be interpreted as "when," "when," or "in response to determination."

[0039] This application provides a wiring substrate and an electronic device. The wiring substrate and electronic device of this application embodiment are described in detail below with reference to the accompanying drawings. Unless otherwise specified, the features in the following embodiments can complement or combine with each other.

[0040] This application provides a wiring substrate. For example... Figure 1 and Figure 2 As shown, the wiring substrate includes a substrate and shielded signal lines 40 disposed on the substrate. The substrate includes a functional region 101, on which a plurality of pad groups 30 are disposed. The plurality of pad groups 30 are arrayed along a first direction X and a second direction Y, respectively, the second direction Y intersecting the first direction X. The shielded signal lines 40 include a first portion 41 surrounding all pad groups 30 and a second portion 42 connected to the first portion 41, the second portion 42 being located between two adjacent pad groups 30 in the second direction Y. Each pad group 30 includes a plurality of sub-pads 311.

[0041] In one embodiment, such as Figure 3 As shown, the wiring substrate includes an insulating layer 50 located on the side of the shielded signal line 40 away from the substrate 10. The insulating layer 50 can cover most of the conductive layer of the wiring substrate, preventing water and oxygen intrusion and improving the reliability of the wiring substrate.

[0042] In some embodiments, the insulating layer 50 includes an inorganic layer. Inorganic layers provide better protection against water and oxygen, thus improving the reliability of the wiring substrate. In an exemplary embodiment, the insulating layer is made of an inorganic material, which may include at least one of silicon nitride, silicon oxide, or silicon oxynitride. The insulating layer 50 may include a single inorganic layer, multiple inorganic layers, or a stacked structure of organic and inorganic layers.

[0043] In one embodiment, such as Figure 2 As shown, the insulating layer 50 has a plurality of second openings 52, and each second opening 52 exposes one sub-pad 311. That is, the area of ​​the conductive layer of the wiring substrate exposed by the second opening 52 is the sub-pad 311.

[0044] In the manufacturing process of electronic devices containing wiring substrates, changes in process conditions between preceding and subsequent steps necessitate transferring the wiring substrate from one step to the next. In some embodiments, this involves the application and removal of protective films. Specifically, after the wiring substrate has completed the fabrication of each circuit film layer, and before applying an anti-oxidation treatment to the area where the sub-pads are located using the nickel-gold plating process, the application and removal of protective films are involved. Similarly, after the anti-oxidation treatment of the area where the sub-pads are located using the nickel-gold plating process, and before setting a reflective material layer on the wiring substrate, the application and removal of protective films are involved. The insulating layer 50 is made of inorganic material. During the process of applying the protective film to the insulating layer 50, static charge is injected into the sub-pads 311 of the pad group 30. The static charge accumulated on the sub-pads 311 cannot be effectively discharged, causing electrostatic breakdown between adjacent sub-pads 311.

[0045] The wiring substrate provided in this application embodiment includes a shielded signal line 40 with a second part 42 located between two adjacent pad groups 30 in the second direction Y. The second part 42 can discharge the static charge accumulated in the sub-pads 311 of the adjacent pad group 30, thereby improving the ability of the shielded signal line 40 to discharge static charge, and thus improving the problem of electrostatic breakdown between adjacent sub-pads 311, and improving the product yield of the wiring substrate.

[0046] In one embodiment, the first direction X and the second direction Y are perpendicular to each other. For example, the first direction X is a column direction, and the second direction Y is a row direction.

[0047] In one embodiment, the multiple pad groups 30 provided in the functional area 101 can be arranged in multiple rows and columns. Each row of pad groups includes multiple pad groups 30 spaced apart in the row direction, and each column of pad groups includes multiple pad groups 30 spaced apart in the column direction.

[0048] In one embodiment, the substrate may further include a border region 102 that surrounds the functional region 101. A first portion 41 of the shielded signal line 40 may be located in the border region 102. The border region 102 may include a bonding region 1021. The bonding region 1021 is provided with a flexible circuit board.

[0049] In one embodiment, as shown, Figure 1 and Figure 2 As shown, the wiring substrate also includes multiple signal lines disposed on the substrate. These signal lines include, for example, a common voltage line GND, a drive voltage line VLED, a source power line PWR, and a source address line DI. Each signal line is electrically connected to the flexible circuit board of the bonding area 1021. The flexible circuit board provides signals to the shielded signal line 40 and the multiple signal lines; for example, the flexible circuit board can provide the same signal to the common voltage line GND and the shielded signal line 40.

[0050] In one embodiment, sub-pads 311 of the pad group 30 are used for soldering to electronic components. The electronic components may include inorganic light-emitting diodes (LEDs) with dimensions on the order of hundreds of micrometers or smaller, and may also include driver chips with dimensions on the order of hundreds of micrometers or smaller. The inorganic LEDs with dimensions on the order of hundreds of micrometers or smaller can be mini LEDs or micro LEDs. Mini LEDs have a size range of approximately 100 μm to 500 μm, while micro LEDs have a size less than 100 μm. The driver chip can be a chip used to provide signals to the inorganic LEDs to cause them to emit light.

[0051] In some embodiments, such as Figure 1 , Figure 2 and Figure 4 As shown, each pad group 30 includes a first sub-pad group 31 and a second sub-pad group 32. The first sub-pad group 31 includes at least two sub-pads 311, which are used for soldering to inorganic light-emitting diodes (LEDs). For example, an inorganic LED may include two pins corresponding to the two sub-pads 311 of the first sub-pad group 31, one of which is an anode pad and the other is a cathode pad. The second sub-pad group 32 includes at least two sub-pads 311, which are used for soldering to driver chips. Figure 4 As shown, a driver chip includes four pins, and its corresponding second sub-pad group 32 includes four sub-pads: address pad Di, power pad Pwr, common voltage pad Gnd, and output pad Out. Within the same pad group, the output pad Out of the second sub-pad group 32 is connected to at least one sub-pad 311 of a first sub-pad group 31; the common voltage pad Gnd of the second sub-pad group 32 is connected to the common voltage line GND to receive the common voltage (e.g., ground voltage) transmitted by the common voltage line GND; the power pad Pwr of the second sub-pad group 32 is connected to the source power line PWR. The drive voltage line VLED is connected to one sub-pad 311 of a first sub-pad group 31. The source address line DI is connected to the address pad Di soldered to the first-stage driver chip in each row of pad groups and is configured to transmit address signals to the first-stage driver chip soldered to each row of pad groups.

[0052] In one embodiment, a pad group 30 may include four first sub-pad groups 31 and one second sub-pad group 32, meaning that four inorganic light-emitting diodes can be driven by a single driver chip. For example... Figure 2 As shown, among the four first sub-pad groups 31, the first sub-pad group 31 electrically connected to the driving voltage line VLED serves as the starting point for the series connection of these four first sub-pad groups 31, and the first sub-pad group 31 electrically connected to the second sub-pad group 32 serves as the ending point for the series connection of these four inorganic light-emitting diodes. It should be noted that, in the embodiments of this application, the number of first sub-pad groups 31 of each pad group 30 is not limited, and can be any number such as five, six, seven, or eight, and is not limited to four.

[0053] In one embodiment, the wiring substrate further includes connecting wires, through which at least two sub-pads in the same pad group are connected. For example, sub-pads 311 of adjacent first sub-pad groups 31 in the same pad group 30 are connected in series via connecting wires 60.

[0054] In one embodiment, the shielded signal line 40, each sub-pad 311 of the pad group 30, and the multiple signal lines are located on the same layer. That is, a single conductive layer can be used to fabricate multiple sub-pads and traces connecting adjacent sub-pads, and also to fabricate multiple signal lines to transmit corresponding electrical signals to the driver chip soldered to the sub-pads of the second sub-pad group and the inorganic light-emitting diode soldered to the sub-pads of the first sub-pad group. This helps simplify the film structure of the wiring substrate and reduces manufacturing costs. In this application, the term "A and B are located on the same layer" means that A and B are located on the surface of the same film layer and are both in direct contact with that surface. In some embodiments, A and B are formed from the same film layer using the same process. In some embodiments, A and B are located on the surface of the same film layer and are both in direct contact with that surface, and A and B have substantially the same height or thickness.

[0055] In one embodiment, such as Figure 5 As shown, the wiring substrate further includes an insulating material layer 82 located between the substrate 10 and the sub-pad 311. The insulating material layer 82 has a plurality of third openings 801, and each sub-pad 311 is at least partially located within the third opening 801. The orthographic projection of each third opening 801 on the substrate 10 falls within the orthographic projection of a second opening 52 on the substrate 10. The sub-pad 311 is at least partially located within the third opening 801, meaning that at least a portion of the sub-pad 311 is recessed downwards within the third opening 801. The orthographic projection of the third opening 801 on the substrate falls within the orthographic projection of the second opening 52 on the substrate, thus exposing the insulating layer 50 to the sub-pad 311. Electronic component 90 includes electronic component body 91 and pins 92 on one side of electronic component body 91. During the soldering process of electronic component 90 pins 92 to sub-pads 311, the solder covering the surface of pins 92 melts and flows into the third opening 801, causing each pin 92 to move towards the sub-pad 311 to be soldered. The movement of pins 92 towards sub-pads 311 can improve the offset of electronic component 90 relative to its soldering position, so that pins 92 are effectively soldered to the corresponding sub-pads 311, avoiding the problem of poor soldering caused by the offset of electronic component, and improving the product yield.

[0056] In one embodiment, such as Figure 5 As shown, the insulating material layer 82 includes a first organic layer 821.

[0057] Furthermore, the thickness of the first organic layer 821 ranges from 2 μm to 4 μm. This setting ensures ease of process implementation while avoiding excessive thickness of the first organic layer 821, which would result in a large array substrate thickness. In some embodiments, the thickness of the first organic layer 821 is, for example, 2 μm, 2.5 μm, 3 μm, 3.5 μm, 4 μm, etc.

[0058] In one embodiment, the first organic layer 821 is a single-layer film, or the first organic layer 821 comprises multiple sub-organic layers, that is, the first organic layer 821 is formed through multiple coating processes. The material of the first organic layer 821 can be an organic resin.

[0059] In one embodiment, such as Figure 5 As shown, the wiring substrate further includes a passivation protection layer 81 located between the substrate 10 and the insulating material layer 82, and the passivation protection layer 81 can directly contact the substrate 10. The passivation protection layer 81 protects the substrate 10 from damage during etching of the film layer above the substrate 10. The material of the passivation protection layer 81 can be an inorganic material, such as silicon nitride, silicon oxide, or silicon oxynitride. In one embodiment, such as... Figure 1 As shown, the second part 42 is located between two pad groups 30 that are furthest from the bonding region 1021 and adjacent to each other in the second direction Y among the plurality of pad groups 30 arranged along the first direction X. Since the area of ​​the conductive layer for conducting away static charge is smaller near the pad group 30 furthest from the bonding region 1021 among the plurality of pad groups 30 arranged along the first direction X, electrostatic breakdown is more likely to occur between adjacent sub-pads 311. The second part 42 is located between two adjacent pad groups 30 in these pad groups 30, which can more effectively improve the problem of electrostatic breakdown caused by static charge accumulation in the sub-pads 311 of these pad groups 30.

[0060] In some embodiments, such as Figure 1 As shown, in the row of pad groups 30 arranged along the first direction X, the row of pad groups 30 furthest from the bonding area 1021 has a second part 42 between any two adjacent pad groups 30. This arrangement helps to improve the problem of electrostatic breakdown of sub-pads 311 in the pad group 30 furthest from the bonding area 1021 in the wiring substrate due to the accumulation of static charge.

[0061] In one embodiment, the first part 41 and the second part 42 form an integral structure.

[0062] In one embodiment, the linewidth of the first portion 41 is smaller than the dimension of the second portion 42 in the first direction. The first portion 41 includes a first segment extending along the first direction X and a second segment extending along the second direction Y; the linewidth of the first segment refers to its width in the second direction Y, and the linewidth of the second segment refers to its width in the first direction X. By setting the dimension of the second portion 42 in the first direction X to be larger than the linewidth of the first portion 41, the area of ​​the second portion 42 can be larger. The second portion 42 can conduct away more static charge accumulated on adjacent sub-pads 311, effectively reducing the impedance of the shielded signal line 40 and improving its ability to conduct static charge. This static charge further helps to improve the electrostatic breakdown problem caused by static charge accumulation on the sub-pads 311 in the wiring substrate.

[0063] In one embodiment, such as Figure 2 and Figure 3 As shown, the insulating layer 50 has a plurality of first openings 51, and the orthographic projection of one of the second portions 42 on the substrate covers the orthographic projection of at least one of the first openings 51 on the substrate 10. That is, a portion of the second portion 42 is exposed by the first openings 51. With this configuration, some of the static charge introduced during the application of the protective film will be dispersed to the area of ​​the second portion 42 exposed by the first openings 51, thereby reducing the amount of static charge injected into the sub-pads 311 adjacent to the second portion 42, which can further improve the problem of electrostatic breakdown caused by static charge accumulation in the sub-pads 311 of the wiring substrate. The shape of the first opening 51 can be rectangular, square, circular, etc.

[0064] In one embodiment, such as Figure 2 As shown, the area of ​​the first opening 51 is larger than the area of ​​the second opening 52. With this configuration, static charge introduced during the application of the protective film is more easily injected into the larger first opening 51, thereby helping to reduce the amount of static charge injected into the sub-pad 311 adjacent to the second part 42.

[0065] In one embodiment, such as Figure 2 As shown, the orthographic projection of the second portion 42 on the substrate covers the orthographic projection of at least two first openings 51 on the substrate, and the at least two first openings 51 are spaced apart in the first direction X. With this configuration, the first openings 51 corresponding to the second portion 42 are better dispersed in the first direction X, and more of the static charge introduced into each sub-pad 311 adjacent to the second portion 42 during the application of the protective film is dispersed by the second portion 42.

[0066] In one embodiment, the total area of ​​each of the first openings 51 corresponding to a second portion 42 is greater than the total area of ​​each of the second openings 52 corresponding to an adjacent pad group 30. The orthographic projection of the second portion 42 on the substrate covers the orthographic projection of its corresponding first openings 51 on the substrate. With this configuration, most of the static charge introduced during the application of the protective film is injected into the area of ​​the second portion 42 exposed by the first openings 51 and conducted away through the shielded signal lines, which can more effectively reduce the amount of static charge injected into the sub-pads 311 adjacent to the second portion 42.

[0067] In one embodiment, such as Figure 2 As shown, the shielded signal line 40 also includes a third part 43 connected to the first part 41; the third part 43 is disposed on the side of the pad group 30 located at the corner of the functional area 101 that is not adjacent to other pad groups 30 in the second direction Y. A pad group 30 at the corner refers to a pad group 30 where no other pad group 30 is located between it and the first segment extending along the first direction X of the first part 41, and where no pad group 30 is located between it and the second segment away from the bonding area 1021. By providing the third part 43, the static charge accumulated in the pad group 30 at the corner can be conducted away, improving the problem of electrostatic breakdown occurring in adjacent sub-pads 311 within the pad group 30.

[0068] In one embodiment, the shielded signal line 40 may include two opposing third portions 43 located on opposite sides of the functional area 101.

[0069] In one embodiment, the first part 41 and the third part 43 form an integral structure.

[0070] In one embodiment, the linewidth of the first portion 41 is smaller than the dimension of the third portion 43 in the first direction X. This configuration allows the third portion 43 to have a larger area, enabling it to conduct away more static charge accumulated on adjacent sub-pads 311. It also effectively reduces the impedance of the shielded signal line 40, enhancing its ability to conduct static charge and further mitigating electrostatic breakdown problems caused by static charge accumulation on the sub-pads 311 in the wiring substrate. Furthermore, the linewidth of the first portion 41 is smaller than the dimension of the third portion 43 in the second direction Y, further increasing the area of ​​the third portion 43.

[0071] In one embodiment, the dimension of the third part 43 in the second direction Y is smaller than the dimension of the second part 42 in the second direction Y. This arrangement results in a smaller space occupied by the third part 43 in the second direction Y, and thus has less impact on the dimensions of the wiring substrate in the second direction Y.

[0072] In one embodiment, the orthographic projection of one of the third portions 43 onto the substrate overlaps the orthographic projection of at least one of the first openings 51 onto the substrate. That is, a portion of the third portion 43 is exposed by the first opening 51. With this configuration, some of the static charge introduced during the application of the protective film is dispersed to the area of ​​the third portion 43 exposed by the first opening 51. This reduces the amount of static charge injected onto the sub-pads 311 adjacent to the third portion 43, further improving the problem of electrostatic breakdown caused by static charge accumulation on the sub-pads 311 in the wiring substrate.

[0073] In one embodiment, the orthographic projection of one of the third portions 43 onto the substrate covers the orthographic projections of at least two first openings 51 onto the substrate; the at least two first openings 51 are spaced apart in the first direction X. This arrangement provides better dispersion of the first openings 51 corresponding to the third portion 43 in the first direction X, resulting in more static charge being dispersed by the third portion 43 during the application of the protective film to the sub-pads 311 adjacent to the third portion 43.

[0074] In one embodiment, the total area of ​​each first opening 51 corresponding to a third part 43 is greater than the total area of ​​each second opening 52 corresponding to an adjacent pad group 30. The orthographic projection of the third part 43 on the substrate covers the orthographic projection of its corresponding first opening 51 on the substrate. With this configuration, most of the static charge introduced during the application of the protective film is injected into the area of ​​the third part 43 exposed by the first openings 51 and conducted away through the shielded signal lines, which can more effectively reduce the amount of static charge injected into the sub-pads 311 adjacent to the third part 43.

[0075] In one embodiment, among the multiple second openings 52 corresponding to the pad group 30 furthest from the bonding region 1021 among the multiple pad groups 30 arranged along the first direction X, the distance from the second opening 52 with the smallest distance from the bonding region 1021 to the bonding region 1021 is the first distance, the distance from the edge of the second part 42 toward the bonding region 1021 to the bonding region 1021 is the second distance, and the distance from the edge of the third part 43 toward the bonding region 1021 to the bonding region 1021 is the third distance.

[0076] In some embodiments, the second distance is greater than or equal to the first distance. This configuration ensures that the second part 42 does not extend beyond the sub-pad 311 of its adjacent pad group in the first direction X, and that the arrangement of the second part 42 does not affect the arrangement of signal lines on the side of the pad group 30 adjacent to the second part facing the bonding area 1021.

[0077] In some embodiments, the third distance is greater than or equal to the first distance. This configuration ensures that the third portion 43 does not extend beyond the sub-pad 311 of its adjacent pad group in the first direction X, and that the arrangement of the third portion 43 does not affect the arrangement of signal lines in the pad group 30 adjacent to the third portion 43 toward the bonding area 1021.

[0078] In one embodiment, of the plurality of signal lines on the wiring substrate, at least one signal line is located on the side of the second portion 42 facing the bonding region 1021; in the first direction X, the distance between the second portion 42 and the signal line located on the side of the second portion 42 facing the bonding region 1021 is greater than or equal to 200 micrometers. Here, the distance between the second portion 42 and the signal line located on the side of the second portion 42 facing the bonding region 1021 refers to the minimum distance between the second portion 42 and the signal line located on the side of the second portion 42 facing the bonding region 1021. Figure 2 As shown, the signal lines located on the side of the second part 42 facing the bonding area 1021 include a common voltage line GND, a source power line PWR, and a source address line DI. The distance between the common voltage line GND and the second part 42 is minimal. The distance between the second part 42 and the common voltage line GND located on the side of the second part 42 facing the bonding area 1021 is d1, and d1 is greater than or equal to 200 micrometers. This configuration avoids signal crosstalk caused by the small distance between the second part 42 and the signal lines located on the side of the second part 42 facing the bonding area 1021.

[0079] In one embodiment, of the plurality of signal lines on the wiring substrate, at least one signal line is located on the side of the third portion 43 facing the bonding region 1021; in the first direction X, the distance between the third portion 43 and the signal line located on the side of the third portion 43 facing the bonding region 1021 is greater than or equal to 200 micrometers. Here, the distance between the third portion 43 and the signal line located on the side of the third portion 43 facing the bonding region 1021 refers to the minimum distance between the third portion 43 and the signal line located on the side of the third portion 43 facing the bonding region 1021. Figure 2 As shown, the signal line located on the side of the third part 43 facing the bonding area 1021 includes a driving voltage line VLED. The distance between the driving voltage line VLED and the third part 43 is d2, where d2 is greater than or equal to 200 micrometers. This configuration avoids signal crosstalk caused by the distance between the third part 43 and the signal line located on the side of the third part 43 facing the bonding area 1021 being too small.

[0080] In one embodiment, at least two sub-pads 311 within the same pad group 30 are connected via the connecting wire 60. In the second direction Y, the minimum distance between the second portion 42 and the adjacent connecting wire 60 is greater than or equal to 200 micrometers. Figure 2 As shown, in the second direction Y, the minimum distance between the second part 42 and the adjacent connecting wire 60 is d3, where d3 is greater than or equal to 200 micrometers. This configuration avoids signal crosstalk between the second part 42 and the adjacent connecting wire 60.

[0081] In one embodiment, in the second direction Y, the minimum distance between the third part 43 and the adjacent connecting wire 60 is greater than or equal to 200 micrometers. Figure 2 As shown, in the second direction Y, the minimum distance between the third part 43 and the adjacent connecting wire 60 is d4, where d4 is greater than or equal to 200 micrometers. This configuration avoids signal crosstalk between the third part 43 and the adjacent connecting wire 60.

[0082] In one embodiment, the wiring substrate further includes a reflective material layer 83 located on the side of the insulating layer 50 facing away from the substrate 10, the reflective material layer 83 covering the first opening 51. The reflective material layer 83 has an opening through which the inorganic light-emitting diode soldered to the first sub-pad group is exposed. The reflective material layer can increase the amount of light emitted by the inorganic light-emitting diode. Covering the first opening 51 with the reflective material layer can prevent water and oxygen from entering the shielded signal line 40 through the first opening 51 and causing corrosion of the shielded signal line 40, thus helping to improve the reliability of the wiring substrate. In some embodiments, the material of the reflective material layer may be a white ink, specifically including resin (e.g., epoxy resin, polytetrafluoroethylene resin), titanium dioxide (chemical formula TiO2), and organic solvents (e.g., dipropylene glycol methyl ether), etc.

[0083] In one embodiment, such as Figure 3 As shown, the wiring substrate further includes a stress matching layer 70 located between the substrate 10 and the shielded signal line 40 and each signal line. The stress matching layer 70 can reduce the stress difference between the substrate 10 and the shielded signal line 40 and each signal line, preventing film warping. The material of the stress matching layer 70 can be silicon nitride, silicon oxide, or silicon oxynitride.

[0084] This application also provides an electronic device, which includes the wiring substrate described in any of the above embodiments and electronic components connected to the pad group. Specifically, in the die bonding process, each pin of the electronic component can be bonded to each sub-pad by soldering metal S, and then in the reflow soldering process, each pin of the electronic component is fixedly connected to each sub-pad.

[0085] In one embodiment, the electronic component may include an inorganic light-emitting diode (LED) with a size on the order of hundreds of micrometers or smaller, and may also include a driver chip with a size on the order of hundreds of micrometers or smaller. The inorganic LED with a size on the order of hundreds of micrometers or smaller can be a mini LED or a micro LED. The size range of a mini LED is approximately 100 μm to 500 μm, and the size of a micro LED is less than 100 μm. The driver chip can be a chip used to provide signals to the inorganic LED to cause it to emit light.

[0086] In some embodiments, each pad group 30 includes a first sub-pad group 31 and a second sub-pad group 32. Sub-pads 311 of the first sub-pad group 31 are soldered to inorganic light-emitting diodes. Sub-pads 311 of the second sub-pad group 32 are soldered to driver chips.

[0087] In one embodiment, the electronic device can be used as a backlight for a liquid crystal display panel.

[0088] In another embodiment, the electronic device may be a liquid crystal display device, which further includes a liquid crystal panel located on the side of the electronic components away from the substrate. This liquid crystal display device can have more uniform backlight brightness and better display contrast.

[0089] In another embodiment, when the electronic device is used as a display device, each inorganic light-emitting diode is used as a sub-pixel.

[0090] This application does not impose specific limitations on the application of display devices, which can be any product or component with display function, such as televisions, laptops, tablets, wearable display devices, mobile phones, in-vehicle displays, navigation systems, e-books, digital photo frames, and advertising light boxes.

[0091] It should be noted that the dimensions of layers and regions may be exaggerated in the accompanying drawings for clarity. Furthermore, it is understood that when an element or layer is referred to as being "on" another element or layer, it can be directly on the other element, or there may be intermediate layers. Additionally, it is understood that when an element or layer is referred to as being "below" another element or layer, it can be directly below the other element, or there may be more than one intermediate layer or element. Furthermore, it is also understood that when a layer or element is referred to as being "between" two layers or two elements, it can be the only layer between the two layers or two elements, or there may be more than one intermediate layer or element. Similar reference numerals throughout indicate similar elements.

[0092] Other embodiments of this application will readily occur to those skilled in the art upon consideration of the specification and practice of the disclosure herein. This application is intended to cover any variations, uses, or adaptations of this application that follow the general principles of this application and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this application are indicated by the following claims.

[0093] It should be understood that this application is not limited to the precise structure described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this application is limited only by the appended claims.

Claims

1. A wiring substrate, characterized in that, Includes a substrate, shielded signal lines disposed on the substrate, and an insulating layer; The substrate includes a functional region; the functional region is provided with a plurality of pad groups; the plurality of pad groups are respectively arrayed along a first direction and a second direction, the second direction intersecting the first direction; The shielded signal line includes a first part that surrounds all pad groups and a second part that is connected to the first part, the second part being located between two adjacent pad groups in the second direction; The insulating layer is located on the side of the shielded signal line away from the substrate. The insulating layer has a plurality of first openings, and the orthographic projection of a second part on the substrate covers the orthographic projection of at least one of the first openings on the substrate.

2. The wiring substrate according to claim 1, characterized in that, The wiring substrate further includes a bonding area located on one side of the functional area, and the second part is located between two pad groups that are furthest from the bonding area and adjacent to each other in the second direction among a plurality of pad groups arranged along the first direction.

3. The wiring substrate according to claim 2, characterized in that, The first part and the second part form an integral structure.

4. The wiring substrate according to claim 2, characterized in that, The line width of the first part is smaller than the dimension of the second part in the first direction.

5. The wiring substrate according to claim 1, characterized in that, The orthographic projection of the second part on the substrate covers the orthographic projection of at least two first openings on the substrate, and the at least two first openings are spaced apart in the first direction.

6. The wiring substrate according to claim 1, characterized in that, The pad group includes at least two sub-pads; the insulating layer is also provided with a plurality of second openings, one second opening exposing one of the sub-pads; the total area of ​​each of the first openings corresponding to a second part is greater than the total area of ​​each of the second openings corresponding to an adjacent pad group.

7. The wiring substrate according to claim 1, characterized in that, The shielded signal line also includes a third part connected to the first part; The third part is located on the side of the pad group at the corner of the functional area that is not adjacent to other pad groups in the second direction.

8. The wiring substrate according to claim 7, characterized in that, The first part and the third part form an integral structure.

9. The wiring substrate according to claim 7, characterized in that, The line width of the first part is smaller than the dimension of the third part in the first direction; and / or, the dimension of the third part in the second direction is smaller than the dimension of the second part in the second direction.

10. The wiring substrate according to claim 7, characterized in that, The wiring substrate further includes an insulating layer located on the side of the shielded signal line away from the substrate. The insulating layer has a plurality of first openings, and the orthographic projection of one of the third parts on the substrate covers the orthographic projection of at least one of the first openings on the substrate.

11. The wiring substrate according to claim 10, characterized in that, The orthographic projection of one of the third parts on the substrate covers the orthographic projections of at least two first openings on the substrate; the at least two first openings are spaced apart in the first direction.

12. The wiring substrate according to claim 10, characterized in that, The pad group includes at least two sub-pads; the insulating layer is also provided with a plurality of second openings, one of the second openings exposing one of the sub-pads; The total area of ​​each first opening corresponding to a third part is greater than the total area of ​​each second opening corresponding to an adjacent pad group.

13. The wiring substrate according to claim 10, characterized in that, The wiring substrate further includes a bonding area located on one side of the functional area; among the multiple second openings corresponding to the pad group furthest from the bonding area among the multiple pad groups arranged along the first direction, the distance from the second opening with the smallest distance from the bonding area to the bonding area is the first distance, the distance from the edge of the second part facing the bonding area to the bonding area to the bonding area is the second distance, and the distance from the edge of the third part facing the bonding area to the bonding area to the bonding area is the third distance; The second distance is greater than or equal to the first distance; and / or, the third distance is greater than or equal to the first distance.

14. The wiring substrate according to claim 1 or 10, characterized in that, The insulating layer includes an inorganic layer.

15. The wiring substrate according to claim 1 or 10, characterized in that, The wiring substrate further includes a reflective material layer located on the side of the insulating layer opposite to the substrate, the reflective material layer covering the first opening.

16. The wiring substrate according to claim 7, characterized in that, The wiring substrate also includes multiple signal lines disposed on the substrate, and the wiring substrate also includes a bonding area located on one side of the functional area; Of the plurality of signal lines, at least one signal line is located on the side of the second part facing the bonding area; in the first direction, the distance between the second part and the signal line located on the side of the second part facing the bonding area is greater than or equal to 200 micrometers; And / or, of the plurality of signal lines, at least one signal line is located on the side of the third part facing the bonding area; in the first direction, the distance between the third part and the signal line located on the side of the third part facing the bonding area is greater than or equal to 200 micrometers.

17. The wiring substrate according to claim 7, characterized in that, The pad group includes multiple sub-pads, and the wiring substrate further includes connecting wires. At least two sub-pads in the same pad group are connected by the connecting wires. In the second direction, the minimum distance between the second part and the adjacent connecting wire is greater than or equal to 200 micrometers. And / or, in the second direction, the minimum distance between the third part and the adjacent connecting wire is greater than or equal to 200 micrometers.

18. The wiring substrate according to claim 1, characterized in that, The pad group includes multiple sub-pads, which are arranged on the same layer as the shielded signal line.

19. An electronic device, characterized in that, The electronic device includes a wiring substrate as described in any one of claims 1 to 18 and electronic components connected to the pad assembly.

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