Display device

Abstract

A display device is disclosed. The display device includes display modules. Each of the display modules includes a display panel including inorganic light emitting devices arranged in row lines and sub-pixel circuits respectively corresponding to the inorganic light emitting devices, and a driving unit driving the sub-pixel circuits in order of the row lines based on a start signal provided from a timing controller, wherein the timing controller provides a first start signal to the driving unit of a first display module to control the inorganic light emitting devices to sequentially emit light from a first row line to a last row line, and provides a second start signal to the driving unit of a second display module to control the inorganic light emitting devices to sequentially emit light after an emission sequence of the inorganic light emitting devices included in the last row line of the first display module.

Description

Technical Field

[0001] This disclosure relates to a display device, and more specifically, to a display device comprising a pixel array including self-emissive elements. Background Technology

[0002] Inorganic light-emitting elements, such as red light-emitting diodes (LEDs), green LEDs, and blue LEDs (hereinafter, LEDs refer to inorganic light-emitting elements), can be driven as sub-pixels, and the grayscale of the sub-pixels can be controlled by pulse amplitude modulation (PAM) driving methods.

[0003] In the PAM driving method, both the wavelength and brightness (i.e., grayscale) of the emitted light can be changed based on the amplitude of the driving current, resulting in a decrease in the color reproducibility of the image. Figure 1 The wavelength variation is shown based on the amplitude of the drive current flowing through the blue, green, and red LEDs.

[0004] Therefore, a method is needed to drive a self-emissive display panel with improved color reproduction. At this point, issues such as power consumption and brightness uniformity need to be considered.

[0005] When configuring a modular display panel by combining multiple display modules, the potential image distortion at the boundary between the upper and lower display modules should be taken into account. Summary of the Invention

[0006] Technical issues

[0007] One or more embodiments provide a display device and a driving method thereof, the display device being able to prevent the wavelength of light emitted from an inorganic light-emitting element from changing according to grayscale.

[0008] One or more embodiments provide a display device and a driving method thereof, the display device being able to compensate for blemishes that may appear in an image due to threshold voltage differences between driving transistors, and to correct colors.

[0009] One or more embodiments provide a display device including display modules or a display device including a modular display panel composed of multiple display modules and a driving method thereof, the display device being able to compensate for blemishes that may appear in an image due to threshold voltage differences between driving transistors and to correct colors.

[0010] One or more embodiments provide a display device and a driving method thereof that can reduce the power consumption when driving a display panel.

[0011] One or more embodiments provide a display device and a method for driving the display device, the display device being able to compensate for the effect of driving voltage drops generated differently for each location of the display panel on the process of setting data voltages.

[0012] One or more embodiments provide a display device with optimized driving circuitry and a driving method thereof, the display device being able to stably and effectively drive inorganic light-emitting elements.

[0013] One or more embodiments provide a display device and a driving method thereof, which, when a modular display panel is formed by combining multiple display modules, can eliminate image distortion that may occur at the boundary between the upper and lower display modules.

[0014] Technical solution

[0015] According to one aspect of this disclosure, a display device includes: a modular display panel comprising a plurality of display modules arranged in a matrix; and a timing controller. Each of the plurality of display modules includes: a display panel including a pixel array of pixels arranged in multiple row lines and sub-pixel circuitry, each pixel comprising a plurality of inorganic light-emitting elements, the sub-pixel circuitry corresponding to the inorganic light-emitting elements of the pixel array; and a driver configured to drive the sub-pixel circuitry sequentially along the multiple row lines based on a start signal provided from the timing controller. The timing controller is further configured to: provide a first start signal to a driver of a first display module to control the inorganic light-emitting elements of the first display module to emit light sequentially from a first row line to a last row line; and provide a second start signal to a driver of a second display module disposed adjacent to the bottom of the first display module to control the inorganic light-emitting elements of the second display module to emit light sequentially after the emission sequence of the inorganic light-emitting elements included in the last row line of the first display module.

[0016] The driver can also be configured to provide gate signals to the sub-pixel circuits in the order of multiple row lines based on a start signal, so as to drive the sub-pixel circuits in the order of multiple row lines, and the gate signals may include a scan signal configured to provide an image data voltage to the sub-pixel circuits and an emission signal configured to control the emission of inorganic light-emitting elements of the pixel array based on the image data voltage.

[0017] Relative to an image frame, for each of multiple line lines, the sub-pixel circuit can be driven in the order of data setting segments and multiple emission segments, and the driver can also be configured to: provide a scan signal to the sub-pixel circuit of the corresponding line line during the data setting segment of the corresponding line line, and apply an emission signal to the sub-pixel circuit of the corresponding line line during each of the multiple emission segments of the corresponding line line.

[0018] The first transmission segment in a plurality of transmission segments can be adjacent to the data setting segment in time, and the plurality of transmission segments can have a preset time interval between each other.

[0019] The image data voltage may include a constant current generator data voltage and a pulse width modulation (PWM) data voltage. Each of the sub-pixel circuits may include: a constant current generator circuit, including a first driving transistor, and configured to provide a constant current to the corresponding inorganic light-emitting element based on the constant current generator data voltage; and a PWM circuit, including a second driving transistor, and configured to control the timing of providing the constant current to the corresponding inorganic light-emitting element based on the PWM data voltage.

[0020] The constant current generator circuit can also be configured to provide a constant current to the corresponding inorganic light-emitting element in each of the plurality of emission segments based on a first voltage applied to the gate terminal of the first driving transistor, and the first voltage can be based on the constant current generator data voltage and the threshold voltage of the first driving transistor.

[0021] The constant current generator circuit may include: a first transistor, including a source terminal to which the constant current generator data voltage is applied and a drain terminal connected to the source terminal of the first driving transistor; and a second transistor, including a source terminal connected to the drain terminal of the first driving transistor and a drain terminal connected to the gate terminal of the first driving transistor. The constant current generator circuit may also be configured to: in a data setting segment, based on the simultaneous conduction of the first driving transistor and the first and second transistors, apply a voltage to the gate terminal of the first driving transistor, the voltage being the sum of the constant current generator data voltage and the threshold voltage of the first driving transistor.

[0022] The PWM circuit can be configured to control the duration of a constant current supplied to the corresponding inorganic light-emitting element in each of the plurality of emitter segments based on a second voltage applied to the gate terminal of the second driving transistor, and the second voltage can be based on the threshold voltage of the second driving transistor, the PWM data voltage, and a scan voltage scanned between the two voltages.

[0023] The PWM circuit may include a first capacitor having a first end connected to the source terminal of the second driving transistor and a second end connected to the gate terminal of the second driving transistor. When a constant current generator data voltage is applied to the drain terminal of the second driving transistor, the second driving transistor can operate as a source follower. The threshold voltage of the second driving transistor can be obtained at the source terminal of the second driving transistor when the second driving transistor operates as a source follower and can be coupled to the gate terminal of the second driving transistor through the first capacitor.

[0024] The PWM circuit may include a second capacitor having a first end connected to the gate terminal of a second driving transistor and a second end to which a PWM data voltage and a scan voltage are applied. The PWM data voltage may be applied to the second end of the second capacitor in a data setting segment, and based on the scan voltage being applied to the second end of the second capacitor in each of a plurality of emitter segments, the PWM data voltage may be coupled to the gate terminal of the second driving transistor together with the scan voltage through the second capacitor.

[0025] The drain terminal of the second driving transistor can be connected to the source terminal of the first driving transistor. The constant current generator circuit can be configured to provide a constant current to the corresponding inorganic light-emitting element in each of the plurality of emitter segments when a driving voltage is applied to the source terminal of the first driving transistor. The PWM circuit can be configured to apply a driving voltage to the source terminal of the first driving transistor in each of the plurality of emitter segments during the period when the second driving transistor is turned on, while the second voltage varies according to the scan voltage. The period when the second driving transistor is turned on can be based on the amplitude of the PWM data voltage.

[0026] The scan voltage can be a part of the input scan signal based on the transmit signal selection. The input scan signal can have a voltage that changes linearly and repeatedly from a first voltage to a second voltage, and the input scan signal can be applied together to each of the sub-pixel circuits in the display panel.

[0027] In each of the multiple transmit sections, the scan voltage can scan the voltage between the first voltage and the second voltage once, and the starting voltage for the scan voltage to begin scanning can vary according to the row line.

[0028] The PWM circuit can be configured to control the duration of a constant current supplied to the corresponding inorganic light-emitting element in each of the plurality of emitter segments based on a third voltage applied to the gate terminal of the second driving transistor, and the third voltage can be based on a PWM data voltage that compensates for the threshold voltage of the second driving transistor and a scan voltage that is scanned between the two voltages.

[0029] Multiple sub-pixel circuits can be driven by a first driving voltage in each of multiple emission segments, and can be driven by a second driving voltage separate from the first driving voltage in the data setting segment.

[0030] The sub-pixel circuit is driven by a first driving voltage in each of the plurality of emission sections, and by a second driving voltage separate from the first driving voltage in the data setting section.

[0031] Invention Effects

[0032] According to various embodiments, by driving the inorganic light-emitting element with PWM in an AM matrix manner, the phenomenon that the wavelength of the light emitted from the inorganic light-emitting element changes according to the gray level can be prevented.

[0033] Furthermore, it can compensate for blemishes that may appear in the image due to variations in the threshold voltage of the driving transistor. Additionally, it facilitates color correction.

[0034] Furthermore, a display device including a display module or a display device including a modular display panel can facilitate spot compensation or color correction of the display panel, wherein the modular display panel includes multiple display modules.

[0035] In addition, by driving the display panel to make the inorganic light-emitting elements emit light sequentially in the order of the rows, the instantaneous peak power consumption can be reduced.

[0036] In addition, it can compensate for the impact of the driving voltage drop generated differently for each position of the display panel on the process of setting the data voltage.

[0037] Optimized driving circuits can be designed, and inorganic light-emitting elements can be driven stably and effectively.

[0038] Furthermore, when a modular display panel is configured by combining multiple display modules, image distortion that may occur at the boundary between the upper and lower display modules can be eliminated. Attached Figure Description

[0039] The above and other aspects, features, and advantages of certain embodiments of this disclosure will become clearer from the following description taken in conjunction with the accompanying drawings, in which:

[0040] Figure 1 It is a graph showing the wavelength variation based on the amplitude of the drive current flowing through the blue light-emitting diode (LED), green LED, and red LED;

[0041] Figure 2 The pixel structure of a display panel according to an embodiment is shown;

[0042] Figure 3a This is a conceptual diagram illustrating a driving method for a prior art display panel;

[0043] Figure 3b This is a conceptual diagram illustrating a driving method for a display panel according to an embodiment;

[0044] Figure 3c This is a conceptual diagram illustrating a driving method for a display panel according to an embodiment;

[0045] Figure 4 This is a block diagram illustrating a display module according to an embodiment;

[0046] Figure 5a This is a cross-sectional view of the display panel according to an embodiment;

[0047] Figure 5b This is a cross-sectional view of the display panel according to an embodiment;

[0048] Figure 5c This is a plan view of the TFT layer according to an embodiment;

[0049] Figure 6a This is a diagram illustrating a progressive driving method for a display panel according to an embodiment;

[0050] Figure 6b This is a diagram illustrating a progressive driving method for a display panel according to an embodiment;

[0051] Figure 7 This is a detailed block diagram of the display module according to an embodiment;

[0052] Figure 8 This is a schematic block diagram of the sub-pixel circuit according to an embodiment;

[0053] Figure 9a This is a detailed circuit diagram of the sub-pixel circuit according to an embodiment;

[0054] Figure 9b According to the embodiment, during the image frame time and blanking interval, it is used to drive including Figure 9a Timing diagram of various signals of the display panel of the sub-pixel circuit;

[0055] Figure 10a The operation of the sub-pixel circuit according to an embodiment based on Vini(n) and VST(n) in the scan signal is shown;

[0056] Figure 10b This is a diagram illustrating the operation of the sub-pixel circuit according to SP(n) in the scan signal according to an embodiment;

[0057] Figure 10c This is a diagram illustrating the operation of the sub-pixel circuit according to Vcomp(n) in the scan signal according to an embodiment;

[0058] Figure 10d This is a diagram illustrating the operation of the sub-pixel circuit according to the transmitted signal Emi(n) according to an embodiment;

[0059] Figure 11a It is shown that, according to an embodiment, it has Figure 9a A diagram showing the PWM operation of the sub-pixel circuit configuration shown;

[0060] Figure 11b It is shown that, according to an embodiment, it has Figure 9aA diagram showing the PWM operation of the sub-pixel circuit configuration shown;

[0061] Figure 11c It is shown that, according to an embodiment, it has Figure 9a A diagram showing the PWM operation of the sub-pixel circuit configuration shown;

[0062] Figure 12a This is a detailed circuit diagram of a sub-pixel circuit according to another embodiment;

[0063] Figure 12b According to the embodiment, during the image frame time and blanking interval, it is used to drive including Figure 12a Timing diagram of various signals of the display panel of the sub-pixel circuit;

[0064] Figure 13a This is a diagram illustrating the operation of the sub-pixel circuit according to an embodiment based on Vini(n) and VST(n) in the scan signal;

[0065] Figure 13b The operation of the sub-pixel circuit according to an embodiment based on SCCG(n) and Vini2(n) in the scan signal is shown;

[0066] Figure 13c This is a diagram illustrating the operation of the sub-pixel circuit according to Vcomp(n) in the scan signal according to an embodiment;

[0067] Figure 13d This is a diagram illustrating the operation of the sub-pixel circuit according to the SPWM(n) in the scan signal according to an embodiment;

[0068] Figure 13e The operation of the sub-pixel circuit based on the transmitted signal Emi(n) according to an embodiment is shown;

[0069] Figure 14a It is shown that, according to an embodiment, it has Figure 12a A diagram showing the PWM operation of the sub-pixel circuit configuration shown;

[0070] Figure 14b It is shown that, according to an embodiment, it has Figure 12a A diagram showing the PWM operation of the sub-pixel circuit configuration shown;

[0071] Figure 14c It is shown that, according to an embodiment, it has Figure 12a A diagram showing the PWM operation of the sub-pixel circuit configuration shown;

[0072] Figure 15a This is a detailed circuit diagram of a sub-pixel circuit according to another embodiment;

[0073] Figure 15b According to the embodiment, during the image frame time and blanking interval, it is used to drive including Figure 15a Timing diagram of various signals of the display panel of the sub-pixel circuit;

[0074] Figure 16a The operation of the sub-pixel circuit according to an embodiment based on Vini(n) and VST(n) in the scan signal is shown;

[0075] Figure 16b This is a diagram illustrating the operation of the sub-pixel circuit based on SP(n) in the scan signal according to an embodiment;

[0076] Figure 16c This is a diagram illustrating the operation of the sub-pixel circuit according to the transmitted signal Emi(n) according to an embodiment;

[0077] Figure 17a It is shown that, according to an embodiment, it has Figure 15a A diagram showing the PWM operation of the sub-pixel circuit configuration shown;

[0078] Figure 17b It is shown that, according to an embodiment, it has Figure 15a A diagram showing the PWM operation of the sub-pixel circuit configuration shown;

[0079] Figure 17c It is shown that, according to an embodiment, it has Figure 15a A diagram showing the PWM operation of the sub-pixel circuit configuration shown;

[0080] Figure 18 This is a schematic diagram illustrating the configuration of a display device according to an embodiment;

[0081] Figure 19a The method by which the data setting segment and the transmission segment are performed when a modular display panel is driven in a simultaneous scanning manner, according to an embodiment, is shown.

[0082] Figure 19b The method by which the data setting segment and the transmission segment are performed when a modular display panel is driven in a high-speed continuous scan mode, according to an embodiment, is shown.

[0083] Figure 20 This is a block diagram of a display device according to an embodiment;

[0084] Figure 21a This is a block diagram illustrating a method for driving a gate driver according to an embodiment; and

[0085] Figure 21b The setting according to the embodiment is shown. Figure 18 The display module in the first column of multiple display modules. Detailed Implementation

[0086] Various embodiments will be described more fully below with reference to the accompanying drawings. In the drawings, similar reference numerals always denote similar elements. As used herein, the terms “first” or “first” and “second” or “second” may be used with respect to the corresponding components, regardless of importance or order, and are used to distinguish one component from another without limiting the components. Expressions such as “at least one of…” modify the entire list of components when preceding the list of components, rather than individual elements in the list. For example, the expression “at least one of a, b, and c” should be understood to include only a, only b, only c, both a and b, both a and c, both b and c, or all of a, b, and c.

[0087] The terminology used in this disclosure is for describing embodiments and is not intended to limit and / or restrict this disclosure to the described embodiments. Furthermore, any singular representation of a configuration used in this disclosure includes multiple representations, except where the singular representation refers only to a single value.

[0088] It should be understood that terms such as “including,” “comprising,” or “containing” may be used to indicate the presence of a feature, quantity, step, operation, element, component, or combination thereof, without excluding the possibility of the presence or addition of one or more other features, quantities, steps, operations, elements, components, or combinations thereof.

[0089] If it is described that a certain element (e.g., the first element) is “connected” to another element (e.g., the second element), it should be understood that the first element may be directly connected to the second element, or may be connected to the second element through another element (e.g., the third element).

[0090] On the other hand, if it is described that a certain element (e.g., the first element) is "directly connected" to another element (e.g., the second element), it can be understood that there is no element (e.g., the third element) between the first element and the second element.

[0091] Unless otherwise defined, the terms used herein shall be interpreted in the sense that are known to those skilled in the art.

[0092] Figure 1 The wavelength variation is shown based on the amplitude of the drive current flowing through the blue, green, and red LEDs.

[0093] Figure 2 The pixel structure of a display panel according to an embodiment is shown.

[0094] refer to Figure 2The display panel 100 includes a plurality of pixels 10 arranged or configured in a matrix, which may be referred to as a pixel array.

[0095] A pixel array consists of multiple row lines or multiple column lines. Row lines can also be called horizontal lines, scan lines, or gate lines, while column lines can also be called vertical lines or data lines.

[0096] According to the example, terms such as row line, column line, horizontal line and vertical line can be used as words to refer to lines formed by pixels on a pixel array, and terms scan line, gate line and data line can be used as words to refer to the actual wiring on the display panel 100 to which data or signals are transmitted.

[0097] Each pixel 10 of the pixel array may include three types of subpixels, including red (R) subpixel 20-1, green (G) subpixel 20-2 and blue (B) subpixel 20-3.

[0098] Each pixel 10 may include multiple inorganic light-emitting elements that respectively constitute multiple sub-pixels 20-1, 20-2 and 20-3.

[0099] For example, each pixel 10 may include three types of inorganic light-emitting elements, such as the R inorganic light-emitting element constituting the R sub-pixel 20-1, the G inorganic light-emitting element constituting the G sub-pixel 20-2, and the B inorganic light-emitting element constituting the B sub-pixel 20-3.

[0100] Each pixel 10 may include three blue inorganic light-emitting elements. In this example, a color filter for achieving R, G, or B colors may be provided on each inorganic light-emitting element. The color filter may be a quantum dot (QD) color filter, but the embodiment is not limited to this.

[0101] Sub-pixel circuits for driving inorganic light-emitting elements can be set on the display panel 100 for each inorganic light-emitting element.

[0102] Each sub-pixel circuit can provide driving current to the corresponding inorganic light-emitting element based on the image data voltage supplied from the outside.

[0103] In detail, the image data voltage includes a constant current generator (CCG) data voltage and a pulse width modulation (PWM) data voltage. By providing a drive current corresponding to the amplitude of the CCG data voltage to the inorganic light-emitting element within the time corresponding to the PWM data voltage, each sub-pixel circuit can represent the grayscale of the image. This will be described in detail later.

[0104] The sub-pixel circuits included in each row line of the display panel 100 can be driven in the order of "setting (or programming) the image data voltage" and "providing drive current based on the set image data voltage".

[0105] According to an embodiment, the sub-pixel circuits included in each row line of the display panel 100 can be driven sequentially in the order of the row lines.

[0106] For example, the image data voltage setting operation of the sub-pixel circuit included in one row line (e.g., the first row line) and the image data voltage setting operation of the sub-pixel circuit included in the next row line (e.g., the second row line) can be performed sequentially according to the row line order. Furthermore, the drive current supply operation of the sub-pixel circuit included in one row line (e.g., the first row line) and the drive current supply operation of the sub-pixel circuit included in the next row line (e.g., the second row line) can also be performed sequentially according to the row line order.

[0107] refer to Figure 2 In a pixel region, subpixels 20-1 to 20-3 are arranged in an inverted L-shape. However, the embodiments are not limited to this, and the R, G, and B subpixels 20-1 to 20-3 can be arranged in rows within the pixel region, and can be arranged in various shapes according to the embodiments.

[0108] refer to Figure 2 As an example, three types of subpixels can form a pixel. However, according to embodiments, a pixel can include other numbers of subpixels. For example, a pixel can include four types of subpixels such as R, G, B, and white (W), or any other number of subpixels.

[0109] Figure 3a This is a conceptual diagram illustrating a driving method for a prior art display panel; and Figure 3b and Figure 3c This is a conceptual diagram illustrating a driving method for a display panel according to an embodiment.

[0110] Figures 3a to 3c This illustrates a method for driving a display panel within one image frame time. (Reference) Figures 3a to 3c The vertical axis represents the row lines of the display panel 100, and the horizontal axis represents time. The data setting section can represent the driving period of the display panel 100, wherein image data voltage is set for the sub-pixel circuits included in each row line, and the emission section can represent the driving period of the display panel 100, wherein the sub-pixel circuits included in each row line provide driving current to the inorganic light-emitting elements based on the image data voltage set in the data setting section. The inorganic light-emitting elements emit light in the emission section according to the driving current.

[0111] refer to Figure 3a In the prior art, after setting the image data voltage of all the rows of the display panel in the order of the rows, the transmission segments of all the rows are simultaneously and together.

[0112] In this example, all row lines of the display panel emit light simultaneously during the emission segment, requiring high peak current. Therefore, there is an issue of increased peak power consumption required by the product. As peak power consumption increases, the capacity of power supply devices such as switch-mode power supplies (SMPS) installed in the product increases, leading to increased cost and size, which imposes design limitations.

[0113] Conversely, according to the embodiment, the data setting segments and transmission segments (specifically, multiple transmission segments) of the row lines can be sequentially arranged in the order of the row lines.

[0114] Figure 3b and Figure 3c Two embodiments are shown, in which the data setting section and the transmission section are sequentially performed in the order of the row lines.

[0115] refer to Figure 3b The data setting for all line segments can be performed within one frame. (Reference) Figure 3c The data setup segments for all line lines can be performed in a much shorter time than a frame. In both embodiments, both the data setup segments and the transmission segments are performed sequentially in the order of the line lines.

[0116] In the following text, such as Figure 3b and Figure 3c As shown, the driving method that sequentially executes the data setting segment and the transmission segment according to the row line order is called the "progressive driving method," to distinguish it from... Figure 3a Batch-driven methods.

[0117] In the case of the progressive driving method, the required peak current can be reduced because the number of row lines emitting light simultaneously is reduced compared to existing technologies, and thus the peak power consumption can be reduced.

[0118] As described above, according to the embodiment, the display panel 100 can be driven by an active matrix (AM) method, and each sub-pixel can represent the grayscale of the image in a PWM scheme. Therefore, unlike existing technologies that represent grayscale in a PAM method, the problem of the wavelength of light emitted from the inorganic light-emitting element changing according to grayscale can be prevented. Furthermore, by driving the display panel 100 so that the sub-pixels emit light sequentially in the order of the row lines, instantaneous peak power consumption can be reduced.

[0119] Figure 4 This is a block diagram illustrating a display module according to an embodiment. (Reference) Figure 4 The display module 1000 includes a display panel 100 and a driver 500.

[0120] Driver 500 drives display panel 100. Driver 500 can provide various control signals, data signals, drive voltages, etc. to display panel 100 to drive display panel 100.

[0121] As described above, according to the embodiment, the display panel 100 can be driven in the order of row lines. For this purpose, the driver 500 may include a gate driver for driving pixels on the pixel array based on row lines. The gate driver can drive pixels row by row by providing a scan signal (e.g., VST(n), SP(n), SCCG(n), SPWM(n), Vcomp(n), Vini(n), Vini2(n)) and an emit signal (e.g., Emi(n)) for each row line. In this case, the gate driver providing the scan signal can be referred to as a scan driver, as opposed to the gate driver providing the emit signal, which is referred to as an emitter driver.

[0122] The driver 500 may also include a data driver (or source driver) for providing PWM data voltages (e.g., VPWM_R / G / B) to each pixel (or each sub-pixel) of the display panel 100.

[0123] The driver 500 may include demultiplexer circuitry for selecting each of the plurality of sub-pixels 20-1 to 20-3 included in a pixel 10.

[0124] The driver 500 may include a power integrated circuit (IC) (or a DC voltage supply circuit) for supplying various DC voltages (e.g., a first drive voltage (VDD_PAM), a second drive voltage (VDD_PWM), a ground voltage (VSS), a reference voltage (Vref), etc.) or constant current generator data voltages (e.g., VCCG_R / G / B) to each sub-pixel circuit included in the display panel 100.

[0125] The driver 500 may include a level shifter for shifting the levels of various signals provided by the timing controller (TCON) to levels used in the driver (e.g., a gate driver or a data driver) or levels used in the display panel 100.

[0126] A level shifter can shift the level of the start signal VST or various clock signals provided from TCON to the gate driver. It should be noted that the start signal VST is different from VST(n), which is one of the scan signals described above. VST(n) is a scan signal applied from the gate driver to the sub-pixel circuit, while VST is a control signal provided from TCON to the gate driver via a level shifter. Details of VST(n) and VST will be described below.

[0127] The level shifter can shift the level of the scan signal (scan) or test signal (test) generated in TCON and provide the shifted signal to the sub-pixel circuit of the display panel 100. A detailed description of the test signal or scan signal will be described later.

[0128] According to an embodiment, at least some of the various components of the driver 500 described above can be mounted on a printed circuit board (PCB) separate from the display panel 100, and can be connected to the sub-pixel circuit formed on the thin-film transistor (TFT) layer of the display panel 100 via glass-on-glass (FOG) wiring.

[0129] At least some of the aforementioned components can be arranged on a chip-on-film (COF) formed on a thin film and can be connected to a sub-pixel circuit formed on a TFT layer via FOG wiring, the TFT layer being formed on the display panel 100.

[0130] At least some of the above-mentioned components can be arranged in the form of a COG (i.e., arranged on the rear surface of the glass substrate (described below) of the display panel 100 (the side on which the TFT layer is formed is opposite to the glass substrate)) and can be connected to the sub-pixel circuit formed on the TFT layer of the display panel 100 by connection wiring.

[0131] At least some of the above-mentioned components may be formed in the TFT layer together with the sub-pixel circuit formed in the TFT layer of the display panel 100, and may be connected to the sub-pixel circuit.

[0132] For example, among the various components described above, the gate driver circuit and the demultiplexer circuit can be formed in the TFT layer of the display panel 100, the data driver can be arranged on the rear surface of the glass substrate of the display panel 100, and the level shifter can be arranged on the thin film in COF format, and the power IC and the timing controller (TCON) can be arranged on a separate external PCB, but the embodiments are not limited thereto.

[0133] The driver 500 can drive the display panel 100 in a progressive driving manner. During the data setting phase, the driver 500 can set the image data voltage of the sub-pixel circuit of the display panel 100 in the order of the row lines, and during the emission phase, it can drive the sub-pixel circuit so that the pixels of the pixel array emit light in the order of the row lines based on the set image data voltage.

[0134] The display panel 100 may include, for example, Figure 2 The pixel array shown can display an image corresponding to the applied image data voltage.

[0135] Each sub-pixel circuit included in the display panel 100 can provide a driving current to the corresponding inorganic light-emitting element, wherein the amplitude and driving time (or pulse width) of the driving current are controlled based on the image data voltage.

[0136] The inorganic light-emitting elements constituting the pixel array can emit light according to the driving current provided from the corresponding sub-pixel circuit, thus enabling the display of images on the display panel 100.

[0137] Figure 5a This is a cross-sectional view of the display panel 100 according to an embodiment. (See reference) Figure 5a For simplicity, only one pixel included in the display panel 100 is shown.

[0138] refer to Figure 5a The display panel 100 may include a glass substrate 80, a TFT layer 70, and inorganic light-emitting elements R 120-1, G120-2, and B 120-3. In this example, the sub-pixel circuit 110 may be implemented as a thin-film transistor (TFT) and may be included in the TFT layer 70 on the glass substrate 80.

[0139] Each of the inorganic light-emitting elements R 120-1, G 120-2 and B 120-3 can be mounted on the TFT layer 70 so as to be electrically connected to the corresponding sub-pixel circuit 110 to form the aforementioned sub-pixel.

[0140] For each inorganic light-emitting element 120-1, 120-2, and 120-3, there may be a sub-pixel circuit 110 for providing driving current to the inorganic light-emitting elements 120-1, 120-2, and 120-3, and each of the inorganic light-emitting elements 120-1, 120-2, and 120-3 may be mounted or arranged on the TFT layer 70 to be electrically connected to the corresponding sub-pixel circuit 110.

[0141] refer to Figure 5a The inorganic light-emitting elements R 120-1, G 120-2, and B 120-3 are flip-chip micro LEDs. However, the embodiments are not limited to this, and according to the embodiments, the inorganic light-emitting elements R 120-1, G 120-2, and B 120-3 can be horizontal or vertical micro LEDs.

[0142] Figure 5b This is a cross-sectional view of the display panel 100 according to an embodiment.

[0143] refer to Figure 5bThe display panel 100 may include a TFT layer 70 formed on one surface of a glass substrate 80, inorganic light-emitting elements R 120-1, G120-2, B 120-3 mounted on the TFT layer 70, a driver 500, and connection wiring 90 for electrically connecting the sub-pixel circuit 110 and the driver 500 formed on the TFT layer 70.

[0144] As described above, according to the embodiment, at least some of the various components that may be included in the driver 500 may be disposed on the rear surface of the glass substrate 80 and may be connected to the sub-pixel circuit 110 formed in the TFT layer 70 via the connection wiring 90.

[0145] refer to Figure 5b The sub-pixel circuit 110 included in the TFT layer 70 is electrically connected to the driver 500 (specifically, at least some of the various components described above) via connection wiring 90 formed at the edge (or side) of the TFT panel (hereinafter, the combination of the TFT layer 70 and the glass substrate 80 will be referred to as the TFT panel).

[0146] The reason why the sub-pixel circuit 110 and the driving unit 500 are connected by the connection wiring 90 formed in the edge region of the display panel 100 is that when the sub-pixel circuit 110 and the driver 500 are connected by forming a hole through the glass substrate 80, problems such as cracks may occur in the glass substrate 80 due to the temperature difference between the process of manufacturing the TFT panels 70 and 80 and the process of filling the hole with conductive material.

[0147] As described above, according to another embodiment, at least some of the various components that may be included in the driver 500 may be formed on the TFT layer together with the sub-pixel circuit to be connected to the sub-pixel circuit. Figure 5c Such an embodiment is shown.

[0148] Figure 5c This is a plan view of the TFT layer 70 according to an embodiment. (Reference) Figure 5c In the TFT layer 70, there is a remaining region 11 other than the area occupied by a pixel 10 (there is a sub-pixel circuit 110 corresponding to each of the R sub-pixels, G sub-pixels and B sub-pixels included in the pixel 10 in this region), and some of the above-mentioned components may be formed in the remaining region 11.

[0149] Figure 5c This is shown as implementation in the remaining region 11 of the TFT layer 70. Figure 5c An example of a gate driver. As described above, the structure in which the gate driver is formed in the TFT layer 70 can be referred to as a gate-in-panel (GIP) structure, but the name is not limited thereto. Furthermore, the location of the gate driver formed on the TFT layer 70 is not limited to... Figure 5c The location shown.

[0150] Figure 5c This is merely an example, and components that may be included in the remaining area 11 of the TFT layer 70 are not limited to the gate driver. According to embodiments, the TFT layer 70 may also include demultiplexing circuitry for selecting R sub-pixels, G sub-pixels, and B sub-pixels, and electrostatic discharge (ESD) protection circuitry for protecting the sub-pixel circuitry 110 from electrostatic effects, etc.

[0151] It has been described that the substrate on which the TFT layer 70 is formed is a glass substrate 80, but the embodiments are not limited thereto. For example, the TFT layer 70 may be formed on a synthetic resin substrate. In this example, the sub-pixel circuit 100 and the driver 500 of the TFT layer 70 may be connected through holes passing through the synthetic resin substrate.

[0152] As an example, a sub-pixel circuit 110 is described implemented in TFT layer 70. However, the embodiments are not limited to this. That is, according to another embodiment, the sub-pixel circuit 110 can be implemented as a pixel circuit chip in the form of an ultra-small micro-IC without using TFT layer 70. In this case, the sub-pixel circuit 110 can be implemented on a sub-pixel or pixel-by-pixel basis. The pixel circuit chip can be mounted on a substrate. In this example, the location where the sub-pixel circuit chip is mounted can be, for example, the periphery of the corresponding inorganic light-emitting element 120, but the embodiments are not limited to this.

[0153] It has been described that the gate driver is formed in the TFT layer 70, but the embodiments are not limited thereto. According to another embodiment, the gate driver can be implemented as a gate driver chip in the form of an ultra-small micro-IC and can be mounted on the TFT layer 70.

[0154] In various embodiments, the TFTs constituting the TFT layer (or TFT panel) are not limited to a specific structure or type. The TFTs listed in the various examples of this disclosure can be implemented as low-temperature polycrystalline silicon (LTPS) TFTs, oxide TFTs, polycrystalline silicon or monocrystalline silicon TFTs, organic TFTs, graphene TFTs, etc., and can be implemented using only P-type (or N-type) MOSFETs in Si wafer CMOS processes.

[0155] Figure 6a and Figure 6b This is a diagram illustrating a progressive driving method for a display panel 100 according to various embodiments. Figure 6a Corresponding to Figure 3b ,and Figure 6b Corresponding to Figure 3c .

[0156] Figure 6aA conceptual driving method for a display panel 100 used for three consecutive image frames is illustrated. (Reference) Figure 6a The vertical axis represents the row lines of the display panel 100, while the horizontal axis represents time.

[0157] refer to Figure 6a The display panel 100 includes 312 row lines and performs four emission segments 62-1 to 62-4 based on the image data voltage set in the data setting segment 61. However, the number of row lines or emission segments is not limited to this.

[0158] More specifically, see reference Figure 6a For an image frame, a data setting segment 61 and multiple transmission segments 62-1 to 62-4 can be performed for each line.

[0159] During the data setting section 61, the image data voltage of the image frame can be set for the sub-pixel circuits included in the row lines. In each of the emission sections 62-1 to 62-4, a drive current can be provided to the corresponding inorganic light-emitting element based on the image data voltage set during the data setting section 61.

[0160] During the data setting section 61, the driver 500 may apply control signals (hereinafter referred to as scan signals, which may include, for example, VST(n), SP(n), SCCG(n), SPWM(n), Vcomp(n), Vini(n), and Vini2(n), which will be described below) to the sub-pixel circuit of each row line for setting the image data voltage.

[0161] During each of the emission segments 62-1 to 62-4, the driver 500 may apply a control signal (hereinafter referred to as the emission signal, for example, including Emi(n) as described below) for controlling the operation of the drive current to the sub-pixel circuit of each row line.

[0162] refer to Figure 6a For the entire row of the display panel 100, each of the data setting section 61 and the transmission sections 62-1 to 62-4 can be executed sequentially according to the row order.

[0163] For this purpose, the driver 500 can apply scan signals to the sub-pixel circuit from the first row line to the last row line of the display panel 100 in row line order. The driver 500 can also apply transmit signals to the sub-pixel circuit from the first row line to the last row line of the display panel 100 in row line order.

[0164] According to the embodiments, such as Figure 6aAs shown, the first transmission segment 62-1 of each line can be temporally continuous with the data setting segment 61, and the multiple transmission segments 62-1 to 62-4 can have a predetermined time interval with each other.

[0165] The number of emission segments performed in each line of an image frame and the predetermined time interval between emission segments can be set based on the size of the display panel 100, the frame rate, and / or the camera shutter speed. However, the embodiments are not limited thereto.

[0166] Typically, because the camera's shutter speed is several times faster than an image frame time, when the display panel 100 is driven to execute a transmission segment from the first row line to the last row line in the order of the row lines during an image frame time, the image displayed on the display panel 100 captured by the camera may be distorted.

[0167] Therefore, according to the embodiment, the display panel 100 can be driven to perform multiple transmission segments at predetermined time intervals during an image frame time, and the predetermined time intervals can be set based on the camera speed, so that even if the display panel 100 is captured at any time, the image displayed on the display panel 100 captured by the camera will not be distorted.

[0168] There can be a blanking interval between one image frame time and the next image frame time. The blanking interval can be a time interval between consecutive image frame times.

[0169] According to an embodiment, the blanking interval may include a non-emissive section in which all inorganic light-emitting elements of the display panel 100 do not emit light. Because no current flows into the display panel 100 in the non-emissive section, operations such as fault detection of the display panel 100 can be performed.

[0170] For example, a malfunction of display panel 100 can be determined based on whether current flows to display panel 100 during the non-emitting phase. Because the sub-pixels of display panel 100 do not emit light in the non-emitting phase, no current flows into display panel 100. However, when a short circuit occurs in the sub-pixel circuit, current can flow to display panel 100 during the non-emitting phase. Therefore, when current flows in display panel 100 during the non-emitting phase, the processor or timing controller can determine that display panel 100 has malfunctioned.

[0171] According to an embodiment, an operation for releasing residual charge in the inorganic light-emitting element can be performed during the blanking interval. A detailed description of this will follow later.

[0172] Figure 6b and Figure 6aThe difference lies in the fact that the data setting segment 61, comprising a total of 312 line lines, is performed in a time much shorter than a frame, but for... Figure 6a The description can be applied as is. Figure 6b Therefore, repeated descriptions will be omitted. The differences between the two embodiments are described below.

[0173] Figure 7 This is a detailed block diagram illustrating a display module 1000 according to an embodiment. In the description... Figure 7 In this case, descriptions that are repeated above will be omitted.

[0174] refer to Figure 7 The display module 1000 includes a display panel 100 and a driver 500. The display panel includes a sub-pixel circuit 110 and an inorganic light-emitting element 120.

[0175] The display panel 100 may have a structure in which sub-pixel circuits 110 are formed on a glass substrate and inorganic light-emitting elements 120 are mounted on the sub-pixel circuits 110, but the embodiments are not limited thereto. (See reference...) Figure 7 For the sake of convenience, only one sub-pixel related structure included in the display panel 100 is shown, but each sub-pixel is provided with a sub-pixel circuit 110 and an inorganic light-emitting element 120.

[0176] The inorganic light-emitting element 120 can be mounted on the sub-pixel circuit 110 so as to be electrically connected to the sub-pixel circuit 110 and can emit light based on the driving current provided from the sub-pixel circuit 110.

[0177] The inorganic light-emitting element 120 can constitute the sub-pixels of the display panel 100, and can be of various types depending on the color of the emitted light. For example, the inorganic light-emitting element 120 can be one of an R inorganic light-emitting element that emits red light, a G inorganic light-emitting element that emits green light, or a B inorganic light-emitting element that emits blue light.

[0178] The type of the aforementioned sub-pixel can be determined based on the type of inorganic light-emitting element 120. The R inorganic light-emitting element can constitute the R sub-pixel 20-1, the G inorganic light-emitting element can constitute the G sub-pixel 20-2, and the B inorganic light-emitting element can constitute the B sub-pixel 20-3.

[0179] Inorganic light-emitting element 120 can refer to a light-emitting element made of inorganic materials, which is different from organic light-emitting diodes (OLEDs) made of organic materials.

[0180] According to an embodiment, the inorganic light-emitting element 120 may be a micro light-emitting diode (micro LED or μLED) with a size of less than or equal to 100 micrometers (μm).

[0181] A display panel in which each subpixel is implemented using a micro-LED can be called a micro-LED display panel. A micro-LED display panel can be a flat panel display panel and can include multiple inorganic light-emitting diodes, each less than or equal to 100 micrometers. Compared to liquid crystal display (LCD) panels that require backlighting, micro-LED display panels can provide better contrast, response time, and energy efficiency. While organic light-emitting diodes (OLEDs) and micro-LEDs have good energy efficiency, micro-LEDs offer better performance than OLEDs in terms of brightness, luminous efficacy, and operating life.

[0182] Depending on the amplitude or pulse width of the driving current supplied from the sub-pixel circuit 110, the inorganic light-emitting element 120 can represent various gray levels. The pulse width of the driving current can be referred to as the duty cycle of the driving current or the duration of the driving current.

[0183] For example, as the amplitude of the driving current increases, the inorganic light-emitting element 120 can exhibit a brighter grayscale. As the pulse width of the driving current increases (i.e., the duty cycle of the driving current increases or the duration of the driving current increases), the inorganic light-emitting element 120 can exhibit a brighter grayscale.

[0184] The sub-pixel circuit 110 can provide driving current to the inorganic light-emitting element 120.

[0185] The sub-pixel circuit 110 can provide the inorganic light-emitting element 120 with a drive current having a controlled amplitude and a controlled drive time based on image data voltage (e.g., constant current generator data voltage, PWM data voltage), drive voltage (e.g., first drive voltage, second drive voltage, ground voltage), various control signals (e.g., scan signal, transmit signal, test signal), various input signals (e.g., sweep frequency signal, reference voltage), etc.

[0186] The sub-pixel circuit 110 can drive the inorganic light-emitting element 120 using pulse amplitude modulation (PAM) and / or pulse width modulation (PWM) methods.

[0187] The sub-pixel circuit 110 may include a constant current generator circuit 111 for providing a constant current to the inorganic light-emitting element 120 based on the amplitude of the constant current generator data voltage, and a PWM circuit 112 for controlling the duration of the constant current provided to the inorganic light-emitting element 120 based on the PWM data voltage. Here, the constant current provided to the inorganic light-emitting element 120 is referred to as the aforementioned drive current.

[0188] According to the embodiment, the same constant current generator data voltage can be applied to each of the constant current generator circuits 111. Therefore, since the same driving current (i.e., constant current) is provided to all inorganic light-emitting elements 120 of the display panel 100, the problem of LED wavelength variation according to the amplitude of the driving current can be solved.

[0189] According to the embodiment, the constant current generator circuit 111 of the display panel 100 can be applied with the same constant current generator data voltage for each sub-pixel. Because the characteristics can differ depending on the type of inorganic light-emitting element 120, constant current generator data voltages of different amplitudes can be applied to different types of sub-pixel circuits. Even in this example, the same constant current generator data voltage can be applied to the same type of sub-pixel circuit.

[0190] The PWM data voltage corresponding to the grayscale value of each sub-pixel can be applied to each PWM circuit 112 of the display panel 100. Therefore, the driving time of the driving current (i.e., constant current) supplied to the inorganic light-emitting element 120 of each sub-pixel can be controlled by the PWM circuit 112. Thus, the grayscale of the image can be represented.

[0191] According to an embodiment, the display module 1000 can be applied in a single unit to wearable devices, portable devices, handheld devices, and various electronic products or electronic components that require a display.

[0192] Furthermore, according to another embodiment, a display panel can be configured by combining or assembling multiple display modules. As mentioned above, a display panel in which multiple display modules are combined can be referred to as a "modular display panel." However, the name is not limited thereto. In this example, each display module 1000 becomes a component constituting the modular display panel. Modular display panels can be applied to small display products such as monitors and televisions, or large display products such as digital signage and electronic displays.

[0193] In a modular display panel, the same constant current generator data voltage is applied to the sub-pixel circuits included in one display module 1000, but constant current generator data voltages of different amplitudes can be applied to the sub-pixel circuits included in another display module 1000. Therefore, when multiple display modules are combined to form a display panel, brightness or color deviations that may occur between display modules can be compensated by adjusting the constant current generator data voltage.

[0194] Figure 8 This is a schematic block diagram of the sub-pixel circuit 110 according to an embodiment. (See reference) Figure 8The sub-pixel circuit 110 includes a constant current generator circuit 111 and a PWM circuit 112.

[0195] The constant current generator circuit 111 may include a first driving transistor and may provide a constant current to the inorganic light-emitting element 120 based on a constant current generator data voltage applied from the driver 500.

[0196] In detail, when a driving voltage is applied to the second driving transistor of the PWM circuit 112 in the emission section, the constant current generator circuit 111 can apply a driving voltage to the inorganic light-emitting element 120 through the first driving transistor. Therefore, a constant current can flow through the inorganic light-emitting element 120.

[0197] The amplitude of the constant current can vary depending on the amplitude of the constant current generator data voltage applied to the constant current generator circuit 111. The constant current generator circuit 111 can be capable of performing PAM driving of the inorganic light-emitting element 120. Therefore, the constant current generator data voltage can be referred to as the PAM data voltage, and the constant current generator circuit 111 can be referred to as the PAM circuit.

[0198] As described above, according to the embodiment, a constant current generator data voltage of the same amplitude can be applied to all constant current generator circuits 111 of the display panel 100, and in this example, the constant current generator circuit 111 can provide a constant current of constant amplitude (or the same amplitude) to all inorganic light-emitting elements 120 of the display panel 100.

[0199] The names “constant current generator circuit” and “constant current generator data voltage” can indicate that when the same PAM data voltage is applied to all PAM circuits of the display panel 100, the PAM circuit operates as a constant current generator, but this capability is not limited by the name.

[0200] Deviations may exist between the threshold voltages Vth of the first driving transistors included in the sub-pixel circuit of the display panel 100. Theoretically, the threshold voltages Vth of the first driving transistors should be the same, but in reality, deviations can occur due to various factors such as process variations or changes over time. This deviation leads to a decrease in image quality and therefore requires compensation.

[0201] More specifically, if the threshold voltage of the first driving transistor is not compensated, then even when the same constant current generator data voltage is applied to the constant current generator circuit 111 of each sub-pixel, the inorganic light-emitting element 120 is provided with a different magnitude of driving current due to the deviation of the threshold voltage, and this manifests as blemishes in the image, etc.

[0202] To compensate for the threshold voltage deviation between the first driving transistors, according to an embodiment, when a constant current generator data voltage is applied during the data setting segment, the constant current generator circuit 111 can apply a voltage combining the constant current generator data voltage and the threshold voltage of the first driving transistor to the gate terminal (C node) of the first driving transistor.

[0203] In the emission section, the constant current generator 111 can provide the inorganic light-emitting element 120 with a constant current based on the magnitude of a value corresponding to the square of the voltage obtained by subtracting the threshold voltage of the first driving transistor from the voltage between the gate terminal and the source terminal of the first driving transistor, i.e., a constant current based on the magnitude of (|Vgs|-|Vth|)2.

[0204] During the data setting segment, a voltage (VCCG+Vth) combining a constant current generator data voltage (e.g., VCCG) and a threshold voltage (e.g., Vth) is applied to the gate terminal of the first driving transistor. Thus, it can be seen that the threshold voltage of the first driving transistor is erased when the voltage between the gate terminal and the source terminal of the first driving transistor is subtracted from the threshold voltage of the first driving transistor.

[0205] More specifically, the first driving transistor can be a PMOS TFT, so (|Vgs|-|Vth|). 2 =(Vsg+Vth) 2 At this point, Vsg = Vs - (VCCG + Vth), so Vsg + Vth = Vs - (VCCG + Vth) + Vth, and Vth is deleted.

[0206] Therefore, the amplitude of the constant current provided by the constant current generator circuit 111 is independent of the threshold voltage of the first driving transistor, thus compensating for the threshold voltage deviation between the first driving transistors.

[0207] PWM circuit 112 includes a second drive transistor and can control the duration of a constant current supplied to inorganic light-emitting element 120 based on the PWM data voltage and scan signal applied from driver 500.

[0208] In detail, the PWM circuit 112 can control the time when a constant current flows to the inorganic light-emitting element 120 by applying a driving voltage to the constant current generator circuit 111 (specifically, the source terminal of the first driving transistor) only during the time period when the second driving transistor is turned on in the emitter segment.

[0209] As described above, the constant current generator circuit 111 can provide a constant current to the inorganic light-emitting element 120 by applying the driving voltage applied by the second driving transistor of the PWM circuit 112 to the inorganic light-emitting element 120.

[0210] At this time, the drive voltage is supplied from the PWM circuit 112 to the constant current generator circuit 111 only when the second drive transistor is turned on in the emitter segment. Furthermore, as described below, the time period during which the second drive transistor is turned on in the emitter segment is determined based on the PWM data voltage and the scan voltage.

[0211] PWM circuit 112 can control the duration of a constant current supplied to inorganic light-emitting element 120 based on PWM data voltage and scan signal.

[0212] The problems caused by the deviation in the threshold voltage of the first driving transistor may similarly occur with the second driving transistor. That is, if the threshold voltage of the second driving transistor is not compensated, even if the same PWM data voltage is applied to the PWM circuit 112 of each sub-pixel, the constant current is supplied to the inorganic light-emitting element 120 at different times due to the difference between the threshold voltages, which leads to blemishes in the image, etc.

[0213] To compensate for the deviation of the threshold voltage of the second driving transistor, according to an embodiment, when the second driving transistor operates as a source follower in the data setting segment, the PWM circuit 112 can obtain the threshold voltage of the second driving transistor.

[0214] The threshold voltage thus obtained can be applied to the gate terminal of the second driving transistor, and the threshold voltage of the second driving transistor can be compensated by it.

[0215] More specifically, during the transmit phase, the voltage at the gate terminal of the second driving transistor can be changed according to the scan voltage from the sum of the PWM data voltage component (e.g., -VPWM) and the threshold voltage component of the second driving transistor (e.g., +Vth). (Actually, a reference voltage component +Vref also exists, as described below, but is omitted for ease of description.)

[0216] Here, the scan voltage is a voltage signal that scans once between two different voltages. Furthermore, in a scan signal where the voltage changes linearly and repeatedly from a first voltage to a second voltage, the scan voltage can be selected based on the transmission signal Emi(n), which will be described later. The scan signal is a global signal applied to all sub-pixel circuits 110 of the display panel 100, and the rate of change of the scan voltage over time is constant.

[0217] The second driving transistor turns on when the voltage at the gate terminal is lower than the sum of the voltage at the source terminal and the threshold voltage. As described below, because a driving voltage (e.g., VDD_PAM) is applied to the source terminal of the second driving transistor in the emitter section, the second driving transistor turns on when the voltage at the gate terminal becomes lower than the sum of the driving voltage VDD_PAM and the threshold voltage Vth (VDD_PAM+Vth).

[0218] Therefore, in the emitter region, the voltage at the gate terminal of the second driving transistor changes from -VPWM+Vth according to the scan voltage, and the second driving transistor turns on when the gate terminal voltage becomes VDD_PAM+Vth, so that the threshold voltage value (i.e., Vth value) of the second driving transistor does not affect the on-time of the second driving transistor. The on-time of the second driving transistor in the emitter region is determined independently of the threshold voltage value (Vth value) of the second driving transistor.

[0219] This can compensate for the threshold voltage deviation between the second driving transistors.

[0220] Figure 9a This is a detailed circuit diagram of the sub-pixel circuit according to an embodiment.

[0221] refer to Figure 9a The sub-pixel circuit 110 includes a constant current generator circuit 111, a PWM circuit 112, and a transistor T16. As described above, the constant current generator circuit 111 includes a first driving transistor T14, and the PWM circuit 112 includes a second driving transistor T13.

[0222] Transistor T16 is connected between the anode and cathode terminals of the inorganic light-emitting element 120. The transistor can be used for different purposes before and after the inorganic light-emitting element 120 is mounted on the TFT layer and electrically connected to the sub-pixel circuit 110.

[0223] For example, before the inorganic light-emitting element 120 and the sub-pixel circuit 110 are electrically connected to each other, the transistor T16 can be turned on according to a test signal to check whether the sub-pixel circuit 110 is abnormal. After the inorganic light-emitting element 120 and the sub-pixel circuit 110 are connected to each other, the transistor T16 can be turned on according to a test signal to release the remaining charge in the junction capacitance of the inorganic light-emitting element 120.

[0224] The test signal is a control signal provided from TCON through a level shifter to control the on / off state of transistor T16, and is a global signal equally applied to all sub-pixel circuits 110 of the display panel 110.

[0225] VDD_PAM refers to the first drive voltage (e.g., +12V), VDD_PWM refers to the second drive voltage (e.g., +12V), and VSS refers to the ground voltage (e.g., 0V). Vref represents the reference voltage (e.g., +5V). Vref can be used to obtain the threshold voltage of the second drive transistor T13, as described later. VDD_PAM, VDD_PWM, VSS, and Vref can be provided from, but are not limited to, the aforementioned power supply IC.

[0226] Vini(n) represents the scan signal applied to the sub-pixel circuit 110 to apply a reference voltage Vref to nodes B and D in the data setting section, and to apply a second drive voltage VDD_PWM to node F. The Vref voltage applied to nodes B and D is used to obtain the threshold voltage of the second drive transistor T13, and the second drive voltage VDD_PWM applied to node F can be the reference potential when setting the constant current generator data voltage.

[0227] VST(n) represents the scan signal applied to the sub-pixel circuit 110 in the data setting section to initialize the voltage of node C. When the voltage of node C is initialized according to the VST(n) signal, the first driving transistor T14 is in the on state.

[0228] SP(n) refers to the scan signal applied to the sub-pixel circuit 110 in the data setting section, so as to apply the constant current generator data voltage (VCCG_R / G / B) to node C and the PWM data voltage (VPWM_R / G / B) to node A.

[0229] Vcomp(n) represents the scan signal applied to the sub-pixel circuit 110 in the data setting section so as to apply the threshold voltage of the second driving transistor to node B.

[0230] Emi(n) refers to the emission signal applied to the sub-pixel circuit 110 in the emission section, so as to apply the first driving voltage VDD_PAM to the E node and the F node, apply the scan voltage to the A node, and turn on the transistor T15.

[0231] In the aforementioned gate signals (scan signal and transmit signal), n represents the nth row line. As described above, the driver 500 can drive the display panel 110 for each row line (or scan line or gate line), and each of Vini(n), VST(n), SP(n), Vcomp(n), and Emi(n) can be applied equally to the sub-pixel circuit 110 included in the nth row line.

[0232] The term "sweep" refers to a scan signal. The scan signal can be generated in the TCON and applied equally to all sub-pixel circuits 110 of the display panel 100 via a level shifter. The same scan signal can be applied to all sub-pixel circuits 110 of the display panel 100. In this case, the scan signal can be in the form of a voltage that continuously and repeatedly changes linearly from a first voltage to a second voltage.

[0233] As described above, a scan signal, or transmit signal, can be applied individually to each row line from the gate driver, driving the pixels of the pixel array on a row-line basis. In this way, a signal applied individually to each row line can be called a local signal. Conversely, because the scan signal is applied equally to all row lines of the display panel, the scan signal can be called a global signal separate from the local signals.

[0234] When transistor T1 is turned on according to the emit signal Emi(n), a portion of the scan signal is applied to node A. As described above, the portion of the scan signal selectively applied to node A can be the scan voltage as described above.

[0235] At this time, because the transistors T1 of the display panel 100 are turned on in the order of the row lines according to the transmitted signal, the waveform of the scan voltage applied to node A of the sub-pixel circuit 110 can vary depending on the row lines, except that the scan signal is a global signal applied equally to all row lines. A detailed description will be given later.

[0236] VPWM_R / G / B represents the PWM data voltage applied to the sub-pixel circuit 110. The PWM data voltage can be applied from the data driver. According to an embodiment, the PWM data voltage of each of the R sub-pixels, G sub-pixels, and B sub-pixels constituting a pixel can be time-division multiplexed and applied from the data driver. In this way, the time-division multiplexed PWM data voltage can be applied to the corresponding sub-pixels respectively through a demultiplexer circuit.

[0237] Figure 9a The sub-pixel circuit 110 shown corresponds to one of the R, G, and B sub-pixels (e.g., the R sub-pixel). Therefore, in Figure 9a In the sub-pixel circuit 110, only the PWM data voltage of the R sub-pixel (e.g., VPWM_R) in the time-division multiplexed PWM data voltage can be selected and applied by the demultiplexer circuit.

[0238] VCCG_R / G / B can refer to the constant current generator data voltage applied to the sub-pixel circuit 110.

[0239] As described above, according to the embodiment, a constant current generator data voltage of the same amplitude can be applied to the display panel 100 for each type of sub-pixel. Since the same constant current generator data voltage can be applied to the same type of sub-pixel regardless of whether it is a column line or a row line, DC voltage can be used as the constant current generator data voltage. Therefore, for example, three types of DC voltages (e.g., +3.1 [V], +2.8 [V], +3.0 [V]) corresponding to each of the R sub-pixel, G sub-pixel, and B sub-pixel can be directly applied from the power supply IC to each of the R sub-pixel circuit, G sub-pixel circuit, and B sub-pixel circuit of the display panel 100.

[0240] In this example, no separate data driver or demultiplexer circuit is required to apply the constant current generator data voltage to the sub-pixel circuit 110.

[0241] According to another embodiment, the same constant current generator data voltage can be applied from the power supply IC to all sub-pixel circuits 110 of the display panel 100, regardless of the type of sub-pixel.

[0242] According to yet another embodiment, a constant current generator data voltage can be applied from the data driver.

[0243] There is a resistive component in the display panel 100. Therefore, when the drive current flows in the emitter section, an IR drop occurs, which leads to a voltage drop in the drive voltage. As described below, since the drive voltage is a reference even when the constant current generator data voltage is set, the drive voltage drop interferes with the accurate setting of the constant current generator data voltage.

[0244] In various embodiments, as described above, because the data setting section and the emission section are arranged in the order of the row lines, when the sub-pixel circuits of some row lines of the display panel 100 are operating in the emission section, the sub-pixel circuits of other row lines are operating in the data setting section.

[0245] Therefore, when the same driving voltage applied through a single wiring is applied to the constant current generator circuit 111 of the display panel 100 regardless of which segment the row line is driven in, the driving voltage drop caused by the sub-pixel circuit operating in the emission segment affects the constant current generator data voltage setting operation of the sub-pixel circuit operating in the data setting segment.

[0246] To address the aforementioned issues, according to various embodiments, separate drive voltages applied via separate wiring are applied to constant current generator circuits in the data setting section and the transmit section, respectively.

[0247] exist Figure 9aIn the example, in the data setting section, the second drive voltage VDD_PWM is applied to the constant current generator circuit 111 according to the Vini(n) signal, and in the transmit section, the first drive voltage VDD_PAM is applied to the constant current generator circuit 111 according to the Emi(n) signal.

[0248] Therefore, even if a voltage drop occurs in the first drive voltage VDD_PAM due to the sub-pixel circuit operating in the transmit section, regardless of the drive current, a separate second drive voltage VDD_PWM is applied to the sub-pixel circuit operating in the data setting section, thereby setting a stable constant current generator data voltage available.

[0249] Figure 9b It is used to drive the image frame time and blanking interval. Figure 9a The timing diagram of various signals of the display panel 100 of the sub-pixel circuit 110. For example, in Figure 9b In the middle, the display panel 100 includes 312 rows.

[0250] As described above, according to an embodiment, an image frame, each line may include a data setting segment and multiple transmission segments. For this purpose, reference is made to... Figure 9b During the image frame time, the scan signals VST, SP, Vcomp, and Vini used for data setting operations are applied once for each line line, and the emission signal Emi used for emission operations can be applied multiple times relative to each line line.

[0251] In other words, the time interval between applying low-level VST, SP, Vcomp, and Vini signals becomes the data setting segment of the corresponding row line, and the time interval between applying low-level Emi signals becomes the transmission segment of the corresponding row line.

[0252] As described above, according to the embodiment, the data setup segment and the transmission segment can be arranged in the order of the rows. For this purpose, refer to Figure 9b Each of the gate signals VST, SP, Vcomp, Vini, and Emi can be applied sequentially according to the row line order. That is, for example, with a 1H time difference (in... Figure 9b In the example, a low-level VST(n) signal and a low-level VST(n+1) signal are applied at 1.4 μs. This is the same for the remaining gate signals SP (SP(n) and SP(n+1)), Vcomp (Vcomp(n) and Vcomp(n+1)), Vini (Vini(n) and Vini(n+1)), and Emi (Emi(n) and Emi(n+1)).

[0253] refer to Figure 9bA low-level test signal (test) is applied during the blanking interval. Because the test signal is a global signal, it is applied equally to all sub-pixel circuits 110 of the display panel 100, so that the remaining charge on all inorganic light-emitting elements 120 of the display panel 100 can be released.

[0254] refer to Figures 10a to 10d The specific operation of the sub-pixel circuit 110 will be described.

[0255] Figure 10a The operation of the sub-pixel circuit 110 based on Vini(n) and VST(n) in the scan signal is shown.

[0256] When the data setting segment begins, driver 500 can apply a reference voltage Vref (e.g., +5 [V]) to one end of capacitor C3 (node ​​D) and the gate terminal of the second drive transistor T13 (node ​​B), and can apply a second drive voltage VDD_PWM (e.g., +12 [V]) to one end of capacitor C2 (node ​​F).

[0257] Therefore, the driver 500 can apply a Vini(n) signal, such as Figure 10a As shown. Reference Figure 10a Vref can be applied to nodes B and D by transistors T3 and T5, which are turned on according to the Vini(n) signal. At this time, since the first driving voltage VDD_PAM (e.g., +12[V]) floats in node E (i.e., the source terminal of the second driving transistor T13) according to the progress of the emission segment of the previous image frame, if we assume that the threshold voltage of the second driving transistor T13 is -2.2[V], then the second driving transistor T13 is turned on when Vref (+5[V]) is applied to node B.

[0258] refer to Figure 10a The second drive voltage VDD_PWM can be applied to node F by transistor T4, which is turned on according to the Vini(n) signal. At this time, when the constant current generator data voltage is set for node C, the second drive voltage VDD_PWM applied to node F is the reference potential.

[0259] When the second drive voltage VDD_PWM is applied to node F via the Vini(n) signal, driver 500 can initialize the voltage at node C, the gate terminal of the first drive transistor T14.

[0260] Therefore, such as Figure 10aAs shown, the driver 500 can apply a low voltage (e.g., -5 [V]) to the sub-pixel circuit 110 via the VST(n) signal. When the voltage of node C is initialized to a low voltage (e.g., -5 [V]), the first driving transistor T14 can be in an on state (e.g., in a channel-forming state).

[0261] Figure 10b This is a diagram illustrating the operation of the sub-pixel circuit based on SP(n) in the scan signal.

[0262] The SP(n) signal is a scan signal used to apply image data voltage to the sub-pixel circuit 110. In the data setting section, when a low voltage (e.g., -5 [V]) is applied to the sub-pixel circuit 110 through the SP(n) signal line, transistors T2, T10, and T11 are turned on.

[0263] When transistor T2 is turned on, the PWM data voltage (VPWM_R / G / B) can be applied to one end (node ​​A) of capacitor C1 through the turned-on transistor T2.

[0264] When transistors T10 and T11 are turned on, the constant current generator data voltage (VCCG_R / G / B) can be applied to node C through the turned-on transistor T10, the first drive transistor T14 turned on based on the VST(n) signal, and the turned-on transistor T11.

[0265] At this point, in node C, the constant current generator data voltage (VCCG_R / G / B) is not applied (or set) as is. Instead, a constant current generator voltage is applied that compensates for the threshold voltage Vth of the first drive transistor T14 (i.e., the voltage obtained by adding the threshold voltage of the first drive transistor T14 and the constant current generator data voltage (VCCG_R / G / B+Vth)).

[0266] When transistors T10 and T11 are turned on according to the SP(n) signal, and the first drive transistor T14 is turned on according to the VST(n) signal, the constant current generator data voltage is input to node C through transistors T10, T14, and T11. That is, the voltage at node C begins to rise from a low voltage (e.g., -5V).

[0267] However, the voltage at node C may not rise to the constant current generator data voltage (e.g., +3 [V]), but may rise to the voltage obtained by summing the constant current generator data voltage (+3 [V]) and the threshold voltage of the first driving transistor T14 (e.g., -2.2 [V]) (i.e., +0.8 [V]).

[0268] This is because when the voltage difference between the gate terminal and the source terminal of the first driving transistor T14 decreases as the voltage of node C increases and becomes the threshold voltage of the first driving transistor T14, the first driving transistor T14 is turned off and the current stops flowing.

[0269] In other words, because the constant current generator data voltage is applied to the source terminal of the first driving transistor T14 through the conducting transistor T10, the voltage at node C only increases to the voltage (VCCG_R / G / B+Vth).

[0270] When the constant current generator data voltage is applied to the source terminal of the first driving transistor T14, and the transistor T10 is turned on according to the SP(n) signal, the second driving transistor T13 can operate as a source follower.

[0271] A source follower is also known as a common-drain amplifier because a DC voltage is applied to the drain terminal, and the gate terminal can be used as the input terminal, while the source terminal can be used as the output terminal. When an input voltage is applied to the gate terminal, the source follower has a DC characteristic, where a voltage corresponding to the difference between the input voltage and the source follower's threshold voltage is output from the source terminal, and for this reason, the source follower is also called a level shifter.

[0272] refer to Figure 10b Because the source terminal of the first driving transistor T14 is directly connected to the drain terminal of the second driving transistor T13, the second driving transistor T13 operates as a source follower when the constant current generator data voltage, which is a DC voltage, is applied to the source terminal of the first driving transistor T14 (i.e., the drain terminal of the second driving transistor T13).

[0273] At this time, since the reference voltage Vref is applied to the gate terminal of the second driving transistor T13, the voltage Vref-Vth, which corresponds to the difference between the reference voltage Vref and the threshold voltage Vth of the second driving transistor, can be output from the source terminal of the second driving transistor T13 (i.e., the other end of capacitor C3 (E node)).

[0274] More specifically, in the second driving transistor T13, when a DC voltage is applied to the drain terminal and a reference voltage Vref is applied to the gate terminal and the second driving transistor is turned on, the voltage at the source terminal can change with the current flow until the second driving transistor T13 is turned off. When a voltage Vref-Vth, corresponding to the difference between the reference voltage Vref and the threshold voltage Vth of the second driving transistor, is applied to the source terminal, the second driving transistor T13 is turned off, thereby outputting Vref-Vth at the source terminal.

[0275] According to an embodiment, when the second driving transistor T13 operates as a source follower, a threshold voltage of the second driving transistor T13 can be obtained at the source terminal of the second driving transistor T13. The threshold voltage of the second driving transistor T13 can then be coupled through capacitor C3 and applied to node B.

[0276] When the voltage at the source terminal of the second driving transistor T13 becomes Vref-Vth, Vref is applied to one end of capacitor C3 (node ​​D), causing the voltage difference between the two ends of capacitor C3 (i.e., the voltage difference between node E and node D) to become -Vth. Figure 10b The +|Vth| shown is another representation of -Vth. Because the threshold voltage of the PMOS TFT is negative, +|Vth| equals -Vth.

[0277] Figure 10c This is a diagram illustrating the operation of the sub-pixel circuit 110 based on Vcomp(n) in the scan signal.

[0278] The Vcomp(n) signal is a scan signal used to apply the threshold voltage of the second driving transistor T14 obtained at the source terminal (E node) of the second driving transistor T13 to the gate terminal (B node) of the second driving transistor T14.

[0279] like Figure 10c As shown, when a low voltage (e.g., -5V) is applied through the Vcomp(n) signal line, transistors T6 and T9 are turned on. Therefore, the threshold voltage applied to the second driving transistor at node E can be coupled to node B through capacitor C3.

[0280] In detail, when transistor T6 is turned on, and Vref-Vth is applied to node E and Vref is applied to node D, the voltage at node E becomes Vref. Therefore, the voltage change at node E (i.e., +Vth) is coupled to node D through capacitor C3, and the voltage at node D becomes Vref+Vth. At this time, because transistor T9 is turned on according to the Vcomp(n) signal, the voltage Vref+Vth at node D is applied to node B as is through the turned-on transistor T9. Figure 10c As shown, -|Vth| is another representation of +Vth. Because the threshold voltage of the PMOS transistor TFT has a negative value, -|Vth| and +Vth become the same value.

[0281] Figure 10d This is a diagram illustrating the operation of the sub-pixel circuit 110 based on the transmitted signal Emi(n).

[0282] like Figure 10dAs shown, when a low voltage (e.g., -5V) is applied through the Emi(n) signal line, transistors T12, T15, T8 and T1 are turned on.

[0283] When the second driving transistor T13 and the first driving transistor T14 are turned on, and transistors T12 and T15 are also turned on, the first driving voltage VDD_PAM is applied to the anode terminal of the inorganic light-emitting element 120. Therefore, a potential difference exceeding the forward voltage Vf is generated across the inorganic light-emitting element 120, and a driving current (i.e., a constant current) flows through the inorganic light-emitting element 120 to make it emit light.

[0284] When the second driving transistor T13 is turned on, the first driving transistor T14 is also turned on.

[0285] Specifically, when transistors T12 and T15 are turned on according to the Emi(n) signal, a voltage (e.g., +0.8V) obtained by summing the constant current generator data voltage (e.g., +3[V]) and the threshold voltage of the first driving transistor T14 (e.g., -2.2[V]) is applied to node C, as described above. Figure 10b As described above. Therefore, when the second driving transistor T13 is turned on, and the first driving voltage VDD_PAM (e.g., +12 [V]) is applied to the source terminal of the first driving transistor T14, the first driving transistor T14 is also turned on.

[0286] Therefore, whether the first driving voltage VDD_PAM will be applied to the anode terminal of the inorganic light-emitting element 120 can be determined based on the on / off operation of the second driving transistor T13.

[0287] Because the second driving transistor T13 is a PMOS TFT, it turns on when a voltage less than the threshold voltage Vth is applied between the gate and source terminals. In other words, the second driving transistor T13 turns on when the voltage at the gate terminal is less than the sum of the voltage at the source terminal and the threshold voltage. For example, when the first driving voltage VDD_PAM applied to the source terminal is +12 [V] and the threshold voltage Vth of the second driving transistor is -2.2 [V], the second driving transistor T13 can turn on when a voltage less than +9.8 [V] is applied to the gate terminal.

[0288] In this regard, such as Figure 10d As shown, during the emitter phase, Vsweep-VPWM_R / G / B+Vref-|Vth| is applied to the gate terminal (node ​​B) of the second drive transistor T13.

[0289] refer to Figure 10dWhen transistor T1 is turned on according to the Emi(n) signal, a portion of the scan signal (scan) is applied to node A simultaneously with the turn-on of transistor T1. At this time, this portion of the scan signal applied to node A becomes the scan voltage (Vsweep). When the scan voltage (Vsweep) is applied to node A, the PWM data voltage (VPWM_R / G / B) is coupled to node B along with the scan voltage (Vsweep) via capacitor C1. Specifically, during the data setting segment as described above, VPWM_R / G / B is applied to node A, and Vref-|Vth| is applied to node B. In this state, when the scan voltage Vsweep is applied to node A, the voltage of node A changes from VPWM_R / G / B to Vsweep. Because the voltage difference across capacitor C1 must remain constant, the voltage of node B also changes due to the voltage change at node A (i.e., Vsweep - VPWM_R / G / B). Therefore, the voltage at node B becomes Vsweep-VPWM_R / G / B+Vref-|Vth|.

[0290] At this time, the PWM data voltage (VPWM_R / G / B), the reference voltage (Vref), and the threshold voltage (Vth) of the second driving transistor have fixed values, while the scan voltage (Vsweep) has a value that varies linearly between +15 [V] and +10 [V].

[0291] Therefore, during the emitter phase, the voltage at node B varies according to the sweep voltage (Vsweep), and the second drive transistor T13 is turned on during the time period when the voltage at node B (i.e., the gate terminal) (Vsweep-VPWM_R / G / B+Vref-|Vth|) is lower than the voltage (VDD_PAM+Vth) corresponding to the sum of the source terminal voltage VDD_PAM and the threshold voltage Vth.

[0292] Here, -|Vth| and +Vth are the same value, and the time period during which the second driving transistor T13 is turned on is determined, regardless of the value of Vth.

[0293] As described above, because the rate of change of the scanning voltage with respect to time is constant, the period during which the second driving transistor T13 is turned on in the emitter segment varies depending on the voltage at node B at the start of the emitter segment. At this time, the voltage at node B at the start of the emitter segment varies according to the VPWM_R / G / B value (i.e., the PWM data voltage value), thus the grayscale of the image can be represented by the PWM data voltage.

[0294] Reference Figures 11a to 11c The PWM operation of the sub-pixel circuit 110 described above will be described in more detail.

[0295] In the transmit section, the drive voltage applied to the constant current generator circuit 111 is changed from the second drive voltage VDD_PWM to the first drive voltage VDD_PAM.

[0296] As described above, in the data setting section, the second drive voltage VDD_PWM is applied to node F based on the Vini(n) signal. However, refer to Figure 10d The first driving voltage VDD_PAM is applied to one end (node ​​F) of capacitor C2 through transistors T12 and T8, which are turned on according to the Emi(n) signal.

[0297] In the emission section, a voltage drop may occur in the first driving voltage VDD_PAM due to the IR drop generated when the driving current flows to the inorganic light-emitting element 120.

[0298] However, even if a voltage drop occurs in the first driving voltage VDD_PAM, the voltage difference between the two ends of capacitor C2 (node ​​F and node C) remains as set in the data setting section, so the image quality is not affected.

[0299] According to an embodiment, in the data setting section, separate from the first drive voltage VDD_PAM, the constant current generator data voltage can be set for the constant current generator circuit 111 by applying the constant current generator data voltage to node C based on the second drive voltage VDD_PWM, which has no voltage drop, regardless of the voltage drop of the first drive voltage VDD_PAM.

[0300] In the transmit section, a first drive voltage (VDD_PAM) that can have a voltage drop is used, but the constant current generator circuit 111 can operate precisely according to the voltage set in the data setting section, because as described above, the voltage difference between the two ends of capacitor C2 is maintained regardless of the voltage drop of the first drive voltage VDD_PAM.

[0301] Figures 11a to 11c It shows that it has Figure 9a A view of the PWM operation of the sub-pixel circuit configuration shown. (Reference) Figures 11a to 11c The PWM data voltage corresponding to low grayscale is +4 [V], the PWM data voltage corresponding to medium grayscale is +7 [V], and the PWM data voltage corresponding to high grayscale is +14 [V], but the PWM data voltage corresponding to each grayscale is not limited to these.

[0302] Figures 11a to 11c The diagram shows the voltage changes at node A, the voltage changes at node B, and the changes in drive current Id when PWM data voltages are applied to the sub-pixel circuits 110 included in the nth and (n+36)th row lines, respectively.

[0303] like Figures 11a to 11c As shown, the threshold voltage of the second driving transistor Vth is -2.2 [V], the reference voltage Vref is +5 [V], and the first driving voltage VDD_PAM is +12 [V]. Furthermore, a scan signal (scan (global)) with a shape where the voltage changes linearly from +15 [V] to +10 [V] every 100 μs is continuously repeated as an example. Here, (global) is an expression indicating that the scan signal is a global signal that is commonly applied to all row lines.

[0304] Figure 11a An example is shown in which a PWM data voltage (e.g., +4 [V]) corresponding to a low grayscale is applied to the sub-pixel circuit 110 included in the nth row line and the (n+36)th row line, respectively.

[0305] The operation of the sub-pixel circuit 110 included in the nth row will be described.

[0306] During the data setting segment, +4[V] (i.e., PWM data voltage) is applied to node A(n) of the sub-pixel circuit 110 included in the nth row according to the SP(n) signal, and +2.8[V] (i.e., Vref-|Vth|) is applied to node B(n) according to the Vcomp(n) signal.

[0307] Subsequently, when the transmit segment begins, a scan voltage (i.e., a voltage that varies linearly from +15 [V] to +10 [V]) is applied to node A (n), as shown in the figure.

[0308] Because the voltage change of node A (n) according to the scanning voltage is coupled to node B (n) through capacitor C1, the voltage of node B (n) changes from +15 [V] to +10 [V] at the same time as the voltage of node A (n) changes from +13.8 [V] to +8.8 [V].

[0309] As described above, the second driving transistor T13 is turned on during the time period when the voltage at the gate terminal (node ​​B) is lower than the sum of the voltage VDD_PAM at the source terminal and the threshold voltage Vth, VDD_PAM+Vth.

[0310] During the period when the voltage at node B(n) is below +9.8 [V] (i.e., during the period when the voltage at node B(n) changes from +9.8 [V] to +8.8 [V]), the second driving transistor T13 is turned on, and during the period when the second driving transistor T13 is turned on, the driving current flows through the inorganic light-emitting element 120. Id(n) shows the change in driving current.

[0311] The operation of the sub-pixel circuit 110 included in the (n+36th)th row will be described.

[0312] During the data setting segment, +4[V] (i.e., PWM data voltage) is applied to node A (n+36) of the sub-pixel circuit 110 included in the (n+36) row according to the SP(n+36) signal, and +2.8[V] (i.e., Vref-|Vth|) is applied to node B (n+36) according to the Vcomp(n+36) signal.

[0313] Subsequently, when the transmission period begins, the scan voltage (i.e., the voltage changes linearly from +12.5[V] to +10[V] and from +15[V] to +12.5[V]) is applied to node A (n+36) as part of the scan signal (scan (global)) according to the Emi(n+36) signal.

[0314] More specifically, as described above, in various embodiments, the transmission segments are executed sequentially in the order of the rows, such that when the transmission segments are executed sequentially at intervals of 1H time (e.g., 1.4μs), the Emi(n+36) signal has the same waveform as the Emi(n) signal, but is delayed by 50.4μs.

[0315] Therefore, the scan voltage applied to node A (n+36) of the sub-pixel circuit 110 included in the (n+36)th row can have a waveform that linearly changes from +12.5 [V] to +10 [V] and then linearly changes from +15 [V] to +12.5 [V].

[0316] In other words, all scan voltages are scanned once between +15 [V] and +10 [V], but the starting voltage for the scan is variable depending on the row line.

[0317] Because the voltage change at node A (n+36) according to the scanning voltage is coupled to node B (n+36) as is through capacitor C1, the voltage at node B (n+36) changes from +12.5 [V] to +10 [V] at the same time as the voltage at node A (n+36) changes from +11.3 [V] to +8.8 [V], and when the voltage at node A (n+36) changes from +15 [V] to +12.5 [V], the voltage at node B (n+36) changes from +13.8 [V] to +11.3 [V].

[0318] During the period when the voltage at node B (n+36) is below +9.8 [V], i.e., during the time period when the voltage at node B (n+36) changes from +9.8 [V] to +8.8 [V], the second driving transistor T13 is turned on, and during the time the second driving transistor T13 is turned on, driving current flows through the inorganic light-emitting element 120. Id(n+36) shows the change in driving current.

[0319] Figure 11b The illustration shows the case where a PWM data voltage (e.g., +8 [V]) corresponding to the medium grayscale is applied to the sub-pixel circuits 110 included in the nth and (n+36)th row lines, respectively.

[0320] The operation of the sub-pixel circuit 110 included in the nth row will be described.

[0321] During the data setting segment, +7[V] (i.e., PWM data voltage) is applied to node A(n) of the sub-pixel circuit 110 included in the nth row according to the SP(n) signal, and +2.8[V] (i.e., Vref-|Vth|) is applied to node B(n) according to the Vcomp(n) signal.

[0322] Subsequently, when the transmission segment begins, a scan voltage (i.e., the voltage changes linearly from +15[V] to +10[V]) is applied to node A(n) as part of the scan signal (scan(global)) according to the Emi(n) signal.

[0323] Because the voltage change of node A (n) according to the scanning voltage is coupled to node B (n) as is through capacitor C1, the voltage of node B (n) changes from +15 [V] to +10 [V] at the same time as the voltage of node A (n) changes from +10.8 [V] to +5.8 [V].

[0324] As described above, during the period when the voltage of node B(n) is below +9.8 [V], that is, during the period when the voltage of node B(n) changes from +9.8 [V] to +5.8 [V], the second driving transistor T13 is turned on, and during the period when the second driving transistor T13 is turned on, the driving current flows through the inorganic light-emitting element 120. Id(n) illustrates the above.

[0325] The operation of the sub-pixel circuit 110 included in the (n+36)th row will be described.

[0326] During the data setting segment, +7[V] (i.e., PWM data voltage) is applied to node A (n+36) of the sub-pixel circuit 110 included in the (n+36) row according to the SP(n+36) signal, and +2.8[V] (i.e., Vref-|Vth|) is applied to node B (n+36) according to the Vcomp(n+36) signal.

[0327] Subsequently, when the transmission segment begins, the scan voltage (i.e., the voltage changes linearly from +12.5[V] to +10[V] and from +15[V] to +12.5[V]) is applied to node A (n+36) as part of the scan signal (scan (global)) according to the Emi(n+36) signal.

[0328] Because the voltage change at node A (n+36) according to the scanning voltage is coupled to node B (n+36) as is through capacitor C1, when the voltage at node A (n+36) changes from +12.5 [V] to +10 [V], the voltage at node B (n+36) changes from +8.3 [V] to +5.8 [V], and when the voltage at node A (n+36) changes from +15 [V] to +12.5 [V], the voltage at node B (n+36) changes from +10.8 [V] to +8.3 [V].

[0329] As described above, during the period when the voltage at node B (n+36) is below +9.8 [V], that is, during the time periods when the voltage at node B (n+36) changes from +8.3 [V] to +5.8 [V] and from +9.8 [V] to 8.3 [V], the second driving transistor T13 is turned on, and during the time period when the second driving transistor T13 is turned on, the driving current flows through the inorganic light-emitting element 120. Id(n+36) illustrates the above.

[0330] refer to Figure 11b For the same PWM data voltage (+7V), the waveforms of Id(n) and Id(n+36) are different. However, since the integral value of the drive current, i.e., the brightness of the inorganic light-emitting element 120, is the same, this is not a problem.

[0331] Figure 11c The illustration shows the case where a PWM data voltage corresponding to high grayscale (e.g., +14 [V]) is applied to the sub-pixel circuits 110 included in the nth and (n+36)th row lines, respectively.

[0332] The operation of the sub-pixel circuit 110 included in the nth row will be described.

[0333] During the data setting segment, +14[V] (i.e., PWM data voltage) is applied to node A(n) of the sub-pixel circuit 110 included in the nth row according to the SP(n) signal, and +2.8[V] (i.e., Vref-|Vth|) is applied to node B(n) according to the Vcomp(n) signal.

[0334] Subsequently, when the transmission segment begins, a scan voltage (i.e., the voltage changes linearly from +15[V] to +10[V]) is applied to node A(n) as part of the scan signal (scan(global)) according to the Emi(n) signal.

[0335] Because the voltage change at node A (n) based on the scanning voltage is coupled to node B (n) as is through capacitor C1, the voltage at node B (n) changes from +15 [V] to +10 [V] at the same time as the voltage at node A (n) changes from +3.8 [V] to -1.2 [V].

[0336] As described above, during the period when the voltage of node B(n) is below +9.8 [V], that is, during the period when the voltage of node B(n) changes from +3.8 [V] to -1.2 [V], the second driving transistor T13 is turned on, and during the period when the second driving transistor T13 is turned on, the driving current flows through the inorganic light-emitting element 120. Id(n) illustrates the above.

[0337] The operation of the sub-pixel circuit 110 included in the (n+36th)th row will be described.

[0338] During the data setting segment, +14[V] (i.e., PWM data voltage) is applied to node A (n+36) of the sub-pixel circuit 110 included in the n+36th row according to the SP(n+36) signal, and +2.8[V] (i.e., Vref-|Vth|) is applied to node B (n+36) according to the Vcomp(n+36) signal.

[0339] Subsequently, when the transmission segment begins, the scan voltage (i.e., the voltage changes linearly from +12.5[V] to +10[V] and from +15[V] to +12.5[V]) is applied to node A (n+36) as part of the scan signal (scan (global)) according to the Emi(n+36) signal.

[0340] Because the voltage change at node A (n+36) based on the scanning voltage is coupled to node B (n+36) as is through capacitor C1, the voltage at node B (n+36) changes from +12.5 [V] to +10 [V] at the same time as the voltage at node A (n+36) changes from +1.3 [V] to -1.2 [V]. Furthermore, when the voltage at node A (n+36) changes from +15 [V] to +12.5 [V], the voltage at node B (n+36) changes from +3.8 [V] to +1.3 [V].

[0341] As described above, during the period when the voltage at node B (n+36) is below +9.8 [V], that is, during the time periods when the voltage at node B (n+36) changes from +1.3 [V] to -1.2 [V] and from +3.8 [V] to +1.3 [V], the second driving transistor T13 is turned on, and during the time periods when the second driving transistor T13 is turned on, the driving current flows through the inorganic light-emitting element 120. Id(n+36) illustrates the above.

[0342] refer to Figure 11c For the same PWM data voltage (+14V), the waveforms of Id(n) and Id(n+36) are slightly different. However, since the integral value of the drive current, i.e., the brightness of the inorganic light-emitting element 120, is the same, this is not a problem.

[0343] In the following text, reference will be made to Figures 12a to 14c Another embodiment is described.

[0344] Figure 12a This is a detailed circuit diagram of a sub-pixel circuit according to another embodiment.

[0345] refer to Figure 12a The sub-pixel circuit 110 includes a constant current generator circuit 111, a PWM circuit 112, and a transistor T16. As described above, the constant current generator circuit 111 includes a first driving transistor T14, and the PWM circuit 112 includes a second driving transistor T13.

[0346] Because transistor T16 has the same Figure 9a The transistor T16 has the same connection structure and function, so a redundant description of it is omitted. The test signal is also the same, and a redundant description of it is omitted as well.

[0347] The descriptions of VDD_PAM, VDD_PWM, VSS, and Vref are also consistent with... Figure 9a The descriptions are identical, and duplicate descriptions will be omitted.

[0348] Vini(n) refers to the scan signal applied to the sub-pixel circuit 110 in the data setting section to apply the reference voltage Vref to nodes B and D, and to apply the second driving voltage VDD_PWM to node F. Vref applied to nodes B and D is used to obtain the threshold voltage of the second driving transistor T13, and when the constant current generator data voltage is set, the second driving voltage VDD_PWM applied to node F becomes the reference potential.

[0349] VST(n) represents the scan signal applied to the sub-pixel circuit 110 in the data setting section to initialize the voltage of node C. When the voltage of node C is initialized according to the VST(n) signal, the first driving transistor T14 is turned on.

[0350] Vini2(n) represents the scan signal applied to the sub-pixel circuit 110 in the data setting section to apply the reference voltage Vref to node A. The Vref applied to node A can be used to apply the threshold voltage of the second driving transistor T13 to node B (i.e., the gate terminal of the second driving transistor T13), as described later.

[0351] SCCG(n) represents the scan signal applied to the sub-pixel circuit 110 in the data setting section to apply the constant current generator data voltage (VCCG_R / G / B) to node C.

[0352] SPWM(n) represents the scan signal applied to the sub-pixel circuit 110 in the data setting section to apply the PWM data voltage (VPWM_R / G / B) to node A.

[0353] Vcomp(n) represents the scan signal applied to the sub-pixel circuit 110 in the data setting section to apply the threshold voltage of the second driving transistor to the B node.

[0354] Emi(n) refers to the signal applied to the sub-pixel circuit 110 to apply the first driving voltage VDD_PAM to nodes E and F in the emission section, apply the scan voltage to node A, and turn on the emission signal of transistor T15.

[0355] In the aforementioned gate signals (scan signal and transmit signal), n represents the nth row line. As described above, the driver 500 can drive the display panel 110 for each row line (or scan line or gate line), and each of Vini(n), Vini2(n), VST(n), SCCG(n), SPWM(n), Vcomp(n), and Emi(n) can be equally applied to the sub-pixel circuit 110 included in the nth row line.

[0356] The scan refers to the scan signal. The scan signal is a global signal equally applied to all sub-pixel circuits 110 of the display panel 100, and can have a voltage that continuously and repeatedly changes linearly from a first voltage to a second voltage. When transistor T1 is turned on according to the emission signal Emi(n), a portion of the scan signal can be applied to node A, and a portion of the scan signal selectively applied to node A can be the aforementioned scan voltage. Because the content related to the scan signal is the same as the above reference... Figure 9a Since the content described is the same, further redundant descriptions will be omitted.

[0357] VPWM_R / G / B represents the PWM data voltage applied to the sub-pixel circuit 110. The PWM data voltage can be applied from the data driver. According to an embodiment, the PWM data voltage of each of the R sub-pixels, G sub-pixels, and B sub-pixels constituting a pixel can be time-division multiplexed and applied from the data driver. In this way, the time-division multiplexed PWM data voltage can be applied to the respective sub-pixels respectively through the demultiplexer circuit.

[0358] Figure 12aThe sub-pixel circuit 110 illustrates a sub-pixel circuit 110 corresponding to any one of the R sub-pixel, G sub-pixel, and B sub-pixel (e.g., the R sub-pixel). Therefore, in Figure 12a In the sub-pixel circuit 110, only the PWM data voltage of the R sub-pixel (e.g., VPWM_R) in the time-division multiplexed PWM data voltage can be selected and applied by the demultiplexer circuit.

[0359] VCCG_R / G / B represents the constant current generator data voltage applied to the sub-pixel circuit 110.

[0360] As described above, according to the embodiment, a constant current generator data voltage of the same amplitude can be applied to the display panel 100 for each type of sub-pixel. Since the same constant current generator data voltage is applied to the same type of sub-pixel regardless of whether it is a column line or a row line, DC voltage can be used as the constant current generator data voltage. For example, three types of DC voltages (e.g., +3.1 [V], +2.8 [V], +3.0 [V]) corresponding to each of the R sub-pixel, G sub-pixel, and B sub-pixel can be directly applied from the power supply IC to each of the R sub-pixel circuit, G sub-pixel circuit, and B sub-pixel circuit of the display panel 100.

[0361] In this example, no separate data driver or demultiplexer circuit is required to apply the constant current generator data voltage to the sub-pixel circuit 110.

[0362] Regardless of the type of sub-pixel, the same constant current generator data voltage can be applied from the power supply IC to all sub-pixel circuits 110 of the display panel 100.

[0363] In another embodiment, a constant current generator data voltage can be applied from the data driver.

[0364] The drop in driving voltage generated in the launch section and the problems it causes are referenced above. Figure 9a The descriptions are the same.

[0365] In various embodiments, the problem caused by the drop in drive voltage is overcome by applying separate drive voltages via separate wiring to the constant current generator circuit 111 in the data setting section and the transmit section, respectively. Figure 12a The same applies to the embodiments shown.

[0366] exist Figure 12aIn the example, in the data setting section, the second drive voltage VDD_PWM is applied to the constant current generator circuit 111 according to the Vini(n) signal, and in the transmit section, the first drive voltage VDD_PAM is applied to the constant current generator circuit 111 according to the Emi(n) signal.

[0367] Therefore, even if a voltage drop occurs in the first drive voltage VDD_PAM due to the sub-pixel circuit operating in the transmit section, a separate second drive voltage VDD_PWM is applied to the sub-pixel circuit operating in the data setting section, thus setting a stable constant current generator data voltage is available.

[0368] Figure 12b It is used to drive the image frame time and blanking interval. Figure 12a Timing diagram of various signals of the display panel 100 in the sub-pixel circuit 110. (Reference) Figure 12b It describes an example of a display panel 100 including 312 rows.

[0369] As described above, according to the embodiment, for a single image frame, one data setup segment and multiple transmission segments can be performed for each line. (See reference...) Figure 12b During the image frame time, the scan signals VST, Vini, SCCG, Vini2, Vcomp, and SPWM used for data setting operations are applied to each line line once, and the emission signal Emi used for light emission operations is applied to each line line multiple times.

[0370] In other words, the time interval between applying VST, Vini, SCCG, Vini2, Vcomp, and SPWM signals becomes the data setting segment of the corresponding row line, and the time interval between applying the low-level Emi signal becomes the transmission segment of the corresponding row line.

[0371] As described above, according to the embodiment, the data setting segment and the transmission segment can be arranged in the order of the rows. (Reference) Figure 12b Each of the gate signals VST, Vini, SCCG, Vini2, Vcomp, SPWM, and Emi is applied sequentially in the order of the row lines. That is, for example, with a time difference of 1H (in Figure 12bIn the example, a low-level VST(n) signal and a low-level VST(n+1) signal are applied at 1.4 μs. This is the same for the remaining gate signals (Vini signals (Vini(n) and Vini(n+1)), SCCG signals (SCCG(n) and SCCG(n+1)), Vini2 signals (Vini2(n) and Vini2(n+1)), Vcomp signals (Vcomp(n) and Vcomp(n+1)), SPWM signals (SPWM(n) and SPWM(n+1)) and Emi signals (Emi(n) and Emi(n+1)).

[0372] refer to Figure 12b A low-level test signal is applied during the blanking interval. Because the test signal is a global signal, it is applied equally to all sub-pixel circuits 110 of the display panel 100, thus releasing any remaining charge on all inorganic light-emitting elements 120 of the display panel 100.

[0373] refer to Figures 13a to 13e , will describe Figure 12a The specific operation of the sub-pixel circuit 110.

[0374] Figure 13a This is a diagram illustrating the operation of the sub-pixel circuit 110 based on Vini(n) and VST(n) in the scan signal. (Data setting section) Figure 13a The timing shown can be referred to as the initialization period.

[0375] When the data setting segment begins, driver 500 can apply a reference voltage Vref (e.g., +5 [V]) to the gate terminal (B node) of the second drive transistor T13 and one end of capacitor C3 (D node), and can apply a second drive voltage VDD_PWM (e.g., +12 [V]) to one end of capacitor C2 (F node).

[0376] like Figure 13a As shown, driver 500 can apply a Vini(n) signal.

[0377] refer to Figure 13a Vref can be applied to nodes B and D respectively through transistors T3 and T5, which are turned on according to the Vini(n) signal. At this time, the first driving voltage VDD_PAM (e.g., +12[V]) floats on node E (i.e., the source terminal of the second driving transistor T13) according to the progress of the emission segment of the previous image frame. Therefore, if we assume that the threshold voltage of the second driving transistor T13 is -2.2[V], then the second driving transistor T13 is turned on when Vref (+5[V]) is applied to node B.

[0378] In addition, refer to Figure 13a The second drive voltage VDD_PWM can be applied to node F by transistor T4, which is turned on according to the Vini(n) signal. Subsequently, when the constant current generator data voltage is set for node C, the second drive voltage VDD_PWM applied to node F becomes the reference potential.

[0379] When the data setup segment begins, driver 500 can initialize the voltage at the gate terminal (C node) of the first drive transistor T14.

[0380] like Figure 13a As shown, the driver 500 can apply a low voltage (e.g., -5 [V]) to the sub-pixel circuit 110 via the VST(n) signal. When the voltage of node C is initialized to a low voltage (e.g., -5 [V]), the first driving transistor T14 can be in an on state (e.g., a channel-forming state).

[0381] Figure 13b The operation of the sub-pixel circuit 110 based on SCCG(n) and Vini2(n) in the scan signal is shown.

[0382] Because the threshold voltage component of the second driving transistor T13 is Figure 13b The timing period shown first appears in the sub-pixel circuit 110, so the data setting segment... Figure 13b The timing shown can be referred to as the threshold voltage sensing period.

[0383] The SCCG(n) signal is a scan signal used to apply the constant current generator data voltage to the sub-pixel circuit 110. In the data setting section, when a low voltage (e.g., -5 [V]) is applied to the sub-pixel circuit 110 through the SCCG(n) signal line, transistors T10 and T11 are turned on.

[0384] When transistors T10 and T11 are turned on, the constant current generator data voltage VCG_R / G / B can be applied to node C based on the VST(n) signal through the turned-on transistors T10, the first drive transistor T14, and the turned-on transistor T11.

[0385] At node C, instead of applying (or setting) the constant current generator data voltage (VCCG_R / G / B) as is, a constant current generator data voltage that compensates for the threshold voltage Vth of the first driving transistor T14 is applied (i.e., the voltage VCCG_R / G / B+Vth, which is the sum of the threshold voltage of the first driving transistor T14 and the constant current generator data voltage).

[0386] Specifically, when transistors T10 and T11 are turned on according to the SCCG(n) signal, and the first drive transistor T14 is turned on according to the VST(n) signal, the constant current generator data voltage begins to be input to node C through transistors T10, drive transistors T14 and T11. That is, the voltage at node C begins to rise from a low voltage (e.g., -5V).

[0387] However, the voltage at node C will not rise to the constant current generator data voltage (e.g., +3 [V]), but can rise to the voltage that is the sum of the threshold voltage of the first driving transistor T14 (e.g., -2.2 [V]) and the constant current generator data voltage (+3 [V]) (i.e., +0.8 [V]).

[0388] This is because if the voltage difference between the gate terminal and the source terminal of the first driving transistor T14 decreases as the voltage at node C increases, and then becomes the threshold voltage of the first driving transistor T14, then the first driving transistor T14 will be turned off and the current will stop flowing.

[0389] In other words, because the constant current generator data voltage is applied to the source terminal of the first driving transistor T14 through the conducting transistor T10, the voltage at node C only rises to the sum of the constant current generator data voltage VCCG_R / G / B and the threshold voltage Vth of the first driving transistor T14, VCCG_R / G / B + Vth.

[0390] Figure 13b In node C, VCCG-|Vth,T14| is another representation of the same value of VCCG_R / G / B+Vth. Specifically, VCCG represents the constant current generator data voltage applied to the sub-pixel circuit 110, and |Vth,T14| represents the absolute value of the threshold voltage of the first driving transistor T14. Because the first driving transistor T14 is a PMOS TFT, and the threshold voltage of a PMOS TFT is negative, VCCG-|Vth,T14| and VCCG_R / G / B+Vth have the same value. When the constant current generator data voltage is applied to the source terminal of the first driving transistor T14, and transistor T10 is turned on according to the SCCG(n) signal, the second driving transistor T13 can operate as a source follower.

[0391] A source follower is also known as a common-drain amplifier because a DC voltage is applied to the drain terminal, and the gate terminal can be used as the input terminal, while the source terminal can be used as the output terminal. When an input voltage is applied to the gate terminal, the source follower has a DC characteristic, where a voltage corresponding to the difference between the input voltage and the source follower's threshold voltage is output from the source terminal, and for this reason, the source follower is also called a level shifter.

[0392] refer to Figure 13b Because the source terminal of the first driving transistor T14 is directly connected to the drain terminal of the second driving transistor T13, the second driving transistor T13 operates as a source follower when the constant current generator data voltage, which is a DC voltage, is applied to the source terminal of the first driving transistor T14 (i.e., the drain terminal of the second driving transistor T13).

[0393] In this example, because the reference voltage Vref is applied to the gate terminal of the second driving transistor T13, the voltage Vref-Vth, which corresponds to the difference between the reference voltage Vref and the threshold voltage Vth of the second driving transistor, can be output from the source terminal of the second driving transistor T13 (i.e., the other end of capacitor C3 (E node)).

[0394] More specifically, in the second driving transistor T13, when a DC voltage is applied to the drain terminal and a reference voltage Vref is applied to the gate terminal and the second driving transistor is turned on, the voltage at the source terminal can change with the current flow until the second driving transistor T13 is turned off. When a voltage Vref-Vth, corresponding to the difference between the reference voltage Vref and the threshold voltage Vth of the second driving transistor, is applied to the source terminal, the second driving transistor T13 is turned off, thereby outputting Vref-Vth at the source terminal.

[0395] According to an embodiment, when the second driving transistor T13 operates as a source follower, a threshold voltage of the second driving transistor T13 can be obtained at the source terminal of the second driving transistor T13. The threshold voltage of the second driving transistor T13 can then be coupled through capacitor C3 and applied to node B.

[0396] Figure 13b The Vref+|Vth,T13| indicated in the E node is simply a different representation of the same value as the aforementioned Vref-Vth. Specifically, Vref represents the reference voltage, and |Vth,T13| represents the threshold voltage of the second driving transistor T13. Because the second driving transistor T13 is a PMOS TFT, and the threshold voltage of a PMOS TFT is negative, Vref+|Vth,T13| and Vref-Vth can have the same value.

[0397] The Vini2(n) signal is a scan signal used to apply a reference voltage Vref to node A. In the data setup section, when a low voltage (e.g., -5 [V]) is applied to sub-pixel circuit 110 via the Vini2(n) signal line, transistor T17 is turned on, and the reference voltage can be applied to node A through the turned-on transistor T17.

[0398] Figure 13c This is a diagram illustrating the operation of the sub-pixel circuit 110 based on Vcomp(n) of the scan signal. Because the threshold voltage component of the second driving transistor T13 is... Figure 13c The timing period shown is applied to the gate terminal of the second drive transistor T13, so the data setting segment... Figure 13c The timing shown can be referred to as the threshold voltage compensation period.

[0399] The Vcomp(n) signal is a scan signal used to apply the threshold voltage of the second driving transistor T13 obtained at the source terminal E node of the second driving transistor T13 to the gate terminal B node of the second driving transistor T13.

[0400] like Figure 13c As shown, when a low voltage (e.g., -5V) is applied through the Vcomp(n) signal line, transistors T6 and T9 are turned on. Therefore, the threshold voltage Vth of the second driving transistor applied to node E can be coupled to node B through capacitor C3. Specifically, as described above, when the low-level Vini(n) signal, the low-level SCCG(n) signal, and the low-level Vini2(n) signal are applied, the voltages at nodes B and D are Vref, and the voltage at node E becomes Vref-Vth (i.e., Vref+|Vth, T13|), and the voltage at node A becomes Vref.

[0401] When a low-level Vcomp(n) signal is applied to the sub-pixel circuit 110 in this state, nodes B and D are short-circuited through the conducting transistor T9, and the reference voltage Vref is applied to node E through the conducting transistor T6.

[0402] When the Vcomp(n) signal is low, the Vini(n) signal goes high, and the Vini2(n) signal remains low. Therefore, node A maintains the reference voltage Vref, and the voltage change at node E is distributed and coupled to node B (or node D) by capacitors C3 and C1.

[0403] Specifically, because the voltage at node E changes from Vref-Vth to Vref as a low-level Vcomp(n) signal is applied, the voltage change at node E becomes +Vth, and node B is coupled to a voltage of +(C3 / (C1+C3))×Vth, causing the voltage at node B to become Vref+(C3 / (C1+C3))×Vth.

[0404] Figure 13c The Vref-(C3 / (C1+C3))×|Vth,T13| shown is simply another representation of the same value as the aforementioned Vref+(C3 / (C1+C3))×Vth. Vref represents the reference voltage, and |Vth,T13| represents the absolute value of the threshold voltage of the second driving transistor T13. Because the second driving transistor T13 is a PMOS TFT, and the threshold voltage of a PMOS TFT is negative, Vref-(C3 / (C1+C3))×|Vth,T13| and Vref+(C3 / (C1+C3))×Vth can have the same value.

[0405] Figure 13d This is a diagram illustrating the operation of the sub-pixel circuit 110 based on the SPWM(n) in the scan signal. Because the PWM data voltage used for grayscale representation is... Figure 13d The timing period shown is applied to the sub-pixel circuit 110, so the data setting segment Figure 13d The timing shown can be referred to as a programming period.

[0406] SPWM(n) is a scan signal used to apply the PWM data voltage (VPWM_R / G / B) to the sub-pixel circuit 110. In the data setting section, when a low voltage (e.g., -5 [V]) is applied to the sub-pixel circuit 110 through the SPWM(n) signal line, transistor T2 is turned on, and the PWM data voltage (e.g., VPWM) is applied to node A through the turned-on transistor T2.

[0407] When the SPWM(n) signal is low, the Vini2(n) signal goes high, and the Vcomp(n) signal remains low. Therefore, node E maintains the reference voltage Vref, and the voltage change at node A is distributed and coupled to node B (or node D) by capacitors C3 and C1.

[0408] In detail, when a low-level SPWM(n) signal is applied, the voltage at node A changes from Vref to VPWM, causing the voltage change at node A to become VPWM-Vref, and up to (C1 / (C1+C3))×(VPWM-Vref) voltage is coupled to node B.

[0409] As above Figure 13c As stated above, before applying the low-level SPWM(n) signal, the voltage at node B is Vref + (C3 / (C1 + C3)) × Vth. Figure 13c The voltage at node B becomes Vref+(C3 / (C1+C3))×Vth+(C1 / (C1+C3))×(VPWM-Vref).

[0410] As mentioned above, because the threshold voltage +Vth of the second driving transistor is equal to -|Vth,T13|, therefore Figure 13d The voltage at node B shown is equal to the value of Vref+(C3 / (C1+C3))×Vth+(C1 / (C1+C3))×(VPWM-Vref).

[0411] Figure 13e This is a diagram illustrating the operation of the sub-pixel circuit 110 based on the emitted signal Emi(n). Because the inorganic light-emitting element 120 is in... Figure 13e The light is emitted during the timing period shown, so Figure 13e The timing shown can be referred to as the transmission segment.

[0412] like Figure 13e As shown, when a low voltage (e.g., -5V) is applied through the Emi(n) signal line, transistors T12, T15, T8, T1, and T18 are turned on. The time interval during which the low-level Emi(n) signal is applied is called the transmit segment.

[0413] When the second driving transistor T13 and the first driving transistor T14 are turned on, and transistors T12 and T15 are also turned on, the first driving voltage VDD_PAM is applied to the anode terminal of the inorganic light-emitting element 120. Therefore, a potential difference exceeding the forward voltage Vf is generated across the inorganic light-emitting element 120, and a driving current (i.e., a constant current) flows through the inorganic light-emitting element 120 to make it emit light.

[0414] When the second driving transistor T13 is turned on, the first driving transistor T14 is also turned on.

[0415] Specifically, when transistors T12 and T15 are turned on according to the Emi(n) signal, in node C, as follows: Figure 13b As shown, a voltage (e.g., +0.8V) is applied as the sum of the constant current generator data voltage (e.g., +3V) and the threshold voltage (e.g., -2.2V). Therefore, when the first drive voltage VDD_PAM (e.g., +12V) is applied to the source terminal of the first drive transistor T14 as the second drive transistor T13 is turned on, the first drive transistor T14 will also turn on.

[0416] Whether the first driving voltage VDD_PAM is applied to the anode terminal of the inorganic light-emitting element 120 depends on the on / off operation of the second driving transistor T13.

[0417] Because the second driving transistor T13 is a PMOS TFT, it turns on when a voltage less than the threshold voltage Vth is applied between the gate and source terminals. It also turns on when the voltage at the gate terminal is less than the sum of the voltage at the source terminal and the threshold voltage. For example, when the first driving voltage VDD_PAM applied to the source terminal is +12 [V] and the threshold voltage Vth of the second driving transistor is -2.2 [V], the second driving transistor T13 turns on when a voltage less than +9.8 [V] is applied to the gate terminal.

[0418] In this regard, such as Figure 13e As shown, during the emitter phase, the gate terminal (B node) of the second driving transistor T13 is subjected to Vsweep - (C3 / (C1+C3)) × (|Vth, T13| + VPWM - Vref).

[0419] refer to Figure 13e When transistor T1 is turned on according to the Emi(n) signal, a portion of the scan signal Sweep is applied to node A simultaneously with the turn-on of transistor T1. In this example, a portion of the scan signal applied to node A becomes the scan voltage Vsweep. When the scan voltage Vsweep is applied to node A, the PWM data voltage VPWM, together with the scan voltage Vsweep, is coupled to node B through capacitor C1.

[0420] As described above, VPWM is applied to node A via a low-level SPWM(n) signal, and Vref + (C3 / (C1+C3)) × Vth + (C1 / (C1+C3)) × (VPWM - Vref) is applied to node B. In this state, when the sweep voltage Vsweep is applied to node A, the voltage at node A changes from VPWM to Vsweep. Since the voltage difference across capacitor C1 must remain constant, the voltage at node B changes by the same amount as the voltage change at node A (i.e., Vsweep - VPWM). Therefore, the voltage at node B becomes Vsweep - VPWM + Vref + (C3 / (C1+C3)) × Vth + (C1 / (C1+C3)) × (VPWM - Vref). In summary, Vsweep + (C3 / (C1+C3)) × (Vth - VPWM + Vref) is obtained, which is... Figure 13e The Vsweep-(C3 / (C1+C3))×(|Vth,T13|+VPWM-Vref) shown is the same.

[0421] At this point, if the capacitance of C3 is sufficiently large compared to the capacitance of C1, then C3 / (C1+C3) will have a value close to 1. Assuming C3 / (C1+C3) is 1, the voltage at node B in the emitter segment becomes Vsweep-|Vth,T13|-VPWM+Vref, and the conduction time of the second driving transistor T13 can be determined, regardless of the threshold voltage value of the second driving transistor, as described later. The threshold voltage of the second driving transistor T13 can be compensated.

[0422] Specifically, in Vsweep-|Vth,T13|-VPWM+Vref, the PWM data voltage VPWM, the reference voltage Vref, and the threshold voltage Vth,T13 of the second driving transistor all have fixed values. On the other hand, the scan voltage Vsweep has a value that varies linearly between, for example, +15[V] and +10[V].

[0423] Therefore, during the emitter phase, the voltage of node B varies according to the scan voltage Vsweep, and the second drive transistor T13 is turned on during the time period when the voltage of the changing node B (i.e., the gate terminal) (Vsweep+Vth-VPWM+Vref) is lower than the sum of the voltage of the source terminal (VDD_PAM) and the threshold voltage Vth (VDD_PAM+Vth).

[0424] Since both Vsweep+Vth-VPWM+Vref and VDD_PAM+Vth include Vth, the time period during which the second driving transistor T13 is turned on is determined, regardless of the value of Vth.

[0425] As described above, since the rate of change of the scanning voltage over time is constant, the duration for which the second driving transistor T13 is turned on in the emitter segment varies depending on the voltage at node B at the start of the emitter segment. Because the voltage at node B at the start of the emitter segment varies according to the VPWM value (i.e., the PWM data voltage value), the grayscale of the image can be represented by the PWM data voltage.

[0426] Reference Figures 14a to 14c The PWM operation of the sub-pixel circuit 110 described above will be described in more detail.

[0427] In the transmit section, the drive voltage applied to the constant current generator circuit 111 is changed from the second drive voltage VDD_PWM to the first drive voltage VDD_PAM.

[0428] As described above, in the data setting section, the second drive voltage VDD_PWM is applied to node F based on the Vini(n) signal. However, refer to Figure 13e The first driving voltage VDD_PAM is applied to one end (node ​​F) of capacitor C2 through transistors T12 and T8, which are turned on according to the Emi(n) signal.

[0429] In the emission section, due to the IR drop caused by the driving current flowing to the inorganic light-emitting element 120, a voltage drop may occur at the first driving voltage (VDD_PAM).

[0430] However, even if a voltage drop occurs at the first drive voltage (VDD_PAM), the voltage difference between the two ends of capacitor C2 (node ​​F and node C) remains as set during the data setting interval, and the image quality is unaffected.

[0431] According to an embodiment, the constant current generator data voltage of the constant current generator circuit 111 can be set by applying the constant current generator data voltage to node C based on the second drive voltage VDD_PWM, which has no voltage drop, separately from the first drive voltage VDD_PAM, regardless of the voltage drop of the first drive voltage VDD_PAM.

[0432] The constant current generator circuit 111 can operate precisely according to the constant current generator data voltage set in the data setting section, because a first drive voltage VDD_PAM that can have a voltage drop is used in the transmit section, but as described above, the voltage difference across capacitor C2 is maintained regardless of the voltage drop of the first drive voltage VDD_PAM.

[0433] In the emitter section, transistor T18 is turned on according to the low-level Emi(n) signal, and the reference voltage Vref is applied to node D through the turned-on transistor T18.

[0434] If Vref is not applied to node D during the transmit segment, then when Vref is applied to node D during the initialization period of the next image frame, the voltage change at node D is coupled to node E, causing the voltage at node E to be lower than the first drive voltage VDD_PAM. In this example, even when Vref is applied to node B, the second drive transistor T13 may not be turned on, which could lead to the problem that the threshold voltage of the second drive transistor T13 cannot be obtained during the threshold voltage sensing period.

[0435] Therefore, according to the embodiments, such as Figure 13e As shown, Vref can be applied to node D during the transmit segment. In this example, even though Vref is applied to node D during the initialization period of the next image frame, the first drive voltage VDD_PAM floats on node E because the voltage of node D does not change. Therefore, as referenced above... Figures 13a to 13dSpecifically, for the next image frame, the threshold voltage of the second driving transistor T13 can be obtained and compensated.

[0436] Figures 14a to 14c It shows that it has Figure 13a The diagram shows the PWM operation of the sub-pixel circuit configuration shown.

[0437] refer to Figures 14a to 14c Assume the capacitance of C3 is significantly greater than that of C1. In this example, C3 / (C1+C3) has a value close to 1, and C1 / (C1+C3) has a value close to 0, and referencing... Figures 14a to 14c Assume that C3 / (C1+C3) is 1 and C1 / (C1+C3) is 0.

[0438] refer to Figures 14a to 14c When the PWM data voltage corresponding to low grayscale is +4 [V], the PWM data voltage corresponding to medium grayscale is +7 [V], and the PWM data voltage corresponding to high grayscale is +14 [V], the PWM data voltage corresponding to each grayscale is not limited to these values.

[0439] Figures 14a to 14c The diagram shows the voltage changes at node A, node B, and drive current Id when PWM data voltages are applied to the sub-pixel circuits 110 included in the Nth and (N+36)th rows, respectively.

[0440] exist Figures 14a to 14c In the illustrated embodiment, the threshold voltage (Vth, T13) of the second driving transistor is -2.2 [V], the reference voltage Vref is +5 [V], and the first driving voltage VDD_PAM is +12 [V]. A scan signal (scan (global)) with a shape where the voltage linearly varies from +15 [V] to +10 [V] every 100 μs is used as an example. Here, (global) is an expression indicating that the scan signal is a global signal that is commonly applied to all row lines.

[0441] Figure 14a The illustration shows the case where a PWM data voltage (e.g., +4 [V]) corresponding to a low grayscale is applied to the sub-pixel circuit 110 included in the nth row line and the (n+36)th row line, respectively.

[0442] The operation of the sub-pixel circuit 110 included in the nth row will be described.

[0443] During the programming interval of the data setting section, +4 [V] (i.e., PWM data voltage) is applied to node A (n) of the sub-pixel circuit 110 included in the nth row line according to the SPWM(n) signal, and +2.8 [V] (i.e., Vref - |Vth, T13|) is applied to node B (n). The actual voltage applied to node B (n) during the programming period is Vref - (C3 / (C1+C3)) × |Vth, T13| + (C1 / (C1+C3)) × (VPWM - Vref), as shown. Figure 13d As shown, but C3 / (C1+C3) is 1 and C1 / (C1+C3) is 0, so Vref-(C3 / (C1+C3))×|Vth,T13|+(C1 / (C1+C3))×(VPWM-Vref) becomes Vref-|Vth,T13|.

[0444] When the transmission segment begins, some of the scan signals (scan (global)) based on the Emi(n) signal (i.e., the scan voltage (i.e., the voltage that changes linearly from +15[V] to +10[V])) are applied to node A(n).

[0445] Because the voltage change at node A (n) based on the scanning voltage is directly coupled to node B (n) through capacitor C1, when the voltage at node A (n) changes from +15 [V] to +10 [V], the voltage at node B (n) changes from +13.8 [V] to +8.8 [V].

[0446] As described above, the second driving transistor T13 is turned on during the time period when the voltage at the gate terminal B node is lower than the sum of the source terminal voltage VDD_PAM and the source terminal threshold voltage Vth, VDD_PAM+Vth.

[0447] During the period when the voltage at node B(n) is below +9.8 [V] (i.e., during the period when the voltage at node B(n) changes from +9.8 [V] to +8.8 [V]), the second driving transistor T13 is turned on, and during the period when the second driving transistor T13 is turned on, the driving current flows through the inorganic light-emitting element 120. Id(n) shows the change in driving current.

[0448] The operation of the sub-pixel circuit 110 included in the (n+36th)th row is described.

[0449] During the programming interval of the data setting section, +4[V] (i.e., PWM data voltage) is applied to node A (n+36) of the sub-pixel circuit 110 included in the n+36th row according to the SPWM(n+36) signal, and +2.8[V] (i.e., Vref-|Vth, T13|) is applied to node B (n+36).

[0450] Subsequently, when the transmission segment begins, the scan voltage (i.e., a linearly varying voltage that changes from +12.5[V] to +10[V] and from +15[V] to +12.5[V]) is applied to node A (n+36) as part of the scan signal (global) according to the Emi(n+36) signal.

[0451] In various embodiments, as described above, the transmission segments can be sequentially executed in the order of the rows, such that when the transmission segments are executed sequentially at intervals of 1H time (e.g., 1.4μs), the Emi(n+36) signal has the same waveform as the Emi(n) signal, but is delayed by 50.4μs.

[0452] Therefore, the scan voltage applied to node A (n+36) of the sub-pixel circuit 110 included in the (n+36)th row can have a waveform that linearly changes from +12.5 [V] to +10 [V] and then linearly changes from +15 [V] to +12.5 [V].

[0453] In other words, all scan voltages are scanned once between +15 [V] and +10 [V], but the starting voltage for the scan is variable depending on the row line.

[0454] Because the voltage change at node A (n+36) according to the scanning voltage is coupled to node B (n+36) as is through capacitor C1, the voltage at node B (n+36) changes from +12.5 [V] to +10 [V] at the same time as the voltage at node A (n+36) changes from +11.3 [V] to +8.8 [V], and when the voltage at node A (n+36) changes from +15 [V] to +12.5 [V], the voltage at node B (n+36) changes from +13.8 [V] to +11.3 [V].

[0455] In this example, during the time period when the voltage at node B (n+36) is below +9.8 [V], that is, during the time period when the voltage at node B (n+36) changes from +9.8 [V] to +8.8 [V], the second driving transistor T13 is turned on, and during the time the second driving transistor T13 is turned on, the driving current flows through the inorganic light-emitting element 120. Id(n+36) shows the change in driving current.

[0456] Figure 14b The illustration shows the case where a PWM data voltage (e.g., +7 [V]) corresponding to the medium grayscale is applied to the sub-pixel circuits 110 included in the nth and (n+36)th row lines, respectively.

[0457] The operation of the sub-pixel circuit 110 included in the nth row will be described.

[0458] During the data setting segment, +7[V] (i.e., PWM data voltage) is applied to node A(n) of the sub-pixel circuit 110 included in the nth row line according to the SPWM(n) signal, and +2.8[V] (i.e., Vref-|Vth, T13|) is applied to node B(n).

[0459] Subsequently, when the transmission segment begins, a scan voltage (i.e., the voltage changes linearly from +15[V] to +10[V]) is applied to node A(n) as part of the scan signal (scan(global)) according to the Emi(n) signal.

[0460] The voltage change at node A (n) based on the scanning voltage is coupled to node B (n) as is through capacitor (C1). Therefore, the voltage at node A (n) changes from +15 [V] to +10 [V], while the voltage at node B (n) changes from +10.8 [V] to +5.8 [V].

[0461] In this example, during the period when the voltage of node B (n) is below +9.8 [V], that is, during the time period when the voltage of node B (n) changes from +9.8 [V] to +5.8 [V], the second driving transistor T13 is turned on, and during the time period when the second driving transistor T13 is turned on, the driving current flows through the inorganic light-emitting element 120. Id(n) illustrates the above.

[0462] The operation of the sub-pixel circuit 110 included in the (n+36th)th row will be described.

[0463] During the programming interval in the data setting section, +7[V] (i.e., PWM data voltage) is applied to node A (n+36) of the sub-pixel circuit 110 included in the n+36th row according to the SPWM(n+36) signal, and +2.8[V] (i.e., Vref-|Vth|) is applied to node B (n+36).

[0464] Subsequently, when the transmission segment begins, the scan voltage (i.e., the voltage changes linearly from +12.5[V] to +10[V] and from +15[V] to +12.5[V]) is applied to node A (n+36) as part of the scan signal (scan (global)) according to the Emi(n+36) signal.

[0465] Because the voltage change at node A (n+36) according to the scanning voltage is coupled to node B (n+36) as is through capacitor C1, when the voltage at node A (n) changes from +12.5 [V] to +10 [V], the voltage at node B (n+36) changes from +8.3 [V] to +5.8 [V], and when the voltage at node A (n+36) changes from +15 [V] to +12.5 [V], the voltage at node B (n+36) changes from +10.8 [V] to +8.3 [V].

[0466] In this example, during the period when the voltage at node B (n+36) is below +9.8 [V], that is, during the time periods when the voltage at node B (n+36) changes from +8.3 [V] to +5.8 [V] and from +9.8 [V] to 8.3 [V], the second driving transistor T13 is turned on, and during the time the second driving transistor T13 is turned on, driving current flows through the inorganic light-emitting element 120. Id(n+36) illustrates the above.

[0467] refer to Figure 14b For the same PWM data voltage (+7V), the waveforms of Id(n) and Id(n+36) are different. However, since the integral value of the drive current, i.e., the brightness of the inorganic light-emitting element 120, is the same, this is not a problem.

[0468] Figure 14c The illustration shows the case where a PWM data voltage corresponding to high grayscale (e.g., +14 [V]) is applied to the sub-pixel circuits 110 included in the nth and (n+36)th row lines, respectively.

[0469] The operation of the sub-pixel circuit 110 included in the nth row will be described.

[0470] During the programming interval of the data setting section, +14[V] (i.e., PWM data voltage) is applied to node A(n) of the sub-pixel circuit 110 included in the nth row according to the SPWM(n) signal, and +2.8[V] (i.e., Vref-|Vth|) is applied to node B(n).

[0471] Subsequently, when the transmission segment begins, a scan voltage (i.e., the voltage changes linearly from +15[V] to +10[V]) is applied to node A(n) as part of the scan signal (scan(global)) according to the Emi(n) signal.

[0472] Because the voltage change at node A (n) based on the scanning voltage is coupled to node B (n) as is through capacitor C1, the voltage at node B (n) changes from +15 [V] to +10 [V] at the same time as the voltage at node A (n) changes from +3.8 [V] to -1.2 [V].

[0473] In this example, during the period when the voltage of node B (n) is below +9.8 [V], that is, during the time period when the voltage of node B (n) changes from +3.8 [V] to -1.2 [V], the second driving transistor T13 is turned on, and during the time period when the second driving transistor T13 is turned on, the driving current flows through the inorganic light-emitting element 120. Id(n) illustrates the above.

[0474] The operation of the sub-pixel circuit 110 included in the (n+36th)th row will be described.

[0475] During the programming interval of the data setting section, +14[V] (i.e., PWM data voltage) is applied to node A (n+36) of the sub-pixel circuit 110 included in the n+36th row according to the SPWM(n+36) signal, and +2.8[V] (i.e., Vref-|Vth|) is applied to node B (n+36).

[0476] Subsequently, when the transmission segment begins, the scan voltage (i.e., the voltage changes linearly from +12.5[V] to +10[V] and from +15[V] to +12.5[V]) is applied to node A (n+36) as part of the scan signal (scan (global)) according to the Emi(n+36) signal.

[0477] Because the voltage change at node A (n+36) based on the scanning voltage is coupled to node B (n+36) as is through capacitor C1, the voltage at node B (n+36) changes from +12.5 [V] to +10 [V] at the same time as the voltage at node A (n+36) changes from +1.3 [V] to -1.2 [V]. Furthermore, when the voltage at node A (n+36) changes from +15 [V] to +12.5 [V], the voltage at node B (n+36) changes from +3.8 [V] to +1.3 [V].

[0478] As described above, during the period when the voltage at node B (n+36) is below +9.8 [V], that is, during the time periods when the voltage at node B (n+36) changes from +1.3 [V] to -1.2 [V] and from +3.8 [V] to +1.3 [V], the second driving transistor T13 is turned on, and during the time periods when the second driving transistor T13 is turned on, the driving current flows through the inorganic light-emitting element 120. Id(n+36) illustrates the above.

[0479] refer to Figure 14c For the same PWM data voltage (+14V), the waveforms of Id(n) and Id(n+36) are slightly different. However, since the integral value of the drive current, i.e., the brightness of the inorganic light-emitting element 120, is the same, this is not a problem.

[0480] In the following text, reference will be made to Figures 15a to 17c Another embodiment is described. As referenced above... Figures 9a to 14c As described, when the second driving transistor operates as a source follower, a threshold voltage of the second driving transistor can be obtained, and the obtained threshold voltage is applied to the gate terminal of the second driving transistor, thereby compensating for the threshold voltage deviation of the second driving transistor.

[0481] However, the methods used to compensate for threshold voltage deviations in the second driving transistor are not limited to this. (See reference...) Figures 15a to 17c An embodiment of correcting the PWM data voltage to compensate for the threshold voltage deviation of the second drive transistor will be described.

[0482] Reference Figures 15a to 17c In the described embodiment, the number of transistors constituting the sub-pixel circuit is reduced compared to the embodiment described above, so this embodiment can be applied to display panels with higher resolution.

[0483] In reference Figures 15a to 17c In the described embodiments, in accordance with the above reference Figures 9a to 14c The described embodiment compensates for the threshold voltage deviation of the first driving transistor in the same manner.

[0484] Figure 15a This is a detailed circuit diagram of a sub-pixel circuit according to another embodiment. (See reference) Figure 15a The sub-pixel circuit 110 includes a constant current generator circuit 111, a PWM circuit 112, and a transistor T1. Specifically, the constant current generator circuit 111 includes a first driving transistor T11, and the PWM circuit 112 includes a second driving transistor T10.

[0485] Because transistor T13 has the same Figure 9a The transistor T16 has the same connection structure and function, so a redundant description of it is omitted. The test signal is also the same, and a redundant description of it is omitted as well.

[0486] The descriptions of VDD_PAM, VDD_PWM, and VSS are also consistent with... Figure 9a The descriptions are identical, and duplicate descriptions will be omitted.

[0487] and Figure 9a Unlike the sub-pixel circuit 110, the reference voltage Vref is not applied. Figure 15aThe sub-pixel circuit 110. In Figure 15a In one embodiment, when the sub-pixel circuit 110 is operating, it is not necessary to obtain the threshold voltage of the second driving transistor.

[0488] Vini(n) represents the scan signal applied to the sub-pixel circuit 110 during the data setting segment to apply the second drive voltage VDD_PWM to nodes B and D. The second drive voltage VDD_PWM applied to node B is used to keep the second drive transistor T10 in the off state during the data setting segment, and the second drive voltage VDD_PWM applied to node D becomes the reference potential when the constant current generator data voltage is set.

[0489] VST(n) represents the scan signal applied to the sub-pixel circuit 110 in the data setting section to initialize the voltage of node C. When the voltage of node C is initialized according to the VST(n) signal, the first driving transistor T11 is turned on.

[0490] SP(n) represents the scan signal applied to the sub-pixel circuit 110 to apply a constant current generator data voltage (VCCG_R / G / B) to node C and a PWM data voltage (VPWM_R / G / B) to node A in the data setting section. Here, the PWM data voltage VPWM_R / G / B can be a voltage reflecting a compensation value based on the threshold voltage deviation of the second drive transistor. The content of the compensation value will be described later in the description of the VPWM_R / G / B signal.

[0491] and Figure 9a Unlike the sub-pixel circuit 110, the Vcomp(n) signal was not applied. Figure 15a The sub-pixel circuit 110. In Figure 15a In one embodiment, during the operation of the sub-pixel circuit 110, it is not necessary to apply the threshold voltage of the second driving transistor to the B node.

[0492] Emi(n) refers to the emission signal applied to the sub-pixel circuit 110 to apply the first driving voltage VDD_PAM to nodes E and D in the emission section, apply the scan voltage to node A, and turn on transistor T12.

[0493] In the aforementioned gate signals (scan signal and transmit signal), n represents the nth row line. As described above, the driver 500 drives the display panel 110 for each row line (or scan line or gate line), and each of Vini(n), VST(n), SP(n), and Emi(n) can be applied equally to the sub-pixel circuit 110 included in the nth row line.

[0494] Scan refers to scanning the signal. Details of the scan signal are shown in the reference. Figure 9a The above description will be omitted, and repeated descriptions will be omitted.

[0495] VPWM_R / G / B represents the PWM data voltage applied to the sub-pixel circuit 110. The PWM data voltage can be applied from the data driver. According to an embodiment, the PWM data voltage of each of the R sub-pixels, G sub-pixels, and B sub-pixels constituting a pixel can be time-division multiplexed to be applied from the data driver. As described above, the time-division multiplexed PWM data voltage can be applied to the corresponding sub-pixel through a demultiplexer circuit.

[0496] Figure 15a The sub-pixel circuit 110 shown corresponds to one of the R, G, and B sub-pixels (e.g., the R sub-pixel). Therefore, in Figure 15a In the sub-pixel circuit 110, only the PWM data voltage of the R sub-pixel in the time-division multiplexed PWM data voltage can be selected and applied by the demultiplexer circuit.

[0497] Reference Figures 9a to 14c In the described embodiment, the PWM data voltage can be a voltage corresponding to the grayscale value of a sub-pixel, while the reference... Figures 15a to 17c The described PWM data voltage can be a voltage corresponding to a compensation value that reflects the grayscale value of a sub-pixel.

[0498] The compensation value is a value used to compensate for the brightness deviation of the sub-pixel based on the threshold voltage deviation of the second driving transistor, and can be calculated for each sub-pixel and stored in memory during the manufacturing of the display panel 100. Therefore, the TCON can read the compensation value stored in memory, reflect the compensation value in the image data, and send the image data reflecting the compensation value to the data driver, so that the PWM data voltage reflecting the compensation value can be applied to the sub-pixel circuit 110.

[0499] More specifically, for example, during a manufacturing operation, a test image (e.g., an image with the same grayscale value) can be displayed on a display panel 100, and the display panel 100 can be captured by an image capture device. When the test image is displayed, the compensation value has not yet been reflected, and in the captured image, blemishes or brightness differences may exist for each pixel due to deviations in the threshold voltage of the second driving transistor. Therefore, the compensation value for each sub-pixel can be calculated by calculating the grayscale value reflected in each sub-pixel, making blemishes or brightness deviations imperceptible in the captured image.

[0500] VCCG_R / G / B represents the constant current generator data voltage applied to the sub-pixel circuit 110. Because the description of the constant current generator data voltage is the same as above... Figure 9aThe same descriptions are as described above, so repeated descriptions will be omitted. Furthermore, the problems and solutions arising from the IR drop when the drive current flows in the emitter section are also the same as those described above. Figure 9a Since the descriptions are the same as those in the previous text, repeated descriptions will be omitted.

[0501] Figure 15b It is used to drive the image frame time and blanking interval. Figure 15a Timing diagram of various signals of the display panel 100 in the sub-pixel circuit 110. (Reference) Figure 15b The display panel 100 includes 312 rows.

[0502] As described above, according to the embodiment, for an image frame, each line can have one data setting segment and multiple transmission segments. Therefore, refer to... Figure 15b During the image frame time, the scan signals VST, SP, and Vini are applied once for each line line, and the emission signal Emi used for the emission operation can be applied multiple times for each line line.

[0503] The time interval between applying low levels to the VST, SP, and Vini signals becomes the data setting segment of the corresponding row line, and the time interval between applying low levels to the Emi signal becomes the transmission segment of the corresponding row line.

[0504] As described above, according to the embodiment, the data setting segment and the transmission segment can be arranged in the order of the rows. (Reference) Figure 15b Each of the gate signals VST, SP, Vini, and Emi can be applied sequentially according to the row line order. For example, with a 1H time difference (in Figure 15b In the example, a low-level VST(n) signal and a low-level VST(n+1) signal are applied at 1.4 μs. This is the same for the remaining gate signals SP (SP(n) and SP(n+1)), Vini (Vini(n) and Vini(n+1)), and Emi (Emi(n) and Emi(n+1)).

[0505] refer to Figure 15b A low-level test signal is applied during the blanking interval. Because the test signal is a global signal, it is applied equally to all sub-pixel circuits 110 of the display panel 100, so that the remaining charge on all inorganic light-emitting elements 120 of the display panel 100 can be released.

[0506] In the following text, reference will be made to Figures 16a to 16c describe Figure 15a Detailed operation of the sub-pixel circuit 110.

[0507] Figure 16aThe operation of the sub-pixel circuit 110 based on Vini(n) and VST(n) in the scan signal is shown.

[0508] When the data setting segment begins, driver 500 may first apply the second drive voltage VDD_PWM (e.g., +12 [V]) to the gate terminal (B node) of the second drive transistor T10 and one end of capacitor C2 (D node).

[0509] like Figure 16a As shown, driver 500 can apply a Vini(n) signal. (Reference) Figure 16a The VDD_PWM signal can be applied to nodes B and D by transistors T3 and T4, which are turned on according to the Vini(n) signal. At this time, when the constant current generator data voltage is set for node C, the second drive voltage VDD_PWM applied to node D becomes the reference potential.

[0510] When the second drive voltage VDD_PWM is applied to node D via the Vini(n) signal, driver 500 can initialize the voltage at node C, the gate terminal of the first drive transistor T11.

[0511] like Figure 16a As shown, the driver 500 can apply a low voltage (e.g., -5 [V]) to the sub-pixel circuit 110 via the VST(n) signal. When the voltage of node C is initialized to a low voltage (e.g., -5 [V]), the first driving transistor T11 can be in an on state (e.g., in a channel-forming state).

[0512] Figure 16b This is a diagram illustrating the operation of the sub-pixel circuit 110 based on SP(n) in the scan signal.

[0513] The SP(n) signal is a scan signal used to apply image data voltage to the sub-pixel circuit 110. In the data setting section, when a low voltage (e.g., -5 [V]) is applied to the sub-pixel circuit 110 through the SP(n) signal line, transistors T2, T17, and T8 are turned on.

[0514] When transistor T2 is turned on, the PWM data voltage (VPWM_R / G / B) can be applied to one end of capacitor C1, node A, through the turned-on transistor T2. At this time, the PWM data voltage reflects the compensation value.

[0515] When transistors T7 and T8 are turned on, the constant current generator data voltage (VCCG_R / G / B) can be applied to node C through the turned-on transistor T7, the first drive transistor T11 turned on based on the VST(n) signal, and the turned-on transistor T8.

[0516] At this point, instead of applying (or setting) the constant current generator data voltage (VCCG_R / G / B) as is in the C node, a constant current generator data voltage that compensates for the threshold voltage Vth of the first driving transistor T11 is applied (i.e., the voltage obtained by adding the threshold voltage of the first driving transistor T11 to the constant current generator data voltage (VCCG_R / G / B+Vth)).

[0517] Detailed instructions and references for applying VCCG_R / G / B+Vth to node C Figure 10b The operations described are the same, so redundant descriptions will be omitted.

[0518] Figure 16c This is a diagram illustrating the operation of the sub-pixel circuit 110 based on the transmitted signal Emi(n).

[0519] like Figure 16c As shown, when a low voltage (e.g., -5V) is applied through the Emi(n) signal line, transistors T6, T9, T12 and T1 are turned on.

[0520] When the second driving transistor T10 and the first driving transistor T11 are turned on, and simultaneously transistors T9 and T12 are turned on, the first driving voltage VDD_PAM is applied to the anode terminal of the inorganic light-emitting element 120. Therefore, a potential difference exceeding the forward voltage Vf is generated across the inorganic light-emitting element 120, and a driving current (i.e., a constant current) flows through the inorganic light-emitting element 120 to cause it to emit light.

[0521] When the second driving transistor T10 is turned on, the first driving transistor T11 is also turned on.

[0522] When transistors T9 and T12 are turned on according to the Emi(n) signal, a voltage (e.g., +0.8V) obtained by adding the constant current generator data voltage (e.g., +3V) and the threshold voltage of the first driving transistor T14 (e.g., -2.2V) is applied to node C, as described above. Figure 16b As described above. Therefore, as the second driving transistor T10 is turned on, the first driving transistor T11 is also turned on when the first driving voltage VDD_PAM (e.g., +12 [V]) is applied to the source terminal of the first driving transistor T11.

[0523] Therefore, whether the first driving voltage VDD_PAM will be applied to the anode terminal of the inorganic light-emitting element 120 can be determined based on the on / off operation of the second driving transistor T10.

[0524] Because the second driving transistor T10 is a PMOS TFT, it turns on when a voltage less than the threshold voltage Vth is applied between the gate and source terminals. The second driving transistor T10 turns on when the voltage at the gate terminal is less than the sum of the voltage at the source terminal (E node) and the threshold voltage Vth. For example, when the first driving voltage VDD_PAM applied to the source terminal (E node) is +12 [V] and the threshold voltage Vth of the second driving transistor is -2.2 [V], the second driving transistor T10 can turn on when a voltage less than +9.8 [V] is applied to the gate terminal (B node).

[0525] In this regard, during the emitter phase, Vsweep-VPWM_R / G / B+VDD_PWM is applied to the gate terminal (B node) of the second drive transistor T10.

[0526] refer to Figure 16c When transistor T1 is turned on according to the Emi(n) signal, a portion of the scan signal (scan) is applied to node A simultaneously with the turn-on of transistor T1. At this time, part of the scan signal applied to node A becomes the scan voltage (Vsweep). When the scan voltage Vsweep is applied to node A, the PWM data voltage VPWM_R / G / B, together with the scan voltage Vsweep, is coupled to node B via capacitor C1. Specifically, during the data setting segment as described above, VPWM_R / G / B is applied to node A, and VDD_PWM is applied to node B. In this state, when the scan voltage Vsweep is applied to node A, the voltage of node A changes from VPWM_R / G / B to Vsweep. Because the voltage difference across capacitor C1 must remain constant, the voltage of node B also changes as much as the voltage change of node A (i.e., Vsweep - VPWM_R / G / B). Therefore, the voltage of node B becomes Vsweep - VPWM_R / G / B + VDD_PWM.

[0527] At this time, the PWM data voltage VPWM_R / G / B and the second drive voltage VDD_PWM have fixed values, while the scan voltage Vsweep has a value that varies linearly between +5 [V] and +0 [V].

[0528] Therefore, during the emitter segment, the voltage of node B varies according to the scan voltage Vsweep, and the second drive transistor T10 is turned on during the time period when the voltage Vsweep-VPWM_R / G / B+VDD_PWM of node B (i.e., the gate terminal) is lower than the voltage (VDD_PAM+Vth) which is the sum of the voltage VDD_PAM of the source terminal (E node) and the threshold voltage Vth.

[0529] As described above, because the rate of change of the scanning voltage with respect to time is constant, the period during which the second driving transistor T10 is turned on in the emitter segment varies depending on the voltage at node B at the start of the emitter segment. At this time, the voltage at node B at the start of the emitter segment varies according to the VPWM_R / G / B value (i.e., the PWM data voltage value), thus the grayscale of the image can be represented by the PWM data voltage.

[0530] Reference Figures 17a to 17c The PWM operation of the sub-pixel circuit 110 described above will be described in more detail.

[0531] In the transmit section, the drive voltage applied to the constant current generator circuit 111 is changed from the second drive voltage VDD_PWM to the first drive voltage VDD_PAM.

[0532] As described above, in the data setting section, the second drive voltage VDD_PWM is applied to node D based on the Vini(n) signal. However, refer to Figure 16c The first driving voltage VDD_PAM is applied to one end (node ​​D) of capacitor C2 through transistors T9 and T6, which are turned on according to the Emi(n) signal.

[0533] In the emission section, a voltage drop may occur in the first driving voltage VDD_PAM due to the IR drop generated when the driving current flows to the inorganic light-emitting element 120. However, even if a voltage drop occurs in the first driving voltage VDD_PAM, the voltage difference between the two ends of capacitor C2 (node ​​D and node C) remains as set in the data setting section, and therefore, the image quality is not affected.

[0534] According to an embodiment, the constant current generator data voltage of the constant current generator circuit 111 can be set by applying the constant current generator data voltage to node C based on the second drive voltage VDD_PWM, which has no voltage drop, separately from the first drive voltage VDD_PAM, regardless of the voltage drop of the first drive voltage VDD_PAM.

[0535] Furthermore, in the transmit section, a first drive voltage VDD_PAM that can cause a voltage drop is used. However, as mentioned above, regardless of the voltage drop of the first drive voltage VDD_PAM, the voltage difference across capacitor C2 is maintained. Therefore, the constant current generator circuit 111 can operate precisely according to the voltage set in the data setting section.

[0536] Figures 17a to 17c It shows that it has Figure 15a A view of the PWM operation of the sub-pixel circuit configuration shown. (Reference) Figures 17a to 17cThe PWM data voltage corresponding to low grayscale is +3 [V], the PWM data voltage corresponding to medium grayscale is +7 [V], and the PWM data voltage corresponding to high grayscale is +13 [V], but the PWM data voltage corresponding to each grayscale is not limited to these values. Each of the PWM data voltage values ​​(+3 [V], +7 [V], +13 [V]) is a value reflecting the above compensation value.

[0537] Figures 17a to 17c The diagram shows the voltage change at node A, the voltage at node B, and the drive current Id when PWM data voltages are applied to the sub-pixel circuits 110 included in the nth and (n+36th)th row lines, respectively.

[0538] exist Figures 17a to 17c In the illustrated embodiment, the threshold voltage Vth of the second driving transistor is -2.2 [V], and the first driving voltage VDD_PAM is +12 [V]. Furthermore, a scan signal (scan (global)) with a shape where the voltage linearly varies from +5 [V] to +0 [V] every 100 μs is used as an example. Here, (global) is an expression indicating that the scan signal is a global signal that is commonly applied to all row lines.

[0539] Figure 17a An example is shown in which a PWM data voltage (e.g., +3 [V]) corresponding to a low grayscale is applied to the sub-pixel circuit 110 included in the nth row line and the (n+36)th row line, respectively.

[0540] The operation of the sub-pixel circuit 110 included in the nth row will be described.

[0541] During the data setting segment, +3[V] (i.e., PWM data voltage) is applied to node A(n) of the sub-pixel circuit 110 included in the nth row according to the SP(n) signal, and +12[V] (i.e., second drive voltage VDD_PWM) is applied to node B(n) according to the Vini(n) signal.

[0542] After the start of the transmission segment, a portion of the scan signal (scan (global), i.e., the scan voltage (i.e., the voltage that changes linearly from +5 [V] to +0 [V])) is applied to node A (n), as shown in the figure.

[0543] Because the voltage change of node A (n) according to the scanning voltage is coupled to node B (n) through capacitor C1, the voltage of node B (n) changes from +5 [V] to +0 [V] at the same time as the voltage of node A (n) changes from +14 [V] to +9 [V].

[0544] As described above, the second driving transistor T10 is turned on during the time period when the voltage at the gate terminal B node is lower than the sum of the source terminal voltage VDD_PAM and the threshold voltage Vth, VDD_PAM+Vth.

[0545] During the time when the voltage at node B(n) is below +9.8[V] (i.e., during the time when the voltage at node B(n) changes from +9.8[V] to +9[V]), the second driving transistor T10 is turned on, and during the time when the second driving transistor T10 is turned on, the driving current flows through the inorganic light-emitting element 120. Id(n) shows the change in driving current.

[0546] The operation of the sub-pixel circuit 110 included in the (n+36th)th row will be described.

[0547] During the data setting segment, +3[V] (i.e., PWM data voltage) is applied to node A (n+36) of the sub-pixel circuit 110 included in the (n+36) row according to the SP(n+36) signal, and +12[V] (i.e., second drive voltage VDD_PWM) is applied to node B (n+36) according to the Vini(n+36) signal.

[0548] Subsequently, when the transmission segment begins, the scan voltage (i.e., the voltage changes linearly from +2.5[V] to +0[V] and from +5[V] to +2.5[V]) is applied to node A (n+36) as part of the scan signal (scan (global)) according to the Emi(n+36) signal.

[0549] More specifically, as described above, in various embodiments, the transmission segments are executed sequentially in the order of the rows, such that when the transmission segments are executed sequentially at intervals of 1H time (e.g., 1.4μs), the Emi(n+36) signal has the same waveform as the Emi(n) signal, but is delayed by 50.4μs.

[0550] Therefore, the scan voltage applied to node A (n+36) of the sub-pixel circuit 110 included in the (n+36)th row can have a waveform that linearly changes from +2.5 [V] to +0 [V] and then linearly changes from +5 [V] to +2.5 [V].

[0551] In other words, all scan voltages are scanned once between +5 [V] and +0 [V], but the starting voltage for the scan is variable depending on the row line.

[0552] Because the voltage change at node A (n+36) based on the scanning voltage is coupled to node B (n+36) as is through capacitor C1, the voltage at node B (n+36) changes from +2.5V to +0V at the same time as the voltage at node A (n+36) changes from +11.5V to +9V. Furthermore, when the voltage at node A (n+36) changes from +5V to +2.5V, the voltage at node B (n+36) changes from +14V to +11.5V.

[0553] As described above, during the period when the voltage at node B (n+36) is below +9.8 [V], that is, during the period when the voltage at node B (n+36) changes from +9.8 [V] to +9 [V], the second driving transistor T10 is turned on, and during the period when the second driving transistor T10 is turned on, the driving current flows through the inorganic light-emitting element 120. Id(n+36) shows the change in driving current.

[0554] Figure 17b The illustration shows the case where a PWM data voltage (e.g., +7 [V]) corresponding to the medium grayscale is applied to the sub-pixel circuits 110 included in the nth and (n+36)th row lines, respectively.

[0555] The operation of the sub-pixel circuit 110 included in the nth row will be described.

[0556] During the data setting segment, +7[V] (i.e., PWM data voltage) is applied to node A(n) of the sub-pixel circuit 110 included in the nth row according to the SP(n) signal, and +12[V] (i.e., second drive voltage VDD_PWM) is applied to node B(n) according to the Vini(n) signal.

[0557] Subsequently, when the transmission segment begins, a scan voltage (i.e., the voltage changes linearly from +5[V] to +0[V]) is applied to node A(n) as part of the scan signal (scan(global)) according to the Emi(n) signal.

[0558] Because the voltage change of node A (n) according to the scanning voltage is coupled to node B (n) as is through capacitor C1, the voltage of node B (n) changes from +5 [V] to +0 [V] at the same time as the voltage of node A (n) changes from +10 [V] to +5 [V].

[0559] In this example, during the time when the voltage of node B(n) is below +9.8[V] (i.e., the time period during which the voltage of node B(n) changes from +9.8[V] to +5[V]), the second driving transistor T10 is turned on, and during the time interval during which the second driving transistor T10 is turned on, driving current flows through the inorganic light-emitting element 120. Id(n) illustrates the above.

[0560] The operation of the sub-pixel circuit 110 included in the (n+36th)th row will be described.

[0561] During the data setting segment, +7[V] (i.e., PWM data voltage) is applied to node A (n+36) of the sub-pixel circuit 110 included in the n+36th row according to the SP(n+36) signal, and +12[V] (i.e., second drive voltage VDD_PWM) is applied to node B (n+36) according to the Vini(n+36) signal.

[0562] Subsequently, when the transmission segment begins, the scan voltage (i.e., the voltage changes linearly from +2.5[V] to +0[V] and from +5[V] to +2.5[V]) is applied to node A (n+36) as part of the scan signal (scan (global)) according to the Emi(n+36) signal.

[0563] Because the voltage change of node A (n+36) according to the scanning voltage is coupled to node B (n+36) as is through capacitor C1, at the same time that the voltage of node A (n) changes from +2.5 [V] to +0 [V], the voltage of node B (n+36) changes from +7.5 [V] to +5 [V], and when the voltage of node A (n+36) changes from +5 [V] to +2.5 [V], the voltage of node B (n+36) changes from +10 [V] to +7.5 [V].

[0564] In this example, during the time when the voltage at node B (n+36) is below +9.8 [V], that is, during the time periods when the voltage at node B (n+36) changes from +7.5 [V] to +5 [V] and from +9.8 [V] to 7.5 [V], the second driving transistor T10 is turned on, and during the time the second driving transistor T10 is turned on, the driving current flows through the inorganic light-emitting element 120. Id(n+36) illustrates the above.

[0565] refer to Figure 17b For the same PWM data voltage (+7V), the waveforms of Id(n) and Id(n+36) are different. However, since the integral value of the drive current, i.e., the brightness of the inorganic light-emitting element 120, is the same, this is not a problem.

[0566] Figure 17c The illustration shows the case where a PWM data voltage corresponding to high grayscale (e.g., +13 [V]) is applied to the sub-pixel circuits 110 included in the nth and (n+36)th row lines, respectively.

[0567] The operation of the sub-pixel circuit 110 included in the nth row will be described.

[0568] During the programming interval of the data setting section, +13[V] (i.e., PWM data voltage) is applied to node A(n) of the sub-pixel circuit 110 included in the nth row according to the SP(n) signal, and +12[V] (i.e., second drive voltage VDD_PWM) is applied to node B(n) according to the Vini(n) signal.

[0569] Subsequently, when the transmission segment begins, a scan voltage (i.e., the voltage changes linearly from +5[V] to +0[V]) is applied to node A(n) as part of the scan signal (scan(global)) according to the Emi(n) signal.

[0570] Because the voltage change of node A (n) according to the scanning voltage is coupled to node B (n) as is through capacitor C1, the voltage of node B (n) changes from +5 [V] to 0 [V] at the same time as the voltage of node A (n) changes from +4 [V] to -1 [V].

[0571] In this example, the second driving transistor T10 is turned on during the time when the voltage of node B(n) is below +9.8[V] (i.e., the time period during which the voltage of node B(n) changes from +4[V] to -1[V]), and during the time period during which the second driving transistor T10 is turned on, driving current flows through the inorganic light-emitting element 120. Id(n) shows the change in driving current.

[0572] The operation of the sub-pixel circuit 110 included in the (n+36th)th row will be described.

[0573] During the programming interval of the data setting section, +13[V] (i.e., PWM data voltage) is applied to node A (n+36) of the sub-pixel circuit 110 included in the n+36th row according to the SP(n+36) signal, and +12[V] (i.e., second drive voltage VDD_PWM) is applied to node B (n+36) according to the Vini(n+36) signal.

[0574] Subsequently, when the transmission segment begins, the scan voltage (i.e., the voltage changes linearly from +2.5[V] to +0[V] and from +5[V] to +2.5[V]) is applied to node A (n+36) as part of the scan signal (scan (global)) according to the Emi(n+36) signal.

[0575] Because the voltage change at node A (n+36) based on the scanning voltage is coupled to node B (n+36) as is through capacitor C1, the voltage at node B (n+36) changes from +2.5V to 0V at the same time as the voltage at node A (n+36) changes from +1.5V to -1V. Furthermore, when the voltage at node A (n+36) changes from +5V to +2.5V, the voltage at node B (n+36) changes from +4V to +1.5V.

[0576] As described above, during the time period when the voltage at node B (n+36) is below +9.8 [V], that is, during the time periods when the voltage at node B (n+36) changes from +1.5 [V] to -1 [V] and from +4 [V] to +1.5 [V], the second driving transistor T10 is turned on, and during the time period when the second driving transistor T10 is turned on, the driving current flows through the inorganic light-emitting element 120. Id(n+36) shows the change in driving current.

[0577] refer to Figure 17c For the same PWM data voltage (+13V), the waveforms of Id(n) and Id(n+36) are slightly different. However, since the integral value of the drive current, i.e., the brightness of the inorganic light-emitting element 120, is the same, this is not a problem.

[0578] Hereinafter, a method for driving a modular display panel according to an embodiment will be described.

[0579] Figure 18 This is a schematic diagram illustrating the configuration of a display device according to an embodiment. (Reference) Figure 18 The display device 10000 may include nine display modules 1000-1 to 1000-9. The display device 10000 may also include a TCON.

[0580] As shown in the figure, display modules 1000-1 to 1000-9 can be assembled or arranged in a matrix to form a modular display panel. Although Figure 18 The display device 10000 shown includes nine display modules, but display devices with different sizes or resolutions can be achieved by combining different numbers of display modules.

[0581] The configuration and driving method for each of the display modules 1000-1 to 1000-9 can be found in the above reference. Figures 4 to 17c The description provided is as follows. As described above, each of the display modules 1000-1 to 1000-9 can be driven in a progressive driving manner.

[0582] For example, when displaying image frames on a modular display panel, each of display modules 1000-1 to 1000-9 can be in the manner shown below. Figure 6a Drive in the manner shown, and can be as follows Figure 6b The drive is performed as shown.

[0583] In such Figure 6a In the case of the display module driving method shown, since the data setting segment of an image frame is executed during one image frame time, the data setting segment of each display module should be executed simultaneously when an image frame is displayed on the modular display panel.

[0584] As described above, the modular display panel driving method that simultaneously executes the data setting sections of each display module constituting the modular display panel is called the "simultaneous scanning method".

[0585] In such Figure 6b In the case of the display module driving method shown, since the data setting segment of an image frame can be performed in a much shorter time than the time of an image frame, when an image frame is displayed on the modular display panel, the data setting segment of each display module can be executed continuously in the order of the data setting segments of the adjacent display modules set above or below the corresponding display module.

[0586] As described above, the driving method for a modular display panel, in which the data setting sections of each display module constituting the modular display panel follow the progression order of the data setting sections of adjacent display modules located above or below the corresponding display module, can be called a "high-speed continuous scanning method." Here, "high-speed" means faster than... Figure 6a The driving method shown executes the data setting segment at a higher speed.

[0587] Figure 19a and Figure 19b The method of executing the data setting segment and the emission segment is shown when the modular display panel is driven in simultaneous scanning mode and high-speed continuous scanning method, respectively.

[0588] For example, in Figure 19a and Figure 19b In the modular display panel, where 81 display modules are arranged in a 9×9 matrix, nine display modules within the same column are shown displaying three consecutive image frames over four image frame periods. Figure 19a and Figure 19b In this process, for a single image frame, one data setup segment and four emission segments are executed for each line. Figure 19a and Figure 19bIn this design, each display module that makes up the modular display panel is 12.7 inches in size, has a resolution of 550×312, and a scan rate of 240Hz.

[0589] Since each display module has a resolution of 550×312, each display module includes 312 row lines. Therefore, a 9×9 modular display panel includes 2808 row lines, and Figure 16a and Figure 16b The vertical position axis represents 2808 line lines. Since each display module has a scan rate of 240Hz, one image frame time is approximately 4.16ms. Therefore, refer to... Figure 19a and Figure 19b The timeline shows that the display module's driving scheme is represented by four image frame times.

[0590] In the simultaneous scanning method, as described above, the data setting segments for each display module are performed simultaneously. (See reference...) Figure 19a For an image frame, the data setting segment for the first row line of each of the nine display modules is performed simultaneously, and the data setting segment for the second row line of each of the nine display modules is performed simultaneously, and in this way, the data setting segments are performed simultaneously up to the 312th row line of each of the nine display modules.

[0591] As described above, because the transmission segment is performed after the data setting segment in a predetermined manner (i.e., the first transmission segment of the plurality of transmission segments is sequential in time with the data setting segment, and each of the transmission segments is processed at a predetermined time interval), each transmission segment of each display module is also performed simultaneously in the simultaneous scanning mode.

[0592] When the modular display panel is driven by the simultaneous scanning method described above, for the same image frame, the emission segments are discontinuous at the boundaries of adjacent upper and lower display modules.

[0593] More specifically, see reference Figure 19a When the display modules from the topmost to the bottommost are referred to as the first to ninth display modules, for example, for the 313th row (the first row of the second display module), four transmission segments are performed for the first image frame during the time period from 0 to 4.16 ms. However, in the case of the 312th row (the last row of the first display module), the transmission segments may not even be performed once during the same time period. For the 312th row, four transmission segments can be performed for the first image frame during the time period from 4.16 ms to 8.33 ms. However, during the same time period, the 313th row performs four transmission segments for the second image frame.

[0594] Therefore, when a moving object (e.g., a vertical line moving left or right) is displayed on a modular display panel in a simultaneous scanning manner, image distortion can be seen at the boundary between adjacent upper and lower display modules.

[0595] When displaying still images, distortion is not visible at the boundary between the upper and lower modules because the same image frames are repeated. When the left and right display modules are adjacent to each other (e.g., nine display modules in the same row of a 9×9 modular display panel), the emission segments of the same row of each display module can be emitted simultaneously, so the aforementioned distortion does not occur even when displaying moving objects.

[0596] In the case of the high-speed continuous scanning method, as described above, a data setting segment can be executed in each display module within a time much shorter than one frame. Therefore, according to the embodiment, a modular display panel can be driven such that, during one frame, the data setting segment is performed continuously from the first row line of the uppermost display module to the last row line of the lowermost display module using the high-speed continuous scanning method.

[0597] For example, when the display modules included in the same column of a 9×9 modular display panel are referred to as the first to ninth display modules, from the topmost display module to the bottommost display module, such as... Figure 19b As shown, the data setting segment can be continuously processed from the first row line (the first row line of the first display module) to the 2808th row line (the last row line of the ninth display module) within one frame.

[0598] As described above, since the transmission segment is performed after the data setting segment in a predetermined manner (i.e., the first transmission segment of the plurality of transmission segments is sequential in time with the data setting segment, and each of the transmission segments is performed at a predetermined time interval), each transmission segment of each display module can also be performed continuously from the first row line to the 2808th row line.

[0599] When a modular display panel is driven using the high-speed continuous scanning method described above, unlike the simultaneous scanning method, the emission segments can be performed continuously even at the boundary between adjacent upper and lower display modules. Therefore, even when a moving object (e.g., a vertical line moving left or right) is displayed on the modular display panel, image distortion does not occur at the boundary between adjacent upper and lower display modules.

[0600] In the following text, reference will be made to Figures 20 to 21b A method for driving a modular display panel according to an embodiment is described.

[0601] Figure 20 This is a block diagram of a display device according to an embodiment.

[0602] refer to Figure 20 The display device 10000 may include multiple display modules 1000-1 to 1000-n and a timing controller 2000.

[0603] like Figure 18 As shown, multiple display modules 1000-1 to 1000-n can be coupled or assembled in a matrix to form a modular display panel.

[0604] Each of the display modules 1000-1 to 1000-n may include a display panel 100. Here, the display panel 100 may include a pixel array and sub-pixel circuits corresponding to inorganic light-emitting elements of the pixel array, wherein pixels composed of a plurality of inorganic light-emitting elements are arranged in a plurality of row lines.

[0605] Each of the display modules 1000-1 to 1000-n may include a gate driver for driving sub-pixel circuits in the row line sequence based on various signals (e.g., clock signal, start signal (VST) etc.) provided by TCON2000, such that the inorganic light-emitting elements of the pixel array emit light in the row line sequence.

[0606] Figure 21a This is a block diagram illustrating a method for driving a gate driver according to an embodiment. (Reference) Figure 21a The gate driver 500' may include unit circuits G1 to Gn corresponding to the row lines respectively, and each of the unit circuits G1 to Gn may receive a drive voltage, a clock signal, a control signal and a start signal VST to output gate signals S1 to Sn corresponding to each row line.

[0607] In this example, the unit circuit can receive the output signal of the unit circuit corresponding to the previous row as a start signal. As shown, G2 can receive the output signal S1 of G1 as a start signal, and G3 can receive the output signal S2 of G2 as a start signal. This is the same before Gn. Because the unit circuit G1 corresponding to the first row does not have a previous row, the start signal VST can be provided to the unit circuit G1 separately from TCON 2000.

[0608] Therefore, the gate driver 500' can sequentially output gate signals S1 to Sn in the order of the row lines based on the start signal VST provided by TCON 2000.

[0609] The gate driver may include a scan driver for providing scan signals to the sub-pixel circuits in the order of the row lines, such that image data voltages are set to the sub-pixel circuits in the order of the row lines. As described above, since the scan signals include VST(n), SP(n), Vcomp(n), SCCG(n), SPWM(n), Vini(n), and Vini2(n), each of the display modules 1000-1 to 1000-n may include at least one scan driver for providing each scan signal (VST(n), SP(n), Vcomp(n), SCCG(n), SPWM(n), Vini(n), and Vini2(n)).

[0610] Therefore, for example, the scan driver for providing the VST(n) signal can provide the scan signal VST(n) in row line order based on the start signal provided by TCON 2000. The scan driver for providing the SP(n) signal can provide the scan signal SP(n) in row line order based on the start signal provided by TCON 2000. The scan driver for providing the SCCG(n) signal can provide the scan signal SCCG(n) in row line order based on the start signal provided by TCON 2000. The scan driver for providing the SPWM(n) signal can provide the scan signal SPWM(n) in row line order based on the start signal provided by TCON 2000. The scan driver for providing the Vcomp(n) signal can provide the scan signal Vcomp(n) in row line order based on the start signal provided by TCON 2000. The scan driver for providing the Vini(n) signal can provide the scan signal Vini(n) in row line order based on the start signal provided by TCON 2000. The scan driver used to provide the Vini2(n) signal can provide the scan signal Vini2(n) in the order of the row lines based on the start signal provided by TCON 2000.

[0611] The gate driver may include an emitter driver that provides emitter signals to the sub-pixel circuitry in the order of the row lines, such that the inorganic light-emitting elements of the pixel array emit light in the order of the row lines based on image data voltages set according to the scan signal. As described above, because the emitter signal includes Emi(n), each of the display modules 1000-1 to 1000-n may include an emitter driver for providing the emitter signal Emi(n).

[0612] The transmit driver used to provide the Emi(n) signal can provide the transmit signal Emi(n) in the order of the row lines based on the start signal provided by TCON 2000.

[0613] The TCON 2000 controls the overall operation of the display device 10000. According to an embodiment, the TCON 2000 can drive the modular display panel in a high-speed continuous scanning manner. In the following text, for convenience... Figure 18 The 3×3 modular display panel shown is described as an example. Figure 21b Display modules 1000-1, 1000-4, and 1000-7 are shown in the first column of a plurality of display modules 1000-1 to 1000-9.

[0614] TCON 2000 can control the driver 500 of each of the display modules 1000-1, 1000-4 and 1000-7, so that the inorganic light-emitting elements of the display modules 1000-1, 1000-4 and 1000-7 arranged in the first column line of the multiple display modules 1000-1 to 1000-9 arranged in a matrix emit light sequentially from the first row line of the display module 1000-1 to the last row line of the display module 1000-7.

[0615] As described above, since the gate driver 500' of each display module outputs the gate signal in the order of the row lines based on the start signal VST provided by TCON 2000, TCON 2000 can control the timing of providing the start signal to control the driving timing of each display module.

[0616] refer to Figure 21b TCON 2000 can provide a first start signal VST1 to the gate driver 500'-1 of the first display module 1000-1, so that the inorganic light-emitting elements of the first display module 1000-1 in the display modules 1000-1, 1000-4 and 1000-7 arranged in the first column line emit light sequentially from the first row line to the last row line.

[0617] When the first start signal VST1 is provided, the scan driver and the emitter driver of the first display module 1000-1 can provide scan signals and emitter signals to the sub-pixel circuits included in the display panel 100-1 in the order of the row lines.

[0618] TCON 2000 can provide a second start signal VST2 to the gate driver 500'-4 of the second display module 1000-4, so that the inorganic light-emitting elements of the second display module 1000-4, which is disposed adjacent to the lower part of the first display module 1000-1, emit light in the row line sequence after the light-emitting sequence of the inorganic light-emitting elements included in the last row line of the first display module 1000-1.

[0619] TCON 2000 can provide a second start signal VST2 to the gate driver 500'-4 of the second display module 1000-4, such that the sub-pixel circuits included in the first row line of the second display module 1000-4 are driven after the driving sequence of the sub-pixel circuits included in the last row line of the first display module 1000-1.

[0620] When the second start signal VST2 is provided, the scan driver and the emitter driver of the second display module 1000-4 can sequentially provide scan signals and emitter signals to the sub-pixel circuits included in the display panel 100-4 in the order of the row lines.

[0621] TCON 2000 can provide a third start signal VST3 to the gate driver 500'-7 of the third display module 1000-7, so that the inorganic light-emitting elements of the third display module 1000-7, which is disposed adjacent to the lower part of the second display module 1000-4, emit light in the row line sequence after the light-emitting sequence of the inorganic light-emitting elements included in the last row of the second display module 1000-4.

[0622] TCON 2000 can provide a third start signal VST3 to the gate driver 500'-7 of the third display module 1000-7, such that the sub-pixel circuits included in the first row line of the third display module 1000-7 are driven after the driving sequence of the sub-pixel circuits included in the last row line of the second display module 1000-4.

[0623] When the third start signal VST3 is provided, the scan driver and emit driver of the third display module 1000-7 can provide scan signals and emit signals to the sub-pixel circuits included in the display panel 100-7 in the order of the row lines.

[0624] Although the operation of display modules 1000-1, 1000-4 and 1000-7 set in the first column line has been described above, the operation of display modules 1000-2, 1000-5 and 1000-8 set in the second column line or display modules 1000-3, 1000-6 and 1000-9 set in the third column line is the same.

[0625] As described above, by driving the modular display panel with a high-speed continuous scanning method, the visible image distortion at the boundary between the upper and lower display modules when driving the panel with a simultaneous scanning method can be fundamentally eliminated.

[0626] Although Figure 20In the display device 10000, a plurality of display modules 1000-1 to 1000-n are controlled by a timing controller 2000, but the embodiments are not limited thereto. According to an embodiment, the display device 10000 may include at least one timing controller for controlling the plurality of display modules 1000-1 to 1000-n.

[0627] As described above, according to various embodiments, by using an active matrix (AM) method to drive inorganic light-emitting elements in PWM mode, the phenomenon of wavelength variation of light emitted by inorganic light-emitting elements with grayscale can be prevented. Furthermore, blemishes caused by differences in threshold voltages between driving transistors can be significantly eliminated. Additionally, color correction can be facilitated. In display devices comprising a single display module or a modular display panel comprising multiple display modules, blemish compensation or color correction of the display panel can be facilitated. By driving the display panel so that inorganic light-emitting elements emit light sequentially in the order of row lines, instantaneous peak power consumption can be reduced. The effect of driving voltage drops generated differently at each location of the display panel can be compensated for by the process of setting data voltages. When a modular display panel is configured by combining multiple display modules, image distortion that may occur at the boundary between the upper and lower display modules can be eliminated.

[0628] The description in this disclosure is merely an illustration of the technical concept of this disclosure, and those skilled in the art will recognize that various modifications and variations can be made without departing from the essential characteristics of this disclosure. For example, although the sub-pixel circuit is implemented as a PMOS TFT, those skilled in the art will understand that the sub-pixel circuit can be implemented using an NMOS TFT or a CMOS TFT.

[0629] Although various aspects of the embodiments have been specifically shown and described, it will be understood that various changes in form and detail may be made therein without departing from the spirit and scope of the appended claims.

Claims

1. A display device, comprising: Modular display panel, comprising multiple display modules arranged in a matrix; as well as Timer controller Each of the plurality of display modules includes: A display panel includes a pixel array with pixels arranged in multiple rows and sub-pixel circuits. Each pixel consists of multiple inorganic light-emitting elements, and the sub-pixel circuits correspond to the inorganic light-emitting elements of the pixel array. The driver is configured to drive the sub-pixel circuitry in sequence along the plurality of row lines based on a start signal provided from the timing controller. The timing controller is further configured as follows: A first start signal is provided to the driver of the first display module among the plurality of display modules to control the inorganic light-emitting elements of the first display module to emit light sequentially from the first row line to the last row line, and A second start signal is provided to the driver of the second display module, which is disposed adjacent to the bottom of the first display module, to control the inorganic light-emitting elements of the second display module to emit light sequentially after the emission sequence of the inorganic light-emitting elements included in the last row of the first display module. The modular display panel is configured to be driven using a high-speed continuous scanning method, such that during one frame time, after providing the first start signal to the driver of the first display module, the second start signal is provided to the driver of the second display module, and during one frame time, data setting segments are continuously executed from the first row line of the uppermost display module to the last row line of the lowermost display module within the same column line of the modular display panel. The modular display panel is configured to be driven using a simultaneous scanning method, so that the data setting segments of the multiple display modules are performed simultaneously.

2. The display device according to claim 1, wherein, The driver is further configured to: provide gate signals to the sub-pixel circuit based on the start signal, in the order of the plurality of row lines, to drive the sub-pixel circuit in the order of the plurality of row lines, and The gate signal includes a scan signal and an emission signal. The scan signal is configured to provide an image data voltage to the sub-pixel circuit, and the emission signal is configured to control the inorganic light-emitting element of the pixel array to emit light based on the image data voltage.

3. The display device according to claim 2, wherein, Relative to an image frame, for each of the multiple line lines, the sub-pixel circuit is driven in the order of data setting segments and multiple emission segments, and The driver is further configured to: provide the scan signal to the sub-pixel circuit of the corresponding row line during a data setting segment of the corresponding row line, and apply the emission signal to the sub-pixel circuit of the corresponding row line during each of a plurality of emission segments of the corresponding row line.

4. The display device according to claim 3, wherein, The first transmission segment of the plurality of transmission segments is temporally adjacent to the data setting segment, and The plurality of transmission segments have a preset time interval between each other.

5. The display device according to claim 3, wherein, The image data voltage includes constant current generator data voltage and pulse width modulation (PWM) data voltage, and Each of the sub-pixel circuits includes: A constant current generator circuit includes a first driving transistor and is configured to provide a constant current to a corresponding inorganic light-emitting element based on the constant current generator data voltage; and The PWM circuit includes a second driving transistor and is configured to control the timing of providing the constant current to the corresponding inorganic light-emitting element based on the PWM data voltage.

6. The display device according to claim 5, wherein, The constant current generator circuit is further configured to: in each of the plurality of emission segments, provide the constant current to the corresponding inorganic light-emitting element based on a first voltage applied to the gate terminal of the first driving transistor, and The first voltage is based on the constant current generator data voltage and the threshold voltage of the first driving transistor.

7. The display device according to claim 6, wherein, The constant current generator circuit includes: The first transistor includes a source terminal to which the constant current generator data voltage is applied and a drain terminal connected to the source terminal of the first driving transistor; and The second transistor includes a source terminal connected to the drain terminal of the first driving transistor and a drain terminal connected to the gate terminal of the first driving transistor. The constant current generator circuit is further configured to: in the data setting section, based on the fact that the first driving transistor and the second transistor are both turned on at the same time, apply a voltage to the gate terminal of the first driving transistor, the voltage being the sum of the constant current generator data voltage and the threshold voltage of the first driving transistor.

8. The display device according to claim 5, wherein, The PWM circuit is configured to: in each of the plurality of emitter segments, control the duration for which the constant current is supplied to the corresponding inorganic light-emitting element based on a second voltage applied to the gate terminal of the second driving transistor, and The second voltage is based on the threshold voltage of the second driving transistor, the PWM data voltage, and the scan voltage that is scanned between the two voltages.

9. The display device according to claim 8, wherein, The PWM circuit includes a first capacitor having a first terminal connected to the source terminal of the second driving transistor and a second terminal connected to the gate terminal of the second driving transistor. Specifically, when the constant current generator data voltage is applied to the drain terminal of the second driving transistor, the second driving transistor operates as a source follower, and The threshold voltage of the second driving transistor is obtained at the source terminal of the second driving transistor when the second driving transistor operates as the source follower, and is coupled to the gate terminal of the second driving transistor through the first capacitor.

10. The display device according to claim 8, wherein, The PWM circuit includes a second capacitor having a first terminal connected to the gate terminal of the second driving transistor and a second terminal to which the PWM data voltage and the scan voltage are applied. The PWM data voltage is applied to the second terminal of the second capacitor in the data setting section, and the scan voltage is applied to the second terminal of the second capacitor based on each of the plurality of transmit sections. The PWM data voltage is coupled to the gate terminal of the second driving transistor together with the scan voltage through the second capacitor.

11. The display device according to claim 8, wherein, The drain terminal of the second driving transistor is connected to the source terminal of the first driving transistor. The constant current generator circuit is configured to provide the constant current to the corresponding inorganic light-emitting element in each of the plurality of emission segments when a driving voltage is applied to the source terminal of the first driving transistor. The PWM circuit is configured to: in each of the plurality of emitter segments, during the time period in which the second drive transistor is turned on while the second voltage varies according to the scan voltage, apply the drive voltage to the source terminal of the first drive transistor, and The time period during which the second driving transistor is turned on is based on the amplitude of the PWM data voltage.

12. The display device according to claim 8, wherein, The scan voltage is a portion of the input scan signal selected based on the transmitted signal, wherein the input scan signal has a voltage that changes linearly and repetitively from a first voltage to a second voltage, and The input scanning signal is applied together to each of the sub-pixel circuits of the display panel.

13. The display device according to claim 12, wherein, In each of the plurality of transmission segments, the scanning voltage scans the voltage between the first voltage and the second voltage once, and The starting voltage for the scanning voltage varies depending on the row line.

14. The display device according to claim 5, wherein, The PWM circuit is configured to: in each of the plurality of emitter segments, control the duration for which the constant current is supplied to the corresponding inorganic light-emitting element based on a third voltage applied to the gate terminal of the second driving transistor, and The third voltage is based on the PWM data voltage that compensates for the threshold voltage of the second driving transistor and the scan voltage that is scanned between the two voltages.

15. The display device according to claim 3, wherein, The sub-pixel circuit is driven by a first driving voltage in each of the plurality of emission segments, and by a second driving voltage separate from the first driving voltage in the data setting segment.

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