An electro-optic modulation chip with monolithically integrated active optical devices and a method of manufacture

Abstract

The application discloses an electro-optic modulation chip of a monolithic integrated active optical device and a preparation method thereof, wherein the electro-optic modulation chip comprises, from top to bottom, a compound semiconductor active layer, a germanium thin film layer and an electro-optic material waveguide layer; the electro-optic material waveguide layer is formed with a corresponding waveguide structure through photoetching and etching; the germanium thin film layer is formed with a germanium absorption layer and a germanium substrate growth layer through photoetching and etching; the germanium thin film layer is prepared through an ion scissors technology, which can realize high-speed and high-response O / C band optical detection on one hand, and provides a lattice-matched growth substrate for the compound semiconductor on the other hand, and can integrate an optical gain semiconductor device simultaneously.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor optoelectronic chips, and specifically relates to an electro-optic modulation chip that can be monolithically integrated with active optical devices and its fabrication method. Background Technology

[0002] Electro-optic crystals, represented by lithium niobate, possess large nonlinear optical coefficients and excellent photorefractive, piezoelectric, and acoustic properties, making them suitable for use as frequency doubling / difference crystal materials. They exhibit excellent physical and mechanical properties, a high damage threshold, a broad transparency spectrum, and very low transmission loss. Furthermore, the cost of electro-optic materials is relatively low, making them ideal for fabricating optical modulators. Compared to traditional silicon (Si)-based electro-optic modulation chips implemented using CMOS (complementary metal oxide semiconductor) technology, the nonlinear characteristics of electro-optic crystals, in particular, make them highly promising for research and applications in optical frequency combs, which have emerged in recent years. With technological advancements, these electro-optic crystals can also be integrated in thin film form on wafers 6 inches or larger. Taking lithium niobate-on-insulator (LNOI) thin films as an example, their emergence has solved the problems of low integration density and easy polarization crosstalk in traditional electro-optic waveguides, further simplifying the conditions for the generation of nonlinear effects in electro-optic waveguides. However, existing lithium niobate thin film technology struggles to incorporate active devices beyond modulation. While erbium-doped lithium niobate thin films can partially address the challenge of integrating optical gain into lithium niobate thin film systems, they limit the modulation capabilities themselves, thus presenting significant limitations. In summary, there is an urgent need for an electro-optic material system on an insulating layer that can simultaneously integrate optical gain, optical modulation, and optical detection functions onto a single chip. Summary of the Invention

[0003] The purpose of this invention is to address the shortcomings of existing technologies by providing an electro-optic modulation chip capable of monolithically integrating active optical devices and its fabrication method.

[0004] According to a first part of the present invention, an electro-optic modulation chip capable of monolithically integrating active optical devices is provided, comprising, from top to bottom, a compound semiconductor active layer, a germanium thin film layer, and an electro-optic material waveguide layer; the electro-optic material waveguide layer forms a corresponding waveguide structure through photolithography and etching; the germanium thin film layer forms a germanium absorption layer and a germanium substrate growth layer through photolithography and etching.

[0005] The electro-optic material waveguide layer serves as a coupling medium for optical signals and together with the compound semiconductor active layer grown on the germanium substrate, forms a waveguide, constituting the optical gain portion of the electro-optic modulation chip.

[0006] The electro-optic material waveguide layer serves as a coupling medium for optical signals and together with the germanium absorption layer, forms a waveguide, constituting the photodetector section of the electro-optic modulation chip.

[0007] The electro-optic material waveguide layer serves as the propagation medium for optical signals and constitutes the optical modulation section of the electro-optic modulation chip.

[0008] According to a second part of the present invention, a method for fabricating an electro-optic modulation chip capable of monolithically integrating active optical devices is provided, comprising the following steps:

[0009] Prepare an electro-optic material wafer with an electro-optic material waveguide layer, etch a waveguide structure on the electro-optic material waveguide layer, deposit an insulating substrate layer and flatten the surface;

[0010] Prepare a germanium wafer. After hydrogen ion implantation, a germanium thin film layer, a germanium defect enrichment layer, a germanium fracture layer, and a residual germanium substrate are formed on the surface of the germanium wafer.

[0011] Germanium wafers are bonded to the surface of an upper insulating substrate, and only the germanium thin film layer of the germanium wafer is retained by annealing and polishing.

[0012] The germanium thin film layer is etched to form the germanium substrate growth layer for the light gain section and the germanium absorption layer for the light detection section, respectively; an insulating substrate layer is then deposited, and a growth window is opened in the light gain section to grow a compound semiconductor active layer on the germanium substrate growth layer;

[0013] Continue depositing an insulating substrate layer and forming via electrodes and contact electrodes.

[0014] Furthermore, the impurity doping concentration of the germanium wafer should be 10. 16 cm -3 ~5×10 16 cm -3 Within the specified range, the doping type is n-type or p-type, and the surface roughness should be within 0.5 nm / 100 μm. 2 the following.

[0015] Furthermore, the preparation process of the germanium wafer is specifically as follows:

[0016] The germanium wafer is cleaned and dried; an oxide film is deposited on the germanium wafer to form a protective layer;

[0017] Germanium wafers were subjected to hydrogen ion implantation at room temperature, with an implantation tilt angle of 7° and an implantation dose of 4 × 10⁻⁶. 16 cm -3 ~1×10 17 cm -3 The injection energy is 60keV to 250keV, and the injection beam current is less than or equal to 1000μA / cm. 2 ;

[0018] After injection, the wafer is cleaned and dried again to obtain the prepared germanium wafer.

[0019] Further, the cleaning and drying process specifically involves: cleaning the oxide layer on the surface of the germanium wafer using a buffered hydrofluoric acid solution or a diluted hydrofluoric acid solution for 3 to 5 minutes; after acid cleaning, rinsing in deionized ultrapure water to remove residual hydrofluoric acid solution from the surface; after water rinsing, removing the ultrapure water from the surface by nitrogen blowing or vacuum back-side adsorption and spin drying.

[0020] Furthermore, the bonding process of the germanium wafer is specifically as follows:

[0021] The surface of the germanium wafer and the surface of the upper insulating substrate are treated, specifically by depositing an oxide film several nanometers thick on the surface of the germanium wafer and the upper insulating substrate, or by plasma activation of the surface of the germanium wafer and the upper insulating substrate, with nitrogen or oxygen as the carrier gas atmosphere using argon.

[0022] After surface treatment, the germanium wafer and the upper insulating substrate layer are pre-bonded;

[0023] Bond energy enhancement is performed on the electro-optic modulation chip formed after pre-bonding.

[0024] In a vacuum environment, the germanium wafer is heated uniformly until the temperature reaches 300℃~400℃ for annealing, and held for a sufficient time until the germanium cracked layer and residual germanium substrate are peeled off.

[0025] The germanium defect-rich layer on the surface is removed by grinding, while the germanium thin film layer is retained;

[0026] The germanium thin film is then annealed again in a vacuum environment at a temperature of 500–550°C for 10–60 minutes to further repair any remaining defects in the film.

[0027] Furthermore, the bond energy enhancement specifically involves applying a 5–20 N / cm bond along the longitudinal direction of the electro-optic modulation chip. 2 Uniform pressure, less than 10 -5 Under a vacuum atmosphere of mbar and an ambient temperature of 150℃~250℃, the temperature is slowly increased and held for 0.5~2 hours, followed by a slow decrease, which enhances the bond energy to greater than 2J / m. 2 .

[0028] Furthermore, the annealing methods for stripping the germanium pyrolysis layer and residual germanium substrate are as follows: when the electro-optic modulation chip size is less than or equal to 6 inches, furnace tube heating annealing is used; when the electro-optic modulation chip size is greater than 6 inches, laser annealing is used.

[0029] Furthermore, the etched germanium thin film layer specifically comprises:

[0030] For the optical gain section, the thickness of the germanium thin film is reduced, and a germanium substrate growth layer is formed by photolithography and etching to facilitate the growth of the compound semiconductor active layer.

[0031] For the optical modulation part, the germanium thin film layer needs to be completely etched;

[0032] For the photodetector, the germanium thin film layer serves as the light absorption layer. First, the germanium absorption layer is formed by photolithography and etching, and then a pn junction is formed by doping or by forming interdigitated electrodes to form a photodetector.

[0033] Furthermore, in the optical gain section, a growth window is opened by etching the upper insulating substrate layer on the germanium substrate growth layer. It is necessary to ensure that no natural oxide is generated on the germanium substrate growth layer after the growth window is opened, and then a compound semiconductor active layer is grown.

[0034] The beneficial effects of this invention are as follows: This invention provides an electro-optic modulation chip structure and its fabrication method that can simultaneously integrate optical gain, optical modulation, and optical detection. By using ion-scissor technology to integrate a single-crystal germanium thin film layer on an electro-optic waveguide, on the one hand, high-speed, high-response germanium detectors for communication bands can be fabricated; on the other hand, germanium, as a growth substrate, can be matched with the lattice of compound semiconductors to achieve high-quality crystal growth and realize high-performance optical gain devices. Attached Figure Description

[0035] Figure 1 This is a schematic diagram of the structure of the electro-optic modulation chip that can be monolithically integrated with active optical devices provided in this disclosure;

[0036] Figure 2 This is a flowchart of the fabrication process of an electro-optic modulation chip that can be monolithically integrated with active optical devices, as disclosed in this publication.

[0037] Figure 3 This is a schematic diagram of the structure in preparation step S1 provided in this disclosure;

[0038] Figure 4 This is a schematic diagram of the structure in preparation step S2 provided in this disclosure;

[0039] Figure 5 This is a schematic diagram of the germanium wafer structure in preparation step S4 provided in this disclosure;

[0040] Figure 6 This is a schematic diagram of the pre-bonded structure in preparation step S5 provided in this disclosure;

[0041] Figure 7 This is a schematic diagram of the formation of a germanium thin film layer in preparation step S5 provided in this disclosure;

[0042] Figure 8This is a schematic diagram of the final structure in preparation step S5 provided in this disclosure;

[0043] Figure 9 This is a schematic diagram of the structure in preparation step S6 provided in this disclosure;

[0044] Figure 10 These are schematic diagrams of the structures in preparation steps S7-S8 provided in this disclosure;

[0045] Figure 11 This is a schematic diagram of the structure in preparation step S9 provided in this disclosure;

[0046] Figure 12 This is a schematic diagram of the structure in preparation steps S10-S11 provided in this disclosure;

[0047] Figure 13 This is a schematic diagram of the structure in preparation step S12 provided in this disclosure;

[0048] In the figure, 100 is the electro-optic modulation chip, 10 is the electro-optic material wafer, 101 is the contact electrode, 102 is the via electrode, 103 is the compound semiconductor active layer, 11 is the germanium wafer, 104 is the germanium thin film layer, 104-a is the germanium fracture layer, 104-b is the germanium defect enrichment layer, 104-c is the residual germanium substrate, 104-1 is the germanium substrate growth layer, 104-2 is the germanium absorption layer, 105 is the electro-optic material waveguide layer, 12 is the waveguide structure, 106a is the upper insulating substrate layer, 106b is the lower insulating substrate layer, 107 is the chip substrate layer, 200 is the optical gain section, 300 is the optical modulation section, and 400 is the optical detection section. Detailed Implementation

[0049] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, the specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0050] Many specific details are set forth in the following description in order to provide a full understanding of the invention. However, the invention may also be practiced in other ways different from those described herein, and those skilled in the art can make similar extensions without departing from the spirit of the invention. Therefore, the invention is not limited to the specific embodiments disclosed below.

[0051] For clarity, the following description of embodiments and related structures of the present invention primarily characterizes single-chip structures formed on semiconductor substrates and their fabrication steps. However, for efficiency reasons, the embodiments can actually be performed at the wafer level.

[0052] It should be noted that references to "an embodiment," "an embodiment," "an exemplary embodiment," "some embodiments," etc., in the application documents may describe embodiments that include specific features, structures, or characteristics, but each embodiment may not necessarily include that specific feature, structure, or characteristic. Furthermore, this phrase does not necessarily refer to the same embodiment. Moreover, when a specific feature, structure, or characteristic is described in connection with an embodiment, whether explicitly described or not, implementing that feature, structure, or characteristic in connection with other embodiments is within the knowledge of those skilled in the art.

[0053] Terminology is generally understood, at least in part, based on its use in context. For example, the term "one or more," as used herein, can be used, at least in part, depending on the context, to describe any feature, structure, or characteristic in a singular sense, or to describe a combination of features, structures, or characteristics in a plural sense. Similarly, terms such as "a," "an," or "described" can again be understood to convey either singular or plural usage, at least in part, depending on the context. Furthermore, the term "based on" can be understood not necessarily to convey an exclusive set of factors, but rather to allow for the existence of additional factors that are not necessarily clearly described, again, at least in part, depending on the context.

[0054] It will be readily understood that the meanings of “on,” “above,” and “on top of” in this disclosure should be interpreted in the broadest possible sense, such that “on” not only means “directly on,” but also includes “on,” with an intermediate feature or layer, and that “above” or “on top of” not only means “above,” but also includes “above,” without an intermediate feature or layer (i.e., directly on).

[0055] Furthermore, spatially relative terms such as "below," "under," "lower," "above," and "upper" are used to readily describe the relationship between one element or feature and other elements (single or multiple) or features (single or multiple) as exemplified in the figures. In addition to the orientations depicted in the figures, spatially relative terms are also intended to cover different orientations of the device in use or operation. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatially relative descriptors used herein can be interpreted accordingly.

[0056] As used herein, the term "substrate" refers to a material on which subsequent material layers are added. The substrate itself can be patterned. The material added on top of the substrate can also be patterned, or the material added on top of the substrate can remain unpatterned. Furthermore, the substrate can comprise a wide range of semiconductor materials, such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate can be made of non-conductive materials such as glass, plastic, or sapphire wafers.

[0057] As used herein, the term "layer" refers to a portion of material comprising a region of thickness. A layer may extend over the entirety of an undercoat or overcoat structure, or may have a width smaller than that of the undercoat or overcoat structure. Furthermore, a layer may be a region of a homogeneous or heterogeneous continuous structure, the thickness of which is less than the thickness of the continuous structure. For example, a layer may lie between any pair of horizontal planes between the top and bottom surfaces of a continuous structure, or between any pair of horizontal planes at the top and bottom surfaces of a continuous structure. A layer may extend horizontally, vertically, and / or along a tapered surface. A substrate may be a layer, may contain one or more layers, and / or may have one or more layers on, above, and / or below it. A layer may comprise multiple layers. For example, an interconnect layer may comprise one or more conductor and contact layers (where interconnects, and / or via contacts are formed) and one or more dielectric layers.

[0058] As used herein, the term “front” of a structure refers to the surface of a structure used to form a device or which will subsequently be used to form a device.

[0059] As used herein, the term "semiconductor" refers to, but is not limited to, a material having a conductivity value falling between that of a conductor and an insulator. This material can be an elemental material or a compound material. Semiconductors can include, but are not limited to, elemental, binary, ternary, and quaternary alloys. Structures formed using one or more semiconductors can include a single semiconductor material, two or more semiconductor materials, a single-component semiconductor alloy, two or more discretely composed semiconductor alloys, and semiconductor alloys that gradually transition from a first semiconductor alloy to a second semiconductor alloy. A semiconductor can be one of the following: undoped (intrinsic), hole-doped, electron-doped, with doping gradually transitioning from a first doping level of one type to a third doping level of the same type, and with doping gradually transitioning from a first doping level of one type to a third doping level of a different type.

[0060] Furthermore, semiconductors can include, but are not limited to, group IV semiconductors, such as those between carbon (C), silicon (Si), germanium (Ge), and tin (Sn).

[0061] Furthermore, semiconductors may include, but are not limited to, III-V group semiconductors, such as those in aluminum (Al), gallium (Ga), indium (In), nitrogen (N), phosphorus (P), arsenic (As), and tin (Sb).

[0062] Furthermore, semiconductors may include, but are not limited to, group II-VI semiconductors, such as those between zinc (Zn), cadmium (Cd), mercury (Hg), sulfur (S), selenium (Se), tellurium (Te), and oxygen (O).

[0063] As used herein, the term "metal" in the terminology refers to, but is not limited to, materials (elements, compounds, and alloys) that have good electrical and thermal conductivity as a result of readily losing their outermost electrons. This may include, but is not limited to, gold, chromium, aluminum, silver, platinum, nickel, copper, rhodium, palladium, tungsten, and combinations thereof.

[0064] As used herein, the terms "optical waveguide," "dielectric waveguide," or "waveguide" refer to, but are not limited to, a medium or combination of media that supports the propagation of optical signals within a predetermined wavelength range and remains constant along the direction of propagation. An optical waveguide can be at least one of the following: comprising at least a core and a cladding (e.g., optical fiber), formed as part of a carrier, or formed within a substrate (e.g., planar optical wave circuits, photonic integrated circuits, integrated optical devices). This includes, but is not limited to, flexible optical waveguides formed of pressed glass, pressed doped quartz, pressed chalcogenide glass, and polymers. This further includes, but is not limited to, optical waveguides formed of: quartz on insulator, quartz on silicon, silicon oxynitride on silicon, polymer on silicon, polymer on polymer, etc.

[0065] As used herein, the term "optical waveguide layer" refers to a portion of material comprising a region of thickness. More specifically, it may be subsequently processed to achieve the function of confining and transmitting light waves, including but not limited to one or more layers of waveguide material.

[0066] As used herein, the term "dielectric layer" refers to a portion of material comprising a region of thickness. More specifically, it has the function of enabling electrical connections or transporting charge carriers, and may consist of, but is not limited to, one or more layers of metal or other conductive material.

[0067] As used herein, the term "optical-electrical layer via structure" refers to a via structure connecting a dielectric layer and an electro-absorbing layer, which conducts electrical connections between the dielectric layer and the electro-absorbing layer, allowing light, after being converted into electrons in the electro-absorbing layer, to continue to be transmitted to the dielectric layer for further signal processing. Its materials include, but are not limited to, the aforementioned metallic materials or conductive polymer materials.

[0068] like Figure 1The diagram shown is a cross-sectional view of the electro-optic modulation chip 100, which can monolithically integrate active optical devices as mentioned in this invention.

[0069] Specifically, the electro-optic modulation chip 100, which can monolithically integrate active optical devices, includes, from top to bottom, a compound semiconductor active layer 103, a germanium thin film layer 104, and an electro-optic material waveguide layer 105. The electro-optic material waveguide layer 105 is formed with corresponding waveguide structures 12 through photolithography and etching, enabling light propagation within the electro-optic material waveguide layer 105. The germanium thin film layer 104 is formed with a germanium absorption layer 104-2 and a germanium substrate growth layer 104-1 through photolithography and etching.

[0070] The electro-optic material waveguide layer 105 serves as the coupling medium for optical signals. Together with the compound semiconductor active layer 103 grown on the germanium substrate growth layer 104-1, it forms a waveguide. Through electrical injection, the optical signal is amplified by passing through the compound semiconductor active layer 103, thus forming the optical gain portion 200 of the electro-optic modulation chip 100, which can be monolithically integrated with active optical devices.

[0071] The electro-optic material waveguide layer 105 serves as the coupling medium for optical signals and together with the germanium absorption layer 104-2 forms a waveguide. Since germanium has strong absorption of light below 1600nm, the germanium absorption layer 104-2 can act as a photodetector medium. The electro-optic material waveguide layer 105 and the germanium absorption layer 104-2 together constitute the photodetector section 400 of the electro-optic modulation chip 100, which can be monolithically integrated with active optical devices.

[0072] The electro-optic material waveguide layer 105 serves as the propagation medium for optical signals and constitutes the optical modulation section 300 of the electro-optic modulation chip 100, which can be monolithically integrated with active optical devices.

[0073] Figure 2 The fabrication process of the electro-optic modulation chip 100, which can be monolithically integrated with active optical devices, is demonstrated. The specific steps are described below:

[0074] S1: Prepare 10 electro-optic material wafers;

[0075] Specifically, such as Figure 3 As shown, the electro-optic material wafer 10 includes a waveguide layer 105 with lithium niobate, lithium tantalate and other materials with linear electro-optic effects as electro-optic materials, and a lower insulating substrate layer 106b and a chip substrate layer 107.

[0076] In particular, such wafers can be provided by wafer manufacturers, and their specific manufacturing processes are not within the scope of this invention patent discussion.

[0077] Preferably, the thickness of the electro-optic material waveguide layer 105 in the electro-optic material wafer 10 is 400 nanometers, and more broadly, the thickness range is 300 to 500 nm.

[0078] S2: Etching waveguide structure 12;

[0079] like Figure 4 As shown, a waveguide structure 12 needs to be formed on the electro-optic material waveguide layer 105. The specific design of the waveguide structure is not within the scope of this invention, but its types should include common strip waveguides, ridge waveguides, gap waveguides, and subwavelength grating waveguides.

[0080] Preferably, Figure 4 The waveguide structure shown is a ridge waveguide, the purpose of which is to move the local optical mode of the optical waveguide to the region near the top of the waveguide structure 12, so as to facilitate coupling with subsequent structures. At the same time, it has lower propagation loss compared with strip waveguide.

[0081] S3: Deposit the insulating substrate layer 106a and level the surface;

[0082] After waveguide etching is completed, oxide layer deposition is required to form upper insulating substrate layer 106a. During the oxide layer deposition process, the geometry of waveguide structure 12 will gradually transfer to the surface of upper insulating substrate layer 106a as the deposition process proceeds. Therefore, the surface of upper insulating substrate layer 106a needs to be ground and leveled.

[0083] In particular, in order to ensure that the waveguide structure 12 can support its upper structure when it is subsequently used to form the optical gain section 200, the optical modulation section 300 and the optical detection section 400, the distance between the top surface of the upper insulating substrate layer 106a and the top surface of the waveguide structure 12 needs to be limited.

[0084] Preferably, the spacing should be less than 100 nm, and the optimal spacing should be maintained at 50 nm.

[0085] S4: Prepare germanium wafers;

[0086] Traditional group IV semiconductor materials often do not have linear electro-optic effects. Although compound semiconductor materials have linear electro-optic effects, their production and processing costs are too high, so they are not suitable for the fabrication of low-cost and high-performance electro-optic modulation chips 100.

[0087] Common electro-optic materials such as lithium niobate and lithium tantalate are well-suited for fabricating the optical modulation section 300 in the electro-optic modulation chip 100. However, since they are generally insulating materials, it is not possible to simultaneously integrate the optical gain section 200 and the optical detection section 400 through simple doping and implantation methods. Although some researchers have developed an integrated optical chip that uses erbium-doped lithium niobate to achieve optical amplification, its fabrication process is complex and involves global processes, which is not conducive to monolithic integration.

[0088] This invention uses a germanium wafer 11 as the medium for integrating the optical gain section 200 and the photodetector section 400 in the electro-optic modulation chip 100. Integration of a germanium thin film layer 104, fabricated from the germanium wafer 11, onto the electro-optic waveguide layer 105 is achieved using ion-scissor technology. To achieve this, special processing of the germanium wafer 11 is required.

[0089] Specifically, germanium wafer 11 needs to be prepared in advance, and its impurity doping concentration should be 10. 16 cm -3 ~5×10 16 cm -3 Within the specified range, the doping type can be n-type or p-type, and the surface roughness (RMS) should be guaranteed to be within 0.5 nm / 100 μm. 2 the following.

[0090] Subsequently, the germanium wafer 11 was cleaned. First, the oxide layer on the surface of the germanium wafer 11 was cleaned using a 25% buffered hydrofluoric acid solution (BHF) or a diluted hydrofluoric acid solution (DHF) for 3–5 minutes. After acid cleaning, it was rinsed in deionized ultrapure water to remove residual hydrofluoric acid solution from the surface. After rinsing, it was necessary to ensure that a uniform and flat ultrapure water film covered the surface of the germanium wafer 11. This step was to confirm that the dangling bond structure on the surface of the germanium wafer 11 was hydrophilic. Afterward, the surface ultrapure water was removed by nitrogen blowing or vacuum back-side adsorption and spin drying.

[0091] Next, a dense oxide film is deposited on the germanium wafer 11 by vapor deposition as a protective layer for subsequent processes. Preferably, the oxide film is 100 nm thick and made of silicon dioxide. A wider range includes 50 nm to 200 nm.

[0092] Subsequently, germanium wafer 11 was subjected to hydrogen ion (H2) treatment at room temperature. + Injection, injection angle 7°, injection dose 4×10 16 cm -3 ~1×10 17 cm -3 The injection energy is 60keV to 250keV, and the injection beam current is less than or equal to 1000μA / cm. 2 .

[0093] Preferably, to prevent self-heating and ensure that a sufficiently thick germanium thin film layer 104 can be transferred to the surface of the electro-optic waveguide layer 105 in subsequent processes, the injection conditions should be: an injection tilt angle of 7° and an injection dose of 4 × 10⁻⁶. 16 cm -3 The injection energy was 80 keV, and the injection beam current was 100 μA / cm. 2 .

[0094] After injection, the surface oxide layer is cleaned again with BHF or DHF solution for 3–5 minutes. Following acid cleaning, it is rinsed in deionized ultrapure water to remove residual hydrofluoric acid solution. After rinsing, it is essential to ensure a uniform and flat ultrapure water film covers the surface of germanium wafer 11. This step confirms that the dangling bond structure on the germanium wafer 11 surface remains hydrophilic. Subsequently, the surface ultrapure water is removed by nitrogen blowing or vacuum back-side adsorption and spin drying, finally yielding the prepared germanium wafer 11.

[0095] like Figure 5 As shown, the surface of the germanium wafer 11 has a germanium thin film layer 104. Due to its proximity to the surface of the germanium wafer 11, this layer exhibits a low defect density and residual hydrogen ion concentration after ion implantation. With increasing depth, a germanium defect-rich layer 104-b forms at a deeper location on the surface of the germanium wafer 11. The position and thickness of this layer vary with the implantation conditions. More specifically, by adjusting the implantation energy and implantation metering, the depth and thickness of the germanium defect-rich layer 104-b can be altered. Simultaneously, under specific implantation conditions, during the enrichment process, germanium defects will form a germanium fracture layer 104-a with a certain thickness at a specific depth. This layer contains numerous germanium lattice defects, and hydrogen ions passivate the dangling bonds on the defects, accumulating at the defect cores in the form of hydrogen molecules. The deeper residual germanium substrate 104-c, because it is much larger than the depth that hydrogen ions can penetrate after acceleration, has similar basic properties to the germanium thin film layer 104 and can both be considered as single-crystal germanium material.

[0096] S5: Bonded germanium wafer;

[0097] To transfer the germanium thin film layer 104 onto the electro-optic waveguide layer 105, the germanium wafer 11 must first be bonded together by wafer bonding, so that the upper surface of the germanium wafer 11 is tightly bonded to the upper surface of the upper insulating substrate layer 106a formed on the electro-optic modulation chip 100 through intermolecular forces. To achieve this operation, surface treatment of the germanium wafer 11 and the electro-optic modulation chip 100 is required.

[0098] Specifically, a thin oxide film several nanometers thick is deposited on the surface of the germanium wafer 11. The material can be silicon oxide, aluminum oxide, etc., and the deposition method includes plasma-enhanced vapor deposition or ordinary vapor deposition, or it can be formed using an atomic layer deposition (ALD) device. Similarly, a thin oxide film several nanometers thick also needs to be deposited on the electro-optic modulation chip 100. Preferably, the oxide film thickness is 5 nanometers, and the deposition method is atomic layer deposition.

[0099] Another approach is to use plasma surface activation, which uses a radio frequency power source of several hundred watts to activate the dangling bonds on the surface. The gas atmosphere can be nitrogen, oxygen, or other common semiconductor process gases, with argon as the carrier.

[0100] After surface treatment, the two need to be pre-bonded. Precise alignment is not required for this pre-bonding operation. Figure 6 The diagram shows the structure of the electro-optic modulation chip 100 after pre-bonding of the germanium wafer 11. At this time, the germanium thin film layer 104 is pre-transferred onto the upper insulating substrate layer 106a, but the strength of its intermolecular bonding is still very weak, and the germanium defect enrichment layer 104-b, the germanium fracture layer 104-a, and the residual germanium substrate 104-c have not been removed.

[0101] Next, we enhance the bond energy of the pre-bonded electro-optic modulation chip 100 using a bonding device. Specifically, a bond strength of 5–20 N / cm is applied longitudinally to the electro-optic modulation chip 100. 2 Uniform pressure, less than 10 -5 Under a vacuum atmosphere of mbar and an ambient temperature of 150℃~250℃, the temperature is slowly increased and held for 0.5~2 hours, followed by a slow decrease, which enhances the bond energy to greater than 2J / m. 2 .

[0102] Specifically, the pressure and temperature settings must be adjusted according to the actual size of the electro-optic modulation chip 100 to prevent wafer breakage. In this invention, the size of the electro-optic modulation chip 100 ranges from a single chip size (<1-inch wafer) to a 12-inch wafer size. The corresponding germanium wafer 11 should also be consistent with the size of the electro-optic modulation chip 100.

[0103] Next, we need to peel off the germanium thin film layer 104. This step is called the ion shearing technique. By heating and holding the temperature for a sufficiently long time, we induce the residual hydrogen ions in the germanium fracture layer 104-a to aggregate into clusters and apply microscopic stress to the defects they are located at, causing the germanium fracture layer 104-a to fracture extensively parallel to the wafer direction. This allows the germanium fracture layer 104-a and the residual germanium substrate 104-c to be peeled off together, leaving only the germanium thin film layer 104 and the germanium defect-rich layer 104-b. Figure 7 As shown.

[0104] In particular, the heating process should ensure that the temperature changes slowly and is evenly distributed throughout the wafer to avoid wafer breakage due to stress differences.

[0105] Preferably, it should be less than 10 -5In a vacuum environment of mbar, the wafer is uniformly heated at a rate of 1°C per minute until the temperature reaches 300°C to 400°C for annealing. The temperature is maintained for a sufficient time until the germanium fracture layer 104-a breaks.

[0106] Because the fracture process is very rapid, the stress transmission may cause the wafer to inevitably break. Another improved fracture method is to use high-energy laser-induced fracture. In this method, the laser focus is set near the germanium fracture layer 104-a. Annealing is performed by continuous single-point scanning, which gradually induces the fracture of the germanium fracture layer 104-a at various parts of the chip. Finally, the small fracture points spontaneously connect with each other to form a large-scale fracture effect.

[0107] Preferably, when the size of the electro-optic modulation chip 100 is less than or equal to 6 inches, furnace tube heating annealing can be used; when the size of the electro-optic modulation chip 100 is greater than 6 inches, laser annealing should be used.

[0108] Subsequently, the germanium defect-rich layer 104-b on the surface was removed by chemical mechanical polishing, leaving the germanium thin film layer 104, as shown below. Figure 8 As shown. Finally, in cases less than 10 -5 The germanium thin film 104 is annealed again under a vacuum environment of mbar at a temperature of 500–550°C for 10–60 minutes to further repair residual defects in the germanium thin film layer 104.

[0109] S6: Etching the germanium thin film layer;

[0110] The germanium thin film layer 104, as a precursor to the germanium substrate growth layer 104-1 and the germanium absorption layer 104-2, has been transferred to the surface of the upper insulating substrate layer 106a as previously described. The optical gain section 200, the optical modulation section 300, and the optical detection section 400 of this invention will be discussed separately below.

[0111] For the optical gain portion 200, the germanium thin film layer 104, due to its light absorption effect in the target wavelength band, needs to have its thickness reduced to decrease the absorption region. Since germanium itself has a lattice coefficient that matches that of compound semiconductors, especially gallium arsenide (GaAs), it is very suitable as a precursor substrate for compound semiconductor growth. Therefore, its thickness should ensure sufficient seed region for the growth of the compound semiconductor active layer 103. This invention does not discuss its specific growth mode. In contrast, this invention emphasizes that when processing the germanium thin film layer 104 in this step, it needs to be kept relatively thin, typically 50 nanometers, to form the germanium substrate growth layer 104-1, such as... Figure 9 As shown. In addition, a grid-like structural array formed on the germanium substrate growth layer 104-1 can also serve as a precursor for compound semiconductor growth.

[0112] For the optical modulation section 300, the germanium thin film layer 104 needs to be completely etched to ensure that the electro-optic material waveguide layer 105 does not introduce excessive insertion loss during optical modulation.

[0113] For the photodetector section 400, the germanium thin film layer 104 can serve as a light absorption layer. First, the germanium absorption layer 104-2 is formed through photolithography and etching, such as... Figure 9 As shown, a PIN-type photodetector can be formed by doping to create a pn structure, or an MSM-type photodetector can be formed by forming interdigitated electrodes. Its typical thickness should be 200 nanometers.

[0114] S7: Continue depositing the upper insulating substrate layer 106a;

[0115] After the germanium substrate growth layer 104-1 and the germanium absorber layer 104-2 are prepared, an insulating substrate layer 106a needs to be deposited to ensure passivation of the germanium material, such as... Figure 10 As shown. Since the growth window still needs to be opened for compound semiconductor growth, the thickness of the insulating substrate layer 106a deposited in this step should not exceed 200 nanometers.

[0116] S8: Open the growth window;

[0117] The growth window is opened by etching the upper insulating substrate layer 106a on the germanium substrate growth layer 104-1, such as... Figure 10 As shown, this step requires ensuring that no natural oxides are generated on the germanium substrate growth layer 104-1 after the growth window is opened. Therefore, the sample needs to be preserved under vacuum after the etching is completed.

[0118] S9: Growth of compound semiconductors;

[0119] In a vapor phase epitaxy apparatus, a compound semiconductor active layer 103 is grown on a germanium substrate growth layer 104-1, such as... Figure 11 As shown, this invention does not protect the compound semiconductor growth environment and layer structure, but only protects the compound semiconductor growth method using germanium substrate growth layer 104-1 as the seed layer.

[0120] S10: Continue depositing the upper insulating substrate layer 106a;

[0121] like Figure 12 As shown, an insulating substrate layer 106a is deposited to ensure hermetic protection of the grown compound semiconductor.

[0122] S11: Form via electrode 102;

[0123] Via structures are formed in the optical gain section 200, optical modulation section 300, and optical detection section 400 by etching, and via electrodes 102 are formed by filling them with conductive materials (such as metals, transparent conductive oxides, etc.). Figure 12 As shown.

[0124] S12: Form contact electrode 101;

[0125] Finally, as Figure 13 As shown, the contact electrode 101 is formed on the via electrode 102 by etching, electroplating or stripping, and its material is generally a metal.

[0126] The above description is merely a preferred embodiment of the present invention. Although the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make many possible variations and modifications to the technical solutions of the present invention using the methods and techniques disclosed above, or modify them into equivalent embodiments with equivalent changes, without departing from the scope of the technical solutions of the present invention. Therefore, any simple modifications, equivalent changes, and modifications made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solutions of the present invention shall still fall within the protection scope of the technical solutions of the present invention.

Claims

1. An electro-optic modulation chip capable of monolithically integrating active optical devices, characterized in that, From top to bottom, it includes a compound semiconductor active layer, a germanium thin film layer, and an electro-optic waveguide layer; The electro-optic material waveguide layer is formed into a corresponding waveguide structure through photolithography and etching; the germanium thin film layer is formed into a germanium absorption layer and a germanium substrate growth layer through photolithography and etching. The electro-optic material waveguide layer serves as a coupling medium for optical signals and together with the compound semiconductor active layer grown on the germanium substrate, forms a waveguide, constituting the optical gain portion of the electro-optic modulation chip. The electro-optic material waveguide layer serves as a coupling medium for optical signals and together with the germanium absorption layer, forms a waveguide, constituting the photodetector section of the electro-optic modulation chip. The electro-optic material waveguide layer serves as the propagation medium for optical signals and constitutes the optical modulation section of the electro-optic modulation chip.

2. A method for fabricating an electro-optic modulation chip capable of monolithically integrating active optical devices as described in claim 1, characterized in that, Includes the following steps: Prepare an electro-optic material wafer with an electro-optic material waveguide layer, etch a waveguide structure on the electro-optic material waveguide layer, deposit an insulating substrate layer and flatten the surface; Prepare a germanium wafer. After hydrogen ion implantation, a germanium thin film layer, a germanium defect enrichment layer, a germanium fracture layer, and a residual germanium substrate are formed on the surface of the germanium wafer. Germanium wafers are bonded to the surface of an upper insulating substrate, and only the germanium thin film layer of the germanium wafer is retained by annealing and polishing. Etching germanium thin film layers to form germanium substrate growth layer for optical gain section and germanium absorption layer for optical detection section respectively; Continue depositing the insulating substrate layer, and open the growth window in the optical gain section to grow the compound semiconductor active layer on the germanium substrate growth layer; Continue depositing an insulating substrate layer and forming via electrodes and contact electrodes.

3. The preparation method according to claim 2, characterized in that, The impurity doping concentration of the germanium wafer should be within 10%. 16 cm -3 ~5×10 16 cm -3 Within the specified range, the doping type is n-type or p-type, and the surface roughness should be within 0.5 nm / 100 μm. 2 the following.

4. The preparation method according to claim 2, characterized in that, The preparation process for the germanium wafer is as follows: The germanium wafer is cleaned and dried; an oxide film is deposited on the germanium wafer to form a protective layer; Germanium wafers were subjected to hydrogen ion implantation at room temperature, with an implantation tilt angle of 7° and an implantation dose of 4 × 10⁻⁶. 16 cm -3 ~1×10 17 cm -3 The injection energy is 60keV~250keV, and the injection beam current is less than or equal to 1000μA / cm. 2 ; After injection, the wafer is cleaned and dried again to obtain the prepared germanium wafer.

5. The preparation method according to claim 4, characterized in that, The cleaning and drying process specifically involves: cleaning the oxide layer on the surface of the germanium wafer with a buffered hydrofluoric acid solution or a diluted hydrofluoric acid solution for 3-5 minutes; after acid cleaning, rinsing in deionized ultrapure water to remove residual hydrofluoric acid solution from the surface; and after rinsing, removing ultrapure water from the surface by blowing with nitrogen or vacuum back-side adsorption and spin drying.

6. The preparation method according to claim 2, characterized in that, The bonding process of the germanium wafer is as follows: The surface of the germanium wafer and the surface of the upper insulating substrate are treated, specifically by depositing an oxide film several nanometers thick on the surface of the germanium wafer and the upper insulating substrate, or by plasma activation of the surface of the germanium wafer and the upper insulating substrate, with nitrogen or oxygen as the carrier gas atmosphere using argon. After surface treatment, the germanium wafer and the upper insulating substrate layer are pre-bonded; Bond energy enhancement is performed on the electro-optic modulation chip formed after pre-bonding. In a vacuum environment, the germanium wafer is heated uniformly until the temperature reaches 300℃~400℃ for annealing, and held for a sufficient time until the germanium cracked layer and residual germanium substrate are peeled off. The germanium defect-rich layer on the surface is removed by grinding, while the germanium thin film layer is retained; The germanium thin film is then annealed again in a vacuum environment at a temperature of 500-550°C for 10-60 minutes to further repair any remaining defects in the film.

7. The preparation method according to claim 6, characterized in that, The bond energy enhancement specifically involves applying a 5~20 N / cm² bond energy longitudinally to the electro-optic modulation chip. 2 Uniform pressure, less than 10 -5 Under a vacuum atmosphere of mbar and an ambient temperature of 150℃~250℃, the temperature is slowly increased and held for 0.5~2 hours, followed by a slow decrease, which enhances the bond energy to greater than 2J / m. 2 .

8. The preparation method according to claim 6, characterized in that, The annealing methods for stripping the germanium pyrolysis layer and residual germanium substrate are as follows: when the electro-optic modulation chip size is less than or equal to 6 inches, furnace tube heating annealing is used; when the electro-optic modulation chip size is greater than 6 inches, laser annealing is used.

9. The preparation method according to claim 2, characterized in that, The etched germanium thin film layer is specifically: For the optical gain section, the thickness of the germanium thin film is reduced, and a germanium substrate growth layer is formed by photolithography and etching to facilitate the growth of the compound semiconductor active layer. For the optical modulation part, the germanium thin film layer needs to be completely etched; For the photodetector, the germanium thin film layer serves as the light absorption layer. First, the germanium absorption layer is formed by photolithography and etching, and then a pn junction is formed by doping or by forming interdigitated electrodes to form a photodetector.

10. The preparation method according to claim 2, characterized in that, In the optical gain section, a growth window is opened by etching the upper insulating substrate layer on the germanium substrate growth layer. It is necessary to ensure that no natural oxide is generated on the germanium substrate growth layer after the growth window is opened, and then a compound semiconductor active layer is grown.

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