Substrate and display device

Abstract

The embodiments of the present disclosure provide a substrate and a display device. The substrate includes a first gate line and a second gate line respectively located on both sides of the corresponding row of sub-pixels, the first gate line is connected to the thin film transistors corresponding to a part of the sub-pixels in the corresponding row of sub-pixels, and the second gate line is connected to the thin film transistors corresponding to another part of the sub-pixels. The substrate includes a first metal layer, a first insulating layer, and a second metal layer sequentially arranged on the substrate. The first metal layer includes a first gate line and a second gate line and a first metal trace. The first metal trace is located between two adjacent columns of sub-pixels and avoids the first gate line and the second gate line; the second metal layer includes a data line, and the data line located between the same two adjacent columns of sub-pixels corresponds to the first metal trace, and both ends of the first metal trace are connected to the corresponding data line. The present disclosure reduces the resistance of the data line, which can improve insufficient pixel charging and improve the vertical stripe defects of the product.

Description

Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a substrate and a display device. Background Art

[0002] With fierce competition in the MNT (Monitor) market, cost reduction is crucial to enhance product competitiveness. While dual-gate drive can reduce costs, dual-gate drive display products are prone to insufficient charging at high refresh rates, leading to vertical streaks. Existing solutions for improving vertical streak defects are limited by product manufacturing processes and are no longer able to meet future product requirements. Summary of the Invention

[0003] Embodiments of the present disclosure provide a substrate and a display device to solve or alleviate one or more technical problems in the prior art.

[0004] As a first aspect of an embodiment of the present disclosure, an embodiment of the present disclosure provides a substrate, comprising a plurality of sub-pixels arranged in an array and a data line located between two adjacent columns of sub-pixels. The substrate further comprises a plurality of gate lines, the gate lines comprising a first gate line and a second gate line corresponding to each row of sub-pixels, the first gate line and the second gate line being located on either side of the corresponding row of sub-pixels, the first gate line being connected to thin film transistors corresponding to a portion of the sub-pixels in the corresponding row, and the second gate line being connected to thin film transistors corresponding to another portion of the sub-pixels in the corresponding row. The substrate comprises:

[0005] substrate;

[0006] a first metal layer located on one side of the substrate, the first metal layer including a first gate line and a second gate line, the first metal layer further including a first metal routing line, the first metal routing line being located between two adjacent columns of sub-pixels, the first metal routing line avoiding the first gate line and the second gate line;

[0007] a first insulating layer, located on a side of the first metal layer facing away from the substrate;

[0008] The second metal layer is located on the side of the first insulating layer away from the substrate. The second metal layer includes data lines. The data lines located between the same two adjacent columns of sub-pixels correspond to the first metal lines. Both ends of the first metal lines are connected to the corresponding data lines.

[0009] In some embodiments, there are at least two first metal traces connected to the same data line, and each first metal trace is defined between a corresponding first gate line and a corresponding second gate line.

[0010] In some embodiments, the thickness of the second metal layer is less than the thickness of the first metal layer.

[0011] In some embodiments, the thickness of the first metal layer ranges from 6000 angstroms to 8000 angstroms; and / or the thickness of the second metal layer ranges from 3000 angstroms to 6000 angstroms.

[0012] In some embodiments, the substrate further includes a first transparent conductive layer and a second insulating layer located between the substrate and the first metal layer, the second insulating layer is located between the first transparent conductive layer and the first metal layer, and the first transparent conductive layer includes a pixel electrode;

[0013] The substrate further includes a thin film transistor, which includes a gate, a first electrode, and a second electrode. The first metal layer includes the gate, which is connected to the gate line. The second metal layer includes a first electrode and a second electrode, which is connected to the data line and the second electrode is connected to the pixel electrode.

[0014] The substrate also includes a passivation layer and a second transparent conductive layer. The passivation layer is located on the side of the second metal layer away from the substrate. The second transparent conductive layer is located on the side of the passivation layer away from the substrate. The second transparent conductive layer includes a common electrode corresponding to the pixel electrode.

[0015] In some embodiments, the passivation layer is provided with a first via hole, a second via hole, and a third via hole, the first via hole exposing the pixel electrode and the second electrode, the second via hole exposing the data line and one end of the first metal trace, and the third via hole exposing the other end of the data line and the first metal trace;

[0016] The second transparent conductive layer also includes a first connecting portion, a second connecting portion and a third connecting portion respectively located in the first via hole, the second via hole and the third via hole, the pixel electrode and the second electrode are connected through the first connecting portion, the data line and one end of the first metal routing are connected through the second connecting portion, and the data line and the other end of the first metal routing are connected through the third connecting portion.

[0017] In some embodiments, the first metal trace is provided with a first protrusion and a second protrusion located at both ends, the orthographic projections of the first protrusion and the second protrusion on the substrate are located outside the orthographic projections of the corresponding data lines on the substrate, the second via exposes at least a portion of the surface of the first protrusion, and the third via exposes at least a portion of the surface of the second protrusion.

[0018] In some embodiments, the first insulating layer has a thickness ranging from 3000 angstroms to 4000 angstroms; and / or the passivation layer has a thickness ranging from 7500 angstroms to 9000 angstroms.

[0019] In some embodiments,

[0020] A data line is provided for every two columns of sub-pixels, the jth data line is connected to the thin film transistors corresponding to the sub-pixels in the 2j-1th and 2jth columns in odd rows, and the jth data line is connected to the thin film transistors corresponding to the sub-pixels in the 2j-3th and 2j-2nd columns in even rows, where j ≥ 1 and is a positive integer; or

[0021] A data line is set for every two columns of sub-pixels, the jth data line is connected to the thin film transistors corresponding to the sub-pixels in the 2j-3th and 2j-2th columns in the odd rows, and the jth data line is connected to the thin film transistors corresponding to the sub-pixels in the 2j-1th and 2jth columns in the even rows, where j≥1 and j is a positive integer.

[0022] In some embodiments, each row of sub-pixels includes a plurality of pixel units, each pixel unit includes three sub-pixels, and in a row of sub-pixels, two adjacent columns of pixel units constitute a pixel unit group;

[0023] In the pixel unit group, the first gate line is connected to the thin film transistors corresponding to the 1st, 4th and 6th columns of sub-pixels in the pixel unit group, and the second gate line is connected to the thin film transistors corresponding to the 2nd, 3rd and 5th columns of sub-pixels in the pixel unit group.

[0024] As a second aspect of the embodiments of the present disclosure, the embodiments of the present disclosure provide a display device, including the substrate in any embodiment of the present disclosure.

[0025] According to the technical solution of the embodiment of the present disclosure, the first metal layer is further provided with a first metal trace, and the first metal trace and the corresponding data line are located between the same two adjacent columns of sub-pixels, and both ends of the first metal trace are connected to the corresponding data lines. Thus, the first metal trace and the corresponding data line are connected in parallel in the substrate, which greatly reduces the resistance of the data line, can improve the charging efficiency of the pixel, improve the insufficient charging of the pixel, and further improve the vertical stripe defect of the product, thereby enhancing the competitiveness of the product.

[0026] The above summary is for illustrative purposes only and is not intended to be limiting in any way. In addition to the illustrative aspects, embodiments and features described above, further aspects, embodiments and features of the present disclosure will be readily apparent by reference to the accompanying drawings and the following detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] In the accompanying drawings, unless otherwise specified, the same reference numerals throughout the multiple drawings represent the same or similar components or elements. These drawings are not necessarily drawn to scale. It should be understood that these drawings only depict some embodiments according to the present disclosure and should not be regarded as limiting the scope of the present disclosure.

[0028] Figure 1Schematic diagram of the planar connection of the substrate in one embodiment of the present disclosure;

[0029] Figure 2 for Figure 1 Schematic diagram of the plane structure of part A;

[0030] Figure 3 for Figure 2 BB cross-sectional structure diagram in;

[0031] Figure 4 This is a schematic diagram of a planar connection of a substrate in another embodiment of the present disclosure;

[0032] Figure 5A is a partial plan view of a substrate after forming a first transparent conductive layer in one embodiment;

[0033] Figure 5B for Figure 5A BB cross-section diagram in;

[0034] Figure 6A is a partial plan view of a substrate after a first metal layer is formed in an embodiment;

[0035] Figure 6B for Figure 6A BB cross-section diagram in;

[0036] Figure 7A is a partial plan view of a substrate after a second metal layer is formed in an embodiment;

[0037] Figure 7B for Figure 7A BB cross-section diagram in;

[0038] Figure 8A A schematic partial plan view of a substrate after a passivation layer is formed in an embodiment;

[0039] Figure 8B for Figure 8A Schematic diagram of the BB cross section.

[0040] Description of reference numerals:

[0041] 11. Substrate; 121. Pixel electrode; 13. Second insulating layer; 140. Gate electrode; 141. First gate line; 142. Second gate line; 143. First metal trace; 15. First insulating layer; 161. Active layer; 171. First electrode; 172. Second electrode; 173. Data line; 18. Passivation layer; 181. First via hole; 182. Second via hole; 183. Third via hole; 191. First connecting portion; 192. Second connecting portion; 193. Third connecting portion. DETAILED DESCRIPTION

[0042] In the following, only certain exemplary embodiments are briefly described. As will be appreciated by those skilled in the art, the described embodiments may be modified in various ways without departing from the spirit or scope of the present disclosure, and different embodiments may be combined in any manner without conflict. Therefore, the drawings and description are to be regarded as illustrative in nature and not restrictive.

[0043] With dual-gate line drive, the charging time of the pixel electrode 121 is about half of that of single-gate line drive. Therefore, under high refresh rate conditions, the pixel electrode 121 is prone to insufficient charging. In the case of insufficient charging of the pixel electrode 121, vertical streaks will appear. In order to improve the vertical streak defects, several solutions are proposed in the related art: (1) increasing the thickness of the gate metal layer and the source and drain metal layer to reduce the RC delay; (2) reducing the thickness of the gate insulating layer to increase the turn-on current of the thin film transistor, thereby increasing the charging rate; (3) increasing the thickness of the passivation layer 18 (PVX) to reduce the storage capacitance Cst, thereby increasing the charging rate, etc.

[0044] The solutions in related technologies will lead to increased material usage, increase product costs, and affect product yield and production capacity. Moreover, as product refresh rates continue to increase, it is difficult to further meet the film thickness requirements in terms of process.

[0045] In order to solve the problem of vertical streaks, an embodiment of the present disclosure provides a substrate.

[0046] Figure 1 Schematic diagram of the planar connection of the substrate in one embodiment of the present disclosure. Figure 2 for Figure 1 Schematic diagram of the plane structure of part A; Figure 3 for Figure 2 In one embodiment, as shown in FIG. Figure 1 As shown, the substrate may include a plurality of sub-pixels 100 arranged in an array. The substrate further includes a data line 173 and a gate line. The data line 173 is located between two adjacent columns of sub-pixels 100. The gate lines may include a first gate line 141 and a second gate line 142 corresponding to each row of sub-pixels 100. In other words, each row of sub-pixels 100 corresponds to a first gate line 141 and a second gate line 142. The first gate line 141 and the second gate line 142 are respectively located on either side of the corresponding row of sub-pixels 100. For example, the first gate line 141 is located on the upper side of the corresponding row of sub-pixels 100, and the second gate line 142 is located on the lower side of the corresponding row of sub-pixels 100. The first gate line 141 is connected to the thin film transistors corresponding to a portion of the sub-pixels 100 in the corresponding row of sub-pixels 100, and the second gate line 142 is connected to the thin film transistors corresponding to another portion of the sub-pixels 100 in the corresponding row of sub-pixels 100. Thus, one row of sub-pixels 100 corresponds to two gate lines.

[0047] like Figure 2 and Figure 3 As shown, the substrate includes a substrate 11, a first metal layer 14, a first insulating layer 15, and a second metal layer. The first metal layer 14 is located on one side of the substrate 11 and includes a first gate line 141 and a second gate line 142. The first metal layer 14 also includes a first metal trace 143, which is located between two adjacent columns of sub-pixels 100.

[0048] The first metal trace 143 is arranged on the same layer as the first gate line 141 and the second gate line 142 . Therefore, the first metal trace 143 needs to avoid the first gate line 141 and the second gate line 142 to ensure that the first metal trace 143 is not connected to the first gate line 141 and the first metal trace 143 is not connected to the second gate line 142 .

[0049] The first insulating layer 15 is located on the side of the first metal layer 14 facing away from the substrate 11. The second metal layer is located on the side of the first insulating layer 15 facing away from the substrate 11. The second metal layer includes a data line 173, and the data line 173 located between the same two adjacent columns of sub-pixels 100 corresponds to the first metal trace 143. In other words, the first metal trace 143 connected to the data line 173 corresponds to the data line 173, and the corresponding data line 173 and the first metal trace 143 are located between the same two adjacent columns of sub-pixels 100. Both ends of the first metal trace 143 are connected to the corresponding data line 173. It should be noted that the end of the first metal trace 143 should be understood as a portion of the first metal trace 143 close to one end edge.

[0050] In the embodiment of the present disclosure, the first metal layer 14 is also provided with a first metal trace 143. The first metal trace 143 and the corresponding data line 173 are located between the same two adjacent columns of sub-pixels 100, and both ends of the first metal trace 143 are connected to the corresponding data line 173. Thus, the first metal trace 143 and the corresponding data line 173 are connected in parallel in the substrate, which greatly reduces the resistance of the data line 173, can improve the charging efficiency of the pixel, improve the insufficient charging of the pixel, and further improve the vertical stripe defect of the product, thereby improving the competitiveness of the product.

[0051] In the related art, in order to improve the vertical streak defect, it is necessary to increase the thickness of the first metal layer 14 and the second metal layer at the same time. In the embodiment of the present disclosure, by setting the first metal trace 143 in the first metal layer 14, and connecting both ends of the first metal trace 143 to the corresponding data line 173, the resistance of the data line 173 is greatly reduced. Such a solution achieves the purpose of reducing the resistance of the data line 173 without increasing the thickness of the second metal layer where the data line 173 is located, ensuring that the second metal layer adopts a smaller thickness. It is understandable that the source and drain of the thin film transistor in the substrate are usually arranged in the same layer as the data line 173. When a thinner second metal layer is used, the etching of the active layer 161 channel in the process can be reduced, which is conducive to reducing the channel width, increasing the turn-on current of the thin film transistor, further improving the charging efficiency, improving the problem of insufficient charging, and thus improving the vertical streak defect. In addition, the thinner thickness of the second metal layer can greatly improve the product yield and save production capacity.

[0052] In one embodiment, the thickness of the second metal layer may be less than the thickness of the first metal layer 14 .

[0053] Exemplarily, the thickness of the first metal layer 14 ranges from 6000 angstroms to 8000 angstroms. For example, the thickness of the first metal layer 14 can be 6000 angstroms, 6500 angstroms, 7000 angstroms, 7500 angstroms, or 8000 angstroms.

[0054] The thickness of the second metal layer ranges from 3000 angstroms to 6000 angstroms. For example, the thickness of the second metal layer can be 3000 angstroms, 3500 angstroms, 4000 angstroms, 4500 angstroms, 5000 angstroms, 5500 angstroms, or 8000 angstroms.

[0055] It should be noted that, in the present disclosure, the thickness of the film layer A refers to the dimension of the film layer A in a direction perpendicular to the substrate 11 .

[0056] To further reduce the resistance of the data line 173, there can be multiple first metal traces 143. There can be at least two first metal traces 143 connected to the same data line 173, with each first metal trace 143 being located between the corresponding first gate line 141 and second gate line 142. The multiple first metal traces 143 corresponding to the data line 173 are all located between the same two adjacent columns of sub-pixels 100. In this way, each first metal trace 143 corresponding to a data line 173 is connected in parallel with the data line 173, further reducing the resistance of the data line 173 and improving the charging efficiency of the pixel.

[0057] For example, Figure 1The data line 173b is located between the third column of sub-pixels 100 and the fourth column of sub-pixels 100, and the multiple first metal traces 143 corresponding to the data line 173b are all located between the third column of sub-pixels 100 and the fourth column of sub-pixels 100, and each first metal trace 143 is connected in parallel to the data line 173.

[0058] Among them, Figure 1 and Figure 2 As shown, the corresponding first gate line 141 and the second gate line 142 are the first gate line 141 and the second gate line 142 corresponding to the sub-pixels 100 in the same row. For example, Figure 1 The first gate line 141a and the second gate line 142a corresponding to the second row of sub-pixels 100. Each first metal trace 143 is defined between the corresponding first gate line 141 and the second gate line 142. It can be understood that the first metal trace 143a is defined between the first gate line 141a and the second gate line 142a.

[0059] The substrate may also include a thin film transistor, which includes a gate electrode 140, a first electrode 171, and a second electrode 172. Gate electrode 140 is connected to a gate line, and first electrode 171 is connected to a data line 173. The substrate may also include a pixel electrode 121 and a common electrode 190. Pixel electrode 121 is connected to second electrode 172, and common electrode 190 is connected to a common electrode signal of the substrate. Pixel electrode 121 and common electrode 190 form a storage capacitor Cst.

[0060] In one embodiment, a pixel electrode 121 may be formed on the side of the second metal layer facing away from the substrate 11 , a passivation layer 18 may be provided on the side of the pixel electrode 121 facing away from the substrate 11 , and a common electrode 190 may be formed on the side of the passivation layer 18 facing away from the substrate 11 .

[0061] In one embodiment, Figure 2 and 3 As shown, the substrate further includes a first transparent conductive layer and a second insulating layer 13 located between the substrate 11 and the first metal layer 14. The first transparent conductive layer and the second insulating layer 13 are sequentially located between the substrate 11 and the first metal layer 14, with the first transparent conductive layer located on the side of the substrate 11 facing the first metal layer 14, and the second insulating layer 13 located between the first transparent conductive layer and the first metal layer 14. The material of the first transparent conductive layer may include a transparent conductive material, such as indium tin oxide (ITO) or indium zinc oxide (IZO). The first transparent conductive layer includes a pixel electrode 121.

[0062] The substrate may further include a thin film transistor, which includes a gate electrode 140, a first electrode 171, and a second electrode 172. The first metal layer 14 includes the gate electrode 140, which is connected to the gate line. The second metal layer includes a first electrode 171 and a second electrode 172. The first electrode 171 is connected to the data line 173, and the second electrode 172 is connected to the pixel electrode 121. One of the first electrode 171 and the second electrode 172 can be a source electrode, and the other can be a drain electrode.

[0063] The substrate may further include a passivation layer 18 and a second transparent conductive layer. The passivation layer 18 is located on the side of the second metal layer facing away from the substrate 11. The second transparent conductive layer may be located on the side of the passivation layer 18 facing away from the substrate 11. The second transparent conductive layer includes a common electrode 190, which corresponds to the pixel electrode 121. The common electrode 190 and the pixel electrode 121 form a storage capacitor Cst. The material of the second transparent conductive layer may include a transparent conductive material, such as indium tin oxide (ITO) or indium zinc oxide (IZO).

[0064] The substrate of the embodiment of the present disclosure includes at least three film layers, namely, a second insulating layer 13, a first insulating layer 15, and a passivation layer 18, between the pixel electrode 121 and the common electrode 190. Compared with a storage capacitor in which only the passivation layer 18 is provided between the pixel electrode 121 and the common electrode 190, the distance between the pixel electrode 121 and the common electrode 190 is increased, and the storage capacitance Cst is reduced, which can improve the charging rate of the pixel and improve the problem of insufficient charging.

[0065] In one embodiment, corresponding via holes exposing the surfaces of both ends of the first metal trace 143 may be opened on the first insulating layer 15 . When forming the data line 173 , the data line 173 may be connected to both ends of the first metal trace 143 through the via holes.

[0066] In one embodiment, Figure 3 As shown, the passivation layer 18 is provided with a first via hole 181, a second via hole 182, and a third via hole 183. The first via hole 181 exposes the pixel electrode 121 and the second electrode 172. The second via hole 182 exposes the data line 173 and one end of the first metal trace 143. The third via hole 183 exposes the other end of the data line 173 and the first metal trace 143.

[0067] The first via hole 181 exposes the pixel electrode 121 and the second electrode 172. It should be understood that the first via hole 181 exposes a portion of the surface of the pixel electrode 121 and a portion of the surface of the second electrode 172. The second via hole 182 exposes the data line 173 and one end of the first metal trace 143. The third via hole 183 exposes the data line 173 and the other end of the first metal trace 143. It should be understood that the second via hole 182 exposes a portion of the surface of the data line 173 and a portion of the surface of one end of the first metal trace 143, and the third via hole 183 exposes a portion of the surface of the data line 173 and a portion of the surface of the other end of the first metal trace 143.

[0068] like Figure 2 and Figure 3 As shown, the second transparent conductive layer further includes a first connecting portion 191, a second connecting portion 192, and a third connecting portion 193. The first connecting portion 191 is located in the first via hole 181. That is, the orthographic projection of the first via hole 181 on the substrate 11 can be located within the orthographic projection of the first connecting portion 191 on the substrate 11. Thus, the pixel electrode 121 and the second electrode 172 are connected via the first connecting portion 191.

[0069] Second connection portion 192 is located in second via 182, that is, the orthographic projection of second via 182 on substrate 11 can be located within the projection of second connection portion 192 on substrate 11. Third connection portion 193 is located in third via 183, that is, the orthographic projection of third via 183 on substrate 11 can be located within the orthographic projection of third connection portion 193 on substrate 11. Thus, one end of data line 173 is connected to first metal trace 143 via second connection portion 192, and the other end of data line 173 is connected to first metal trace 143 via third connection portion 193.

[0070] With such a structure, the first connection portion 191 between the pixel electrode 121 and the second electrode 172 and the second connection portion 192 and the third connection portion 193 between the data line 173 and the first metal trace 143 are simultaneously formed when forming the common electrode 190, which can simplify the substrate manufacturing process and reduce costs.

[0071] In one embodiment, Figure 2 As shown, in the direction perpendicular to the data line 173 ( Figure 2 The orthographic projection of data line 173 on substrate 11 is within the orthographic projection of first metal trace 143 on substrate 11. The width of data line 173 is smaller than the width of first metal trace 143. This increases the width of first metal trace 143 and reduces its resistance, further reducing the resistance of data line 173 and improving pixel charging efficiency, thereby preventing pixel undercharging.

[0072] In order to facilitate the connection between the data line 173 and the first metal trace 143, as shown in FIG. Figure 2 As shown, the first metal trace 143 is provided with a first protrusion 1431 and a second protrusion 1432 at its two ends. The first protrusion 1431 is located at one end of the first metal trace 143, and the second protrusion 1432 is located at the other end of the first metal trace 143. The orthographic projections of the first protrusion 1431 and the second protrusion 1432 on the substrate 11 are both located outside the orthographic projections of the corresponding data line 173 on the substrate 11. The second via 182 exposes at least a portion of the surface of the first protrusion 1431, and the third via 183 exposes at least a portion of the surface of the second protrusion 1432. Thus, the second connecting portion 192 connects the data line 173 to the first protrusion 1431 through the second via 182, and the third connecting portion 193 connects the data line 173 to the second protrusion 1432 through the third via 183, thereby connecting the data line 173 to the two ends of the first metal trace 143.

[0073] By providing the first protrusion 1431 and the second protrusion 1432, the data line 173 and the first protrusion 1431, as well as the data line 173 and the second protrusion 1432 are formed in a stepped shape in position, thereby making it easier to form the second connection portion 192 that can connect the data line 173 to the first protrusion 1431, and easier to form the third connection portion 193 that can connect the data line 173 to the second protrusion 1432, thereby reducing the difficulty of the process.

[0074] For example, the thin film transistor may further include an active layer 161 , which may be located between the first insulating layer 15 and the second metal layer. A first electrode 171 and a second electrode 172 of the thin film transistor are both connected to the active layer 161 .

[0075] In one embodiment, Figure 3 As shown, the thickness of the first insulating layer 15 can range from 3000 angstroms to 4000 angstroms. For example, the thickness of the first insulating layer 15 can be 3000 angstroms, 3500 angstroms, or 4000 angstroms. The first insulating layer 15 is located between the gate 140 (located on the first metal layer 14) and the active layer 161. Setting the thickness of the first insulating layer 15 to 3000 angstroms to 4000 angstroms can increase the turn-on current of the thin film transistor and improve the charging rate of the pixel.

[0076] The thickness of the passivation layer 18 can range from 7500 angstroms to 9000 angstroms. For example, the thickness of the passivation layer 18 can be 7500 angstroms, 8000 angstroms, 8500 angstroms, or 9000 angstroms. This thickness of the passivation layer 18 is significantly greater than that of the passivation layer 18 in the related art, which can reduce the storage capacitance Cst, thereby increasing the charging rate of the pixel and improving the problem of insufficient charging.

[0077] like Figure 1 As shown, a row of sub-pixels 100 corresponds to two gate lines, namely a first gate line 141 and a second gate line 142. The first gate line 141 is connected to the thin film transistors corresponding to a part of the sub-pixels 100 in the corresponding row of sub-pixels 100, and the second gate line 142 is connected to the thin film transistors corresponding to another part of the sub-pixels 100 in the corresponding row of sub-pixels 100. Thus, a row of sub-pixels 100 is driven by dual gate lines.

[0078] like Figure 1 As shown, each row of sub-pixels 100 includes multiple pixel units, each of which includes three sub-pixels 100, for example, the three sub-pixels 100 are R sub-pixels 100, G sub-pixels 100, and B sub-pixels 100. In a row of sub-pixels 100, two adjacent columns of pixel units form a pixel unit group 200. In the pixel unit group 200, the first gate line 141 is connected to the thin film transistors corresponding to the sub-pixels 100 in the first, fourth, and sixth columns in the pixel unit group 200; and the second gate line 142 is connected to the thin film transistors corresponding to the sub-pixels 100 in the second, third, and fifth columns in the pixel unit group.

[0079] For example, in Figure 1 For the pixel unit group 200, in the pixel unit group 200, the first gate line 141 is connected to the gates 140 of the thin film transistors corresponding to the 1st column (R1 sub-pixel), the 4th column (R2 sub-pixel) and the 6th column (B2 sub-pixel); the second gate line 142 is connected to the gates 140 of the thin film transistors corresponding to the 2nd column (G1 sub-pixel), the 3rd column (B1 sub-pixel) and the 5th column (G2 sub-pixel).

[0080] It should be noted that the connection method between the first gate line 141 and the second gate line 142 and the corresponding row of sub-pixels 100 is not limited to Figure 1 As shown, as long as the first gate line 141 is connected to the thin film transistors corresponding to a part of the sub-pixels 100 in the corresponding row, the second gate line 142 is connected to the thin film transistors corresponding to another part of the sub-pixels 100 in the row.

[0081] For example, Figure 1As shown, a data line 173 is provided for every two columns of sub-pixels 100. The j-th data line 173 is connected to the thin film transistors corresponding to the sub-pixels 100 in the 2j-1 and 2j columns in odd rows, and the j-th data line 173 is connected to the thin film transistors corresponding to the sub-pixels 100 in the 2j-3 and 2j-2 columns in even rows. Wherein, j ≥ 1, and j is a positive integer.

[0082] For example, the second data line 173 is connected to the first electrode 171 of the thin film transistor corresponding to the 3rd and 4th columns of sub-pixels 100 in the 3rd row, and the second data line 173 is connected to the first electrode 171 of the thin film transistor corresponding to the 1st and 2nd columns of sub-pixels 100 in the 4th row.

[0083] It should be noted that, when j=1, there are no sub-pixels 100 in the 2j-3th column and the 2j-2nd column, and thus the first data line 173 has no connection in the even-numbered rows.

[0084] Figure 4 FIG. 1 is a schematic diagram of a planar connection of a substrate in another embodiment of the present disclosure. For example, Figure 4 As shown, a data line 173 is set for every two columns of sub-pixels 100, the j-th data line 173 is connected to the thin film transistors corresponding to the 2j-3 column and the 2j-2 column sub-pixels 100 in the odd rows, and the j-th data line 173 is connected to the thin film transistors corresponding to the 2j-1 column and the 2j column sub-pixels 100 in the even rows, where j≥1 and j is a positive integer.

[0085] For example, the second data line 173 is connected to the thin film transistors corresponding to the first and second columns of sub-pixels 100 in the first row, and the second data line 173 is connected to the thin film transistors corresponding to the third and fourth columns of sub-pixels 100 in the second row.

[0086] It should be noted that, when j=1, there are no sub-pixels 100 in the 2j-3th column and the 2j-2nd column, and thus the first data line 173 has no connection in the odd-numbered rows.

[0087] In other embodiments, a data line may be provided for every other column of sub-pixels, that is, a plurality of data lines correspond one-to-one to a plurality of columns of sub-pixels.

[0088] The following combination Figure 3 The technical solutions of the embodiments of the present disclosure will be described in detail. It is understood that the "patterning" mentioned herein includes processes such as photoresist coating, mask exposure, development, etching, and photoresist stripping when the patterned material is an inorganic material or metal, and includes processes such as mask exposure and development when the patterned material is an organic material. The evaporation, deposition, coating, and coating mentioned herein are all mature preparation processes in the relevant technology.

[0089] A first transparent conductive film is deposited on the substrate 11, and a patterning process is used to form a first transparent conductive layer. The first transparent conductive layer includes a pixel electrode 121. The pixel electrode 121 is located in the sub-pixel 100. Figure 5A and Figure 5B As shown, Figure 5A This is a partial plan view of a substrate after forming a first transparent conductive layer in one embodiment. Figure 5B for Figure 5A Schematic diagram of the BB cross section.

[0090] A second insulating layer 13 is formed on a side of the first transparent conductive layer facing away from the substrate 11 .

[0091] A first metal film is deposited on the side of the second insulating layer 13 facing away from the substrate 11, and a patterning process is used to form a first metal layer 14. The first metal layer 14 includes a first gate line 141, a second gate line 142, and a first metal trace 143. The first gate line 141 and the second gate line 142 are respectively located on the upper and lower sides of each row of sub-pixels 100. The first metal trace 143 is located between two adjacent columns of sub-pixels 100, and the first metal trace 143 avoids the first gate line 141 and the second gate line 142. Figure 6A and Figure 6B As shown, Figure 6A This is a partial plan view of a substrate after a first metal layer is formed in an embodiment. Figure 6B for Figure 6A The first metal trace 143 is provided with a first protrusion 1431 and a second protrusion 1432 at both ends.

[0092] A first insulating layer 15 is formed on the side of the first metal layer 14 facing away from the substrate 11; an active layer 161 is formed on the side of the first insulating layer 15 facing away from the substrate 11; a second metal layer is formed on the side of the active layer 161 facing away from the substrate 11, and the second metal layer includes a data line 173, a first electrode 171 and a second electrode 172. Figure 7A and Figure 7B As shown, Figure 7A FIG. 1 is a partial plan view of a substrate after forming a second metal layer in an embodiment. Figure 7B for Figure 7A The orthographic projections of the first protrusion 1431 and the second protrusion 1432 on the substrate 11 are located outside the orthographic projection of the data line 173 on the substrate 11 .

[0093] A passivation layer 18 is formed on the side of the second metal layer facing away from the substrate 11. The passivation layer 18 is provided with a first via hole 181, a second via hole 182, and a third via hole 183. The first via hole 181 exposes the pixel electrode 121 and the second electrode 172. The second via hole 182 exposes the data line 173 and one end of the first metal trace 143. The third via hole 183 exposes the other end of the data line 173 and the first metal trace 143. Figure 8A and Figure 8B As shown, Figure 8A This is a partial plan view of a substrate after a passivation layer is formed in an embodiment. Figure 8B for Figure 8A Exemplarily, the second via hole 182 exposes at least a portion of the surface of the first protrusion 1431 , and the third via hole 183 exposes at least a portion of the surface of the second protrusion 1432 .

[0094] A second transparent conductive layer is formed on the side of the passivation layer 18 facing away from the substrate 11. The second transparent conductive layer includes a common electrode 190, which corresponds to the pixel electrode 121. The second transparent conductive layer may also include a common electrode signal line 191, which is connected to the common electrode signal line. The common electrode signal line 191 may be located between two adjacent columns of sub-pixels and between two adjacent data lines. For example, Figure 1 and Figure 4 In the example, the data line is located between the second and third columns of sub-pixels, and the common electrode signal line 191 is located between the first and second columns of sub-pixels and between the first and second data lines.

[0095] The second transparent conductive layer further includes a first connecting portion 191, a second connecting portion 192, and a third connecting portion 193 located in the first via hole 181, the second via hole 182, and the third via hole 183, respectively. The pixel electrode 121 and the second electrode 172 are connected via the first connecting portion 191, the data line 173 and one end of the first metal trace 143 are connected via the second connecting portion 192, and the other end of the data line 173 and the first metal trace 143 are connected via the third connecting portion 193. Figure 2 and Figure 3 shown.

[0096] In an exemplary embodiment, the first insulating layer 15 and the second insulating layer 13 may be made of any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), and may be a single layer, multiple layers, or a composite layer. The gate 140, source, drain, and metal traces may be made of metal materials such as any one or more of silver (Ag), copper (Cu), aluminum (Al), titanium (Ti), and molybdenum (Mo), or alloys of the above metals, such as aluminum neodymium (AlNd) or molybdenum niobium (MoNb), and may be a single layer or a multilayer composite structure, such as Ti / Al / Ti. The active layer 161 may be made of various materials, such as amorphous indium gallium zinc oxide (a-IGZO), zinc oxynitride (ZnON), indium zinc tin oxide (IZTO), amorphous silicon (a-Si), polycrystalline silicon (p-Si), sexithiophene, and polythiophene. This means that the present disclosure is applicable to transistors manufactured using oxide, silicon, and organic technologies.

[0097] Based on the inventive concept of the aforementioned embodiments, the present disclosure further provides a display device, which includes the substrate of any embodiment of the present disclosure. The display device may be a liquid crystal display device.

[0098] The display device can be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, a navigator, or the like.

[0099] The refresh rate of the display device in the embodiment of the present disclosure may be 100 Hz or 120 Hz.

[0100] In the display device of the embodiment of the present disclosure, the first metal layer of the substrate is further provided with a first metal trace. The first metal trace and the corresponding data line are located between the same two adjacent columns of sub-pixels, and both ends of the first metal trace are connected to the corresponding data line. Therefore, the first metal trace and the corresponding data line are connected in parallel in the substrate, which greatly reduces the resistance of the data line, improves the charging efficiency of the pixel, improves the insufficient charging of the pixel, and further improves the vertical stripe defect of the product, thereby enhancing the competitiveness of the product. In addition, the thickness of the second metal layer in such a display device is relatively thin, which greatly improves the product yield, saves production capacity, and is conducive to the quantification of the product.

[0101] In the description of this specification, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", "axial", "radial", "circumferential" and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present disclosure and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present disclosure.

[0102] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features being referred to. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of such features. Throughout the present disclosure, "plurality" means two or more, unless otherwise specifically defined.

[0103] In this disclosure, unless otherwise expressly specified or limited, terms such as "mounted," "connected," "connect," and "fixed" should be understood broadly. For example, they may refer to fixed connections, detachable connections, or integration; mechanical connections, electrical connections, or communication; direct connections or indirect connections through an intermediate medium; and internal connections between two components or interactions between two components. Those skilled in the art will understand the specific meanings of these terms in this disclosure based on specific circumstances.

[0104] In the present disclosure, unless otherwise expressly specified or limited, a first feature being "above" or "below" a second feature may include the first and second features being in direct contact, or may include the first and second features being in contact not directly but through another feature between them. Moreover, a first feature being "above," "above," and "above" a second feature includes the first feature being directly above and obliquely above the second feature, or simply indicates that the first feature is higher in level than the second feature. A first feature being "below," "below," and "below" a second feature includes the first feature being directly above and obliquely above the second feature, or simply indicates that the first feature is lower in level than the second feature.

[0105] The disclosure above provides many different embodiments or examples for implementing different structures of the present disclosure. In order to simplify the present disclosure, the components and settings of specific examples are described above. Of course, these are merely examples and are not intended to limit the present disclosure. In addition, the present disclosure may repeat reference numbers and / or reference letters in different examples. Such repetition is for the purpose of simplicity and clarity and does not in itself indicate the relationship between the various embodiments and / or settings discussed.

[0106] The above are only specific embodiments of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any person skilled in the art can easily conceive of various modifications or substitutions within the technical scope disclosed in this disclosure, and such modifications or substitutions should be included in the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection of the claims.

Claims

1. A substrate, characterized in that The substrate includes a plurality of sub-pixels arranged in an array and a data line located between two adjacent columns of sub-pixels. The substrate also includes a plurality of gate lines, the gate lines including a first gate line and a second gate line corresponding to each row of sub-pixels, the first gate line and the second gate line being located on both sides of the corresponding row of sub-pixels, the first gate line being connected to thin film transistors corresponding to a portion of the sub-pixels in the corresponding row, and the second gate line being connected to thin film transistors corresponding to another portion of the sub-pixels in the corresponding row. The substrate includes: substrate; a first metal layer located on one side of the substrate, the first metal layer including the first gate line and the second gate line, the first metal layer further including a first metal routing line, the first metal routing line being located between two adjacent columns of sub-pixels, and the first metal routing line avoiding the first gate line and the second gate line; a first insulating layer, located on a side of the first metal layer facing away from the substrate; a second metal layer located on a side of the first insulating layer facing away from the substrate, the second metal layer including the data line, the data line located between two adjacent columns of sub-pixels corresponding to the first metal line, and both ends of the first metal line connected to the corresponding data line; The substrate further includes a first transparent conductive layer and a second insulating layer located between the substrate and the first metal layer, the second insulating layer is located between the first transparent conductive layer and the first metal layer, and the first transparent conductive layer includes a pixel electrode; The substrate further includes a thin film transistor, the thin film transistor including a gate, a first electrode, and a second electrode, the first metal layer including the gate, the gate being connected to the gate line, the second metal layer including the first electrode and the second electrode, the first electrode being connected to the data line, and the second electrode being connected to the pixel electrode; The substrate further includes a passivation layer and a second transparent conductive layer, the passivation layer is located on a side of the second metal layer facing away from the substrate, the second transparent conductive layer is located on a side of the passivation layer facing away from the substrate, the second transparent conductive layer includes a common electrode, and the common electrode corresponds to the pixel electrode; The passivation layer is provided with a first via hole, a second via hole, and a third via hole, wherein the first via hole exposes the pixel electrode and the second electrode, the second via hole exposes the data line and one end of the first metal wiring, and the third via hole exposes the other end of the data line and the first metal wiring; The second transparent conductive layer further includes a first connecting portion, a second connecting portion, and a third connecting portion respectively located in the first via hole, the second via hole, and the third via hole, the pixel electrode and the second electrode are connected via the first connecting portion, the data line and one end of the first metal trace are connected via the second connecting portion, and the data line and the other end of the first metal trace are connected via the third connecting portion; The first metal trace is provided with a first protrusion and a second protrusion located at both ends, the orthographic projections of the first protrusion and the second protrusion on the substrate are located outside the orthographic projections of the corresponding data line on the substrate, the second via exposes at least a portion of the surface of the first protrusion, and the third via exposes at least a portion of the surface of the second protrusion.

2. The substrate according to claim 1, wherein There are at least two first metal wirings connected to the same data line, and each first metal wiring is defined between the corresponding first gate line and the second gate line.

3. The substrate according to claim 1, wherein The thickness of the second metal layer is smaller than that of the first metal layer.

4. The substrate according to claim 3, wherein The thickness of the first metal layer ranges from 6000 angstroms to 8000 angstroms; and / or the thickness of the second metal layer ranges from 3000 angstroms to 6000 angstroms.

5. The substrate according to claim 1, wherein The thickness of the first insulating layer ranges from 3000 angstroms to 4000 angstroms; and / or the thickness of the passivation layer ranges from 7500 angstroms to 9000 angstroms.

6. The substrate according to claim 1, wherein A data line is provided for every two columns of sub-pixels, the jth data line is connected to the thin film transistors corresponding to the sub-pixels in the 2j-1th and 2jth columns in odd rows, and the jth data line is connected to the thin film transistors corresponding to the sub-pixels in the 2j-3th and 2j-2nd columns in even rows, where j ≥ 1 and is a positive integer; or A data line is set for every two columns of sub-pixels, the jth data line is connected to the thin film transistors corresponding to the 2j-3th and 2j-2th columns of sub-pixels in odd rows, and the jth data line is connected to the thin film transistors corresponding to the 2j-1th and 2jth columns of sub-pixels in even rows, where j≥1 and j is a positive integer.

7. The substrate according to claim 1, wherein Each row of sub-pixels includes a plurality of pixel units, each pixel unit includes three sub-pixels, and in a row of sub-pixels, two adjacent columns of pixel units constitute a pixel unit group; In the pixel unit group, the first gate line is connected to the thin film transistors corresponding to the sub-pixels in the 1st, 4th and 6th columns in the pixel unit group, and the second gate line is connected to the thin film transistors corresponding to the sub-pixels in the 2nd, 3rd and 5th columns in the pixel unit group.

8. A display device, characterized in that: The invention comprises the substrate according to any one of claims 1 to 7.

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