TFT back plate and electronic paper for improving frame gray of electronic paper
Patent Information
- Application Number
- CN202311349355.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2023-10-18
- Publication Date
- 2026-10-16
- Estimated Expiration
- 2043-10-18
AI Technical Summary
[0002]电子纸的显示区的四周围设有一圈边界区(border区),显示区内设有正常像素,边界区内设有虚拟像素(dummy pixel),在正常像素上设有像素电极层,在虚拟像素上设有边界像素电极层(边界像素电极层通常是用导电ITO层连成一圈),现有电子纸产品设计的虚拟像素处于floating状态以用于保护显示区像素的工艺稳定性作用;在显示区中,显示区的颜色显示是通过控制正常像素上方的电子膜纸两侧的电压进行的,电子膜纸上侧的公共极层与正常像素上的公共电极层电连接,电子膜纸另一侧的像素电极层与正常像素的漏极层电连接,显示区的正常像素通过驱动IC给定data信号,经过TFT充放电后进行显示;而常规设计的虚拟像素不具备充放电功能,边界区的颜色显示是通过驱动IC输出电压信号后通过边界线(border line)连接到边界像素电极层,即现有设计的边界区的电压信号是通过驱动IC输出信号经过边界线提供,并再传递到边界像素电极层的四周,而边界像素电极层(ITO)本身的阻抗较大,因此越远离边界线,边界区的电压信号衰减越多,导致边界区不同区域的电压信号不同,使得边界区的显示出现发灰情况,造成边界区和显示区颜色显示差异,主要有负载差异、信号稳定性、TFT充放电特性等因素影响
[0011] This invention uses low-impedance virtual data scan lines to be electrically connected to the driver IC via boundary lines, so that the virtual data scan lines and boundary lines are at the same potential. First virtual layer switching holes are set in the first virtual pixels on the left and right sides of the boundary area, thereby directly or indirectly connecting the first virtual pixels. This makes the virtual source layer electrically connected to the boundary pixel electrode layer, ensuring the signal voltage of the boundary pixel electrode layers on the left and right sides of the boundary area to maintain the uniformity and stability of the entire boundary area. A TFT backplane that improves the graying of the electronic paper edge is used, thereby improving the display effect of the electronic paper boundary area and avoiding graying of the boundary area display.
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Figure CN117452738B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of display technology, and in particular to a TFT backplate and electronic paper that improves the graying of the electronic paper bezel. Background Technology
[0002] Electronic paper displays are surrounded by a border area. Normal pixels are located within the display area, while dummy pixels are located within the border area. Pixel electrode layers are located on the normal pixels, and border pixel electrode layers (typically formed by a conductive ITO layer) are located on the dummy pixels. In current electronic paper designs, the dummy pixels are in a floating state to protect the manufacturing stability of the display area pixels. Color display in the display area is achieved by controlling the voltage on both sides of the electronic film paper above the normal pixels. The common electrode layer on the upper side of the electronic film paper is electrically connected to the common electrode layer on the normal pixels, and the pixel electrode layer on the other side of the electronic film paper is electrically connected to the drain layer of the normal pixels. The normal pixels in the display area are displayed after the TFT is charged and discharged following a data signal from the driver IC. Conventional dummy pixels do not have charging and discharging capabilities; the color display in the border area is achieved by the driver IC outputting a voltage signal through the border line. The voltage signal of the boundary region in the existing design is provided by the output signal of the driver IC through the boundary line and then transmitted to the periphery of the boundary pixel electrode layer. However, the impedance of the boundary pixel electrode layer (ITO) itself is relatively large. Therefore, the further away from the boundary line, the more the voltage signal of the boundary region attenuates, resulting in different voltage signals in different areas of the boundary region. This causes the boundary region to appear grayish and results in color display differences between the boundary region and the display area. The main factors affecting this are load differences, signal stability, and TFT charging and discharging characteristics. Summary of the Invention
[0003] The purpose of this invention is to provide a TFT backplane and electronic paper that improves the graying of the electronic paper border. By electrically connecting the virtual source layer and the boundary pixel electrode layer, the signal voltage in the boundary area is guaranteed to maintain the uniformity and stability of the entire boundary area, thus avoiding graying of the boundary area display.
[0004] To achieve the above objectives, one aspect of the present invention provides a TFT backplane for improving graying edges on electronic paper, comprising a display area and a boundary area surrounding the outer periphery of the display area. The display area contains normal pixels arranged in a matrix, with a pixel electrode layer above each normal pixel. The gate layer of each row of normal pixels is electrically connected to a horizontal row of gate scan lines, and the source layer of each column of normal pixels is electrically connected to a vertical column of data scan lines. Both the gate scan lines and the data scan lines are electrically connected to a driver IC. The boundary area contains virtual pixels arranged in a matrix, with a boundary pixel electrode layer above each virtual pixel. The virtual pixels include a first virtual pixel located on the left and right sides of the display area, and a second virtual pixel located on the right. The display area includes second virtual pixels on the upper and lower sides; the first virtual pixel has a first virtual layer switching hole, the boundary pixel electrode layer is connected to the virtual source layer on the first virtual pixel through the first virtual layer switching hole, the virtual gate layers on the second virtual pixels are all electrically connected to a horizontal row of virtual gate scan lines, the gate scan lines are electrically connected to the virtual gate layers on the first virtual pixels in the same horizontal row, the virtual source layers on the second virtual pixels and the virtual source layers on the first virtual pixels are all electrically connected to a vertical column of virtual data scan lines, the data scan lines are electrically connected to the virtual source layers on the second virtual pixels in the same vertical column, and each of the virtual data scan lines is electrically connected to the driver IC through a boundary line.
[0005] In a preferred embodiment of the present invention, both the second virtual pixel and the first virtual pixel include a virtual gate layer and a virtual common electrode layer spaced apart on the substrate. A first insulating layer is disposed above the virtual gate layer and the virtual common electrode layer, and a second insulating layer is disposed above the first insulating layer. The virtual source layer is disposed between the first insulating layer and the second insulating layer, and the boundary pixel electrode layer is disposed above the second insulating layer. The first virtual layer-swapping hole is disposed through the second insulating layer of the first virtual pixel, and the boundary pixel electrode layer is electrically connected to the virtual source layer of the first virtual pixel through the first virtual layer-swapping hole.
[0006] As a preferred embodiment of the present invention, the second virtual pixel is provided with a second virtual layer switching hole, the boundary pixel electrode layer is connected to the virtual gate layer of the second virtual pixel through the second virtual layer switching hole, and the virtual data scan line is electrically connected to the virtual gate scan line.
[0007] In a preferred embodiment of the present invention, the second virtual layer-swapping hole is disposed through the second insulating layer and the first insulating layer, and the boundary pixel electrode layer is electrically connected to the virtual gate layer through the second virtual layer-swapping hole.
[0008] As a preferred embodiment of the present invention, both the first virtual layer-changing hole and the second virtual layer-changing hole are provided with at least one.
[0009] Furthermore, another aspect of the present invention provides an electronic paper, including the aforementioned TFT backplate for improving the graying of the electronic paper's bezel.
[0010] The advantages of this invention, which improves the graying of the electronic paper frame and the electronic paper itself, compared with the prior art, are as follows:
[0011] This invention uses low-impedance virtual data scan lines to be electrically connected to the driver IC via boundary lines, so that the virtual data scan lines and boundary lines are at the same potential. First virtual layer switching holes are set in the first virtual pixels on the left and right sides of the boundary area, thereby directly or indirectly connecting the first virtual pixels. This makes the virtual source layer electrically connected to the boundary pixel electrode layer, ensuring the signal voltage of the boundary pixel electrode layers on the left and right sides of the boundary area to maintain the uniformity and stability of the entire boundary area. A TFT backplane that improves the graying of the electronic paper edge is used, thereby improving the display effect of the electronic paper boundary area and avoiding graying of the boundary area display. Attached Figure Description
[0012] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings of the embodiments will be briefly described below.
[0013] Figure 1 This is a schematic diagram of the structure of a TFT backplane in the prior art;
[0014] Figure 2 This is a schematic diagram of normal pixels and virtual pixels in a TFT backplane in the prior art;
[0015] Figure 3 yes Figure 2 A sectional view of aa;
[0016] Figure 4 This is a schematic diagram of the structure of a first embodiment of the TFT backplate for improving graying of electronic paper bezels provided by the present invention;
[0017] Figure 5 This is a schematic diagram of the connection between the virtual data scan line and the boundary line in Embodiment 1 of the TFT backplane for improving the graying of the electronic paper frame provided by the present invention;
[0018] Figure 6 This is a pixel diagram of the display area and boundary area in Embodiment 1 of the TFT backplate for improving graying of electronic paper edges provided by the present invention;
[0019] Figure 7 yes Figure 6 A sectional view along line AA in the middle;
[0020] Figure 8This is a schematic diagram of the structure of the second embodiment of the TFT backplate for improving the graying of the electronic paper frame provided by the present invention;
[0021] Figure 9 This is a schematic diagram of the connection between the virtual data scan line / the virtual gate scan line and the boundary line in Embodiment 2 of the TFT backplane for improving the graying of the electronic paper frame provided by the present invention;
[0022] Figure 10 This is a pixel diagram of the display area and boundary area in Embodiment 2 of the TFT backplate for improving the graying of the electronic paper frame provided by the present invention;
[0023] In the diagram, 1 represents the display area; 2 represents the boundary area; 3 represents a normal pixel; 31 represents the gate layer; 32 represents the source layer; 33 represents the drain layer; 34 represents the semiconductor layer; 35 represents the common electrode layer; 36 represents the layer-swapping via; 37 represents the pixel electrode layer; 4 represents a virtual pixel; 4a represents the first virtual pixel; 4b represents the second virtual pixel; 41 represents the virtual gate layer; 42 represents the virtual source layer; 43 represents the virtual common electrode layer; 44 represents the first virtual layer-swapping via; 45 represents the first insulating layer; 46 represents the second insulating layer; 47 represents the boundary pixel electrode layer; 48 represents the second virtual layer-swapping via; 49 represents the virtual drain layer; 61 represents the gate scan line; 62 represents the data scan line; 63 represents the virtual gate scan line; 64 represents the virtual data scan line; 65 represents the boundary line; 66 represents the connection point between the virtual gate scan line and the virtual data scan line; 7 represents the electronic film paper; 71 represents the common electrode layer; 8 represents the substrate; and 9 represents the driver IC. Detailed Implementation
[0024] The specific embodiments of the present invention will be described in further detail below with reference to the accompanying drawings and examples. The following examples are for illustrative purposes only and are not intended to limit the scope of the invention.
[0025] In the description of this invention, it should be understood that the terms "upper," "lower," "left," "right," "top," "bottom," etc., indicating orientation or positional relationships based on the orientation or positional relationships shown in the accompanying drawings, are only for the convenience of describing the invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the invention. It should be understood that the terms "first," "second," etc., are used in this invention to describe various information, but this information should not be limited to these terms; these terms are only used to distinguish information of the same type from each other. For example, without departing from the scope of this invention, "first" information can also be referred to as "second" information, and similarly, "second" information can also be referred to as "first" information.
[0026] like Figures 4-7As shown, a preferred embodiment of the present invention provides a TFT backplane for improving graying of the electronic paper bezel, comprising a display area 1 and a boundary area 2 surrounding the outer periphery of the display area 1. The display area 1 contains normal pixels 3 arranged in a matrix, with a pixel electrode layer 37 above each normal pixel 3. The gate layer 31 of each row of normal pixels 3 is electrically connected to a horizontal row of gate scan lines 61, and the source layer 32 of each column of normal pixels 3 is electrically connected to a vertical column of data scan lines 62. Both the gate scan lines 61 and the data scan lines 62 are electrically connected to a driver IC 9. The boundary area 2 contains virtual pixels 4 arranged in a matrix, with a boundary pixel electrode layer 47 above each virtual pixel 4. The virtual pixels 4 include first virtual pixels 4a located on the left and right sides of the display area 1 and a virtual pixel 4a located on the upper side of the display area 1. The first virtual pixel 4a is provided with a first virtual layer switching hole 44. The boundary pixel electrode layer 47 is connected to the virtual source layer 42 on the first virtual pixel 4a through the first virtual layer switching hole 44. The virtual gate layer 41 on the second virtual pixel 4b is electrically connected to a horizontal row of virtual gate scan lines 63. The gate scan lines 61 are electrically connected to the virtual gate layer 41 on the first virtual pixel 4a in the same horizontal row. The virtual source layer 42 on the second virtual pixel 4b and the virtual source layer 42 on the first virtual pixel 4a are both electrically connected to a vertical column of virtual data scan lines 64. The data scan lines 62 are electrically connected to the virtual source layer 42 on the second virtual pixel 4b in the same vertical column. Each of the virtual data scan lines 64 is electrically connected to the driver IC9 through a boundary line 65.
[0027] This invention uses a low-impedance virtual data scan line 64 electrically connected to the driver IC9 via a boundary line 65, so that the virtual data scan line 64 and the boundary line 65 are at the same potential. A first virtual layer switching hole 44 is set on the first virtual pixel 4a on the left and right sides of the boundary region 2, thereby directly or indirectly connecting the first virtual pixel 4a. This makes the virtual source layer 42 electrically connected to the boundary pixel electrode layer 47, ensuring that the signal voltage of the boundary pixel electrode layer 47 on the left and right sides of the boundary region 2 is maintained to keep the uniformity and stability of the entire boundary region 2. The TFT backplate that improves the graying of the electronic paper frame is used to improve the display effect of the electronic paper boundary region 2 and avoid the graying of the boundary region 2 display.
[0028] Specifically, both the second virtual pixel 4b and the first virtual pixel 4a include a virtual gate layer 41 and a virtual common electrode layer 43 spaced apart on the substrate 8. A first insulating layer 45 is provided above the virtual gate layer 41 and the virtual common electrode layer 43, and a second insulating layer 46 is provided above the first insulating layer 45. A virtual source layer 42 is disposed between the first insulating layer 45 and the second insulating layer 46. A boundary pixel electrode layer 47 is disposed above the second insulating layer 46. A first virtual layer-switching hole 44 is disposed through the second insulating layer 46 of the first virtual pixel 4a. The boundary pixel electrode layer 47 is electrically connected to the virtual source layer 42 of the first virtual pixel 4a through the first virtual layer-switching hole 44. The first virtual layer-switching hole 44 enables each first virtual pixel 4a to conduct with the boundary pixel electrode layer 47, thereby improving the uniformity and stability of the signal voltage in the boundary region 2.
[0029] like Figures 8-10 As shown in Embodiment 2, a second virtual layer-switching hole 48 is provided on the second virtual pixel 4b. The boundary pixel electrode layer 47 is connected to the virtual gate layer 41 of the second virtual pixel 4b through the second virtual layer-switching hole 48. The virtual data scan line is electrically connected to the virtual gate scan line. By arranging the second virtual layer-switching hole 48, the voltage signal of the entire boundary region 2 is made uniform and stable. Specifically, the second virtual layer-switching hole 48 is disposed through the second insulating layer 46 and the first insulating layer 45. The boundary pixel electrode layer 47 is electrically connected to the virtual gate layer 41 through the second virtual layer-switching hole 48. The main difference between Embodiment 2 and Embodiment 1 is that a second virtual layer-switching hole 48 is provided on the second virtual pixel 4b.
[0030] Furthermore, each first virtual pixel 4a is provided with at least one first virtual layer-switching hole 44, and each second virtual pixel 4b is provided with at least one second virtual layer-switching hole 48, thus ensuring that the first virtual pixel 4a and the second virtual pixel 4b are effectively connected to the boundary pixel electrode layer 47.
[0031] In addition, the present invention also provides an electronic paper, including the aforementioned TFT backplate for improving the graying of the electronic paper frame, thus the electronic paper has all the beneficial effects of the aforementioned TFT backplate for improving the graying of the electronic paper frame, which will not be described in detail here.
[0032] The above description is only a preferred embodiment of the present invention. It should be noted that for those skilled in the art, several improvements and substitutions can be made without departing from the technical principles of the present invention, and these improvements and substitutions should also be considered within the scope of protection of the present invention.
Claims
1. A TFT backplane for improving graying edges on electronic paper, comprising a display area and a boundary area surrounding the outer periphery of the display area, wherein normal pixels are arranged in a matrix within the display area, a pixel electrode layer is disposed above the normal pixels, the gate layer of each row of normal pixels is electrically connected to a horizontal row of gate scan lines, the source layer of each column of normal pixels is electrically connected to a vertical column of data scan lines, and both the gate scan lines and the data scan lines are electrically connected to a driver IC; characterized in that, The boundary area contains virtual pixels arranged in a matrix. A boundary pixel electrode layer is provided above the virtual pixels. The virtual pixels include first virtual pixels located on the left and right sides of the display area and second virtual pixels located on the upper and lower sides of the display area. The first virtual pixels have a first virtual layer switching hole. The boundary pixel electrode layer is connected to the virtual source layer on the first virtual pixel through the first virtual layer switching hole. The virtual gate layers on the second virtual pixels are all electrically connected to a horizontal row of virtual gate scan lines. The gate scan lines are electrically connected to the virtual gate layers on the first virtual pixels in the same horizontal row. The virtual source layers on the second virtual pixels and the virtual source layers on the first virtual pixels are all electrically connected to a vertical column of virtual data scan lines. The data scan lines are electrically connected to the virtual source layers on the second virtual pixels in the same vertical column. Each virtual data scan line is electrically connected to the driver IC through a boundary line.
2. The TFT backplate for improving graying of electronic paper bezels as described in claim 1, characterized in that, Both the second virtual pixel and the first virtual pixel include a virtual gate layer and a virtual common electrode layer spaced apart on the substrate. A first insulating layer is disposed above the virtual gate layer and the virtual common electrode layer, and a second insulating layer is disposed above the first insulating layer. A virtual source layer is disposed between the first insulating layer and the second insulating layer. A boundary pixel electrode layer is disposed above the second insulating layer. A first virtual layer-swapping hole is disposed through the second insulating layer of the first virtual pixel. The boundary pixel electrode layer is electrically connected to the virtual source layer of the first virtual pixel through the first virtual layer-swapping hole.
3. The TFT backplate for improving graying of electronic paper bezels as described in claim 2, characterized in that, The second virtual pixel is provided with a second virtual layer switching hole, the boundary pixel electrode layer is connected to the virtual gate layer of the second virtual pixel through the second virtual layer switching hole, and the virtual data scan line is electrically connected to the virtual gate scan line.
4. The TFT backplate for improving graying of electronic paper bezels as described in claim 3, characterized in that, The second virtual layer-swapping hole is disposed through the second insulating layer and the first insulating layer, and the boundary pixel electrode layer is electrically connected to the virtual gate layer through the second virtual layer-swapping hole.
5. The TFT backplate for improving graying of electronic paper bezels as described in claim 3, characterized in that, Both the first virtual layer-changing hole and the second virtual layer-changing hole are provided with at least one.
6. An electronic paper, characterized in that, Including the TFT backplate for improving graying of the electronic paper bezel as described in any one of claims 1 to 5.
Citation Information
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