Real-time signal processing architecture design method based on tmsc6678 platform

Abstract

The application provides a real-time signal processing architecture design method based on a TMSC6678 platform, and belongs to the technical field of radar signal processing; the method comprises the following steps: taking the TMSC6678 platform as a signal processing module of a radar system, acquiring RD domain data of the FPGA after phase correlation accumulation by a DSP, and performing regional division on the RD domain data; subsequently, a multi-core processor of the TMSC6678 platform is applied to obtain the amplitude of the RD domain data in a multi-core parallel mode, and target CFAR detection is completed in parallel in a multi-core cooperative mode; finally, the core 0 of the multi-core processor is used for target clustering and target tracking operation, and the result is uploaded to an upper computer; the upper computer supports online modification of algorithm parameters, and accepts key frame return of the RD domain data and the result data and SRIO re-linking operation; the application guarantees the reliability of the radar signal processing module, and solves the problems of difficult field debugging, long algorithm modification period and low efficiency.

Description

Technical Field

[0001] This invention belongs to the field of radar signal processing technology, specifically a real-time signal processing architecture design method based on the TMSC6678 platform. Background Technology

[0002] Radar signal processing systems are characterized by high floating-point computing density, high parallelism, and centralized algorithms. The hardware of the current mainstream parallel processing solutions generally adopts embedded platforms such as DSP+FPGA. Generally speaking, the FPGA platform completes signal processing processes such as pulse compression, range movement correction, and coherent accumulation, while the DSP completes data processing processes such as target detection, quantity estimation, and target trajectory tracking.

[0003] Another mainstream processing solution uses GPUs for signal acquisition and processing. This solution utilizes the GPU's CUDA library to perform parallel signal and data processing within the GPU. Meanwhile, some solutions employ embedded platforms based on FPGA+ARM architecture to complete the signal processing flow. The FPGA performs AD signal acquisition and digital down-conversion, while the ARM performs pulse compression, coherent accumulation, detection, and clustering tracking.

[0004] While the aforementioned parallel processing solution using a GPU platform offers high efficiency, it also suffers from drawbacks such as reliance on the CUDA library and high cost. As for the FPGA+ARM signal processing solution, ARM, being a general-purpose CPU, lacks optimizations for radar signal processing-related computational modules, thus posing challenges in real-time computation. In summary, while using embedded platforms like DSP+FPGA for radar signal processing offers relatively lower computational efficiency compared to GPU platforms, it also boasts advantages such as lower cost, mature software platforms, and ease of portability. Furthermore, compared to the FPGA+ARM solution, DSPs can be specifically optimized for radar signal processing-related computational modules, resulting in significantly improved computational efficiency at a similar cost.

[0005] However, even with the established mainstream DSP+FPGA embedded platform architecture, the reliability of radar signal processing, the long algorithm modification cycle, and the low efficiency problems have not been well solved. Furthermore, it is difficult to update the program in the field testing environment, which makes the debugging process difficult. These problems urgently need to be solved, and those skilled in the art have begun to study new architecture designs and application methods to maximize the advantages of the DSP+FPGA embedded platform and improve the real-time processing effect of radar signals. Summary of the Invention

[0006] To address the current state of the technology, this invention provides a novel design method that employs a mainstream DSP+FPGA parallel processing platform to complete the real-time radar signal processing flow. This invention particularly considers the field testing environment, supports network transmission of RD domain data, and allows for the re-establishment of the link between the DSP and FPGA via a host computer. Therefore, this invention ensures the reliability of the radar signal processing module and solves the problems of difficult field debugging, long algorithm modification cycles, and low efficiency.

[0007] The present invention employs the following technical solutions to achieve its objective:

[0008] A real-time signal processing architecture design method based on the TMSC6678 platform is proposed. The TMSC6678 platform serves as the signal processing module of a radar system. Under the requirements of 26ms algorithm runtime and 50Hz data refresh rate in the radar system, it completes the RD domain data amplitude calculation, target CFAR detection, target angle calculation, target clustering, target tracking, and filtering operations.

[0009] In the TMSC6678 platform, the DSP obtains the RD domain data after coherent accumulation from the FPGA through the SRIO interface and divides the RD domain data into regions. Then, the multi-core processor of the TMSC6678 platform is used to obtain the amplitude of the RD domain data in a multi-core parallel manner, and then the target CFAR detection is completed in parallel in a multi-core cooperative manner. Finally, the target clustering and target tracking operations are performed through core 0 of the multi-core processor, and the obtained result data is uploaded to the host computer.

[0010] When connected to the TMSC6678 platform, the host computer can edit and modify the platform algorithm and control its execution. It can also receive key frame feedback of RD domain data and result data to complete the real-time processing of radar signals. At the same time, the host computer can judge the connection status with the DSP and FPGA in real time and perform a re-connection operation when the connection is abnormal.

[0011] Furthermore, in the multi-core processor of the TMSC6678 platform, core 0 performs initialization operations on the driver modules of the serial port, SPI interface, network port and SRIO interface in the DSP; during the initialization operation, the other cores in the multi-core processor other than core 0 enter the IPC multi-core synchronization module and wait for core 0 to complete the initialization operation.

[0012] After all cores complete multi-core synchronization, core 0 initializes the relevant parameters of the radar signal processing algorithm and requests static memory space corresponding to intermediate variables and result data. Subsequently, all cores enter a blocked state, waiting for interrupt information from other modules in the radar system.

[0013] Furthermore, the FPGA first completes the AD intermediate frequency signal acquisition, digital down-conversion, pulse compression and coherent accumulation operations to obtain RD domain data, and at the same time obtains the radar system servo speed and azimuth information from various interfaces of the DSP; the FPGA transmits the complete data packet to the DSP through the SRIO interface, and sends a doorbell interrupt to core 0 after the transmission is completed;

[0014] After receiving the doorbell interrupt, core 0 releases its semaphore and sends an IPC interrupt signal to core 1, then enters the IPC multi-core synchronization module. After receiving the IPC interrupt signal, core 1 also releases its semaphore and sends an IPC interrupt signal to the next core, then enters the IPC multi-core synchronization module, and so on until the last core in the multi-core processor. Cores entering the IPC multi-core synchronization module wait continuously until all cores have entered before starting to perform real-time radar signal processing operations. After completing its own signal processing tasks, each core waits for the other cores to complete their respective signal processing tasks.

[0015] Furthermore, after all cores have completed the signal processing tasks for their current step in the IPC multi-core synchronization module, they synchronously summarize the signal processing results of the current step and decompose the intermediate results into multiple independent inputs, which are then left to the corresponding cores for the next step of signal processing.

[0016] Once all signal processing steps are completed, the final signal processing result is passed to kernel 0 through the shared space. Kernel 0 performs clustering, tracking, and filtering operations, and then transmits the final signal processing result and related data to the host computer through the DSP network port.

[0017] In the architecture design using the TMSC6678 platform as the signal processing module, the signal processing module simultaneously provides a host computer algorithm modification interface with three modes:

[0018] Normal operating mode: Performs the normal data interaction process of the signal processing module;

[0019] RD domain transmission mode: Only transmits RD domain data uploaded by the FPGA;

[0020] Keyframe mode: Only provides information about the target and the RD domain at the target's center unit.

[0021] Furthermore, in the signal processing process using the TMSC6678 platform as the signal processing module, the FPGA polls and sends data to the DSP's PingPongBuffer; when the FPGA sends data to the PingBuffer, the data in the PingBuffer undergoes parallel signal processing; similarly, when the FPGA sends data to the PingBuffer, the data in the PingBuffer undergoes parallel signal processing; the parallel signal processing flow includes RD domain data amplitude calculation, target CFAR detection, and target angle calculation.

[0022] Furthermore, the host computer edits and controls the execution of the platform algorithm by setting the data format and algorithm modification content table. After the host computer sends the algorithm parameters to the DSP of the TMSC6678 platform, the DSP modifies the corresponding parameters and sends the modified parameters back to the host computer, which displays the returned results. When the SRIO interface between the DSP and the FPGA loses connection, the host computer sends a re-establishment command to re-establish the connection between the DSP and the FPGA's SRIO. The specific process is as follows:

[0023] The system determines whether the DSP's SRIO interface initialization was successful, checks whether its link status is X4, and whether the FPGA returns a link establishment success flag. If any one of the conditions is not met, the system controls the DSP to reset the SRIO, initialize the SRIO interface, and send a link establishment request to the FPGA. The system continues to determine whether all three conditions are met. If all three conditions are met, it indicates that the link establishment was successful. The system then destroys the DSP interrupt resources and re-requests the relevant SRIO interrupt resources.

[0024] In summary, due to the adoption of this technical solution, the beneficial effects of this invention are as follows:

[0025] 1. In the method of this invention, the multi-core region is divided and CFAR detection is performed in parallel. By dividing the RD domain into multiple detection regions, each core is responsible for the detection of one region, and the results are finally summarized. This divide-and-conquer approach successfully improves the algorithm's running efficiency.

[0026] 2. In the signal processing flow of the method of the present invention, the multi-core parallel EDMA transfer and the multi-core PingPongBuffer design release CPU resources and save transfer time during the process of DMA transfer performed by multiple cores at the same time, and correspondingly improve the algorithm running efficiency.

[0027] 3. In the multi-core synchronization process design of the present invention, the inter-core interrupt mechanism is used to trigger the inter-core interrupt to release its synchronization-related semaphores, thereby achieving the purpose of synchronizing the signal processing process;

[0028] 4. The method of the present invention enables the system to support the uploading of RD domain data and key frame data through relevant protocol content between the host computer and the DSP; the system also supports the host computer to modify the relevant parameters of the DSP signal processing algorithm, as well as the re-establishment of the link between the FPGA and the DSP. Attached Figure Description

[0029] Figure 1 This is a schematic diagram of the overall process design of the method of the present invention;

[0030] Figure 2 This is a schematic diagram of the overall data processing flow of the RD domain in this invention;

[0031] Figure 3 This is a schematic diagram of the modulo data flow in the RD field of this invention;

[0032] Figure 4 This is a schematic diagram of the CFAR detection process in this invention;

[0033] Figure 5 This is a diagram of the distance-dimensional CFAR detection process in this invention;

[0034] Figure 6 This is a schematic diagram of the angle measurement asymptotic curve of the sum and difference channel in this invention;

[0035] Figure 7 This is a schematic diagram of the SRIO reconnection process in this invention. Detailed Implementation

[0036] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. The components of the embodiments of the present invention described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0037] Therefore, the following detailed description of the embodiments of the invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely to illustrate selected embodiments of the invention. All other embodiments obtained by those skilled in the art based on the embodiments of the invention without inventive effort are within the scope of protection of the invention.

[0038] Example 1

[0039] This embodiment presents a real-time signal processing architecture design method based on the TMSC6678 platform, which is divided into three parts, and the details of the method are described in detail.

[0040] I. Overall Flow Design of TMSC6678 Based on RTOS Signal Processing

[0041] As the signal processing module of a radar system, the TMSC6678 platform, under the requirements of a 26ms algorithm runtime and a 50Hz data refresh rate in radar systems, mainly performs the following functions: RD domain data amplitude calculation, target CFAR detection, target angle calculation, target clustering, target tracking, and filtering. The execution flow of the method can be found in the following text and reference. Figure 1 .

[0042] In this embodiment, the TMSC6678 platform uses an 8-core processor. Core 0 initializes the driver modules for the serial port, SPI interface, Ethernet port, and SRIO interface in the DSP. At this time, the other cores enter the IPC multi-core synchronization module and wait for Core 0 to complete the initialization operation.

[0043] The main purpose of multi-core synchronization is to ensure shared variables across multiple cores and avoid errors in shared memory assignment caused by repeated initialization. After all cores have completed multi-core synchronization, core 0 initializes the relevant parameters of the radar signal processing algorithm and allocates static memory space for intermediate variables and result data. Once these operations are complete, all cores enter a blocked state, waiting for interrupt information from other modules.

[0044] Next, the FPGA first completes the AD intermediate frequency signal acquisition, digital down-conversion, pulse compression and coherent accumulation operations to obtain RD domain data, and at the same time obtains the radar system servo speed and azimuth information from various interfaces of the DSP; the FPGA transmits the complete data packet to the DSP through the SRIO interface, and sends a doorbell interrupt to core 0 after the transmission is completed.

[0045] After receiving the doorbell interrupt, core 0 releases the semaphore and sends an IPC interrupt signal to core 1, then enters the IPC multi-core synchronization module; after receiving the IPC interrupt signal, core 1 also releases the semaphore and sends an IPC interrupt signal to the next core, then enters the IPC multi-core synchronization module, and so on until core 7, the last core in the multi-core processor, is executed; cores entering the IPC multi-core synchronization module wait continuously until all cores have entered before starting to perform real-time radar signal processing operations; after each core completes its own signal processing, it waits for the other cores to complete their respective signal processing.

[0046] After all cores have completed the signal processing tasks for their current step in the IPC multi-core synchronization module, they synchronously summarize the signal processing results of the current step and decompose the intermediate results into multiple independent inputs, which are then left to the corresponding cores for the next step of signal processing.

[0047] After the above process, the final signal processing result is passed to core 0 through the shared space. Core 0 performs clustering, tracking and filtering operations, and then transmits the final signal processing result and related data to the host computer through the DSP network port.

[0048] In this embodiment, based on the TMSC6678 platform as the signal processing module architecture, the signal processing module simultaneously provides a host computer algorithm modification interface with three modes:

[0049] Normal operating mode: Performs the normal data interaction process of the signal processing module;

[0050] RD domain transmission mode: Only transmits RD domain data uploaded by the FPGA;

[0051] Keyframe mode: Only provides information about the target and the RD domain at the target's center unit.

[0052] II. Functional Process Design of Signal Processing Module

[0053] In this section, the overall processing flow of the TMSC6678 platform is as follows: Figure 2 As shown. During signal processing, the FPGA polls and sends data to the DSP's PingPongBuffer; when the FPGA sends data to the PingBuffer, the data in the PingBuffer undergoes parallel signal processing; similarly, when the FPGA sends data to the PingBuffer, the data in the PingBuffer undergoes parallel signal processing.

[0054] Considering that the time for FPGA to sample, pulse compress, coherently accumulate and transmit a frame of data in a radar system is 26ms, the algorithm running time needs to be less than 26ms so that the RD domain data being used by the algorithm will not be overwritten.

[0055] In this embodiment, the parallel signal processing flow includes RD domain data amplitude calculation, target CFAR detection, and target angle calculation.

[0056] First, the amplitude of the RD domain data is obtained, and the process is as follows: Figure 3 As shown, this embodiment uses a specific example for illustration. For RD domain data of size 1024*512*8 bytes (1024 represents distance points, 512 represents velocity points, 1 AD sampling point occupies 2 bytes, and there are two signals in total, I and Q, and two channels for sum and difference), the region is first divided by 8 cores. Each core is responsible for taking the modulus of the RD domain of 32*4*512*8 bytes (32*4 represents 128 distance units) of data and transferring the result to the corresponding region.

[0057] Each core has its own PingPongBuffer, so the total buffer size is 8*2*512*8 bytes (8 represents the number of cores, and 2 represents the PingPongBuffer), with each core having 2*512*8 bytes of space.

[0058] The EDMA module moves 4*512*8 bytes from the DDR space (the EDMA modules for all 8 cores move the data in parallel) to the shared memory unit corresponding to the PingBuffer (the data transfer efficiency of the shared memory unit is higher than that of the DDR space). At the same time, the PingBuffer performs modulo operation on the data in the corresponding unit and moves the modulo result to the corresponding shared memory space. Similarly, when the EDMA moves the DDR data to the PingBuffer, the PingBuffer performs modulo operation on the data and moves the corresponding data to the corresponding DDR space.

[0059] Once a core completes the modulus calculation and data transfer for its assigned area, it enters the IPC multi-core synchronization module and waits for other cores to complete the task. Once all cores have completed the modulus calculation and data transfer, it exits the synchronization module and enters the subsequent CFAR detection module.

[0060] The CFAR detection module performs moving target detection. Considering the significant interference from ground clutter in real-world applications, performing detection at the range cell level first would greatly increase the computational load of CFAR detection. Therefore, in this embodiment, velocity dimension detection is performed first in the RD domain to filter out the corresponding velocity cells before performing range cell detection. The specific steps are as follows:

[0061] First, the 1024 range cells are divided into 8 regions, with each region responsible for detecting 128 range cells. Within each range cell, velocity-dimensional CFAR detection is performed on its 512 velocity cells. The detection algorithm uses the commonly used CA-CFAR. Guard cells are selected to the left and right of the velocity cell to be detected, and comparison cells are selected to the left and right of the guard cells, with the average value taken as the average noise level. The target signal-to-noise ratio (SNR) is obtained by the ratio of signal strength to noise strength. If the SNR is greater than a preset K value and the signal strength is greater than a preset threshold, the velocity cell is considered a target, and its velocity cell index and SNR are retained for subsequent signal processing.

[0062] Considering that radar operational processes require real-time CFAR detection, conventional CFAR detection requires summing the comparison units for each inspected unit, which is time-consuming. Therefore, this embodiment uses the sliding window method, the process of which is as follows: Figure 4As shown. In the sliding window method, the accumulated value of each comparison cell is subtracted from the leftmost sliding window value, and at the same time, one sliding window value is added to the right. If the sliding window moves to the rightmost position, it is returned to the leftmost position. In this way, each update only requires one addition operation and one subtraction operation, thereby improving the computational efficiency.

[0063] After completing the CFAR detection process, each core waits to acquire a hardware semaphore, saves the speed dimension detection result to the DDR space, and then enters the IPC multi-core synchronization module. The hardware semaphore ensures that only one core enters the shared memory area at a time, preventing multiple cores from modifying shared variables simultaneously.

[0064] Once all 8 cores enter the multi-core synchronization module, the distance dimension CFAR begins. First, the 8 cores synchronize, with core 0 responsible for allocating the distance dimension CFAR detection tasks. The allocation process follows an average distribution principle, as shown in the following formula:

[0065]

[0066] In the formula, distribute_num represents the number of tasks assigned to each core; n represents the total number of detection speed dimensions; the total number of cores is 8; coreid = 0 to (N-1) represents the core number.

[0067] For each core assigned to the distance dimension, its distance dimension CFAR detection is as follows: Figure 5 As shown, the speed unit allocated to the core is first moved to the corresponding PingPongBuffer using the DMA module. If the DMA is currently moving distance dimension information to the PingBuffer, the PingBuffer performs distance dimension CFAR detection. Similarly, if the DMA is moving information to the PingBuffer, the PingBuffer completes the corresponding CFAR detection.

[0068] After a core completes the CFAR detection for the corresponding distance dimension, it waits to acquire a hardware semaphore. If the core acquires the hardware semaphore, it blocks other cores from acquiring the corresponding hardware semaphore, aggregates the CFAR detection results, and then releases the hardware semaphore for use by other cores.

[0069] After the target CFAR detection is completed, the target angle is calculated. The azimuth is measured using a servo module, and the elevation is measured using a sum-difference beam angle measurement.

[0070] In this embodiment, by designing and differentiating the antenna pattern, the elevation beamwidth is designed to be 30 degrees, and then the following is calculated: Figure 6The asymptotic curve is shown. CFAR detection yields the RD domain and channel target index. This index is then used to obtain the amplitudes of the difference channel and the sum channel. The amplitude ratio of the difference channel and the sum channel is calculated, and this ratio is compared with the asymptotic curve. The value with the smallest error compared to this ratio is the target pitch angle.

[0071] After all cores complete CFAR detection and azimuth and elevation angle measurement, core 0 then completes the remaining data processing work, including clustering, tracking and filtering operations.

[0072] III. Design of Communication Protocols for Platform-Host Computer Interaction

[0073] For radar systems, it is necessary not only to handle business processes, but also to realize different customized needs of users through interaction with a host computer. In this embodiment, the host computer can issue and modify relevant parameters of radar signal processing, radar RD domain data can be transmitted back to the host computer, and radar key frame data also needs to be uploaded.

[0074] Therefore, the host computer edits and controls the execution of the platform algorithm by setting the data format and modifying the algorithm content table. The data format uploaded by the host computer is shown in Table 1 below:

[0075] Table 1

[0076]

[0077] It includes a frame header, packet length, protocol content, and frame trailer. The protocol content is shown in Table 2 below:

[0078] Table 2

[0079] Algorithm content structure / control related Struct Source mark Enum(uint32)

[0080] The algorithm modifications are shown in Table 3 below, covering the relevant parameters that need to be modified for CFAR detection:

[0081] Table 3

[0082]

[0083]

[0084] After the host computer sends the algorithm parameters, the DSP modifies the relevant parameters and sends the corresponding parameters back to the host computer, which then displays the returned results. When the DSP sends a reply to the host computer, the frame header is defined as 0xEB90, the frame trailer is defined as 0xDADC, and other contents remain unchanged.

[0085] The host computer supports both RD field data and keyframe data formats for transmission. The process of transmitting RD field data and keyframe data is achieved by the host computer issuing commands to modify relevant control parameters, as shown in Table 4 below:

[0086] Table 4

[0087]

[0088] It supports direct return of RD domain data or keyframe data. In this embodiment, keyframe data refers to data near the target within the RD domain, and its format is shown in Table 5 below:

[0089] Table 5

[0090]

[0091] When the SRIO of the DSP and FPGA modules loses connection, the host computer can re-establish the connection between the FPGA and DSP by issuing a re-establishment command; the specific process is as follows. Figure 7 As shown.

[0092] In this embodiment, the system determines whether the DSP's SRIO port initialization was successful, whether its link status is X4, and whether the FPGA returns a link establishment success flag. If any one of these conditions is not met, the DSP resets the SRIO and initializes the SRIO module, and finally sends a link establishment request to the FPGA.

[0093] Continue to determine whether the above three conditions are met. If not, repeat the SRIO initialization and reset process. If all three conditions are met, destroy the resources requested by the SRIO interrupt and the corresponding hardware interrupt thread, and recreate the SRIO interrupt and request the resources corresponding to the interrupt thread.

Claims

1. A method for designing a real-time signal processing architecture based on the TMSC6678 platform, characterized in that: As the signal processing module of the radar system, the TMSC6678 platform completes RD domain data amplitude calculation, target CFAR detection, target angle calculation, target clustering, target tracking and filtering operations under the requirements of 26ms algorithm running time and 50Hz data refresh rate in the radar system. In the TMSC6678 platform, the DSP obtains the RD domain data after coherent accumulation from the FPGA through the SRIO interface and divides the RD domain data into regions. Then, the multi-core processor of the TMSC6678 platform is used to obtain the amplitude of the RD domain data in a multi-core parallel manner, and then the target CFAR detection is completed in parallel in a multi-core cooperative manner. Finally, the target clustering and target tracking operations are performed through core 0 of the multi-core processor, and the obtained result data is uploaded to the host computer. When connected to the TMSC6678 platform, the host computer can edit and modify the platform algorithm and control its execution. It can also receive key frame feedback of RD domain data and result data to complete the real-time processing of radar signals. At the same time, the host computer can judge the connection status with the DSP and FPGA in real time and perform a re-connection operation when the connection is abnormal. In the signal processing process using the TMSC6678 platform as the signal processing module, the FPGA polls and sends data to the DSP's PingPongBuffer. When the FPGA sends data to the PingBuffer, the data in the PingBuffer undergoes parallel signal processing. Similarly, when the FPGA sends data to the PingBuffer, the data in the PingBuffer undergoes parallel signal processing. The parallel signal processing flow includes RD domain data amplitude calculation, target CFAR detection, and target angle calculation. In the process of obtaining the magnitude of RD domain data, the RD domain data is first divided into regions by multiple cores of a multi-core processor, with each core responsible for the RD domain modulus calculation and result transfer of the corresponding region's data; In the TMSC6678 platform, each core has its own PingPongBuffer for the corresponding DSP. During the calculation, the platform's EDMA module moves the data of the region responsible for each core from the DDR space to the shared memory unit corresponding to the PingBuffer. At the same time, the PingBuffer performs modulo operation on the data of the corresponding unit and moves the modulo result to the corresponding DDR space. Similarly, when the EDMA module moves the data to the PingBuffer, the data in the PingBuffer performs modulo operation and moves it to the corresponding DDR space. Once any core has completed all data model calculation and transfer work in its responsible area, it continues to wait in the IPC multi-core synchronization module for other cores to complete their corresponding work; once all cores have completed data model calculation and transfer work, it exits the IPC multi-core synchronization module and enters the CFAR detection module. The CFAR detection module performs moving target detection. First, it performs velocity dimension detection in the RD domain to filter out the corresponding velocity units, and then performs distance unit detection. During the distance unit detection process, the detection algorithm uses CA-CFAR and applies the sliding window method. In the sliding window method, the accumulated value of each comparison unit is subtracted from the leftmost sliding window value, and one sliding window value is added to the right. If the sliding window moves to the rightmost position, it is returned to the leftmost position. After each core completes the CFAR detection process, it saves the velocity dimension detection results to the DDR space based on hardware semaphores before entering the IPC multi-core synchronization module.

2. The real-time signal processing architecture design method based on the TMSC6678 platform according to claim 1, characterized in that: In the multi-core processor of the TMSC6678 platform, core 0 performs initialization operations on the driver modules of the serial port, SPI interface, network port and SRIO interface in the DSP; during the initialization operation, the other cores in the multi-core processor other than core 0 enter the IPC multi-core synchronization module and wait for core 0 to complete the initialization operation. After all cores complete multi-core synchronization, core 0 initializes the relevant parameters of the radar signal processing algorithm and requests static memory space corresponding to intermediate variables and result data. Subsequently, all cores enter a blocked state, waiting for interrupt information from other modules in the radar system.

3. The real-time signal processing architecture design method based on the TMSC6678 platform according to claim 2, characterized in that: After the FPGA completes the AD intermediate frequency signal acquisition, digital down-conversion, pulse compression and coherent accumulation operations, it obtains the RD domain data and simultaneously obtains the radar system servo speed and azimuth information from various interfaces of the DSP. The FPGA transmits the complete data packet to the DSP through the SRIO interface and sends a doorbell interrupt to core 0 after the transmission is completed. After receiving the doorbell interrupt, core 0 releases the semaphore and sends an IPC interrupt signal to core 1, and then enters the IPC multi-core synchronization module; After receiving the IPC interrupt signal, Core 1 also releases the semaphore and sends the IPC interrupt signal to the next core. Then it enters the IPC multi-core synchronization module, and so on, until the last core in the multi-core processor is executed. The cores that enter the IPC multi-core synchronization module wait continuously until all cores have entered before they start to perform real-time radar signal processing operations. After each core completes its own signal processing, it waits for the other cores to complete their respective signal processing.

4. The real-time signal processing architecture design method based on the TMSC6678 platform according to claim 3, characterized in that: After all cores have completed the signal processing tasks for their current step in the IPC multi-core synchronization module, they synchronously summarize the signal processing results of the current step and decompose the intermediate results into multiple independent inputs, which are then left to the corresponding cores for the next step of signal processing. Once all signal processing steps are completed, the final signal processing result is passed to kernel 0 through the shared space. Kernel 0 performs clustering, tracking, and filtering operations, and then transmits the final signal processing result and related data to the host computer through the DSP network port. In the architecture design using the TMSC6678 platform as the signal processing module, the signal processing module simultaneously provides a host computer algorithm modification interface with three modes: Normal operating mode: Performs the normal data interaction process of the signal processing module; RD domain transmission mode: Only transmits RD domain data uploaded by the FPGA; Keyframe mode: Only provides information about the target and the RD domain at the target's center unit.

5. The real-time signal processing architecture design method based on the TMSC6678 platform according to claim 1, characterized in that: After re-entering the multi-core synchronization module, all cores perform distance-dimensional CFAR. After all cores are synchronized, core 0 is responsible for allocating distance-dimensional CFAR detection tasks. The allocation process adopts an average allocation principle, as shown in the following formula: In the formula, This indicates the number of tasks assigned to each core. Represents the total number of detection speed points; Represents the total number of core members; Represents the nuclear number.

6. The real-time signal processing architecture design method based on the TMSC6678 platform according to claim 5, characterized in that: For a core that has completed the distance dimension CFAR, wait for the hardware semaphore; if the core obtains the hardware semaphore, block the other cores from obtaining the corresponding hardware semaphore, while summarizing the CFAR detection results of the core, and then release the hardware semaphore for the other cores to use. After the target CFAR detection is completed, the target angle is calculated to obtain the target azimuth and elevation angles. Then, the remaining data processing work is completed, including clustering, tracking and filtering operations.

7. The real-time signal processing architecture design method based on the TMSC6678 platform according to claim 1, characterized in that: The host computer edits and controls the execution of the platform algorithm by setting the data format and modifying the algorithm content table. After the host computer sends the algorithm parameters to the DSP of the TMSC6678 platform, the DSP modifies the corresponding parameters and sends the modified parameters back to the host computer, which displays the returned results. When the SRIO interface between the DSP and the FPGA drops, the host computer sends a re-establishment command to re-establish the connection between the DSP and the FPGA. The specific process is as follows: The system determines whether the DSP's SRIO interface initialization was successful, checks whether its link status is X4, and whether the FPGA returns a link establishment success flag. If any one of the conditions is not met, the system controls the DSP to reset the SRIO, initialize the SRIO interface, and send a link establishment request to the FPGA. The system continues to determine whether all three conditions are met. If all three conditions are met, it indicates that the link establishment was successful. The system then destroys the DSP interrupt resources and re-requests the relevant SRIO interrupt resources.

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