Host-side cache abnormal power-off protection method and device, and computer equipment

Abstract

The application relates to a host-side cache abnormal power-off protection method and device, computer equipment and a storage medium, wherein the method comprises the following steps: a host acquires SSD information and initializes internal drives; after the initialization is completed, an asynchronous event request command is issued by an abnormal power-off monitoring drive; when the SSD detects that the abnormal power-off is triggered, the SSD replies to the asynchronous event request command and sets an asynchronous event information field in the command to 1; the abnormal power-off monitoring drive informs a cache acceleration drive to flush data in the memory to the SSD; and the host cache drive writes the modified data in the memory to the SSD. The application can write the data into the SSD in time during power-off on the basis of guaranteeing the host-side cache performance, and further guarantees the data integrity.

Description

Technical Field

[0001] This invention relates to the field of solid-state drive technology, and in particular to a method, apparatus, computer device, and storage medium for protecting against abnormal power loss of host-side cache. Background Technology

[0002] SSDs (Solid State Drives) have been widely used in various applications and are gradually replacing traditional HDDs (Hard Disk Drives) in the PC market, providing users with a better experience in terms of reliability and performance. With the increasing speed of host interfaces, from PCIe Gen 3 to Gen 4 and then to Gen 5, the performance ceiling they can provide is getting higher and higher, thus placing increasingly higher demands on the performance that SSDs can offer.

[0003] In typical application scenarios, host applications initiate read / write operation requests based on the file system. The file system parses these requests into LBA-based read / write operations for the corresponding storage device (SSD) and passes them to the appropriate block device driver. The block device driver then forwards these requests to the specific bus protocol driver (such as NVMe / PCIe) to initiate data interaction. Since disk access requires traversing the physical bus, the bandwidth and latency are constrained by the physical bus. To address this, some vendors have developed host-side caching drivers that utilize the host's high-speed memory to cache host read / write data, enabling faster completion of host read / write commands. However, host-side memory is volatile due to power loss; in cases of abnormal power outages, the data cached in the host-side driver will be lost, leading to system malfunctions. Therefore, it is necessary to consider how to protect the data in the buffer during abnormal power outages to ensure user data integrity. Summary of the Invention

[0004] Therefore, it is necessary to provide a method, apparatus, computer device, and storage medium for abnormal power loss protection of host-side cache in response to the above-mentioned technical problems.

[0005] A method for protecting host-side cache from abnormal power loss, the method comprising:

[0006] The host obtains SSD information and initializes the internal drivers;

[0007] After initialization is complete, an asynchronous event request command is sent through the abnormal power failure monitoring driver;

[0008] When the SSD detects an abnormal power failure, it responds to the asynchronous event request command and sets the asynchronous event information field therein to 1;

[0009] The abnormal power failure monitoring driver notifies the cache acceleration driver to refresh the data in memory to the SSD;

[0010] The modified data in memory is written to the SSD via the host cache driver.

[0011] In one embodiment, the method further includes:

[0012] An asynchronous event request command is issued by the abnormal power failure monitoring driver, and the Event Type parameter in the asynchronous event request command is set to 7 to indicate that abnormal power failure information is being obtained.

[0013] When the SSD detects an abnormal power failure, it sends a CQ to the host, wherein the asynchronous event information field in the CQ is set to 1 to indicate that an abnormal power failure event has been detected.

[0014] When the CQ is captured by the abnormal power failure monitoring driver on the host side, the internal asynchronous event information field in the CQ is parsed. If the parsing result is 1, abnormal power failure protection processing is performed.

[0015] In one embodiment, the step of triggering the event when the SSD detects an abnormal power loss includes:

[0016] The host sends read and write requests to the SSD and accelerates read and write operations through a cache acceleration driver. The cache acceleration driver initiates SSD read and write operations in the background as needed until an abnormal power failure is detected.

[0017] In one embodiment, the step of writing the modified data in memory to the SSD via the host cache driver further includes:

[0018] After the host cache driver completes writing data to the SSD, it notifies the abnormal power failure monitoring driver that the cache refresh is complete. The abnormal power failure monitoring driver then enters a waiting power failure state and no longer forwards host read / write commands.

[0019] A host-side cache abnormal power loss protection device, the device comprising:

[0020] An initialization module is used by the host to obtain SSD information and initialize the internal drivers.

[0021] The command issuing module is used to issue asynchronous event request commands through abnormal power failure monitoring after initialization is completed.

[0022] An anomaly monitoring module is used to respond to the asynchronous event request command and set the asynchronous event information field therein to 1 when the SSD detects an abnormal power failure.

[0023] The power-down processing module is used by the abnormal power-down monitoring driver to notify the cache acceleration driver to refresh the data in memory to the SSD, and write the modified data in memory to the SSD through the host cache driver.

[0024] In one embodiment, the apparatus further includes a command processing module, the command processing module being configured to:

[0025] An asynchronous event request command is issued by the abnormal power failure monitoring driver, and the Event Type parameter in the asynchronous event request command is set to 7 to indicate that abnormal power failure information is being obtained.

[0026] When the SSD detects an abnormal power failure, it sends a CQ to the host, wherein the asynchronous event information field in the CQ is set to 1 to indicate that an abnormal power failure event has been detected.

[0027] When the CQ is captured by the abnormal power failure monitoring driver on the host side, the internal asynchronous event information field in the CQ is parsed. If the parsing result is 1, abnormal power failure protection processing is performed.

[0028] In one embodiment, the device further includes a read / write acceleration module, the read / write acceleration module being used for:

[0029] The host sends read and write requests to the SSD and accelerates read and write operations through a cache acceleration driver. The cache acceleration driver initiates SSD read and write operations in the background as needed until an abnormal power failure is detected.

[0030] In one embodiment, the apparatus further includes a command forwarding module, the command forwarding module being configured to:

[0031] After the host cache driver completes writing data to the SSD, it notifies the abnormal power failure monitoring driver that the cache refresh is complete. The abnormal power failure monitoring driver then enters a waiting power failure state and no longer forwards host read / write commands.

[0032] A computer device includes a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to implement the steps of any of the methods described above.

[0033] A computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the steps of any of the above methods.

[0034] The aforementioned host-side cache abnormal power loss protection method, device, computer equipment, and storage medium obtain SSD information from the host and initialize internal drivers. After initialization, an asynchronous event request command is issued through the abnormal power loss monitoring driver. When the SSD detects an abnormal power loss, it replies to the asynchronous event request command and sets the asynchronous event information field to 1. The abnormal power loss monitoring driver notifies the cache acceleration driver to flush data in memory to the SSD. The host cache driver then writes the modified data in memory to the SSD. This invention issues a specific asynchronous event command to the disk. When the disk detects an impending abnormal power loss, it replies with the asynchronous event and marks the impending abnormal power loss. After the host-side power loss monitoring captures this command, it promptly flushes the data to be written in the host buffer to the SSD, completing data persistence. This invention can improve host-side cache performance while ensuring timely data writing to the SSD during power loss, further guaranteeing data integrity. Attached Figure Description

[0035] Figure 1 This is a schematic diagram of a typical file system-based SSD read / write process;

[0036] Figure 2 This is a diagram illustrating an existing method for adding host-side SSD caching acceleration / management.

[0037] Figure 3 This is a flowchart illustrating a host-side cache abnormal power failure protection method in one embodiment;

[0038] Figure 4 This is an architecture diagram of a host-side cache abnormal power loss protection system in one embodiment;

[0039] Figure 5 This is an interactive diagram of a host-side cache abnormal power failure protection method in another embodiment;

[0040] Figure 6 This is a structural block diagram of a host-side cache abnormal power-loss protection device in one embodiment;

[0041] Figure 7 This is a structural block diagram of the host-side cache abnormal power-loss protection device in another embodiment;

[0042] Figure 8 This is a structural block diagram of the host-side cache abnormal power-loss protection device in another embodiment;

[0043] Figure 9 This is a structural block diagram of the host-side cache abnormal power-loss protection device in another embodiment;

[0044] Figure 10 This is an internal structural diagram of a computer device in one embodiment. Detailed Implementation

[0045] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0046] like Figure 1 The diagram shows a typical SSD read / write process based on a file system: In the host user space, there are multiple applications, each of which can initiate read and write operations based on the file system.

[0047] The host kernel mode includes: a file system protocol stack, which translates application file operation requests into corresponding storage device requests; it also collects the completion status of storage device requests and returns it to the file operation requester. A storage device driver protocol stack receives file system operation requests, translates them into corresponding bus driver requests; it also collects the completion status of bus driver requests and returns it to the upper-layer driver caller. A bus driver protocol stack receives storage device driver requests, operates the corresponding hardware device, communicates with the SSD via the bus, and collects completion status / data, returning it to the upper-layer driver caller.

[0048] SSD: Receives host command requests transmitted via the bus and completes the reading / writing of host data through its internal modules.

[0049] During this process, there is usually a cache at the file system level, which keeps the recently accessed file reads and writes in memory to avoid initiating time-consuming operations on the SSD.

[0050] like Figure 2 The diagram illustrates an existing method for accelerating / managing host-side SSD caching to improve host-side access performance.

[0051] Specifically, a custom SSD cache acceleration driver is implemented under the host kernel driver. After loading, this driver operates between the storage device driver and the bus driver, implementing the following functions:

[0052] - Based on the configuration, request a certain number of buffer resources and initialize the Cache Entry List.

[0053] - Receive storage device driver requests and perform hit checks / processing / refreshing on read and write commands.

[0054] - For reads that hit the Read / Write Cache, data can be retrieved directly from the Cache List maintained by the driver for acceleration, and the command can be directly fed back to the upper-layer driver to complete the read, thus improving performance.

[0055] - For writes, data can be cached in the Write Cache List first and then directly fed back to the upper-layer driver command to complete, improving performance; data in the Write Cache is only written to the SSD when specific conditions are met (Cache full / host idle, etc.).

[0056] - For reads that miss, the traditional path is used to load data from the SSD; furthermore, according to specific rules, frequently read data can be placed in the Read Cache List to facilitate subsequent read requests and improve performance.

[0057] Based on this model, frequent read and write commands on the host can be accelerated. However, it should be noted that since host memory is volatile when power is lost, cached write data will be lost in the event of an abnormal power outage, leading to user data integrity issues.

[0058] Based on this, the present invention proposes a host-side cache abnormal power-loss protection method, which aims to introduce a power-loss protection mechanism for the buffer acceleration driver to ensure data integrity.

[0059] In one embodiment, such as Figure 3 As shown, a method for protecting host-side cache from abnormal power loss is provided, the method including:

[0060] Step 302: The host obtains SSD information and initializes the internal drivers;

[0061] Step 304: After initialization is complete, send an asynchronous event request command through the abnormal power failure monitoring driver;

[0062] Step 306: When the SSD detects that an abnormal power failure has been triggered, the SSD replies to the asynchronous event request command and sets the asynchronous event information field therein to 1;

[0063] Step 308: The abnormal power failure monitoring driver notifies the cache acceleration driver to refresh the data in memory to the SSD;

[0064] Step 310: Write the modified data in memory to the SSD through the host cache driver.

[0065] This embodiment proposes a method for protecting the host-side cache from abnormal power loss by implementing a custom power loss monitoring driver at the host-side device driver layer. After the power loss monitoring driver is loaded, it sends a specific asynchronous event to the SSD. When the SSD detects an abnormal power loss signal (such as the host-side PLP signal, Power Loss Protection), it notifies the host power loss monitoring driver via an asynchronous event. Upon receiving the asynchronous event, the host power loss monitoring driver immediately triggers the writing of data from the host cache to the SSD, and then stops operations on the disk. This solution ensures improved host-side cache performance while promptly writing data to the SSD during power loss, thus guaranteeing data integrity.

[0066] Specifically, this method can be applied to, for example... Figure 4 In the system architecture diagram shown, an SSD power failure monitoring driver is added between the storage device driver protocol stack and the SSD cache acceleration driver to monitor whether an abnormal power failure event occurs in the SSD and to promptly trigger the writing of data in the cache to the SSD.

[0067] The driver is specifically used to implement the following functions: After the driver is loaded, it constructs an Asynchronous EventRequest command and sends it to the SSD to collect power failure events.

[0068] Wait for the SSD to reply with asynchronous command information, parse the Async Event Information field in CQ, if it is 1, it means that an abnormal power failure has been triggered, and then notify the power failure handling module.

[0069] After receiving the power failure information from the asynchronous power failure event monitoring module, the power failure handling module notifies the cache acceleration module to immediately write the user data in memory that has not yet been written to the SSD to the SSD. At the same time, the cache acceleration module is set to work in Write-Through mode (no longer caching write commands). After the lower-level cache driver module completes the write buffer writing to the SSD, it informs the power failure handling module that the refresh is complete. At this time, the power failure handling module can selectively suspend subsequent read and write commands of the host and stop processing them, waiting for the power failure.

[0070] Finally, the request from the upper-layer driver is handed over to the lower-layer module for processing, and the completed information is fed back to the upper-layer driver.

[0071] In this embodiment, the host obtains SSD information and initializes its internal drivers. After initialization, an asynchronous event request command is issued by the abnormal power failure monitoring driver. When the SSD detects an abnormal power failure, it replies to the asynchronous event request command and sets the asynchronous event information field to 1. The abnormal power failure monitoring driver notifies the cache acceleration driver to flush the data in memory to the SSD. The host cache driver then writes the modified data in memory to the SSD. This solution issues a specific asynchronous event command to the disk. When the disk detects an impending abnormal power failure, it replies with the asynchronous event and marks the impending failure. After the host-side power failure monitoring captures this command, it promptly flushes the data to be written in the host buffer to the SSD, completing the data persistence.

[0072] In one embodiment, the method further includes:

[0073] An asynchronous event request command is issued by the abnormal power failure monitoring driver, and the Event Type parameter in the asynchronous event request command is set to 7 to indicate that abnormal power failure information is being obtained.

[0074] When the SSD detects an abnormal power failure, it sends a CQ to the host, wherein the asynchronous event information field in the CQ is set to 1 to indicate that an abnormal power failure event has been detected.

[0075] When the CQ is captured by the abnormal power failure monitoring driver on the host side, the internal asynchronous event information field in the CQ is parsed. If the parsing result is 1, abnormal power failure protection processing is performed.

[0076] Specifically, in this embodiment, an Asynchronous Event interaction specification is defined based on the NVMe protocol specification, and several Event Types are defined. To meet the application requirements of this invention, the command parameters are extended and defined, as shown in the table below:

[0077]

[0078]

[0079] The host driver sends an Asynchronous Event Request command, and the EventType parameter in the command is 7 (Vendor Specific event), which means that custom (abnormal power failure event) information is obtained.

[0080]

[0081] When the SSD detects an abnormal power failure, it sends a corresponding Completion Queue (CQ) to the host, with the "Async Event Information" field set to 1, indicating that an abnormal power failure event has been detected. Once this CQ is captured by the host-side power failure monitoring driver, the write buffer can be forcibly flushed to the SSD, preventing data loss.

[0082] In this embodiment, a custom power-loss monitoring driver is used to send specific asynchronous event commands to the disk based on the NVMe protocol. When the disk detects an impending abnormal power loss, it replies with the asynchronous event, marking the impending abnormal power loss. After the host-side power-loss monitoring captures this command, it promptly flushes the data to be written in the host buffer to the SSD, completing the data persistence.

[0083] In one embodiment, before the step of triggering when the SSD detects an abnormal power failure, the method further includes: the host sending read / write requests to the SSD and accelerating read / write operations through a cache acceleration driver, wherein the cache acceleration driver initiates SSD read / write operations in the background as needed until an abnormal power failure is detected.

[0084] In one embodiment, after the step of writing the modified data in memory to the SSD through the host cache driver, the method further includes: after the host cache driver completes the data writing to the SSD, it notifies the abnormal power failure monitoring driver that the cache refresh is complete, and the abnormal power failure monitoring driver enters a waiting power failure state and no longer forwards host read and write commands.

[0085] Specifically, refer to Figure 5 The diagram shows the interaction of a host-side cache abnormal power loss protection method. This method includes the following implementation steps:

[0086] Step 5.1: Power on the system, load the driver, and initialize the SSD.

[0087] Step 5.2: The host obtains SSD information, completes initialization, and initializes each driver.

[0088] Step 5.3: The host abnormal power failure monitoring driver issues the ASYNC EVENT Request command: the AsyncEventType field is set to 7, indicating Vendor Specific.

[0089] Step 5.4: The host sends a read / write request.

[0090] Step 5.5: The host cache acceleration driver accelerates read and write operations.

[0091] Step 5.6: The host cache acceleration driver initiates SSD read and write operations in the background as needed.

[0092] Step 5.7: SSD processes read and write requests.

[0093] Step 5.8: Repeat steps 5.4-5.7 until the system experiences an abnormal power failure.

[0094] Step 5.9: The SSD is triggered by detecting an abnormal power failure (e.g., the host input PLP signal is detected and triggered).

[0095] Step 5.10: SSD responds with an Async Event command (Vendor Specific) and sets the AsyncEventInformation field to 1.

[0096] Step 5.11: The power failure monitoring driver notifies the cache acceleration driver to refresh the data in memory to the SSD.

[0097] Step 5.12: The host cache driver writes the modified data in memory to the SSD.

[0098] Step 5.13: After the host cache driver completes writing the data to the SSD, it notifies the power failure monitoring driver that the cache refresh is complete.

[0099] Step 5.14: The power failure monitoring driver enters the power failure waiting state and no longer forwards host read / write commands.

[0100] In this embodiment, while ensuring improved performance of the host-side cache, data can be written to the SSD in a timely manner during power failure, further ensuring data integrity.

[0101] It should be understood that, although Figures 1-5 The steps in the flowchart are shown sequentially as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified herein, there is no strict order in which these steps are executed, and they can be performed in other orders. Figures 1-5 At least some of the steps in the process may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these sub-steps or stages is not necessarily sequential, but can be executed in turn or alternately with other steps or at least some of the sub-steps or stages of other steps.

[0102] In one embodiment, such as Figure 6 As shown, a host-side cache abnormal power loss protection device 600 is provided, the device comprising:

[0103] An initialization module 601 is used by the host to obtain SSD information and initialize the internal drivers.

[0104] Command issuing module 602, the command issuing module is used to issue asynchronous event request commands through abnormal power failure monitoring drive after initialization is completed;

[0105] Anomaly monitoring module 603 is used to respond to the asynchronous event request command and set the asynchronous event information field therein to 1 when the SSD detects that an abnormal power failure has been triggered.

[0106] The power failure handling module 604 is used by the abnormal power failure monitoring driver to notify the cache acceleration driver to refresh the data in memory to the SSD, and write the modified data in memory to the SSD through the host cache driver.

[0107] In one embodiment, such as Figure 7 As shown, a host-side cache abnormal power failure protection device 600 is provided. This device further includes a command processing module 605, which is used for:

[0108] An asynchronous event request command is issued by the abnormal power failure monitoring driver, and the Event Type parameter in the asynchronous event request command is set to 7 to indicate that abnormal power failure information is being obtained.

[0109] When the SSD detects an abnormal power failure, it sends a CQ to the host, wherein the asynchronous event information field in the CQ is set to 1 to indicate that an abnormal power failure event has been detected.

[0110] When the CQ is captured by the abnormal power failure monitoring driver on the host side, the internal asynchronous event information field in the CQ is parsed. If the parsing result is 1, abnormal power failure protection processing is performed.

[0111] In one embodiment, such as Figure 8 As shown, a host-side cache abnormal power loss protection device 600 is provided, which includes a read / write acceleration module 606. The read / write acceleration module is used for:

[0112] The host sends read and write requests to the SSD and accelerates read and write operations through a cache acceleration driver. The cache acceleration driver initiates SSD read and write operations in the background as needed until an abnormal power failure is detected.

[0113] In one embodiment, such as Figure 9 As shown, a host-side cache abnormal power failure protection device 600 is provided. This device further includes a command forwarding module 607, which is used for:

[0114] After the host cache driver completes writing data to the SSD, it notifies the abnormal power failure monitoring driver that the cache refresh is complete. The abnormal power failure monitoring driver then enters a waiting power failure state and no longer forwards host read / write commands.

[0115] For specific limitations regarding the host-side cache abnormal power-loss protection device, please refer to the limitations of the host-side cache abnormal power-loss protection method mentioned above, which will not be repeated here.

[0116] In one embodiment, a computer device is provided, the internal structure of which can be shown as follows: Figure 10 As shown, the computer device includes a processor, memory, and a network interface connected via a device bus. The processor provides computing and control capabilities. The memory includes non-volatile storage media and internal memory. The non-volatile storage media stores operating devices, computer programs, and databases. The internal memory provides an environment for the operation of the operating devices and computer programs stored in the non-volatile storage media. The network interface is used for communication with external terminals via a network connection. When the computer program is executed by the processor, it implements a host-side cache abnormal power-loss protection method.

[0117] Those skilled in the art will understand that Figure 10 The structure shown is merely a block diagram of a portion of the structure related to the present application and does not constitute a limitation on the computer device to which the present application is applied. Specific computer devices may include more or fewer components than those shown in the figure, or combine certain components, or have different component arrangements.

[0118] In one embodiment, a computer device is provided, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to implement the steps in the various method embodiments described above.

[0119] In one embodiment, a computer-readable storage medium is provided having a computer program stored thereon, which, when executed by a processor, implements the steps in the various method embodiments described above.

[0120] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium, and when executed, it can include the processes of the embodiments of the above methods. Any references to memory, storage, databases, or other media used in the embodiments provided in this application can include non-volatile and / or volatile memory. Non-volatile memory can include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), or flash memory. Volatile memory can include random access memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in various forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), dual data rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchronous link DRAM (SLDRAM), RAMbus direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and RAMbus dynamic RAM (RDRAM), etc.

[0121] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0122] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A method for protecting host-side cache from abnormal power loss, the method comprising: The host obtains SSD information and initializes the internal drivers; After initialization is complete, an asynchronous event request command is issued through the abnormal power failure monitoring driver. The Event Type parameter in the asynchronous event request command is set to 7 to indicate that abnormal power failure information is being obtained. When the SSD detects an abnormal power failure, it sends a CQ to the host, where the asynchronous event information field in the CQ is set to 1 to indicate that an abnormal power failure event has been detected. When the CQ is captured by the abnormal power failure monitoring driver on the host side, the internal asynchronous event information field in the CQ is parsed. If the parsing result is 1, abnormal power failure protection processing is performed. The abnormal power failure monitoring driver notifies the cache acceleration driver to refresh the data in memory to the SSD; The modified data in memory is written to the SSD via the host cache driver; The procedure before the step of triggering the SSD by detecting an abnormal power loss includes: The host sends read and write requests to the SSD and accelerates read and write operations through a cache acceleration driver. The cache acceleration driver initiates SSD read and write operations in the background as needed until an abnormal power failure is detected.

2. The host-side cache abnormal power-loss protection method according to claim 1, characterized in that, Following the step of writing the modified data in memory to the SSD via the host cache driver, the method further includes: After the host cache driver completes writing data to the SSD, it notifies the abnormal power failure monitoring driver that the cache refresh is complete. The abnormal power failure monitoring driver then enters a waiting power failure state and no longer forwards host read / write commands.

3. A host-side cache abnormal power-loss protection device, characterized in that, The device includes: An initialization module is used by the host to obtain SSD information and initialize the internal drivers. The command issuing module is used to issue an asynchronous event request command through the abnormal power failure monitoring driver after initialization is completed, and the Event Type parameter in the asynchronous event request command is set to 7 to indicate that abnormal power failure information is being obtained. An anomaly monitoring module is used to send a CQ to the host when the SSD detects an abnormal power failure. The asynchronous event information field in the CQ is set to 1 to indicate that an abnormal power failure event has been detected. The command processing module is used to parse the internal asynchronous event information field in the CQ after it is captured by the abnormal power failure monitoring driver on the host side. If the parsing result is 1, abnormal power failure protection processing is performed. The power failure handling module is used by the abnormal power failure monitoring driver to notify the cache acceleration driver to refresh the data in memory to the SSD, and write the modified data in memory to the SSD through the host cache driver. The device further includes a read / write acceleration module, which is used for: The host sends read and write requests to the SSD and accelerates read and write operations through a cache acceleration driver. The cache acceleration driver initiates SSD read and write operations in the background as needed until an abnormal power failure is detected.

4. The host-side cache abnormal power-loss protection device according to claim 3, characterized in that, The device further includes a command forwarding module, the command forwarding module being used for: After the host cache driver completes writing data to the SSD, it notifies the abnormal power failure monitoring driver that the cache refresh is complete. The abnormal power failure monitoring driver then enters a waiting power failure state and no longer forwards host read / write commands.

5. A computer device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, When the processor executes the computer program, it implements the steps of the method of claim 1 or 2.

6. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it implements the steps of the method of claim 1 or 2.

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