FPGA-based DDR read-write arbitration method and device

Abstract

The application relates to the technical field of high-speed data transmission, in particular to a DDR read-write arbitration method and device based on FPGA, which comprises an input data buffer module, a DDR read-write arbitration module, an output data buffer module and a DDR IP core control module; wherein the DDR read-write arbitration module is used for controlling the DDR IP core control module to write data into the input data buffer module and read data of the DDR IP core control module to the output data buffer module; and the DDR IP core control module is used for controlling a DDR chip. The application can realize dynamic switching of DDR read-write by decomposing the data amount of each DDR write-read, can meet the high-speed data read-write demand, improves the high-speed read-write efficiency, and moreover, the arbitration control parameter can be changed according to the system design, so that the DDR read-write arbitration is more flexible and reliable.

Description

Technical Field

[0001] This invention relates to the field of high-speed data transmission technology, and more specifically, to a DDR read / write arbitration method and apparatus based on FPGA. Background Technology

[0002] With the rapid development of communication technology, the total amount of data transmission is constantly increasing. Especially for signal processing in communication equipment, when both uplink and downlink processes involve large amounts of data, the equipment's memory capacity is required to meet the simultaneous uplink and downlink data processing demands. To address this, current solutions primarily involve using external DDR or similar memory for data caching within the equipment.

[0003] In some typical application scenarios, such as communication test instruments, it is necessary to test downlink signal transmission and uplink signal reception simultaneously. This requires quickly reading waveform files from DDR, sending signals, and writing high-speed signals acquired by ADC into DDR. It requires simultaneous read and write operations on DDR. However, existing DDR read and write controllers only perform other processing when all data packets are read or written. This greatly limits data processing efficiency.

[0004] Chinese invention patent CN111610934A discloses a DDR controller and control method, specifically outlining the following scheme: an input data read / write controller controls the switching between writing and reading between PING FIFO and PANG FIFO; a DDR read / write control module performs read / write control and arbitration on the DDR controller IP core, improving DDR read / write efficiency. However, this prior art mainly meets the control requirements for single DDR read / write operations, lacking flexibility for large data volumes and high-speed data processing, and is also inefficient. Summary of the Invention

[0005] The purpose of this invention is to provide a DDR read / write arbitration method and apparatus based on FPGA. By decomposing the amount of data written and read in each DDR operation, it can realize dynamic switching of DDR read / write, meet the requirements of high-speed data read / write, and improve the efficiency of high-speed read / write. This solves the problem that the existing technology cannot meet the requirements of large data volume and high-speed data processing, and is inefficient.

[0006] The embodiments of the present invention are implemented through the following technical solution: a DDR read / write arbitration method based on FPGA, comprising: The DDR read / write arbitration module receives DDR read / write commands, which include a first command and / or a second command. Determine whether the DDR read / write instruction contains the first instruction. If not, enable the read operation of the output data cache module. Whenever the data size cached by the output data cache module reaches the second preset cache threshold, complete one read operation and enable it M times until the output data cache module completes the read data length requirement indicated by the second instruction. Here, M is determined by the read data length requirement and the second preset cache threshold. If so, then further determine whether it contains only the first instruction; If so, the write operation of the input data cache module is enabled. Whenever the data cached in the input data cache module reaches the first preset cache threshold, the cached data is written into the DDR IP core control module to complete one write operation. This is repeated N times until the write data length requirement indicated by the first instruction is met. Here, N is determined by the write data length requirement and the first preset cache threshold. The DDR IP core control module is used to control the DDR chip. If not, the read or write operation will be switched after the input data buffer module or the output data buffer module completes a corresponding write or read operation until the write data length requirement or read data length requirement of the corresponding instruction is met.

[0007] According to a preferred embodiment, the input data caching module includes an input FIFO cache and an input FIFO control module. The input FIFO control module is used to control the writing of data into the input FIFO cache for caching, receive FIFO read instructions from the DDR read / write arbitration module, and control the reading of data from the input FIFO cache and its transmission to the DDR read / write arbitration module. The output data buffer module includes an output FIFO buffer and an output FIFO control module. The output FIFO control module is used to control the data read from the DDR read / write arbitration module to be written into the output FIFO buffer for buffering, and to generate an output FIFO reading enable signal to control the output data to be read from the output FIFO buffer.

[0008] According to a preferred embodiment, if so, the write operation of the input data cache module is enabled. Whenever the size of the data cached in the input data cache module reaches a first preset cache threshold, the cached data is written to the DDR IP core control module to complete one write operation. This is repeated N times until the write data length requirement indicated by the first instruction is met. Specifically, this includes: Step S11: The input FIFO control module receives the DDR write command and enables the write operation of the input FIFO buffer; Step S12: The input FIFO control module counts the data written to the input FIFO buffer. When data of size n is written to the input FIFO buffer, a first flag is written to the DDR read / write arbitration module. The first flag indicates that data of size n has been written to the input FIFO buffer. Step S13: The input FIFO control module receives the DDR read command, enables the read operation of the input FIFO buffer, and writes data of size n into the DDRIP core control module; Step S14, repeat steps S11 to S13 until the write data length requirement indicated by the first instruction is met.

[0009] According to a preferred embodiment, if not, then the read operation of the output data buffer module is enabled. Each time the size of the data buffered by the output data buffer module reaches a second preset buffer threshold, a read operation is completed, and this is performed M times until the read data length requirement indicated by the second instruction is met. Specifically, this includes: Step S21: The output FIFO control module receives the DDR read command and enables the write operation of the output FIFO buffer. Step S22: The output FIFO control module counts the data written to the output FIFO buffer. When data of size m equal to the second preset buffer threshold is written to the output FIFO buffer, a second flag is written to the DDR read / write arbitration module. The second flag is used to indicate that data of size m has been written to the output FIFO buffer. Step S23, repeat steps S21 to S22 until the required data length is achieved as indicated by the second instruction.

[0010] According to a preferred embodiment, step S23 further includes: Step S231: The DDR read / write arbitration module verifies the data size in the output FIFO buffer. When the data size in the output FIFO buffer reaches the third preset buffer threshold x, a reading enable signal is generated. The third preset buffer threshold x indicates that the data in the output FIFO buffer is about to be full. Step S232: The output FIFO control module receives the reading enable signal and enables the data in the output FIFO buffer to be read out.

[0011] According to a preferred embodiment, if not, then after the input data buffer module or the output data buffer module completes a corresponding write or read operation, a switch between read and write operations is performed until the write data length requirement or read data length requirement of the corresponding instruction is met, specifically including: Step S31: The DDR read / write arbitration module receives a read / write flag, which includes a third flag or a fourth flag. The third flag indicates that the input FIFO buffer has written data of size n to the DDR IP core control module, and the fourth flag indicates that the output FIFO buffer has read data of size m from the DDR IP core control module or that the data in the output FIFO buffer has been read out. Step S32: Determine if it is a third flag. If so, proceed to step S33. If not, proceed to step S34; Step S33: The DDR read / write arbitration module detects whether the output FIFO buffer has been enabled M times and whether the data size in the output FIFO buffer has reached x. If the output FIFO buffer has been enabled M times, the write operation of the input FIFO buffer is enabled until N times are enabled, and the process ends. If the output FIFO buffer has been enabled M times without completion and the data size in the output FIFO buffer is less than x, enable the read operation of the output FIFO buffer and proceed to step S35; If the output FIFO buffer is enabled M times without ending and the data size in the output FIFO buffer reaches x, enable the data to be read out of the output FIFO buffer and proceed to step S35. Step S34: The DDR read / write arbitration module detects whether the N enable operations of the input FIFO buffer have ended. If the N enable operations of the input FIFO buffer have ended, the read operation of the output FIFO buffer is enabled until the M enable operations are completed, and then proceeds to step S33. If the input FIFO buffer is enabled N times without completion, enable write operations to the input FIFO buffer; Step S35: The DDR read / write arbitration module returns to the read / write control selection. Step S36, repeat steps S31 to S35 until the N enable times of the input FIFO buffer and the M enable times of the output FIFO buffer have been completed.

[0012] According to a preferred embodiment, the first preset cache threshold n is less than the second preset cache threshold m.

[0013] According to a preferred embodiment, n is determined by the DDR selection and the input data processing rate, and m is determined by the DDR selection and the output data processing rate.

[0014] The present invention also provides an FPGA-based DDR read / write arbitration device, applied to the method described above, including an input data cache module, a DDR read / write arbitration module, an output data cache module, and a DDR IP core control module; wherein, the DDR read / write arbitration module is used to control the DDR IP core control module to write data to the input data cache module and read data from the DDR IP core control module to the output data cache module, and the DDR IP core control module is used to control the DDR chip.

[0015] According to a preferred embodiment, the input data cache module, the DDR read / write arbitration module, the output data cache module, and the DDR IP core control module are all mounted on an FPGA.

[0016] The technical solution of the DDR read / write arbitration method and device based on FPGA of the present invention has at least the following advantages and beneficial effects: The present invention can realize dynamic switching of DDR read / write by decomposing the amount of data written and read in each DDR operation, which can meet the high-speed data read / write requirements and improve the high-speed read / write efficiency; In addition, the arbitration control parameters can be changed according to the system design, making DDR read / write arbitration more flexible and reliable. Attached Figure Description

[0017] Figure 1 This is a schematic diagram of the FPGA-based DDR read / write arbitration device provided in Embodiment 1 of the present invention.

[0018] Figure 2 This is a flowchart illustrating the FPGA-based DDR read / write arbitration method provided in Embodiment 1 of the present invention. Figure 3 This is a schematic diagram of the control flow of the DDR read / write arbitration module provided in Embodiment 4 of the present invention; Figure 4 This is a schematic diagram of the control flow of the input FIFO control module provided in Embodiment 2 of the present invention; Figure 5 This is a schematic diagram of the control flow of the output FIFO control module provided in Embodiment 3 of the present invention; Detailed Implementation To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. The components of the embodiments of the present invention described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0019] Example 1 This embodiment provides an FPGA-based DDR read / write arbitration device, such as... Figure 1 As shown, it includes: A. Input data caching module, which includes an input FIFO cache (FPGA storage resource, which can be configured as FIFO, RAM, etc.) and an input FIFO control module. The input FIFO control module is used to control the writing of data into the input FIFO cache for caching, receive FIFO read instructions from the DDR read / write arbitration module, and control the reading of data from the input FIFO cache and its transmission to the DDR read / write arbitration module.

[0020] B. Output data buffer module, the output data buffer module includes an output FIFO buffer and an output FIFO control module. The output FIFO control module is used to control the data read from the DDR read / write arbitration module to be written into the output FIFO buffer for buffering, and to generate an output FIFO reading enable signal to control the output data to be read from the output FIFO buffer.

[0021] C. DDR read / write arbitration module: The DDR read / write arbitration module is used to control the DDR IP core control module to write data to the input data cache module and read data from the DDR IP core control module to the output data cache module.

[0022] D. DDR IP core control module, which is connected to the DDR chip and performs operations such as transmitting DDR read / write mode, DDR read / write address, and reading / writing data in the DDR chip.

[0023] Furthermore, the input data cache module, DDR read / write arbitration module, output data cache module, and DDRIP core control module are all mounted on an FPGA.

[0024] Combination Figure 2 As shown, the FPGA-based DDR read / write arbitration method of this invention includes: The DDR read / write arbitration module receives DDR read / write instructions and selects DDR read / write functions; wherein, the DDR read / write instructions include a first instruction and / or a second instruction. In one embodiment, the first instruction indicates a write instruction, while the second instruction indicates a read instruction.

[0025] Furthermore, it determines whether the DDR read / write instruction contains a first instruction, that is, whether the DDR read / write instruction indicates a write instruction, a read instruction, or a simultaneous read / write operation, and executes different processing flows for the above three different situations.

[0026] In the first scenario, when the DDR read / write instruction does not contain the first instruction (i.e., it indicates a read operation), the read operation of the output data cache module is further enabled. The data in the DDR chip is then written to the output FIFO cache via the DDR IP core control module for caching. It should be noted that a read operation is completed whenever the size of the data cached by the output data cache module reaches the second preset cache threshold. The output FIFO cache is enabled M times until the output data cache module completes the read data length requirement indicated by the second instruction, where M is determined by the read data length requirement and the second preset cache threshold.

[0027] In the second scenario, when the DDR read / write instruction contains only the first instruction (indicating a write operation), the write operation of the input data cache module is further enabled. Data is then written to the input FIFO cache via the input FIFO control module. It should be noted that whenever the data cached in the input data cache module reaches a first preset cache threshold, the cached data is written to the DDR IP core control module, completing one write operation. The input FIFO cache is enabled N times until the write data length requirement indicated by the first instruction is met, where N is determined by the write data length requirement and the first preset cache threshold.

[0028] In the third scenario, when the DDR read / write instruction contains not only the first instruction but also the second instruction, indicating that read and write operations are performed simultaneously, the read or write operation is switched after the input data buffer module or the output data buffer module completes a corresponding write or read operation until the write data length requirement or read data length requirement of the corresponding instruction is met.

[0029] It should be noted that this invention decomposes and controls the above three situations according to the system configuration requirements. Specifically, for write operations, the amount of data written to DDR each time is controlled to be a first preset cache threshold of nKB; for read operations, the amount of data read from DDR each time is controlled to be a second preset cache threshold of mKB. In one embodiment of this invention, taking a comprehensive tester as an example, the downlink playback signal rate is relatively fast, requiring that data can be continuously read from DDR. In data acquisition and processing, it is necessary to ensure that the acquired data can be continuously written to DDR. Therefore, n is determined by the DDR selection and the input data processing rate, and m is determined by the DDR selection and the output data processing rate. The first preset cache threshold n is less than the second preset cache threshold m, meaning that the amount of data read from DDR each time is large, and a large amount of data needs to be buffered in the output FIFO before reading can begin. The data amount written to DDR is designed to be small to ensure that data can be quickly written to DDR as soon as it is available, which can meet the high-speed data read and write requirements and improve the high-speed read and write efficiency. In one embodiment of this invention, n is set to 2 and m is set to 4.

[0030] In summary, this invention enables dynamic switching between DDR read and write operations by decomposing the amount of data written and read in each DDR operation, thus meeting the requirements for high-speed data read and write and improving high-speed read and write efficiency. In addition, the arbitration control parameters, namely m and n, can be changed according to the system design, making DDR read and write arbitration more flexible and reliable.

[0031] Example 2 This embodiment is an improvement upon embodiment 1. See [link to embodiment 1]. Figure 4 As shown, the specific improvements are as follows: For the second scenario, when the DDR read / write instruction only contains the first instruction, indicating a write operation, the specific processing flow in this embodiment includes: Step S11: The input FIFO control module receives the DDR write command, enables the write operation of the input FIFO buffer, and writes data into the input FIFO buffer for caching.

[0032] Step S12: The input FIFO control module counts the data written to the input FIFO buffer. When data of size n is written to the input FIFO buffer, a first flag is written to the DDR read / write arbitration module. The first flag indicates that data of size n has been written to the input FIFO buffer.

[0033] Step S13: The input FIFO control module receives the DDR read command, enables the read operation of the input FIFO buffer, and writes data of size n into the DDRIP core control module.

[0034] Step S14, repeat steps S11 to S13 until the write data length requirement indicated by the first instruction is met.

[0035] The above steps in this embodiment provide a complete processing flow for write instructions. By decomposing and controlling the write instructions, each DDR write operation is nKB, and the input FIFO buffer is enabled N times. When the N enable operations are completed, the write instruction operation is finished.

[0036] Example 3 This embodiment is an improvement upon embodiment 1. See [link to embodiment 1]. Figure 5 As shown, the specific improvements are as follows: For the first scenario, when the DDR read / write instruction only contains the second instruction, indicating a read operation, the specific processing flow in this embodiment includes: Step S21: The output FIFO control module receives the DDR read command, enables the write operation of the output FIFO buffer, and writes data into the output FIFO buffer for caching.

[0037] Step S22: The output FIFO control module counts the data written to the output FIFO buffer. When data of size m equal to the second preset buffer threshold is written to the output FIFO buffer, a second flag is written to the DDR read / write arbitration module. The second flag is used to indicate that data of size m has been written to the output FIFO buffer.

[0038] Step S23, repeat steps S21 to S22 until the required data length is achieved as indicated by the second instruction.

[0039] Furthermore, regarding the situation where the output FIFO buffer is about to fill or is already full when performing the above steps, step S23 further includes: Step S231: The DDR read / write arbitration module verifies the data size in the output FIFO buffer. When the data size in the output FIFO buffer reaches a third preset buffer threshold x, a reading enable signal is generated. The third preset buffer threshold x indicates that the data in the output FIFO buffer is about to be full. In one embodiment of this example, the third preset buffer threshold x is the output FIFO buffer storage capacity minus mKB. In another embodiment of this example, similar to n and m, x is also determined based on the DDR selection, input data processing rate, and output data processing rate. In this embodiment, x is set to 8.

[0040] Step S232: The output FIFO control module receives the reading enable signal and enables the data in the output FIFO buffer to be read out.

[0041] The above steps in this embodiment provide a complete processing flow for read instructions. By decomposing and controlling the read instructions, each DDR reads mKB of data, and the output FIFO buffer is enabled M times. When the M enabling times are finished, the read instruction operation is completed.

[0042] Example 4 This embodiment is an improvement upon embodiment 1. See [link to embodiment 1]. Figure 3 As shown, the specific improvements are as follows: For the third scenario, when the DDR read / write instruction contains both the first and second instructions, indicating that read and write operations are performed simultaneously, the specific processing flow in this embodiment includes: Step S31: The DDR read / write arbitration module receives a read / write flag, which includes a third flag or a fourth flag. The third flag indicates that the input FIFO buffer has written data of size n to the DDR IP core control module, and the fourth flag indicates that the output FIFO buffer has read data of size m from the DDR IP core control module or that the data in the output FIFO buffer has been read out.

[0043] Step S32: Determine if it is the third flag, i.e., whether a write operation or a read operation has been performed. If it is the third flag, it means that a write operation was performed in the previous step, and then proceed to step S33.

[0044] If not, it indicates that a read operation was performed in the previous step, and then proceed to step S34.

[0045] Step S33: After a write operation has been performed, it is necessary to further determine the current read / write execution status. Specifically, the DDR read / write arbitration module is used to detect whether the output FIFO buffer has been enabled M times and whether the data size in the output FIFO buffer has reached x. This mainly includes the following situations: Case 1: If the output FIFO buffer has been enabled M times, that is, the read instruction has ended, enable the write operation of the input FIFO buffer, complete the remaining unexecuted write operations, and so on until N enable operations are completed, then the process ends.

[0046] Case 2: If the output FIFO buffer has not been enabled M times and the data size in the output FIFO buffer is less than x, that is, the read and write instructions have not been completed, enable the read operation of the output FIFO buffer and go to step S35.

[0047] Case 3: If the output FIFO buffer has been enabled M times without completion and the data size in the output FIFO buffer reaches x, that is, the read and write instructions have not been completed, but the output FIFO buffer is about to be full or is already full, enable the data in the output FIFO buffer to be read out, and go to step S35.

[0048] Step S34: The DDR read / write arbitration module checks whether the Nth enable of the input FIFO buffer has ended; this mainly includes the following situations: Case 1: If the input FIFO buffer has been enabled N times, that is, the write command has ended, enable the read operation of the output FIFO buffer, complete the remaining unexecuted read operations, until the M enable operations are completed; for the case where the output FIFO buffer is about to be full or is already full, proceed to step S33 for processing.

[0049] Case 2: If the input FIFO buffer is enabled N times without completion (i.e., neither the read nor the write command has been completed), then the write operation of the input FIFO buffer is enabled.

[0050] Step S35: The DDR read / write arbitration module returns to the read / write control selection, whereby the DDR read / write arbitration module selects whether to enable the write operation of the input FIFO buffer or enable the read operation of the output FIFO buffer in the next step.

[0051] Step S36, repeat steps S31 to S35 until the N enable times of the input FIFO buffer and the M enable times of the output FIFO buffer have been completed.

[0052] The above are merely preferred embodiments of the present invention and are not intended to limit the invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A DDR read / write arbitration method based on FPGA, characterized in that, include: The DDR read / write arbitration module receives DDR read / write commands, which include a first command and / or a second command. Determine whether the DDR read / write instruction contains the first instruction. If not, enable the read operation of the output data cache module. Whenever the data size cached by the output data cache module reaches the second preset cache threshold m, complete one read operation and enable it M times until the output data cache module completes the read data length requirement indicated by the second instruction. Here, M is determined by the read data length requirement and the second preset cache threshold. If so, then further determine whether it contains only the first instruction; If so, the write operation of the input data cache module is enabled. Whenever the size of the data cached in the input data cache module reaches the first preset cache threshold n, the cached data is written into the DDR IP core control module to complete one write operation. This is repeated N times until the write data length requirement indicated by the first instruction is met. Here, N is determined by the write data length requirement and the first preset cache threshold. The DDR IP core control module is used to control the DDR chip. If not, the read or write operation will be switched after the input data buffer module or the output data buffer module completes a corresponding write or read operation until the write data length requirement or read data length requirement of the corresponding instruction is met.

2. The FPGA-based DDR read / write arbitration method as described in claim 1, characterized in that, The input data caching module includes an input FIFO cache and an input FIFO control module. The input FIFO control module is used to control the writing of data into the input FIFO cache for caching, receive FIFO read instructions from the DDR read / write arbitration module, and control the reading of data from the input FIFO cache and its transmission to the DDR read / write arbitration module. The output data buffer module includes an output FIFO buffer and an output FIFO control module. The output FIFO control module is used to control the data read from the DDR read / write arbitration module to be written into the output FIFO buffer for buffering, and to generate an output FIFO reading enable signal to control the output data to be read from the output FIFO buffer.

3. The FPGA-based DDR read / write arbitration method as described in claim 2, characterized in that, If so, then the write operation of the input data cache module is enabled. Whenever the size of the data cached in the input data cache module reaches the first preset cache threshold, the cached data is written to the DDR IP core control module to complete one write operation. This is repeated N times until the write data length requirement indicated by the first instruction is met. Specifically, this includes: Step S11: The input FIFO control module receives the DDR write command and enables the write operation of the input FIFO buffer; Step S12: The input FIFO control module counts the data written to the input FIFO buffer. When data of size n is written to the input FIFO buffer, a first flag is written to the DDR read / write arbitration module. The first flag indicates that data of size n has been written to the input FIFO buffer. Step S13: The input FIFO control module receives the DDR read command, enables the read operation of the input FIFO buffer, and writes data of size n into the DDR IP core control module; Step S14, repeat steps S11 to S13 until the write data length requirement indicated by the first instruction is met.

4. The FPGA-based DDR read / write arbitration method as described in claim 3, characterized in that, If not, then the read operation of the output data buffer module is enabled. Whenever the size of the data buffered by the output data buffer module reaches the second preset buffer threshold, a read operation is completed, and the enable operation is performed M times until the read data length requirement indicated by the second instruction is met. Specifically, this includes: Step S21: The output FIFO control module receives the DDR read command and enables the write operation of the output FIFO buffer. Step S22: The output FIFO control module counts the data written to the output FIFO buffer. When data of size m equal to the second preset buffer threshold is written to the output FIFO buffer, a second flag is written to the DDR read / write arbitration module. The second flag is used to indicate that data of size m has been written to the output FIFO buffer. Step S23, repeat steps S21 to S22 until the required data length is achieved as indicated by the second instruction.

5. The FPGA-based DDR read / write arbitration method as described in claim 4, characterized in that, Step S23 further includes: Step S231: The DDR read / write arbitration module verifies the data size in the output FIFO buffer. When the data size in the output FIFO buffer reaches the third preset buffer threshold x, a reading enable signal is generated. The third preset buffer threshold x indicates that the data in the output FIFO buffer is about to be full. Step S232: The output FIFO control module receives the reading enable signal and enables the data in the output FIFO buffer to be read out.

6. The FPGA-based DDR read / write arbitration method as described in claim 5, characterized in that, If not, then after the input data buffer module or output data buffer module completes a corresponding write or read operation, the read or write operation is switched until the write data length requirement or read data length requirement of the corresponding instruction is met, specifically including: Step S31: The DDR read / write arbitration module receives a read / write flag, which includes a third flag or a fourth flag. The third flag indicates that the input FIFO buffer has written data of size n to the DDR IP core control module, and the fourth flag indicates that the output FIFO buffer has read data of size m from the DDR IP core control module or that the data in the output FIFO buffer has been read out. Step S32: Determine if it is a third flag. If so, proceed to step S33. If not, proceed to step S34; Step S33: The DDR read / write arbitration module detects whether the output FIFO buffer has been enabled M times and whether the data size in the output FIFO buffer has reached x. If the output FIFO buffer has been enabled M times, the write operation of the input FIFO buffer is enabled until N times are enabled, and the process ends. If the output FIFO buffer has been enabled M times without completion and the data size in the output FIFO buffer is less than x, enable the read operation of the output FIFO buffer and proceed to step S35; If the output FIFO buffer is enabled M times without ending and the data size in the output FIFO buffer reaches x, enable the data to be read out of the output FIFO buffer and proceed to step S35. Step S34: The DDR read / write arbitration module detects whether the N enable operations of the input FIFO buffer have ended. If the N enable operations of the input FIFO buffer have ended, the read operation of the output FIFO buffer is enabled until the M enable operations are completed, and then proceeds to step S33. If the input FIFO buffer is enabled N times without completion, enable write operations to the input FIFO buffer; Step S35: The DDR read / write arbitration module returns to the read / write control selection. Step S36, repeat steps S31 to S35 until the N enable times of the input FIFO buffer and the M enable times of the output FIFO buffer have been completed.

7. The FPGA-based DDR read / write arbitration method as described in any one of claims 1 to 6, characterized in that, The first preset cache threshold n is less than the second preset cache threshold m.

8. The FPGA-based DDR read / write arbitration method as described in claim 7, characterized in that, The n is determined by the DDR selection and the input data processing rate, and the m is determined by the DDR selection and the output data processing rate.

9. A DDR read / write arbitration device based on FPGA, characterized in that, The method described in any one of claims 1 to 8 includes an input data cache module, a DDR read / write arbitration module, an output data cache module, and a DDR IP core control module; wherein the DDR read / write arbitration module is used to control the DDR IP core control module to write data to the input data cache module and read data from the DDR IP core control module to the output data cache module, and the DDR IP core control module is used to control the DDR chip.

10. The FPGA-based DDR read / write arbitration device as described in claim 9, characterized in that, The input data cache module, DDR read / write arbitration module, output data cache module, and DDR IP core control module are all mounted on the FPGA.

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