Pixel driving circuit, display panel and display device

Abstract

This invention provides a pixel driving circuit, a display panel, and a display device. The pixel driving circuit includes a driving transistor, a pulse amplitude module, a pulse width module, and a voltage modulation module. The voltage modulation module is electrically connected to the pulse width module. The voltage modulation module is used to adjust the voltage of a reference signal when the pulse amplitude module writes a data signal to the gate of the driving transistor, so that the pulse width module stops writing an initialization signal. By setting the voltage modulation module and controlling it to adjust the voltage of the reference signal when the pulse amplitude module writes a data signal to the gate of the driving transistor, the problem of unstable display panel caused by the pulse data signal being affected when writing to the gate of the driving transistor, resulting in the gate of the driving transistor not reaching the predetermined driving voltage, is solved in related technologies.

Description

Technical Field

[0001] This invention relates to the field of display technology, and more particularly to a pixel driving circuit, a display panel, and a display device. Background Technology

[0002] MLED displays, characterized by high efficiency, high brightness, and fast response time, have attracted widespread attention in the field of new displays. In related technologies, pixel driving circuits using a hybrid driving method control the emission duration of pixels via a Sweep signal. However, due to insufficient DAC (digital-to-analog converter) driving capability or circuit design defects, this signal transition can be too slow, leading to display panel instability. Summary of the Invention

[0003] Embodiments of the present invention provide a pixel driving circuit, a display panel, and a display device to solve the problem of unstable display caused by the slow transition of the Sweep signal.

[0004] To solve the above problems, the technical solution provided by the present invention is as follows:

[0005] In a first aspect, this application provides a pixel driving circuit, the pixel driving circuit comprising: a driving transistor electrically connected to a light-emitting element, the driving transistor being configured to generate a driving current for driving the light-emitting element according to a data signal; a pulse amplitude module electrically connected to the gate of the driving transistor, the pulse amplitude module being configured to write the data signal to the gate of the driving transistor; a pulse width module electrically connected to the gate of the driving transistor, the pulse width module being configured to write an initialization signal to the gate of the driving transistor according to the data signal and a reference signal, the initialization signal being configured to turn off the driving transistor; and a voltage modulation module electrically connected to the pulse width module, the voltage modulation module being configured to adjust the voltage of the reference signal when the pulse amplitude module writes the data signal to the gate of the driving transistor, so as to stop the pulse width module from writing the initialization signal to the gate of the driving transistor.

[0006] In one embodiment, the pulse width module is electrically connected to a reference signal line to receive the reference signal, and the voltage modulation module includes a modulation transistor, one of the source or drain of the modulation transistor being electrically connected to the reference signal line, and the other of the source or drain of the modulation transistor being connected to a first power supply voltage terminal to receive the first power supply voltage.

[0007] In one embodiment, the data signal sequentially has a first data voltage and a second data voltage. The pulse amplitude module is used to write the second data voltage into the gate of the driving transistor, and the pulse width module is used to write an initialization signal into the gate of the driving transistor according to the first data voltage and the voltage of the reference signal. When the data signal has the second data voltage, the modulation signal controls the modulation transistor to turn on, so as to adjust the voltage of the reference signal to the first power supply voltage.

[0008] In one embodiment, the pulse width module includes: a fourth transistor, one of the source or drain of the fourth transistor being electrically connected to the gate of the driving transistor, and the other of the source or drain of the fourth transistor being used to receive the initialization signal; a fifth transistor, one of the source or drain of the fifth transistor being electrically connected to the gate of the fourth transistor, and the other of the source or drain of the fifth transistor being connected to a data signal port for receiving the data signal, the gate of the fifth transistor being connected to the pulse width modulation voltage port for receiving the pulse width modulation voltage; and a second capacitor, one end of the second capacitor being electrically connected to the reference signal line, and the other end of the second capacitor being electrically connected to the gate of the fourth transistor; wherein, when the voltage of the data signal is a first data voltage, the pulse width modulation voltage controls the fifth transistor to be turned on.

[0009] In one embodiment, the fourth transistor is turned off when the voltage of the reference signal is the first power supply voltage.

[0010] In one embodiment, the pulse amplitude module includes: a first transistor, one of the source or drain of the first transistor being electrically connected to the gate of the driving transistor, the other of the source or drain of the first transistor being connected to a data port for receiving the data signal, and the gate of the first transistor being connected to the pulse amplitude modulation voltage port for receiving the pulse amplitude modulation voltage; wherein, when the voltage of the data signal is a second data voltage, the pulse amplitude modulation voltage controls the first transistor to be turned on.

[0011] In one embodiment, one of the source or drain of the driving transistor is connected to a second power supply voltage terminal to receive the second power supply voltage, and the other of the source or drain of the driving transistor is electrically connected to the light-emitting element. The pulse amplitude module further includes: a first capacitor, one end of which is electrically connected to one of the source or drain of the first transistor, and the other end of which is electrically connected to the other of the source or drain of the driving transistor; and a compensation transistor, one of the source or drain of the compensation transistor is electrically connected to the other of the source or drain of the driving transistor, and the other of the source or drain of the compensation transistor is electrically connected to a sensing signal port. The gate of the compensation transistor is connected to a sensing control signal port to receive a sensing control signal. The sensing signal port is used to transmit the initialization signal and sense the voltage of the other of the source or drain of the driving transistor.

[0012] In one embodiment, the timing of the sensing control signal is the same as the timing of the pulse amplitude modulation voltage.

[0013] Secondly, embodiments of this application provide a display panel including the pixel driving circuit as described in any of the above embodiments.

[0014] Thirdly, embodiments of this application provide a display device, including the display panel as described in the above embodiments.

[0015] The beneficial effects of this invention are as follows: by setting a voltage modulation module and controlling the voltage modulation module to adjust the voltage of the reference signal when the pulse amplitude module writes the data signal to the gate of the driving transistor, the pulse width module stops writing the initialization signal to the gate of the driving transistor, thereby ensuring that the data signal is not affected when writing to the gate of the driving transistor. This solves the problem in related technologies where the data signal is affected when writing to the gate of the driving transistor, causing the gate of the driving transistor to fail to reach the predetermined driving voltage, which in turn causes the display panel to be unstable. Attached Figure Description

[0016] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0017] Appendix Figure 1 This is a schematic diagram of the pixel driving circuit in a related technology according to an embodiment of the present invention;

[0018] Appendix Figure 2This is a schematic diagram of the pixel driving circuit in one embodiment of the present invention;

[0019] Appendix Figure 3 This is a schematic diagram of the pixel driving circuit in one embodiment of the present invention;

[0020] Appendix Figure 4 for Figure 3 The timing diagram of each signal in the pixel driving circuit is shown.

[0021] Appendix Figure 5 for Figure 4 Timing diagram of partial signal and modulation signal. Detailed Implementation

[0022] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0023] MLED displays, characterized by high efficiency, high brightness, and fast response time, have attracted widespread attention in the field of new displays. In related technologies, pixel driving circuits using a hybrid driving method control the emission duration of pixels via a Sweep signal. However, due to insufficient DAC (digital-to-analog converter) driving capability or circuit design defects, this signal transition can be too slow, leading to display panel instability.

[0024] like Figure 1 As shown, in the related technology, a pixel driving circuit includes: a first transistor T1, a driving transistor T2, a fourth transistor T4, a fifth transistor T5, a first capacitor C1, and a second capacitor C2.

[0025] The gate of driving transistor T2 is connected to the first node Q, the source of driving transistor T2 is connected to the constant high voltage VDD, and the drain of driving transistor T2 is connected to the second node S.

[0026] The gate of the first transistor T1 is connected to the pulse amplitude modulation control signal line SPAM, the source of the first transistor T1 is connected to the data signal line Data, and the drain of the first transistor T1 is connected to the first node Q. The first capacitor C1 is coupled between the first node Q and the second node S.

[0027] The gate of the fourth transistor T4 is connected to the third node P, the source of the fourth transistor T4 is connected to the first node Q, and the drain of the fourth transistor T4 is connected to the reset signal line Vref.

[0028] The gate of the fifth transistor T5 is connected to the pulse width modulation control signal line SPWM, the source of the fifth transistor T5 is connected to the data signal line Data, and the drain of the fifth transistor T5 is connected to the third node P.

[0029] The second capacitor C2 is coupled between the sweep frequency signal line Sweep and the third node P;

[0030] The workflow of the pixel driving circuit includes: a first writing stage, a second writing stage, and a light emission stage.

[0031] First write stage: SPWM and SWEEP signals are high level, the fifth transistor T5 is turned on, and the data signal line writes the first data voltage VPWM to point P through the fifth transistor T5. At this time, Vgs of the fourth transistor T4 is greater than Vth4, the fourth transistor T4 is turned on, and the initialization signal Vref is written to the gate of the driving transistor.

[0032] Second writing stage: SPAM signal is high level, SWEEP signal jumps from high level to low level, turning off the fourth transistor T4 and turning on the first transistor T1. The data signal line writes the second data voltage VPAM to point Q through the first transistor T1. At this time, Vgs = VQ - VS = VPAM > Vth1 of the driving transistor T2, T1 turns on, VDD is low level, and the LED is still not lit.

[0033] During the light-emitting phase, VDD is at a high level, driving the LED to emit light. The Sweep signal gradually rises, and under the coupling effect of C2, the potential at point P gradually rises from the VPWM potential until Vgs of the fourth transistor T4 > Vth4. At this point, the fourth transistor T4 turns on, and Vref pulls down the potential at point Q through the fourth transistor T4, thereby turning off the driving transistor T2 and stopping the LED from emitting light. Thus, the light-emitting time of the LED can be adjusted by adjusting the magnitude of VPWM and the on-time of the fourth transistor T4.

[0034] However, due to insufficient driving capability of the DAC (digital-to-analog converter) or circuit design defects, the Sweep signal transitions too slowly during the second writing stage. The fourth transistor T4 remains in the on state, which affects the writing of the second data voltage VPAM of the data signal to the Q point (the gate of the first transistor). As a result, the first transistor T1 fails to reach the predetermined driving voltage, leading to unstable display on the display panel.

[0035] Figure 2 , Figure 3 A pixel driving circuit is provided in an embodiment of this application.

[0036] Please refer to Figure 2 and Figure 3This application provides a pixel driving circuit, which includes a driving transistor T2, a pulse amplitude module 100, a pulse width module 200, and a voltage modulation module 300.

[0037] The driving transistor T2 is electrically connected to the light-emitting element LED, and is used to generate a driving current for the LED based on the data signal. The pulse amplitude module 100 is electrically connected to the gate of the driving transistor T2, and is used to write the data signal to the gate of the driving transistor T2. The pulse width module 200 is electrically connected to the gate of the driving transistor T2, and is used to write an initialization signal to the gate of the driving transistor T2 based on the data signal and a reference signal. The initialization signal is used to turn off the driving transistor T2. The voltage modulation module 300 is electrically connected to the pulse width module 200, and is used to adjust the voltage of the reference signal when the pulse amplitude module 100 writes the data signal to the gate of the driving transistor T2, so that the pulse width module 200 stops writing the initialization signal.

[0038] Understandably, the voltage modulation module 300 adjusts the voltage of the reference signal when the pulse amplitude module 100 writes the data signal to the gate of the driving transistor T2, so that the pulse width module 200 stops writing the initialization signal to the gate of the driving transistor T2, thereby ensuring that the data signal is not affected when it is written to the gate of the driving transistor T2.

[0039] In this application, by setting a voltage modulation module 300 and controlling the voltage modulation module 300 to adjust the voltage of the reference signal when the pulse amplitude module 100 writes the data signal to the gate of the driving transistor T2, the pulse width module 200 stops writing the initialization signal to the gate of the driving transistor T2, thereby ensuring that the data signal is not affected when writing to the gate of the driving transistor T2. This solves the problem in related technologies where the data signal is affected when writing to the gate of the driving transistor T2, causing the gate of the driving transistor T2 to fail to reach the predetermined driving voltage, which in turn causes the display panel to be unstable.

[0040] In some embodiments, to save on the number of signal lines, the pulse width module 200 and the pulse amplitude module 100 are electrically connected to the same data signal line. Therefore, the corresponding data signal Data should have different voltages at different times. In this embodiment, the data signal Data sequentially has a first data voltage VPWM and a second data voltage VPAM. When the pulse width module 200 writes the data signal Data, the data signal Data has the first data voltage VPWM; when the pulse amplitude module 100 writes the data signal Data, the data signal Data has the second data voltage VPAM. The pulse amplitude module 100 writes the second data voltage VPAM to the gate of the driving transistor T2, and the pulse width module 200 writes the initialization signal Vref to the gate of the driving transistor T2 according to the first data voltage VPWM and the voltage of the reference signal Sweep.

[0041] To prevent the data signal Data from being affected when it is written to the gate of the driving transistor T2 through the pulse width module 200, thus causing the gate of the driving transistor T2 to fail to reach the predetermined driving voltage and resulting in unstable display on the display panel, in this embodiment, when the data signal Data has the second data voltage VPAM, the voltage modulation module 300 adjusts the voltage of the reference signal Sweep to the first power supply voltage VSS. The first power supply voltage VSS causes the voltage modulation module 300 to stop outputting the initialization signal Vref, so as to prevent the initialization signal Vref from affecting the writing of the second data voltage VPAM to the gate of the driving transistor T2.

[0042] In one embodiment, the voltage modulation module 300 includes a modulation transistor T6, one of the source or drain of the modulation transistor T6 being electrically connected to a reference signal line, the other of the source or drain of the modulation transistor T6 being used to receive a first power supply voltage VSS, and the gate of the modulation transistor T6 being used to receive a modulation signal SWP_DOWN. The modulation signal SWP_DOWN is used to control the modulation transistor T6 to turn on when the data signal Data has a second data voltage VPAM, so as to adjust the voltage of the reference signal Sweep to the first power supply voltage VSS.

[0043] In one embodiment, the pulse width modulation module 200 includes a fourth transistor T4, a fifth transistor T5, and a second capacitor C2. One of the sources or drains of the fourth transistor T4 is electrically connected to the gate of the driving transistor T2, and the other of the sources or drains of the fourth transistor T4 is used to receive the initialization signal Vref. One of the sources or drains of the fifth transistor T5 is electrically connected to the gate of the fourth transistor T4, and the other of the sources or drains of the fifth transistor T5 is used to receive the data signal Data. The gate of the fifth transistor T5 is used to receive the pulse width modulation voltage SPWM. One end of the second capacitor C2 is electrically connected to the reference signal line, and the other end of the second capacitor C2 is electrically connected to the gate of the fourth transistor T4. When the voltage of the data signal Data is a first data voltage VPWM, the pulse width modulation voltage SPWM controls the fifth transistor T5 to turn on, so as to write the first data voltage VPWM into the gate (Q point) of the driving transistor T2.

[0044] In one embodiment, one of the source or drain of the driving transistor T2 is used to receive a first power supply voltage VDD, and the other of the source or drain of the driving transistor T2 is electrically connected to the light-emitting element LED. The pulse amplitude module 100 includes a first transistor T1 and a first capacitor C1. One end of the first capacitor C1 is electrically connected to one of the source or drain of the first transistor T1, and the other end of the first capacitor C1 is electrically connected to the other of the source or drain of the driving transistor T2. One of the source or drain of the first transistor T1 is electrically connected to the gate of the driving transistor T2. The other of the source or drain of the first transistor T1 is used to receive the data signal Data, and the gate of the first transistor T1 is used to receive the pulse amplitude modulation voltage SPAM. When the voltage of the data signal Data is a second data voltage VPAM, the pulse amplitude modulation voltage SPAM controls the first transistor T1 to turn on, so as to write the second data voltage VPAM into the gate (Q point) of the driving transistor T2.

[0045] Figure 4 for Figure 3 The timing diagram of each signal in the pixel driving circuit is shown. Figure 5 For the modulation signal SWP_DOWN and Figure 4 Timing diagram of the middle part of the signal.

[0046] Please refer to Figure 4 and Figure 5The pixel driving circuit includes at least the following two working stages: Write stage and Emitting stage (t3). The write stage can be divided into a first write stage t1 and a second write stage t2 according to the different voltages of the data signals.

[0047] In the first writing stage t1: the pulse width modulation voltage SPWM and the reference signal SWEEP are at high level, the fifth transistor T5 is turned on, and the data signal line writes the first data voltage VPWM to point P through the fifth transistor T5. At this time, the Vgs of the fourth transistor T4 is greater than Vth4, the fourth transistor T4 is turned on, and the initialization signal Vref is written to the gate of the driving transistor.

[0048] In the second writing stage t2: the pulse amplitude modulation voltage SPAM is high, turning on the first transistor T1. The data signal line writes the second data voltage VPAM to point Q through the first transistor T1. At the same time, the modulation signal SWP_DOWN is high, turning on the modulation transistor and pulling the reference signal SWEEP from high to the first power supply voltage (low level). Through the coupling effect of the second capacitor, the potential of point P is pulled down, so that Vgs of the fourth transistor T4 is less than Vth4, turning off the fourth transistor T4 and stopping the output of the initialization signal Vref.

[0049] At this time, Vgs = VPAM > Vth1 for driving transistor T2, T1 is turned on, VDD is at a low level, and the LED does not light up.

[0050] During the light-emitting stage t3, the second power supply signal VDD changes from low to high, driving the LED to start emitting light. The modulation signal SWP_DOWN is low, turning off the modulation transistor. At the same time, the reference signal Sweep gradually rises. Under the coupling effect of C2, the potential at point P gradually rises until Vgs of the fourth transistor T4 is greater than Vth4. Then, the fourth transistor T4 turns on, and the initialization signal Vref pulls down the potential at point Q through the fourth transistor T4, thereby turning off the driving transistor T2 and stopping the LED from emitting light.

[0051] As can be seen from the above working process, the modulation signal SWP_DOWN is at a high level during the second writing stage, which controls the modulation transistor to turn on and pulls the reference signal SWEEP down from a high level to the first power supply voltage (low level). This pulls down the potential of point P through the coupling effect of the second capacitor, making Vgs of the fourth transistor T4 < Vth4. The fourth transistor T4 turns off and stops outputting the initialization signal Vref, thus not affecting the writing of the second data voltage VPAM. This avoids the problem in related technologies where the data signal is affected when writing to the gate of the driving transistor, causing the gate of the driving transistor to fail to reach the predetermined driving voltage, which in turn causes the display panel to be unstable.

[0052] In one embodiment, the pulse amplitude module 100 further includes a compensation transistor T3, one of the source or drain of the compensation transistor T3 being electrically connected to the other of the source or drain of the driving transistor T2, and the other of the source or drain of the compensation transistor T3 being electrically connected to a sensing signal line. The gate of the compensation transistor T3 is used to receive a sensing control signal Sense. It is understood that when the compensation transistor T3 is provided, the pixel driving circuit should include at least a sensing phase in addition to the above-described phases. In the sensing phase, the sensing control signal Sense controls the compensation transistor T3 to turn on, so as to sense the voltage of the other of the source or drain of the driving transistor T2 through the sensing signal line for compensation.

[0053] In one embodiment, the sensing signal line is also used to transmit the initialization signal Vref. If the timing of the sensing control signal Sense is the same as the timing of the pulse amplitude modulation voltage SPAM, that is, when the second control signal is high, the sensing signal Sense is also high, so that the first transistor T1 and the compensation transistor T3 are turned on at the same time. When the first transistor T1 writes the second data voltage VPAM into the gate of the driving transistor T2, the initialization signal Vref is simultaneously written into one of the source or drain of the driving transistor T2 to initialize it.

[0054] Secondly, embodiments of this application provide a display panel including the pixel driving circuit as described in any of the above embodiments.

[0055] Thirdly, embodiments of this application provide a display device, including the display panel as described in the above embodiments.

[0056] In summary, although the present invention has been disclosed above with reference to preferred embodiments, the above preferred embodiments are not intended to limit the present invention. Those skilled in the art can make various modifications and refinements without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the scope defined in the claims.

Claims

1. A pixel driving circuit, characterized in that, The pixel driving circuit includes: A driving transistor is electrically connected to a light-emitting element, and the driving transistor is used to generate a driving current for driving the light-emitting element according to a data signal; A pulse amplitude module, wherein the control terminal of the pulse amplitude module is connected to the pulse amplitude modulation voltage port, and the output terminal of the pulse amplitude module is electrically connected to the gate of the driving transistor, and the pulse amplitude module is used to write the data signal to the gate of the driving transistor; A pulse width module, wherein the control terminal of the pulse width module is connected to the pulse width modulation voltage port, and the output terminal of the pulse width module is electrically connected to the gate of the driving transistor, and the pulse width module is used to write an initialization signal to the gate of the driving transistor according to the data signal and the reference signal; A voltage modulation module is electrically connected to the pulse width module. The voltage modulation module is used to adjust the voltage of the reference signal when the pulse amplitude module writes the data signal to the gate of the driving transistor, so that the pulse width module stops writing the initialization signal to the gate of the driving transistor.

2. The pixel driving circuit according to claim 1, characterized in that, The first terminal of the pulse width module is electrically connected to the reference signal port to receive the reference signal, wherein the voltage modulation module includes: A modulation transistor, wherein one of its source or drain is electrically connected to the reference signal port, the other of its source or drain is connected to a first power supply voltage port to receive a first power supply voltage, and the gate of the modulation transistor is electrically connected to a modulation signal port to receive a modulation signal.

3. The pixel driving circuit according to claim 2, characterized in that, The data signal has a first data voltage and a second data voltage in sequence. The pulse amplitude module is used to write the second data voltage into the gate of the driving transistor. The pulse width module is used to write an initialization signal into the gate of the driving transistor according to the first data voltage and the voltage of the reference signal. When the data signal has the second data voltage, the modulation signal controls the modulation transistor to turn on, so as to adjust the voltage of the reference signal to the first power supply voltage.

4. The pixel driving circuit according to claim 3, characterized in that, The pulse width module includes: A fourth transistor, one of the source or drain of the fourth transistor is electrically connected to the gate of the driving transistor, and the other of the source or drain of the fourth transistor is connected to an initialization signal port to receive the initialization signal; A fifth transistor, one of the source or drain of the fifth transistor is electrically connected to the gate of the fourth transistor, the other of the source or drain of the fifth transistor is connected to a data signal port to receive the data signal, and the gate of the fifth transistor is connected to the pulse width modulation voltage port to receive the pulse width modulation voltage. The second capacitor has one end electrically connected to the reference signal port and the other end electrically connected to the gate of the fourth transistor. Specifically, when the voltage of the data signal is the first data voltage, the pulse width modulation voltage controls the fifth transistor to turn on.

5. The pixel driving circuit according to claim 4, characterized in that, The fourth transistor is turned off when the voltage of the reference signal is the first power supply voltage.

6. The pixel driving circuit according to claim 3, characterized in that, The pulse amplitude module includes: A first transistor, wherein one of the source or drain of the first transistor is electrically connected to the gate of the driving transistor, the other of the source or drain of the first transistor is connected to a data port for receiving the data signal, and the gate of the first transistor is connected to the pulse amplitude modulation voltage port for receiving the pulse amplitude modulation voltage. Specifically, when the voltage of the data signal is the second data voltage, the pulse amplitude modulation voltage controls the first transistor to turn on.

7. The pixel driving circuit according to claim 6, characterized in that, One of the source or drain of the driving transistor is connected to the second power supply voltage terminal to receive the second power supply voltage, and the other of the source or drain of the driving transistor is electrically connected to the light-emitting element. The pulse amplitude module further includes: A first capacitor, one end of which is electrically connected to one of the source or drain terminals of the first transistor, and the other end of which is electrically connected to the other of the source or drain terminals of the driving transistor; and A compensation transistor, wherein one of the source or drain of the compensation transistor is electrically connected to the other of the source or drain of the driving transistor, the other of the source or drain of the compensation transistor is electrically connected to a sensing signal port, and the gate of the compensation transistor is used to connect to a sensing control signal port to receive a sensing control signal. The sensing signal port is used to transmit the initialization signal and sense the voltage of the other of the source or drain of the driving transistor.

8. The pixel driving circuit according to claim 7, characterized in that, The timing of the sensing control signal is the same as the timing of the pulse amplitude modulation voltage.

9. A display panel, characterized in that, Includes the pixel driving circuit as described in any one of claims 1-8.

10. A display device, characterized in that, Includes the display panel as described in claim 9.

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