Display device and display driving method

Abstract

The present application relates to a display device and a display driving method. Light emitting elements, driving transistors for supplying driving currents to the light emitting elements using driving voltages, and a plurality of switching transistors for controlling driving of the driving transistors are provided on a display panel. A gate driving circuit supplies a plurality of scan signals to the display panel through a plurality of gate lines. An emission driving circuit supplies a plurality of emission signals to the display panel through a plurality of emission signal lines. A data driving circuit supplies data voltages to the display panel. A timing controller divides the display panel into a plurality of blocks, and in a low-speed mode operated at a low-speed driving frequency, controls a level of a bias voltage applied to a driving transistor of a corresponding block among the plurality of blocks according to a gray scale of a data voltage supplied to the corresponding block.

Description

Technical Field

[0001] Embodiments of this disclosure relate to a display device and a display driving method, and more specifically, to a display device and a display driving method capable of reducing flicker caused by the grayscale of an image, for example, during driving at a low-speed driving frequency. Background Technology

[0002] In response to the development of the information society, the demand for image display devices is increasing. In this regard, a range of display devices, such as liquid crystal displays (LCDs), organic light-emitting diode displays (OLEDs), electrophoretic displays, micro-LED displays, and quantum dot displays, have recently become widely used.

[0003] Among these display devices, organic light-emitting display devices have advantages in terms of fast response speed, high luminous efficiency, high brightness, and wide viewing angle because they use self-emissive organic light-emitting diodes.

[0004] This organic light-emitting display device may include organic light-emitting diodes (OLEDs) disposed in multiple sub-pixels arranged in a display panel, and the OLEDs can be controlled to emit light by controlling the current flowing through them, thereby displaying images while controlling the brightness of the sub-pixels.

[0005] Here, the image data provided to the display device can be a still image or video where the image changes at a constant or variable rate. Video can correspond to various types of images, such as sports videos, movie videos, and game videos.

[0006] In addition, the display device can switch to various driving modes, for example, automatically, based on user input, or based on the operating status.

[0007] The descriptions provided in the background section should not be assumed to be prior art simply because they are mentioned in or associated with the background section. The background section may include information describing one or more aspects of the subject matter art. Summary of the Invention

[0008] The display device can change the driving frequency, for example, depending on the type of input image data or the driving mode. When the display device operates at a low driving frequency, flickering may occur due to the grayscale of the image, thereby reducing the image quality.

[0009] In this regard, the inventors of this disclosure have invented a display device and a display driving method that can reduce image quality defects that occur when operating at low speed driving frequencies.

[0010] Embodiments of this disclosure may provide a display device and a display driving method that can reduce image quality defects such as flicker by stably maintaining the driving transistor during periods of operation at low driving frequencies.

[0011] Embodiments of this disclosure may provide a display device and a display driving method that can reduce image quality defects by changing the level of the bias voltage applied to the driving transistor according to the grayscale of the image during a period of operation at a low driving frequency.

[0012] Embodiments of this disclosure may provide a display device and a display driving method that can improve image quality by changing the level of the bias voltage while operating at a low-speed driving frequency, by reflecting the grayscale of a block-specific image on the display panel.

[0013] Embodiments of this disclosure can provide a display device and a display driving method that can effectively improve image quality by controlling the bias voltage differently in refresh frames and skip frames while operating at a low driving frequency.

[0014] According to an exemplary embodiment, a display device is provided, comprising: a display panel having a light-emitting element thereon, a driving transistor that provides a driving current to the light-emitting element using a driving voltage, and a plurality of switching transistors that control the driving of the driving transistor; a gating driving circuit that provides a plurality of scanning signals to the display panel through a plurality of gating lines; a light-emitting driving circuit that provides a plurality of light-emitting signals to the display panel through a plurality of light-emitting signal lines; a data driving circuit that provides a data voltage to the display panel; and a timing controller that divides the display panel into a plurality of blocks, and in a low-speed mode operating at a low-speed driving frequency, controls the level of the bias voltage applied to the driving transistor of the corresponding block according to the grayscale of the data voltage provided to the corresponding block among the plurality of blocks.

[0015] A display driving method for driving a display panel is also provided. The display panel includes light-emitting elements, driving transistors that provide driving current to the light-emitting elements using a driving voltage, and multiple switching transistors that control the driving of the driving transistors. This display driving method may include: converting a first mode with a high-speed driving frequency to a second mode with a low-speed driving frequency; detecting the grayscale of each block of the display panel; determining the level of a bias voltage corresponding to the grayscale of each block; and controlling the level of the bias voltage applied to the driving transistors according to the blocks of the display panel.

[0016] According to the embodiments, the display device and display driving method can reduce image quality defects that occur when operating at low-speed driving frequencies.

[0017] Furthermore, according to the embodiments, the display device and display driving method can reduce image quality defects such as flicker by stably maintaining the driving transistor during periods of operation at low driving frequencies.

[0018] Furthermore, according to the embodiments, the display device and display driving method can reduce image quality defects by changing the level of the bias voltage applied to the driving transistor according to the grayscale of the image during periods of operation at low driving frequency.

[0019] Furthermore, according to the embodiments, the display device and display driving method can improve image quality by changing the level of the bias voltage while operating at a low-speed driving frequency, by reflecting the grayscale of a block-specific image on the display panel.

[0020] Furthermore, according to the embodiments, the display device and display driving method can effectively improve image quality by controlling the bias voltage differently in refresh frames and skip frames while operating at a low driving frequency.

[0021] It will be understood that the foregoing general description and the following detailed description are illustrative and exemplary, and are intended to provide further explanation of the claimed inventive concept. Attached Figure Description

[0022] The above and other objects, features and advantages of this disclosure will become clearer from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0023] Figure 1 This is a diagram illustrating a schematic configuration of a display device 100 according to an exemplary embodiment;

[0024] Figure 2 This is an example diagram illustrating a system of a display device according to an exemplary embodiment;

[0025] Figure 3 This is a diagram illustrating a display panel according to an exemplary embodiment in which a gating drive circuit and a light-emitting drive circuit are implemented using a GIP structure.

[0026] Figure 4 This is a diagram schematically illustrating the driving pattern according to frequency variation in a display device according to an exemplary embodiment;

[0027] Figure 5 This is a diagram illustrating a sub-pixel circuit of a display device according to an exemplary embodiment;

[0028] Figure 6 This is a diagram illustrating a case where image data provided during a refresh frame period is divided into multiple gray levels according to an exemplary embodiment, and a bias voltage is set differently according to the gray levels of the image data.

[0029] Figure 7 This is a diagram illustrating the application of different bias voltages to different areas of a display panel in a display device according to an exemplary embodiment;

[0030] Figure 8 This is a diagram illustrating the signal waveform during a refresh frame period in a display device according to an exemplary embodiment;

[0031] Figure 9 This is a diagram illustrating the signal waveform during a skip frame period in a display device according to an exemplary embodiment;

[0032] Figure 10 This is a diagram illustrating cases where the bias voltage applied in a refresh frame and the bias voltage applied in a skip frame are controlled differently in a display device according to an exemplary embodiment;

[0033] Figure 11 This is a diagram illustrating another sub-pixel circuit of the display device according to an embodiment; and

[0034] Figure 12 This is a flowchart illustrating a display driving method according to an exemplary embodiment.

[0035] Throughout the accompanying drawings and detailed embodiments, unless otherwise described, the same reference numerals should be understood to refer to the same elements, features, and structures. For clarity, illustrative purposes, the relative dimensions and descriptions of these elements may be exaggerated. Detailed Implementation

[0036] In the following description, some embodiments of this disclosure will be described in detail with reference to the exemplary accompanying drawings. In the following description of examples or embodiments of the invention, reference will be made to the accompanying drawings, in which specific examples or embodiments that can be implemented are illustrated, and in which the same reference numerals and symbols may be used to denote the same or similar components, even when the same or similar components are shown in different drawings. Furthermore, in the following description of examples or embodiments of the invention, detailed descriptions of well-known functions and components incorporated herein will be omitted where it is determined that such detailed descriptions might obscure the subject matter of some embodiments of the invention. Terms such as “comprising,” “having,” “including,” “constituting,” “made of,” and “formed by” as used herein are generally intended to allow for the addition of additional components, unless these terms are used in conjunction with the term “only.” When used herein, the singular form is intended to include the plural form unless the context clearly indicates otherwise.

[0037] The shapes, dimensions, scales, angles, quantities, etc., shown in the accompanying drawings, which are used to describe various exemplary embodiments of this disclosure, are given by way of example only. Therefore, this disclosure is not limited to what is shown in the figures.

[0038] Terms such as “first,” “second,” “A,” “B,” “(A),” or “(B)” may be used herein to describe elements of the invention. Each of these terms is not intended to define the nature, order, sequence, or number of elements, but is only used to distinguish the corresponding element from other elements.

[0039] When referring to the first element and the second element as "connected or joined," "in contact or overlapping," etc., it should be interpreted as meaning that not only can the first element be "directly connected or joined" or "directly in contact or overlapping" with the second element, but also that a third element can be "inserted" between the first and second elements, or that the first and second elements can be "connected or joined," "in contact or overlapping," etc., through a fourth element. Here, the second element can be included in at least one of two or more elements that are "connected or joined," "in contact or overlapping," etc., with each other.

[0040] When time-related terms such as “after,” “following,” “next,” “before,” etc., are used to describe the handling or operation of an element or configuration, or a process or step in an operation, handling, or manufacturing method, these terms may be used to describe discontinuous or non-sequential handling or operations unless used with the terms “directly” or “immediately.”

[0041] In this document, terms such as “below,” “lower,” “above,” “upper,” etc., may be used to describe the relationships between elements as shown in the figures. It will be understood that these terms are spatially relative and based on the orientation depicted in the figures.

[0042] The term "at least one" should be understood to include any and all combinations of one or more of the relevant listed items. For example, "at least one of the first, second, and third items" means a combination of all listed elements, a combination of any two of the three elements, and each individual element as the first, second, and third element.

[0043] Furthermore, when referring to any size, relative size, etc., even if no specific description is specified, it should be assumed that the numerical values ​​or corresponding information of the component or feature (e.g., level, range, etc.) include the tolerances or error ranges that may be caused by various factors (e.g., process factors, internal or external influences, noise, etc.). In addition, the term "may" fully encompasses all the meanings of the term "able to".

[0044] The features of the various embodiments of this disclosure may be partially or wholly coupled or combined with each other, and may be technically interoperable and driven with each other in various ways, as will be fully understood by those skilled in the art. Furthermore, the embodiments of this disclosure may be implemented independently of each other or may be implemented together in an interdependent relationship.

[0045] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which the exemplary embodiments are described. It will be further understood that terms such as those defined in common dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art, and should not be interpreted in an idealized or overly formal sense unless explicitly defined herein. For example, the terms “component” or “unit” can be applied, for example, to a single circuit or structure, an integrated circuit, a computational block of a circuit device, or any structure configured to perform the described functions, as would be understood by one of ordinary skill in the art.

[0046] In the following, various embodiments of this disclosure will be described in detail with reference to the accompanying drawings.

[0047] Figure 1 This is a diagram illustrating a schematic configuration of a display device 100 according to an exemplary embodiment.

[0048] Reference Figure 1 A display device 100 according to an exemplary embodiment may include: a display panel 110 connected to a plurality of gate lines GL and a plurality of data lines DL, wherein a plurality of sub-pixels SP are arranged, for example, in a matrix; a gate driving circuit 120 for driving the plurality of gate lines GL; a light-emitting driving circuit 122 for driving a plurality of light-emitting signal lines EL; a data driving circuit 130 for providing data voltage through the plurality of data lines DL; a timing controller 140 for controlling the gate driving circuit 120, the light-emitting driving circuit 122, and / or the data driving circuit 130; and a power management circuit 150. The embodiments are not limited thereto. As an example, additional components may be included, and / or at least one of the above components may be omitted. As an example, the light-emitting driving circuit 122 may be omitted according to the design of the display device 100.

[0049] The display panel 110 can display images based on scan signals transmitted from the gating drive circuit 120 via multiple gating lines GL and data voltages transmitted from the data drive circuit 130 via multiple data lines DL.

[0050] When the display panel 110 is a liquid crystal display (LCD) panel, the display panel 110 may include a liquid crystal layer located between two substrates and can operate in any known mode (e.g., twisted nematic (TN) mode, vertical alignment (VA) mode, in-plane switching (IPS) mode, or edge field switching (FFS) mode). Conversely, when the display panel 110 is an organic light-emitting display panel, the display panel 110 may be implemented using a top-emitting structure, a bottom-emitting structure, or a dual-emitting structure.

[0051] In the display panel 110, multiple pixels can be arranged in a matrix. Each pixel includes sub-pixels SP of different colors (e.g., red sub-pixels, green sub-pixels, and blue sub-pixels). The implementation is not limited to this. As an example, at least one pixel may also include a white sub-pixel. Sub-pixels of other color combinations such as cyan, magenta, and yellow are also possible. Each sub-pixel SP can be defined by a data line DL and a gate line GL.

[0052] A single sub-pixel SP is formed in the region where the data line DL and the gate line GL intersect each other. The sub-pixel SP may include a thin-film transistor (TFT) for driving the sub-pixel SP, a light-emitting element (e.g., an organic light-emitting diode (OLED)) providing a data voltage, and a storage capacitor electrically connected to the light-emitting element to maintain the voltage. However, embodiments of this disclosure are not limited thereto, and the sub-pixel SP may also include other elements not shown.

[0053] For example, when a display device 100 with a resolution of 2160×3840 includes four types of sub-pixels SP (e.g., white (W), red (R), green (G), and blue (B) sub-pixels), since 3840 data lines DL are connected to the four (WRGB) sub-pixels respectively, there may be 2160 gating lines GL and a total of 15360 (=3840×4) data lines DL. The resolution, sub-pixel type, gating lines GL, and the number of data lines DL are not limited to this. Multiple sub-pixels SP can be respectively set at the intersection of gating lines GL and data lines DL.

[0054] The gating drive circuit 120 is controlled by the controller 140. The gating drive circuit 120 controls the driving timing of multiple sub-pixels SP by sequentially outputting scan signals to multiple gating lines GL disposed on the display panel 110.

[0055] In a display device 100 with a resolution of 2160×3840, sequentially outputting scan signals to 2160 gate lines GL from the first gate line to the 2160th gate line can be referred to as 2160-phase driving. Alternatively, sequentially outputting scan signals to four corresponding gate lines (for example, sequentially outputting scan signals to the first gate line to the fourth gate line, and then sequentially outputting scan signals to the fifth gate line to the eighth gate line) can be referred to as four-phase driving. As an example, sequentially outputting scan signals to N corresponding gate lines GL can be referred to as N-phase driving.

[0056] Here, the gating drive circuit 120 may include one or more gating drive integrated circuits GDIC (see Figure 2Depending on the driving method, the gate driving circuit 120 may be located on one or both sides of the display panel 110. Alternatively, the gate driving circuit 120 may be implemented using a gate in panel (GIP) structure disposed inside the bezel of the display panel 110. The implementation is not limited thereto. As an example, the gate driving circuit 120 may be connected to the display panel 110 in a tape auto-bonding (TAB) type, or in a chip-on-glass (COG) type or chip-on-panel (COP) type, or in a chip-on-film (COF) type.

[0057] Here, the gating drive circuit 120 located on the left side of the display panel 110 and the light-emitting drive circuit 122 located on the right side of the display panel 110 are shown as examples. As an example, the gating drive circuit 120 and the light-emitting drive circuit 122 can be located in the same position or interchanged with each other.

[0058] The light-emitting driving circuit 122 outputs a light-emitting signal EM under the control of the timing controller 140 (see...). Figure 5 And it provides a light-emitting signal EM to the display panel 110 through the light-emitting signal line EL.

[0059] The light-emitting driving circuit 122 can sequentially provide the light-emitting signal EM to the light-emitting signal line EL by shifting the light-emitting signal EM using a shift register. Here, as an example, under the control of the timing controller 140, the light-emitting driving circuit 122 can drive the display panel 110 at a predetermined duty cycle (e.g., a duty cycle of 30%, 50%, or 80%) by repeatedly flipping the light-emitting signal EM during the image driving period. The predetermined duty cycle can be any ratio below %.

[0060] The light-emitting driving circuit 122 may include one or more light-emitting control circuits (ECC) (see Figure 2 The light-emitting driving circuit 122 can be located on one or both sides of the display panel 110, depending on the driving method. The light-emitting driving circuit 122 can be directly disposed on the display panel 110 together with the gate-in-panel (GIP) process, but is not limited thereto. As an example, the light-emitting driving circuit 122 can be connected to the display panel 110 in a tape-on-board (TAB) type, or in a chip-on-glass (COG) type, chip-on-panel (COP) type, or in a chip-on-film (COF) type. As an example, the light-emitting driving circuit 122 can be connected to the display panel 110 in the same or different manner as the gate-on driving circuit 120.

[0061] A frame can be divided into a recording period and a light emission period following the recording period, but is not limited to this. During the recording period, recording is performed when a data voltage is applied to each sub-pixel SP. During the light emission period, the sub-pixel SP emits light at a predetermined duty cycle in response to the light emission signal EM. Typically, the light emission signal EM can cause the sub-pixel SP to emit light at a duty cycle of 50% or less during the light emission period, but is not limited to this. Since the recording period consists of only about one horizontal period (1H) or more horizontal periods, most of a frame (e.g., the remainder) corresponds to the light emission period.

[0062] During the recording period, the storage capacitor of the subpixel SP is charged with a data voltage. The subpixel SP repeatedly lights up and turns off in response to the emission signal EM. That is, the subpixel SP repeats the light-on and light-off operation by emitting light at a duty cycle of 50% or less during a frame period.

[0063] In this way, after being turned off, the subpixel SP emits light using the voltage charged in the storage capacitor. Therefore, during the light-emitting period following the recording period, the subpixel SP can display data with the same brightness at a duty cycle of 50% or less for a frame period without providing it with additional data voltage.

[0064] The data driving circuit 130 receives image data DATA from the timing controller 140 and converts the received image data DATA into an analog data voltage. Then, the data driving circuit 130 outputs the data voltage to the corresponding data line DL at the timing when a scan signal is applied via the gate line GL. At the timing when the light emission signal EM is applied, each sub-pixel SP connected to the data line DL emits light with a light emission intensity corresponding to the data voltage.

[0065] Similarly, the data drive circuit 130 may include one or more source driver integrated circuits (SDICs) (see...). Figure 2 The source driver integrated circuit SDIC can be connected to the bonding pads of the display panel 110 using a tape-on-board (TAB) structure or a chip-on-glass (COG) structure, or it can be directly mounted on the display panel 110 (COP).

[0066] In some cases, each source driver integrated circuit (SDIC) can be integrated into the display panel 110. Alternatively, each SDIC can be implemented using a chip-on-film (COF) structure. In this case, each SDIC can be mounted on a circuit film and electrically connected to the corresponding data line DL of the display panel 110 via the circuit film.

[0067] The timing controller 140 provides various control signals to the gating drive circuit 120, the light emission drive circuit 122, and the data drive circuit 130, and controls the operation of these circuits. Specifically, the timing controller 140 controls the gating drive circuit 120 to output a scan signal and the light emission drive circuit 122 to output a light emission signal EM, and transmits image data DATA received from an external source to the data drive circuit 130, but is not limited to these functions.

[0068] Here, the timing controller 140 receives various timing signals (including vertical synchronization signal Vsync, horizontal synchronization signal Hsync, data enable signal DE, and master clock MCLK) and image data DATA from an external device, such as the host system 200.

[0069] The host system 200 can be selected from television (TV) systems, set-top boxes, navigation systems, personal computers (PCs), home theater systems, mobile devices, or wearable devices.

[0070] Therefore, the timing controller 140 uses various timing signals received from the host system 200 to generate control signals and transmits the control signals to the gating drive circuit 120, the light-emitting drive circuit 122, and the data drive circuit 130.

[0071] For example, the timing controller 140 outputs various gating control signals (including a gating start pulse GSP, a gating clock GCLK, a gating output enable signal GOE, etc.) to control the gating drive circuit 120. Here, the gating start pulse GSP controls the timing of the start of operation of one or more gating drive integrated circuits GDIC in the gating drive circuit 120. Furthermore, the gating clock GCLK is a clock signal commonly input to one or more gating drive integrated circuits GDIC and controls the shift timing of the scan signal. Additionally, the gating output enable signal GOE specifies the timing information for one or more gating drive integrated circuits GDIC.

[0072] Furthermore, the timing controller 140 outputs various light-emitting signals (including the light-emitting start pulse ESP, the light-emitting clock ECLK, and the light-emitting output enable signal EOE) to control the light-emitting drive circuit 122. Here, the light-emitting start pulse ESP controls the timing of the start of operation of one or more light-emitting control circuits (ECCs) in the light-emitting drive circuit 122. Additionally, the light-emitting clock ECLK is a clock signal commonly input to one or more light-emitting control circuits (ECCs) and controls the shift timing of the light-emitting signals. The light-emitting output enable signal EOE specifies the timing information for one or more light-emitting control circuits (ECCs).

[0073] In addition, the timing controller 140 outputs various data control signals (including the source start pulse SSP, the source sampling clock SCLK, and the source output enable signal SOE) to control the data drive circuit 130. Here, the source start pulse SSP controls the timing of data sampling for one or more source driver integrated circuits (SDICs) of the data drive circuit 130. The source sampling clock SCLK is a clock signal used to control the timing of data sampling by the source driver integrated circuits (SDICs). The source output enable signal SOE controls the output timing of the data drive circuit 130.

[0074] The display device 100 may include a power management circuit 150 to provide various voltages or currents to the display panel 110, the gating drive circuit 120, the light-emitting drive circuit 122, the data drive circuit 130, etc., or to control the various voltages or currents to be provided.

[0075] The power management circuit 150 generates the power required to drive the display panel 110, the gating drive circuit 120, the light-emitting drive circuit 122, and the data drive circuit 130 by regulating the DC input voltage Vin provided from an external device, such as the host system 200.

[0076] Furthermore, the sub-pixel SP is located at the intersection of the gate line GL and the data line DL. Light-emitting elements can be individually disposed within the sub-pixel SP. For example, an organic light-emitting display device includes light-emitting elements such as OLEDs in each sub-pixel. The organic light-emitting display device can display an image by controlling the current flowing through the light-emitting elements according to the data voltage.

[0077] The display device 100 can be any of a variety of displays (including LCD, organic light-emitting display, micro LED display, quantum dot display, etc.).

[0078] Figure 2 This is an example diagram illustrating a system of display devices according to an exemplary embodiment.

[0079] Reference Figure 2 The display device 100 according to an exemplary embodiment is an example in which the source driver integrated circuit SDIC of the data driver circuit 130 is implemented using the COF structure among various structures such as TAB, COG and COF structures, and the gating driver circuit 120 and the light-emitting driver circuit 122 are implemented using the GIP structure among various structures such as TAB, COG, COF and GIP structures.

[0080] When the gate drive circuit 120 has a GIP structure, the multiple gate drive integrated circuits (GDICs) of the gate drive circuit 120 can be directly formed within the bezel of the display panel 110. Here, various signals (e.g., clock signal, gate high signal, and gate low signal) required to generate scan signals can be provided to the gate drive integrated circuits (GDICs) through gate drive related signal lines provided, for example, within the bezel.

[0081] Furthermore, when the light-emitting driving circuit 122 has a GIP structure, the light-emitting control circuit ECC of the light-emitting driving circuit 122 can be directly formed within the bezel of the display panel 110. Here, various signals (e.g., clock signals and light-emitting signals) required to generate light-emitting signals can be provided to the light-emitting control circuit ECC through light-emitting driving related signal lines provided, for example, within the bezel.

[0082] Similarly, the source driver integrated circuit SDIC of the data driver circuit 130 can be mounted on the source film SF. One side of each source film SF can be electrically connected to the display panel 110. Furthermore, the wires that electrically connect the source driver integrated circuit SDIC to the display panel 110 can be provided on the source film SF, for example, on the top of the source film SF.

[0083] The display device 100 may include at least one source printed circuit board (SPCB) and a control printed circuit board (CPCB) for circuit connection of multiple source driver integrated circuits (SDICs) with other devices. Here, control components and various electrical devices may be mounted on the control printed circuit board (CPCB).

[0084] Here, the other side of the source film SF on which the active driver integrated circuit SDIC is mounted can be connected to the source printed circuit board SPCB. That is, each source film SF on which the active driver integrated circuit SDIC is mounted can be configured such that one side of it is electrically connected to the display panel 110, and the other side of it is electrically connected to the source printed circuit board SPCB.

[0085] The timing controller 140 and / or power management circuit 150 may be mounted on a control printed circuit board (CPCB), but are not limited thereto. The timing controller 140 can control the operation of the data drive circuit 130, the gating drive circuit 120, and the light-emitting drive circuit 122. The power management circuit 150 can provide drive voltage or current to the display panel 110, the data drive circuit 130, the gating drive circuit 120, the light-emitting drive circuit 122, etc., and / or can control the provided voltage or current.

[0086] The source printed circuit board (SPCB) and the control printed circuit board (CPCB) can be electrically connected to each other via at least one connecting component. This connecting component can be, for example, a flexible flat cable (FFC), a flexible printed circuit (FPC), etc. Furthermore, the source printed circuit board (SPCB) and the control printed circuit board (CPCB) can be integrated into a single printed circuit board.

[0087] The display device 100 may optionally include a setup board 170 electrically connected to a control printed circuit board (CPCB). Here, the setup board 170 may also be referred to as a power board. The setup board 170 may be equipped with a main power management circuit 160 to manage the overall power supply of the display device 100. The main power management circuit 160 may work in conjunction with the power management circuit 150.

[0088] In the display device 100 with the above configuration, a driving voltage is generated by a setting board 170 and transmitted to a power management circuit 150 in a control printed circuit board (CPCB). The power management circuit 150 transmits the driving voltage required for display driving or feature value sensing to a source printed circuit board (SPCB) via a flexible printed circuit or a flexible flat cable (FFC). The driving voltage transmitted to the source printed circuit board (SPCB) is provided by a source driver integrated circuit (SDIC) to, for example, illuminate or sense specific sub-pixels (SPs) in the display panel 110.

[0089] Here, each sub-pixel SP arranged in the display panel 110 of the display device 100 may include a light-emitting element and circuit elements (e.g., a driving transistor) for driving the light-emitting element.

[0090] The type and number of circuit elements in each sub-pixel SP can be determined differently depending on the functions, design, etc. to be provided.

[0091] Figure 3 This is a diagram illustrating a display panel according to an exemplary embodiment, wherein a gating drive circuit and a light-emitting drive circuit are implemented using a GIP structure.

[0092] Reference Figure 3 In the display device 100 according to the embodiment, n gate lines GL1 to GLn (where n is a natural number) and n light-emitting signal lines EL1 to ELn (where n is a natural number) can be arranged in the effective area A / A of the displayed image. Although the number of gate lines and the number of light-emitting signal lines are the same here, the embodiment is not limited to this. For example, the number of gate lines and the number of light-emitting signal lines can be different.

[0093] Here, the effective area A / A is an area provided with multiple sub-pixels SP (e.g., white, red, green, and / or blue sub-pixels, or sub-pixels of other colors) for emitting light of the corresponding color to display an image. Furthermore, as an example, at least one dummy pixel may optionally be disposed at some location within the effective area A / A. The dummy pixel does not emit light because a scan signal and / or data voltage Vdata is not applied to it. As an example, the dummy pixel may have a load similar to that of the sub-pixels SP.

[0094] In an exemplary embodiment of this disclosure, the plurality of sub-pixel regions emitting light of the corresponding color and the region provided with non-emitting dummy pixels are collectively referred to as the effective area A / A. Alternatively, the plurality of sub-pixel regions emitting light of the corresponding color and the region provided with non-emitting dummy pixels may also be collectively referred to as a pixel array.

[0095] The gating drive circuit 120 may include n gating drive integrated circuits GDIC1 to GDICn corresponding to n gating lines GL1 to GLn. The n gating drive integrated circuits GDIC1 to GDICn may be disposed within the border of an undefined pixel, for example, located on one side of the effective region A / A.

[0096] Therefore, the n gating driver integrated circuits GDIC1 to GDICn can output scanning signals to the n gating lines GL1 to GLn respectively.

[0097] Furthermore, the light-emitting driving circuit 122 may include n light-emitting control circuits ECC1 to ECCn corresponding to the n light-emitting signal lines EL1 to ELn. The n light-emitting control circuits ECC1 to ECCn may be disposed, for example, within the border of an undefined pixel located on the other side of the effective area A / A. As an example, the n light-emitting control circuits ECC1 to ECCn may be disposed on the other side of the effective area A / A opposite to the first side.

[0098] Therefore, n light-emitting control circuits ECC1 to ECCn can output light-emitting signals EM to n light-emitting signal lines EL1 to ELn respectively.

[0099] In this way, when implementing the gating drive circuit 120 and the light-emitting drive circuit 122 using a GIP structure, it is not necessary to manufacture separate integrated circuits with gating or light-emitting functions, nor is it necessary to bond these separate integrated circuits to the display panel 110. Therefore, the number of integrated circuits can be reduced, and the process of connecting the integrated circuits to the display panel 110 can be omitted. Furthermore, the size of the bezel in the display panel 110 where the integrated circuits are bonded can be reduced.

[0100] Alternatively, n gating driver integrated circuits GDIC1 to GDICn and n light emission control circuits ECC1 to ECCn can be arranged together within a frame located on one side.

[0101] Within the pixel-free border located on one side of the effective area A / A, multiple clock lines GCL can be set for transmitting the strobe clock GCLK required to generate and output the scan signal.

[0102] In addition, within the pixel-free border located on the other side of the effective area A / A, multiple light emission clock lines ECL can be set for transmitting the light emission clock ECLK required to generate and output the light emission signal EM.

[0103] Figure 4 This is a diagram schematically illustrating the driving pattern that varies according to frequency in a display device according to an exemplary embodiment.

[0104] Reference Figure 4 The operation modes of the display device 100 according to the exemplary embodiment can be divided into a first mode (Mode 1) and a second mode (Mode 2). In the first mode (Mode 1), an image is displayed while changing at a high speed at a first frequency, and in the second mode (Mode 2), a still image or a low-speed image is displayed at a low speed at a second frequency. The embodiments are not limited thereto. As an example, the operation modes of the display device 100 may also include a third mode in which the image is displayed at a third frequency different from the first or second frequency.

[0105] For example, in the first mode (Mode 1), the display panel 110 can display full-color image data at a frequency of 120Hz, corresponding to a first frequency. When the display device 100 operates in the first mode (Mode 1), the sub-pixels SP of the display panel 110 display image data DATA transmitted from the timing controller 140 every 120 frames.

[0106] In this way, the period of time during which images are continuously displayed or updated on the display panel 110 at a high-speed drive frequency can be called a refresh frame. For example, when the drive frequency is 120Hz, all 120 frames in 1 second of the first mode Mode 1 can be refresh frames for displaying or updating image data.

[0107] Furthermore, when the display device 100 operates in the second mode 2, which displays still images or slow-moving images, the display device 100 may display a specified image on the display panel 110 during the initial period of the second mode 2, and may not output or update image data on the display panel 110 during the remaining time.

[0108] For example, when entering the second mode (Mode 2), the display device 100 can change the driving frequency from a first frequency of 120Hz to a second frequency of 1Hz. Here, in the second mode (Mode 2) where the driving frequency is changed to 1Hz, the image displayed during the last period of the first mode (Mode 1) is displayed on the display panel 110. The implementation is not limited to this. The first and second frequencies can be any frequencies other than 120Hz or 1Hz, as long as the second frequency is lower than the first frequency.

[0109] For example, in the second mode 2 operating at 1Hz, the display device 100 can be operated such that the image displayed in the last period of the first mode 1 is displayed or updated once on the display panel 110, and the image is not displayed or updated during the remaining time.

[0110] In this scenario, in Mode 2, each subpixel SP displays or updates the image once, but the voltage stored in the storage capacitor Cst can be maintained for the remainder of the time. The period during which no image data is transmitted to the display panel 110 and the voltage stored in the storage capacitor Cst is maintained can be referred to as a skip frame. For example, when the drive frequency is 120Hz, the first frame in Mode 2 can be a refresh frame displaying image data, and the remaining frames can be skip frames where no image data is output.

[0111] In this way, in the low-speed drive mode 2, image data is not displayed during a predetermined period (i.e., skipped frames), thereby reducing power consumption.

[0112] Figure 5 This is a diagram illustrating a sub-pixel circuit of a display device according to an exemplary embodiment.

[0113] Reference Figure 5 According to an exemplary embodiment, the sub-pixel SP of the display device 100 includes a first switching transistor T1 to a seventh switching transistor T7, a driving transistor DRT, a storage capacitor Cst, and a light-emitting element ED.

[0114] Here, the light-emitting element ED can be a self-emitting element capable of emitting its own light, such as an organic light-emitting diode (OLED) or a light-emitting diode (LED), but is not limited to these.

[0115] In the sub-pixel SP according to the embodiment, the second switching transistor T2 to the fourth switching transistor T4, the sixth switching transistor T6, the seventh switching transistor T7, and the driving transistor DRT can be P-type transistors, while the first switching transistor T1 and the fifth switching transistor T5 can be N-type transistors, but are not limited thereto. As an example, any one of the first switching transistor T1 to the seventh switching transistor T7 and the driving transistor DRT can be a P-type transistor or an N-type transistor.

[0116] P-type transistors are more reliable than N-type transistors. When the driving transistor DRT is formed from a P-type transistor, since the drain electrode is fixed at a high driving voltage VDD, the current flowing through the light-emitting element ED does not fluctuate due to the capacitor CST. Therefore, current can be supplied reliably and easily.

[0117] For example, a P-type transistor can be connected to the anode of a light-emitting element (ED). Here, because a predetermined amount of current can flow regardless of changes in the current and threshold voltage of the ED, the transistors T4 and T6 connected to the ED operate with high reliability in the saturation region.

[0118] In this structure of the sub-pixel SP, each of the N-type transistors T1 and T5 can be formed by an oxide transistor (e.g., a transistor having a channel formed by an oxide of semiconductor oxide such as In, Ga, or Zn, or indium gallium zinc oxide (IGZO)), while each of the P-type transistors DRT, T2 to T4, T6, and T7 can be formed by a Si transistor (e.g., a transistor called a low-temperature polycrystalline silicon (LTPS) transistor, having a polycrystalline silicon channel formed using a low-temperature process) formed from a transistor material such as silicon (Si). However, the implementation is not limited to this. As an example, any one of the first switching transistors T1 to the seventh switching transistor T7 and the driving transistor DRT can be an oxide transistor, a silicon transistor, or a transistor with other semiconductor materials.

[0119] Oxide transistors are characterized by having lower leakage current than silicon transistors. Therefore, when transistors are formed from oxide transistors, leakage current from the gate electrode of the driving transistor DRT can be reduced or prevented, thereby reducing image quality defects such as flicker.

[0120] Furthermore, as an example, in addition to N-type transistors such as the first switching transistor T1 and the fifth switching transistor T5, each of the P-type transistors DRT, T2 through T4, T6, and T7 can be formed by LTPS transistors. However, this disclosure is not limited thereto, and the N-type transistors and P-type transistors can have the same or different configurations.

[0121] A first scan signal SCAN1 is provided to the gate electrode of the first switching transistor T1. The drain electrode of the first switching transistor T1 is connected to the gate electrode of the driving transistor DRT. Furthermore, the source electrode of the first switching transistor T1 is connected to the source electrode of the driving transistor DRT. The drain and source electrodes of the switching transistors can vary according to the flow of current.

[0122] The first switching transistor T1 can be turned on by the first scan signal SCAN1 to control the operation of the driving transistor DRT using the high-potential driving voltage VDD stored in the storage capacitor Cst.

[0123] The first switching transistor T1 can be formed of an oxide transistor (especially an N-type metal-oxide-semiconductor (MOS) transistor), but is not limited to this. Since N-type MOS transistors use electrons instead of holes as charge carriers, they can have higher mobility than P-type MOS transistors, and thus have higher switching speeds.

[0124] A second scan signal SCAN2 is provided to the gate electrode of the second switching transistor T2. A data voltage Vdata can be provided to the source electrode of the second switching transistor T2. The drain electrode of the second switching transistor T2 is connected to the source electrode of the driving transistor DRT.

[0125] The second switching transistor T2 is turned on by the second scan signal SCAN2 to provide a data voltage Vdata to the source electrode of the driving transistor DRT.

[0126] A light emission signal EM is provided to the gate electrode of the third switching transistor T3. A high-potential drive voltage VDD is provided to the source electrode of the third switching transistor T3. The drain electrode of the third switching transistor T3 is connected to the source electrode of the driving transistor DRT.

[0127] The third switching transistor T3 is turned on by the light-emitting signal EM to provide a high-potential driving voltage VDD to the source electrode of the driving transistor DRT.

[0128] A light-emitting signal EM is provided to the gate electrode of the fourth switching transistor T4. The source electrode of the fourth switching transistor T4 is connected to the drain electrode of the driving transistor DRT. The drain electrode of the fourth switching transistor T4 is connected to the anode of the light-emitting element ED.

[0129] The fourth switching transistor T4 is turned on by the light-emitting signal EM to provide drive current to the anode of the light-emitting element ED.

[0130] The third scan signal SCAN3 is provided to the gate electrode of the fifth switching transistor T5.

[0131] Here, the third scan signal SCAN3 can be a signal with a different phase than the first scan signal SCAN1 provided to the sub-pixel SP at another location. For example, when the first scan signal SCAN1 is applied to the nth gating line, the third scan signal SCAN3 can be the first scan signal SCAN1[n-9] applied to the (n-9)th gating line, but is not limited thereto. As an example, the third scan signal SCAN3 can use the first scan signal SCAN1, the gating line GL of which varies according to the phase of the driving display panel 110.

[0132] An initialization voltage Vini is provided to the source electrode of the fifth switching transistor T5. The drain electrode of the fifth switching transistor T5 is connected to the gate electrode of the driving transistor DRT and the storage capacitor Cst.

[0133] The fifth switching transistor T5 is turned on by the third scan signal SCAN3 to provide the initialization voltage Vini to the gate electrode of the driving transistor DRT.

[0134] The fourth scan signal SCAN4 is provided to the gate electrode of the sixth switching transistor T6.

[0135] A reset voltage VAR is provided to the drain electrode of the sixth switching transistor T6. The source electrode of the sixth switching transistor T6 is connected to the anode of the light-emitting element ED.

[0136] The sixth switching transistor T6 and the seventh switching transistor T7 can be turned on by the fourth scan signal SCAN4.

[0137] The sixth switching transistor T6 provides a reset voltage VAR to the anode of the light-emitting element ED.

[0138] A bias voltage VOBS is provided to the source electrode of the seventh switching transistor T7. The drain electrode of the seventh switching transistor T7 is connected to the source electrode of the driving transistor DRT.

[0139] Furthermore, since the fourth scan signal SCAN4 is used to apply the bias voltage VOBS to the driving transistor DRT and the reset voltage VAR to the anode of the light-emitting element ED, the fourth scan signal SCAN4 can be distinguished from the second scan signal SCAN2 used to apply the data voltage Vdata.

[0140] The gate electrode of the driving transistor DRT is connected to the drain electrode of the first switching transistor T1. The source electrode of the driving transistor DRT is connected to the drain electrode of the second switching transistor T2. The drain electrode of the driving transistor DRT is connected to the source electrode of the first switching transistor T1.

[0141] The driving transistor DRT is turned on due to the voltage difference between the source and drain electrodes of the first switching transistor T1, thereby applying a driving current to the light-emitting element ED.

[0142] A high-potential drive voltage VDD is applied to one side of the storage capacitor Cst, and the other side of the storage capacitor Cst is connected to the gate electrode of the drive transistor DRT. The storage capacitor Cst stores the voltage on the gate electrode of the drive transistor DRT.

[0143] The anode of the light-emitting element ED is connected to the drain electrode of the fourth switching transistor T4 and the source electrode of the sixth switching transistor T6. A low-level drive voltage VSS is applied to the cathode of the light-emitting element ED.

[0144] The light-emitting element (ED) generates light with a predetermined luminous intensity by using a driving current flowing through it due to the driving transistor (DRT).

[0145] Here, an initialization voltage Vini is provided to stabilize the capacitance change generated in the gate electrode of the driving transistor DRT, while a reset voltage VAR is provided to reset the anode of the light-emitting element ED.

[0146] The anode of the light-emitting element ED can be reset when the reset voltage VAR is applied to the anode of the light-emitting element ED while the fourth switching transistor T4, which is to be controlled by the light-emitting signal EM, located between the anode of the light-emitting element ED and the driving transistor DRT, is turned off.

[0147] The sixth switching transistor T6, which provides the reset voltage VAR, is connected to the anode of the light-emitting element ED.

[0148] The third scan signal SCAN3, used to drive or stabilize the driving transistor DRT, is separated from the fourth scan signal SCAN4, used to control the supply of a reset voltage VAR to the anode of the light-emitting element ED. This allows the operation of driving the driving transistor DRT and resetting the anode of the light-emitting element ED to be performed separately.

[0149] In this configuration, the sub-pixel SP can be configured such that when the switching transistors T5 and T6, which provide the initialization voltage Vini and the reset voltage VAR respectively, are turned on, the fourth switching transistor T4, which connects the drain electrode of the driving transistor DRT and the anode of the light-emitting element ED, is turned off. This prevents the driving current of the driving transistor DRT from flowing to the anode of the light-emitting element ED and reduces or prevents other voltages besides the reset voltage VAR from affecting the anode.

[0150] The sub-pixel SP described above, comprising eight transistors DRT, T1, T2, T3, T4, T5, T6, and T7, and a single capacitor Cst, can be referred to as having an 8T1C structure. Implementations are not limited to this. As an example, the sub-pixel SP may include more or fewer transistors, or more or fewer capacitors. As an example, structures such as 2T1C, 3T1C, 5T1C, 5T2C, 9T1C, and 9T2C are also possible.

[0151] As described above, the 8T1C structure in various circuit structures of the sub-pixel SP has been shown, and the structure and number of transistors and capacitors in the sub-pixel SP can be varied. Each sub-pixel in a plurality of sub-pixel SPs can have the same structure, or at least one sub-pixel in a plurality of sub-pixel SPs can have a different structure.

[0152] According to the embodiment, the power management circuit 150 of the display device 100 can, under the control of the timing controller 140, provide a bias voltage VOBS corresponding to the grayscale of the image data provided during the refresh frame period to the source electrode of the driving transistor DRT.

[0153] For example, when the image data provided during the refresh frame period includes low grayscale levels, the display panel 110 displays an image with a grayscale level close to black. Therefore, even if the image has defects, the likelihood of a user visually identifying the defects is very low. Conversely, when the image data provided during the refresh frame period includes high grayscale levels, the display panel 110 displays an image with a grayscale level close to white. Therefore, even if the image has minor defects, the likelihood of a user visually identifying the minor defects is very high.

[0154] Considering this characteristic, the bias voltage VOBS can be set to a high level when the image data provided during the refresh frame period includes low gray levels, and set to a low level when the image data provided during the refresh frame period includes high gray levels, to reduce the visually perceptible image defects.

[0155] Figure 6 This is a diagram illustrating, according to an exemplary embodiment of the present disclosure, the division of image data provided during a refresh frame period into multiple gray levels and the setting of bias voltages differently according to the gray levels of the image data.

[0156] Reference Figure 6 In the display device 100 according to an exemplary embodiment, the bias voltage VOBS, which can reduce image defects, can have different levels depending on the grayscale of the image data.

[0157] In this case, the optimal level can be determined for the bias voltage VOBS applied during the bias period OBS, which causes few or minimal image defects based on the grayscale of the image data.

[0158] For example, when the image data provided during the refresh frame period is 9 grayscale G9, the bias voltage VOBS that can reduce or minimize image defects can be set to the grayscale range VOBS (G0-G9) from 0 grayscale G0 to 9 grayscale G9. When the image data provided during the refresh frame period is 18 grayscale G18, the bias voltage VOBS that can reduce or minimize image defects can be set to the grayscale range VOBS (G10-G18) from 10 grayscale G10 to 18 grayscale G18.

[0159] Furthermore, the bias voltage VOBS that reduces or minimizes image defects when the image data provided during the refresh frame period is 50 grayscale G50 can be set to a grayscale range VOBS (G19-G50) from 19 grayscale G19 to 50 grayscale G50. Similarly, the bias voltage VOBS that reduces or minimizes image defects when the image data provided during the refresh frame period is 144 grayscale G144 can be set to a grayscale range VOBS (G51-G144) from 51 grayscale G51 to 144 grayscale G144.

[0160] In addition, the bias voltage VOBS that can reduce or minimize image defects when the image data provided during the refresh frame period is 255 grayscale G255 can be set to the grayscale range VOBS (G145-G255) from 145 grayscale G145 to 255 grayscale G255.

[0161] As an example, the level of the bias voltage VOBS corresponding to the gray level of the image data is provided above, and the gray level of the image data used to determine the level of the bias voltage VOBS can be changed in various ways.

[0162] The grayscale of the image data can be determined based on the On-Pin Pixel Ratio (OPR), which indicates the ratio between luminous and non-luminous pixels of the display panel 110 in a specific frame. Although the OPR can be based on the entire time span of the display panel 110, the display panel 110 can be divided into any number of blocks, and the grayscale of a specific block can be determined based on the OPR within that block. The implementation is not limited to this. As an example, the grayscale of a specific block can be determined based on the QPR in other blocks, such as adjacent blocks. As another example, the overall grayscale of the display panel can be determined based on the QPR in at least one of the blocks of the display panel. As yet another example, the grayscale of the image data can be determined based on the QPR, which indicates the ratio between luminous and non-luminous pixels of the display panel 110 in specific multiple frames.

[0163] In this way, by dividing the grayscale of the image data input during the refresh frame period into multiple ranges, and determining the voltage that causes few or even minimal image defects according to the corresponding grayscale range as the optimal level, the use of bias voltage VOBS can precisely reduce image defects that are visually identifiable by the user.

[0164] Figure 7 This is a diagram illustrating the application of different bias voltages to different areas of the display panel in a display device according to an exemplary embodiment.

[0165] Reference Figure 7 In the display device 100 according to the embodiment, the display panel 110 can be divided into multiple blocks, and different levels of bias voltages VOBS1, VOBS2 and VOBS3 can be applied according to the grayscale of each block.

[0166] The method of dividing the display panel 110 into multiple blocks can be determined in various ways. Here, as an example, a case is shown where the display panel 110 is divided into a first block 1 at the top, a second block 2 in the center, and a third block 3 at the bottom. The implementation is not limited to this. As an example, the display panel 110 can be divided into blocks with the same or different areas, blocks with the same or different shapes, or blocks with regular or irregular shapes, but is not limited to this. As an example, the display panel 110 can be divided into blocks separated in the vertical direction, such that the edges of the blocks are parallel to the gate lines.

[0167] The grayscale of multiple blocks BLOCK1, BLOCK2, and BLOCK3 of the display panel 110 can be determined based on the OPR, which indicates the ratio between luminous and non-luminous pixels in the corresponding block of a specific frame.

[0168] For example, the first block BLOCK1 and the third block BLOCK3, which each contain a larger number of light-emitting pixels, can have a higher grayscale with higher brightness, while the second block BLOCK2, which contains a smaller number of light-emitting pixels, can have a lower grayscale with lower brightness.

[0169] In this case, the bias voltage VOBS2 applied to the second block 2 with low grayscale can be set to a level higher than the level of each of the bias voltages VOBS1 and VOBS3 applied to the first block 1 and the third block 3 with high grayscale.

[0170] Furthermore, when different bias voltages VOBS1, VOBS2, and VOBS3 are applied to blocks BLOCK1, BLOCK2, and BLOCK3 of the display panel 110, brightness deviations may occur between blocks BLOCK1, BLOCK2, and BLOCK3, resulting in a visually recognizable block darkening phenomenon at the boundaries between blocks.

[0171] In the display device 100 according to an exemplary embodiment of the present disclosure, when bias voltages of different levels are applied to multiple blocks of the display panel 110, block darkening between multiple blocks can be reduced by gradually changing the bias voltage at a rate lower than the reference slope during the boundary periods of the corresponding blocks. As an example, the boundary period can be at least one horizontal period. As an example, the boundary period can be less than 20 horizontal periods, less than 10 horizontal periods, less than 5 horizontal periods, or less than 3 horizontal periods.

[0172] Here, the reference slope of the bias voltage that changes during the boundary period between blocks can be determined by the grayscale difference between adjacent blocks.

[0173] For example, when the level difference between the first bias voltage VOBS1 applied to the first block 1 and the second bias voltage VOBS2 applied to the second block 2 is small (e.g., insignificant), there is an insignificant brightness difference in the boundary period. Therefore, the first slope Slope1 from the first bias voltage VOBS1 to the second bias voltage VOBS2 can have a relatively large value. As another example, for at least one boundary period, when the level difference between the first bias voltage VOBS1 applied to the first block 1 and the second bias voltage VOBS2 applied to the second block 2 is insignificant, the first bias voltage VOBS1 can be directly changed to the second bias voltage VOBS2 without a slope.

[0174] Conversely, when the level difference between the second bias voltage VOBS2 applied to the second block 2 and the third bias voltage VOBS3 applied to the third block 3 is significant, a significant brightness difference exists in the boundary period. Therefore, the value of the second slope Slope2, which changes from the second bias voltage VOBS2 to the third bias voltage VOBS3, can be less than the value of the first slope Slope1.

[0175] Furthermore, the display device 100 according to this disclosure can reduce image defects such as horizontal lines by applying different levels of bias voltage to multiple blocks of the display panel 110 and controlling the bias voltage differently in refresh frames and skip frames.

[0176] Figure 8 This is a diagram illustrating the signal waveform during a refresh frame period in a display device according to an exemplary embodiment.

[0177] Reference Figure 8 According to an exemplary embodiment, the display device 100 can perform conduction biasing processes OBS1 and OBS2 that apply bias voltages during the refresh frame period, thereby reducing flicker caused by brightness deviation between the refresh frame and the skip frame in the second mode Mode2, which operates at a low drive frequency. As an example, at least one of the conduction biasing processes OBS1 and OBS2 can be omitted during the refresh frame period.

[0178] The second mode, Mode 2, which operates at a low drive frequency, can be divided into refresh frames that display image data and skip frames that do not display image data.

[0179] In the refresh frame, the conduction bias processing OBS1 and OBS2 can be additionally performed, which not only apply the data voltage Vdata and initialization voltage Vini and reset voltage VAR for driving sub-pixel SP, but also apply the bias voltage VOBS to set the driving transistor DRT to the conduction bias state before the emission period.

[0180] In addition, during the refresh frame, sampling processing of the characteristic values ​​(e.g., threshold voltage or mobility) of the compensation drive transistor DRT can be performed.

[0181] When performing sampling, conduction biasing processes OBS1 and OBS2 can be performed during periods when sampling is not performed.

[0182] In this case, during the refresh frame, the first conduction bias process OBS1 can be performed with the fifth switching transistor T5 turned on and the first switching transistor T1 and the second switching transistor T2 turned off.

[0183] In other words, when the fifth switching transistor T5 is turned on and the initialization voltage Vini is applied to the gate electrode of the driving transistor DRT, the bias voltage VOBS can be provided to the source electrode of the driving transistor DRT during the first conduction biasing process OBS1 in the refresh frame. In this case, when the driving transistor DRT is turned on by the charge in the storage capacitor Cst, the bias voltage VOBS can be provided to both the source and drain electrodes of the driving transistor DRT.

[0184] Thus, when the first conduction biasing process OBS1 is performed during the period when the initialization voltage Vini is applied, the voltages on the gate and drain electrodes of the driving transistor DRT can remain constant. Therefore, when the first conduction biasing process OBS1 is performed during the period when the initialization voltage Vini is applied, the bias voltage VOBS can be effectively maintained at a fixed level even if the grayscale of the image data applied to the display panel 110 changes or differs depending on the region.

[0185] In other words, during the period when the initialization voltage Vini is applied to the gate electrode of the driving transistor DRT in the refresh frame, the bias voltage can be kept constant.

[0186] As a result, in the refresh frame of Mode 2, which operates at a low drive frequency, the hysteresis of the drive transistor DRT can be reduced, and the brightness of the light-emitting element ED can be reduced less.

[0187] In addition, the second conduction biasing process OBS2 in the refresh frame can be performed when the fifth switching transistor T5, the first switching transistor T1, and the second switching transistor T2 are all turned off.

[0188] Figure 9 This is a diagram illustrating the signal waveform during a skip frame period in a display device according to an exemplary embodiment.

[0189] Reference Figure 9 In the display device 100 according to an exemplary embodiment, after a refresh frame, a skip frame can be performed, wherein the image is not transmitted to the display panel 110 and the voltage stored in the storage capacitor Cst is maintained.

[0190] In this case, in the display device 100, the bias voltage VOBS that can reduce hysteresis in skipped frames can be applied to the drain or source electrode of the driving transistor DRT once or more.

[0191] Here, the case where the third conduction bias process OBS3 and the fourth conduction bias process OBS4 are performed in a skipped frame is shown. As an example, at least one of the third conduction bias process OBS3 and the fourth conduction bias process OBS4 can be omitted in the skipped frame.

[0192] In this case, during the skip frame, the third conduction bias process OBS3 and / or the fourth conduction bias process OBS4 can be performed during the period when the initialization voltage Vini is not applied to the gate electrode of the drive transistor DRT.

[0193] In this way, the voltages on the gate and drain electrodes of the driving transistor DRT can be changed during the period when the initialization voltage Vini is not applied to the gate electrode of the driving transistor DRT. In this case, the bias voltage can vary with the grayscale of the image data provided to the display panel 110, or according to the grayscale difference between areas of the display panel 110.

[0194] Figure 10 This diagram illustrates how the bias voltage applied in a refresh frame and the bias voltage applied in a skip frame are controlled differently in a display device according to an exemplary embodiment.

[0195] Reference Figure 10 According to an exemplary embodiment, the display device 100 can perform conduction biasing processes OBS1 and OBS2 that apply bias voltage VOBS1 during the refresh frame period to reduce flicker caused by brightness deviation in the second mode Mode2, which operates at a low drive frequency.

[0196] In this case, during the period when the initialization voltage Vini is applied to the gate electrode of the drive transistor DRT in the refresh frame, the first bias voltage VOBS1 can be kept constant.

[0197] Here, the initialization voltage Vini can be applied during the first conduction bias processing OBS1 period, and the initialization voltage Vini can be applied during the second conduction bias processing OBS2 period.

[0198] For example, when the initialization voltage Vini is applied during the first conduction bias processing OBS1 period, the voltages on the gate and drain electrodes of the driving transistor DRT can remain constant. Therefore, when the initialization voltage Vini is applied during the first conduction bias processing OBS1 period, even if the grayscale of the image data applied to the display panel 110 changes or differs depending on the blocks of the display panel 110, the first bias voltage VOBS1 can be effectively maintained at a fixed level.

[0199] Furthermore, when the initialization voltage Vini is also applied during the second conduction bias processing OBS2 period, the same bias level as the first bias voltage VOBS1 applied during the first conduction bias processing OBS1 period can be effectively maintained during the second conduction bias processing OBS2 period.

[0200] Here, during the refresh frame, a bias voltage VOBS1 with the same level can be applied according to the time period of the conduction bias processing of OBS1 and OBS2. Furthermore, even when the individual blocks in the multiple blocks of the display panel 110 have different grayscale values, a bias voltage VOBS1 with the same level can still be applied.

[0201] Furthermore, the third conduction bias process OBS3 and the fourth conduction bias process OBS4 can be performed in the skip frame. In this case, the initialization voltage Vini can be omitted from the gate electrode of the drive transistor DRT during the periods of the third conduction bias process OBS3 and the fourth conduction bias process OBS4.

[0202] In this way, during skip frames where the initialization voltage Vini is not applied to the gate electrode of the driving transistor DRT, the voltages on the gate and drain electrodes of the driving transistor DRT can be changed. Therefore, different bias voltages VOBS2 and VOBS3 can be applied during the third conduction bias process OBS3 and the fourth conduction bias process OBS4.

[0203] Furthermore, during the skip frame, bias voltages VOBS2 and VOBS3 with different levels can be applied according to the time period of the conduction bias processing of OBS3 and OBS4, and the bias voltages VOBS2 and VOBS3 can be applied by reflecting the grayscale of each of the multiple blocks in the display panel 110.

[0204] Figure 11 This is a diagram illustrating another sub-pixel circuit of a display device according to an exemplary embodiment.

[0205] Reference Figure 11 According to an exemplary embodiment, the sub-pixel SP of the display device 100 includes a first switching transistor T1 to a sixth switching transistor T6, a driving transistor DRT, a storage capacitor Cst, and a light-emitting element ED.

[0206] Here, the light-emitting element ED can be a self-emissive element capable of emitting its own light, such as OLED or LED.

[0207] In the sub-pixel SP according to an exemplary embodiment, the second switching transistors T2 to T4, the sixth switching transistor T6, and the driving transistor DRT can be P-type transistors, while the first switching transistor T1 and the fifth switching transistor T5 can be N-type transistors, but are not limited thereto. As an example, any one of the transistors can be either a P-type transistor or an N-type transistor.

[0208] P-type transistors are more reliable than N-type transistors. When the driving transistor DRT is formed from a P-type transistor, since the drain electrode is fixed at a high driving voltage VDD, the current flowing through the light-emitting element ED does not fluctuate due to the capacitor CST. Therefore, current can be supplied reliably and easily.

[0209] For example, a P-type transistor can be connected to the anode of a light-emitting element (ED). Here, because a predetermined amount of current can flow regardless of changes in the threshold voltage and current of the ED, the reliability is high when transistors T4 and T6 connected to the ED operate in the saturation region.

[0210] In this structure of the sub-pixel SP, each of the N-type transistors T1 and T5 can be formed by an oxide transistor (e.g., a transistor having a channel formed by a semiconductor oxide such as In, Ga, or Zn oxide or IGZO) using a semiconductor oxide, while each of the P-type transistors DRT, T2 to T4 and T6 can be formed by a Si transistor (e.g., a transistor called an LTPS transistor having a polycrystalline silicon channel formed using a low-temperature process) using a transistor material such as Si.

[0211] Oxide transistors are characterized by lower leakage current than silicon transistors. Therefore, when transistors are formed from oxide transistors, leakage current from the gate electrode of the driving transistor DRT can be prevented, thereby reducing image quality defects such as flicker.

[0212] Furthermore, in addition to N-type transistors such as the first switching transistor T1 and the fifth switching transistor T5, each of the P-type transistors DRT, T2 through T4, and T6 can be formed by LTPS transistors. However, this disclosure is not limited thereto, and the N-type transistors and P-type transistors can have the same or different configurations.

[0213] A first scan signal SCAN1 is provided to the gate electrode of the first switching transistor T1. The drain electrode of the first switching transistor T1 is connected to the gate electrode of the driving transistor DRT. Furthermore, the source electrode of the first switching transistor T1 is connected to the source electrode of the driving transistor DRT. The drain and source electrodes of the switching transistors can vary according to the flow of current.

[0214] The source electrode of the first switching transistor T1 is connected to the drain electrode of the driving transistor DRT.

[0215] The first switching transistor T1 can be turned on by the first scan signal SCAN1 to control the operation of the driving transistor DRT using the voltage stored in the storage capacitor Cst, such as the high-potential drive voltage VDD.

[0216] The first switching transistor T1 can be formed from an oxide transistor (especially an N-type MOS transistor), but is not limited to this. Since N-type MOS transistors use electrons instead of holes as charge carriers, they can have higher mobility than P-type MOS transistors, and thus have higher switching speeds.

[0217] A second scan signal SCAN2 is provided to the gate electrode of the second switching transistor T2. A data voltage Vdata or a bias voltage VOBS can be provided to the source electrode of the second switching transistor T2. The drain electrode of the second switching transistor T2 is connected to the source electrode of the driving transistor DRT.

[0218] The second switching transistor T2 is turned on by the second scan signal SCAN2 to provide a data voltage Vdata or a bias voltage VOBS to the source electrode of the driving transistor DRT.

[0219] A light emission signal EM is provided to the gate electrode of the third switching transistor T3. A high-potential drive voltage VDD is provided to the source electrode of the third switching transistor T3. The drain electrode of the third switching transistor T3 is connected to the source electrode of the driving transistor DRT.

[0220] The third switching transistor T3 is turned on by the light-emitting signal EM to provide a high-potential driving voltage VDD to the source electrode of the driving transistor DRT.

[0221] A light-emitting signal EM is provided to the gate electrode of the fourth switching transistor T4. The source electrode of the fourth switching transistor T4 is connected to the drain electrode of the driving transistor DRT. The drain electrode of the fourth switching transistor T4 is connected to the anode of the light-emitting element ED.

[0222] The fourth switching transistor T4 is turned on by the light-emitting signal EM to provide drive current to the anode of the light-emitting element ED.

[0223] The third scan signal SCAN3 is provided to the gate electrode of the fifth switching transistor T5.

[0224] Here, the third scan signal SCAN3 can be a signal with a different phase from the first scan signal SCAN1 provided to the sub-pixel SP at another location. For example, when the first scan signal SCAN1 is applied to the nth gating line, the third scan signal SCAN3 can be the first scan signal SCAN1[n-9] applied to the (n-9)th gating line, but is not limited thereto. As an example, the third scan signal SCAN3 can use the first scan signal SCAN1, the gating line GL of which varies according to the phase of driving the display panel 110.

[0225] An initialization voltage Vini is provided to the source electrode of the fifth switching transistor T5. The drain electrode of the fifth switching transistor T5 is connected to the gate electrode of the driving transistor DRT and the storage capacitor Cst.

[0226] The fifth switching transistor T5 is turned on by the third scan signal SCAN3 to provide the initialization voltage Vini to the gate electrode of the driving transistor DRT.

[0227] The second scan signal SCAN2 is provided to the gate electrode of the sixth switching transistor T6 together with the second switching transistor T2.

[0228] A reset voltage VAR is provided to the drain electrode of the sixth switching transistor T6. The source electrode of the sixth switching transistor T6 is connected to the anode of the light-emitting element ED.

[0229] The sixth switching transistor T6 is turned on by the second scan signal SCAN2 to provide a reset voltage VAR to the anode of the light-emitting element ED.

[0230] The gate electrode of the driving transistor DRT is connected to the drain electrode of the first switching transistor T1. The source electrode of the driving transistor DRT is connected to the drain electrode of the second switching transistor T2. The drain electrode of the driving transistor DRT is connected to the source electrode of the first switching transistor T1.

[0231] The driving transistor DRT is turned on due to the voltage difference between the source and drain electrodes of the first switching transistor T1, thereby applying a driving current to the light-emitting element ED.

[0232] A high-potential drive voltage VDD is applied to one side of the storage capacitor Cst, and the other side of the storage capacitor Cst is connected to the gate electrode of the drive transistor DRT. The storage capacitor Cst stores the voltage on the gate electrode of the drive transistor DRT.

[0233] The anode of the light-emitting element ED is connected to the drain electrode of the fourth switching transistor T4 and the source electrode of the sixth switching transistor T6. A low-level drive voltage VSS is applied to the cathode of the light-emitting element ED.

[0234] The light-emitting element (ED) generates light with a predetermined luminous intensity by using a driving current flowing through it due to the driving transistor (DRT).

[0235] Here, an initialization voltage Vini is provided to stabilize the capacitance change generated in the gate electrode of the driving transistor DRT, while a reset voltage VAR is provided to reset the anode of the light-emitting element ED.

[0236] The anode of the light-emitting element ED can be reset when the reset voltage VAR is applied to the anode of the light-emitting element ED while the fourth switching transistor T4, which is to be controlled by the light-emitting signal EM, located between the anode of the light-emitting element ED and the driving transistor DRT, is turned off.

[0237] The sixth switching transistor T6, which provides the reset voltage VAR, is connected to the anode of the light-emitting element ED.

[0238] As an example, the third scan signal SCAN3, used to drive or initialize the driving transistor DRT, is separated from the second scan signal SCAN2, used to control the supply of a reset voltage VAR to the anode of the light-emitting element ED, so that the operation of driving the driving transistor DRT and the operation of resetting the anode of the light-emitting element ED can be performed separately.

[0239] In this configuration, the sub-pixel SP can be configured to turn off the fourth switching transistor T4, which connects the drain electrode of the driving transistor DRT and the anode of the light-emitting element ED, when the switching transistors T5 and T6, which provide the initialization voltage Vini and the reset voltage VAR, are turned on. This prevents the driving current of the driving transistor DRT from flowing to the anode of the light-emitting element ED and reduces or prevents other voltages besides the reset voltage VAR from affecting the anode.

[0240] As described above, a sub-pixel SP comprising seven transistors DRT, T1, T2, T3, T4, T5, and T6, and a single capacitor Cst, can be referred to as having a 7T1C structure.

[0241] As described above, the 7T1C structure in various circuit structures of the sub-pixel SP has been shown, and the structure and number of transistors and capacitors in the sub-pixel SP can be changed in various ways. Each sub-pixel in a plurality of sub-pixel SPs can have the same structure, or some sub-pixels in a plurality of sub-pixel SPs can have different structures.

[0242] Figure 12 This is a flowchart illustrating a display driving method according to an exemplary embodiment.

[0243] Reference Figure 12 A display driving method according to an exemplary embodiment may include: step S100: converting a first mode with a high-speed driving frequency to a second mode with a low-speed driving frequency; step S200: detecting the grayscale of each block of the display panel 110; step S300: determining the level of a bias voltage VOBS corresponding to the grayscale of each block; step S400: controlling the bias voltage applied to the driving transistor DRT according to each block of the display panel 110; step S500: applying a bias voltage with the same level during a refresh frame; step S600: applying a bias voltage VOBS with multiple levels corresponding to the grayscale of each block during a skip frame; and step S700: gradually changing the bias voltage VOBS with multiple levels below a reference slope.

[0244] Step S100, which converts the first mode with a high-speed drive frequency to the second mode with a low-speed drive frequency, is, for example, a process of converting from a first mode Mode 1, which displays video images at a high-speed first frequency, to a second mode Mode 2, which displays still images or low-speed images at a low-speed second frequency.

[0245] Step S200, which detects the grayscale of each block of the display panel 110, is a process of dividing the display panel 110 into multiple blocks (or regions) and determining the grayscale based on the on-pixel ratio (OPR), which indicates the ratio between luminous pixels and non-luminous pixels in each block.

[0246] Step S300, which determines the level of the bias voltage VOBS corresponding to the grayscale of each block, is a process of determining the level of the bias voltage VOBS that can reduce or minimize image defects for each block's grayscale determined based on the OPR. For example, the bias voltage VOBS can be set to a higher level for blocks with lower grayscale, while the bias voltage VOBS can be set to a lower level for blocks with higher grayscale.

[0247] Step S400, which controls the bias voltage applied to the driving transistor DRT according to each block of the display panel 110, is a process of applying a bias voltage VOBS having a level determined according to the grayscale of each block to the driving transistor DRT. VOBS with the same bias voltage can be applied to blocks with the same or similar grayscale, while bias voltage VOBS with different levels can be applied to blocks with different grayscale.

[0248] Step S500, which applies a bias voltage of the same level during a refresh frame, is a process of maintaining a constant bias voltage VOBS at a single fixed level during a refresh frame in which image data is provided to the display panel 110.

[0249] During frame refresh, the grayscale of the image data can change according to the frame, or the bias voltage VOBS can be maintained at a single fixed level even if the blocks of the display panel 110 have different grayscale values.

[0250] Specifically, during the refresh frame, when the on-bias process OBS is performed during the period when the initialization voltage Vini is applied, the voltages on the gate and drain electrodes of the driving transistor DRT can be kept constant, thereby keeping the bias voltage VOBS at a single level.

[0251] Step S600, which applies a bias voltage VOBS with multiple levels corresponding to the grayscale of each block during a skip frame, is a process of changing the bias voltage VOBS according to the grayscale of the image data during a skip frame when the image data is not transmitted to the display panel 110 and the voltage stored in the storage capacitor Cst is maintained.

[0252] In this case, the bias voltage VOBS can be determined based on the grayscale of the image data that varies in each frame, or based on the grayscale of each block of the display panel 110.

[0253] Step S700, which gradually changes the bias voltage VOBS with multiple levels to a slope below the reference slope, is a process of controlling the bias voltage to gradually change to a slope below the reference slope when the first level bias voltage is converted to the second level bias voltage in a skip frame.

[0254] When the bias voltage gradually changes below the reference slope as described above, the block darkening phenomenon caused by brightness differences between blocks can be reduced.

[0255] Furthermore, the steps S500 (applying a bias voltage with the same level during refresh frames), S600 (applying a bias voltage VOBS with multiple levels corresponding to the grayscale of each block during skip frames), and S700 (gradually changing the bias voltage VOBS with multiple levels to a slope below the reference slope) can be omitted or selectively used depending on the display device 100.

[0256] The above embodiments of this disclosure will be briefly summarized below.

[0257] The display device 100 according to the embodiment may include: a display panel 110 having a light-emitting element ED, a driving transistor DRT that provides driving current to the light-emitting element using a driving voltage, and a plurality of switching transistors that control the driving of the driving transistor DRT; a gating driving circuit 120 that provides a plurality of scanning signals to the display panel 110 through a plurality of gating lines GL; a light-emitting driving circuit 122 that provides a plurality of light-emitting signals EM to the display panel 110 through a plurality of light-emitting signal lines EL; a data driving circuit 130 that provides a data voltage to the display panel 110; and a timing controller that divides the display panel 110 into a plurality of blocks and, in a low-speed mode operating at a low-speed driving frequency, controls the level of the bias voltage VOBS applied to the driving transistor DRT of the corresponding block according to the grayscale of the data voltage provided to the corresponding block among the plurality of blocks.

[0258] The low-speed mode may include: a refresh frame period in which the data voltage used to drive the light-emitting element ED is applied to the display panel 110; and a skip frame period in which the data voltage is not applied to the display panel 110 and the voltage stored in the storage capacitor is maintained.

[0259] The plurality of switching transistors may include: a first switching transistor T1, having a gate electrode to which a first scan signal SCAN1 is applied, a drain electrode connected to the gate electrode of a driving transistor DRT and a storage capacitor Cst, and a source electrode connected to the drain electrode of the driving transistor DRT; a second switching transistor T2, having a gate electrode to which a second scan signal SCAN2 is applied, a source electrode to which a data voltage or bias voltage VOBS is applied, and a drain electrode connected to the source electrode of the driving transistor DRT; and a third switching transistor T3, having a gate electrode to which a light emission signal EM is applied, a source electrode to which a driving voltage is applied, and a source electrode connected to the driving transistor Cst. The source electrode and drain electrode of the DRT transistor; the fourth switching transistor T4, which has a gate electrode to which a light emission signal EM is applied, a source electrode connected to the drain electrode of the driving transistor DRT, and a drain electrode connected to the anode of the light emission element ED; the fifth switching transistor T5, which has a gate electrode to which a third scan signal SCAN3 is applied, a drain electrode to which an initialization voltage Vini is provided, and a source electrode connected to the gate electrode of the driving transistor DRT; and the sixth switching transistor T6, which has a gate electrode to which a second scan signal SCAN2 is applied, a source electrode to which a reset voltage VAR is provided, and a drain electrode connected to the anode of the light emission element ED.

[0260] The plurality of switching transistors may include: a first switching transistor T1, having a gate electrode to which a first scan signal SCAN1 is applied, a drain electrode connected to the gate electrode of a driving transistor DRT and a storage capacitor Cst, and a source electrode connected to the drain electrode of the driving transistor DRT; a second switching transistor T2, having a gate electrode to which a second scan signal SCAN2 is applied, a source electrode to which a data voltage is applied, and a drain electrode connected to the source electrode of the driving transistor DRT; a third switching transistor T3, having a gate electrode to which a light emission signal EM is applied, a source electrode to which a driving voltage is applied, and a drain electrode connected to the source electrode of the driving transistor DRT; and a fourth switching transistor T4, having a gate electrode to which a light emission signal EM is applied. The first switching transistor T5 has a gate electrode to which a third scan signal SCAN3 is applied, a drain electrode to which an initialization voltage Vini is provided, and a source electrode to which the gate electrode of the driving transistor DRT is connected; the second switching transistor T6 has a gate electrode to which a fourth scan signal SCAN4 is applied, a source electrode to which a reset voltage VAR is provided, and a drain electrode to which the anode of the light-emitting element ED is connected; and the third switching transistor T7 has a gate electrode to which a fourth scan signal SCAN4 is applied, a source electrode to which a bias voltage VOBS is provided, and a drain electrode to which the source electrode of the driving transistor DRT is connected.

[0261] The level of the bias voltage VOBS can be determined based on the conduction pixel ratio of the corresponding block.

[0262] During the boundary periods of multiple blocks, the level of the bias voltage VOBS can be gradually changed below the reference slope.

[0263] The reference slope may include: a first slope Slope1, which is applied when the grayscale difference between adjacent blocks in a plurality of blocks is equal to or less than a reference value; and a second slope Slope2, which is applied when the grayscale difference between adjacent blocks in a plurality of blocks is greater than a reference value, wherein the second slope Slope2 may be less than the first slope Slope1.

[0264] An initialization voltage, Vini, can be applied during the refresh frame period, and a bias voltage, VOBS, can be applied during either the refresh frame period or the skip frame period.

[0265] A bias voltage with the same level can be applied during refresh frames, while multiple bias voltages with gray levels corresponding to the data voltage can be applied during skip frames.

[0266] A bias voltage of the same level can be applied during the period when the initialization voltage Vini is applied.

[0267] According to an embodiment, a display driving method for driving a display panel 110 is also provided. The display panel 110 includes a light-emitting element (ED), a driving transistor (DRT) that provides driving current to the light-emitting element ED using a driving voltage, and a plurality of switching transistors that control the driving of the driving transistor DRT. The display driving method may include: step S100, converting a first mode with a high-speed driving frequency to a second mode with a low-speed driving frequency; step S200, detecting the grayscale of each block of the display panel 110; step S300, determining the level of the bias voltage VOBS corresponding to the grayscale of each block; and step S400, controlling the level of the bias voltage applied to the driving transistor DRT according to each block of the display panel 110.

[0268] The display driving method may further include: step S500, applying a bias voltage of the same level during a refresh frame period when a data voltage for driving the light-emitting element ED is applied to the display panel 110; and step S600, applying a bias voltage of multiple levels corresponding to the grayscale of each block during a skip frame period when no data voltage is applied to the display panel 110 and the voltage stored in the storage capacitor Cst is maintained.

[0269] During the refresh frame period, an initialization voltage Vini can be applied to stabilize the capacitance changes that occur on the gate electrode of the drive transistor DRT.

[0270] A bias voltage of the same level can be applied during the period when the initialization voltage Vini is applied.

[0271] The bias voltage with multiple levels can be gradually changed below the reference slope.

[0272] The above description has been presented to enable any person skilled in the art to implement and use the technical concepts of the present invention, and has been provided in the context of a particular application and its requirements. Various modifications, additions, and substitutions to the described embodiments will be apparent to those skilled in the art, and the general principles defined herein can be applied to other embodiments and applications without departing from the spirit and scope of the invention. The above description and drawings are provided for illustrative purposes only, illustrating examples of the technical concepts of the invention. That is, the disclosed embodiments are intended to illustrate the scope of the technical concepts of the invention.

[0273] Cross-reference to related applications

[0274] This application claims priority to Korean Patent Application No. 10-2022-0091665, filed on July 25, 2022, which is incorporated herein by reference for all purposes as fully set forth herein.

Claims

1. A display device, the display device comprising: The display panel is composed of multiple blocks, and light-emitting elements, driving transistors that provide driving current to the light-emitting elements using driving voltage, and multiple switching transistors that control the driving operation of the driving transistors are disposed on the display panel. A gating drive circuit is configured to provide multiple scan signals to the display panel through multiple gating lines; A data driving circuit configured to provide a data voltage to the display panel; as well as A timing controller configured to control, in a low-speed mode operating at a low-speed drive frequency, the level of a bias voltage of the source electrode of the drive transistor of the corresponding block, based on the grayscale of the data voltage supplied to the corresponding block among the plurality of blocks.

2. The display device according to claim 1, wherein, The low-speed mode includes: During a refresh frame period, the data voltage used to drive the light-emitting element is applied to the display panel; and During a skip frame period, the data voltage is not applied to the display panel and the voltage stored in the storage capacitor is maintained. The storage capacitor is connected to the gate electrode of the driving transistor.

3. The display device according to claim 1, wherein, The level of the bias voltage is determined based on the ratio of the conducting pixels of the corresponding block.

4. The display device according to claim 3, wherein, The conduction pixel ratio indicates the ratio between the luminous pixels and non-luminous pixels of the corresponding block in the corresponding frame.

5. The display device according to claim 4, wherein, During the skip frame period, the bias voltage is set to a higher level for blocks with a lower on-pixel ratio and a lower level for blocks with a higher on-pixel ratio.

6. The display device according to claim 1, wherein, During at least one boundary period of the plurality of blocks, the level of the bias voltage gradually changes at a slope lower than the reference slope.

7. The display device according to claim 6, wherein, The reference slope includes: A first slope is applied when the grayscale difference between adjacent blocks in the plurality of blocks is equal to or less than a reference value; and The second slope is applied when the grayscale difference between adjacent blocks in the plurality of blocks is greater than the reference value. Wherein, the second slope is less than the first slope.

8. The display device according to claim 7, wherein, During at least one boundary period of the plurality of blocks, the level of the bias voltage changes directly.

9. The display device according to claim 6, wherein, The boundary time period is at least one horizontal time period.

10. The display device according to claim 2, wherein, The plurality of switching transistors include: A first switching transistor has a gate electrode to which a first scan signal is applied, a drain electrode connected to the gate electrode of the driving transistor, and a source electrode connected to the drain electrode of the driving transistor. A second switching transistor or a seventh switching transistor, wherein the second switching transistor has a gate electrode to which a second scan signal is applied, a source electrode to which the data voltage is applied, and a drain electrode connected to the source electrode of the driving transistor; and the seventh switching transistor has a gate electrode to which a fourth scan signal is applied, a source electrode to which the bias voltage is applied, and a drain electrode connected to the source electrode of the driving transistor; and The fifth switching transistor has a gate electrode to which a third scan signal is applied, a drain electrode to which an initialization voltage is provided, and a source electrode connected to the gate electrode of the driving transistor.

11. The display device according to claim 10, wherein, The initialization voltage is applied during the refresh frame period, and the bias voltage is applied during the refresh frame period or the skip frame period.

12. The display device according to claim 11, wherein, During the refresh frame period, the bias voltage with the same level is applied to each block, and during the skip frame period, the bias voltage with multiple levels of grayscale corresponding to the data voltage is applied to each block.

13. The display device according to claim 12, wherein, The bias voltage with the same level is applied during the period in which the initialization voltage is applied.

14. The display device according to claim 10, wherein, The plurality of switching transistors also include: The third switching transistor has a gate electrode to which a light emission signal is applied, a source electrode to which the driving voltage is applied, and a drain electrode connected to the source electrode of the driving transistor. A fourth switching transistor, the fourth switching transistor having a gate electrode to which the light-emitting signal is applied, a source electrode connected to the drain electrode of the driving transistor, and a drain electrode connected to the anode of the light-emitting element; and A sixth switching transistor having a gate electrode to which the second scan signal is applied, a source electrode to which a reset voltage is provided, and a drain electrode connected to the anode of the light-emitting element.

15. The display device according to claim 1, wherein, The plurality of blocks are divided such that the edge of each of the plurality of blocks is parallel to the gate line.

16. A display driving method, the display driving method driving a display panel composed of multiple blocks, wherein light-emitting elements, driving transistors that provide driving current to the light-emitting elements using a driving voltage, and multiple switching transistors that control the driving of the driving transistors are disposed on the display panel, the display driving method comprising the following steps: The first mode with high-speed drive frequency is converted into the second mode with low-speed drive frequency. Detect the grayscale of each block of the display panel; Determine the level of the bias voltage corresponding to the grayscale of each block, the bias voltage being configured to be applied to the source electrode of the driving transistor; as well as The level of the bias voltage is controlled according to each block of the display panel.

17. The display driving method according to claim 16, further comprising the following steps: During the refresh frame period when the data voltage used to drive the light-emitting element is applied to the display panel, the bias voltage with the same level is applied to each block; as well as During a skip frame period when the data voltage is not applied to the display panel and the voltage stored in the storage capacitor is maintained, a bias voltage with multiple levels corresponding to the grayscale of each block is applied, the storage capacitor being connected to the gate electrode of the driving transistor.

18. The display driving method according to claim 17, wherein, During the refresh frame period, an initialization voltage is applied to stabilize the capacitance changes that occur on the gate electrode of the driving transistor.

19. The display driving method according to claim 18, wherein, During the period in which the initialization voltage is applied, the bias voltage with the same level is applied to each block.

20. The display driving method according to claim 17, wherein, The bias voltage, having the multiple levels, gradually changes below a reference slope.

21. The display driving method according to claim 17, wherein, The level of the bias voltage is determined based on the conduction pixel ratio of the corresponding block, and The conduction pixel ratio indicates the ratio between the luminous pixels and non-luminous pixels of the corresponding block in the corresponding frame.

22. The display driving method according to claim 21, wherein, During the skip frame period, the bias voltage is set to a higher level for blocks with a lower on-pixel ratio and a lower level for blocks with a higher on-pixel ratio.

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