Pixel circuit, driving method thereof and display panel

Abstract

The application discloses a pixel circuit, a driving method thereof and a display panel. The pixel circuit comprises a driving module, a light-emitting module, a first initialization module, a data writing module and a biasing module. The data writing module is electrically connected with a first end of the driving module, and is used for transmitting a data voltage to the driving module in a data writing stage of a writing frame. The driving module is used for generating a driving current according to a voltage of a control end thereof, and the light-emitting module is used for emitting light in response to the driving current. The first initialization module is used for transmitting a first initialization voltage to the control end of the driving module in a first initialization stage of the writing frame. The biasing module is used for generating a reset voltage according to the first initialization voltage and the data voltage, and transmitting the reset voltage to the first end of the driving module in a biasing stage before a light-emitting stage of a holding frame. The application can improve the flickering problem.

Description

Technical Field

[0001] This invention relates to the field of display technology, and in particular to a pixel circuit and its driving method, and a display panel. Background Technology

[0002] With the development of display technology, display panels are being used more and more widely, and the requirements for display panels are becoming increasingly higher.

[0003] The display panel contains multiple pixel circuits, and the display function is achieved by the light emitted by the pixel circuits. However, in related technologies, the display panel may flicker at low frequencies or during frequency switching, which seriously affects the display effect. Summary of the Invention

[0004] This invention provides a pixel circuit and its driving method, as well as a display panel, to improve the flickering problem.

[0005] According to one aspect of the present invention, a pixel circuit is provided, the pixel circuit comprising: a driving module, a light-emitting module, a first initialization module, a data writing module, and a bias module;

[0006] The data writing module is electrically connected to the first terminal of the driver module, and the data writing module is used to transmit data voltage to the driver module during the data writing phase of the write frame.

[0007] The driving module is used to generate a driving current according to the voltage at its control terminal, and the light-emitting module is used to emit light in response to the driving current;

[0008] The first initialization module is used to transmit the first initialization voltage to the control terminal of the drive module during the first initialization phase of the write frame;

[0009] The bias module is used to generate a reset voltage based on the first initialization voltage and the data voltage, and transmit the reset voltage to the first end of the driving module during the bias phase before the light emission phase in the holding frame.

[0010] Optionally, the bias module is used to subtract the first initialization voltage from the data voltage to obtain the reset voltage.

[0011] Optionally, the duration of the bias phase is the same as the duration of the first initialization phase;

[0012] Preferably, the output terminal of the bias module is electrically connected to the first terminal of the drive module.

[0013] Optionally, the bias module is electrically connected to the first end of the data writing module, and the second end of the data writing module is electrically connected to the first end of the driving module. The bias module is used to transmit the reset voltage to the first end of the data writing module during the bias phase. During the holding frame, the bias phase coincides with the data writing phase.

[0014] Optionally, the pixel circuit further includes a threshold compensation module. A first terminal of the threshold compensation module is electrically connected to a second terminal of the driving module, and the second terminal of the threshold compensation module is electrically connected to a control terminal of the driving module. The control terminal of the threshold compensation module is connected to a first scan signal, and the control terminal of the data writing module is connected to a second scan signal. The first scan signal is configured to be at an on level during the data writing phase of the write frame and at an off level during the hold frame. The second scan signal is configured to be at an on level during both the data writing phase of the write frame and the data writing phase of the hold frame. The bias module is configured to generate the reset voltage when the first scan signal is at an off level and the second scan signal is at an on level.

[0015] Optionally, the bias module includes a voltage calculation unit and a voltage enable unit; the voltage enable unit is electrically connected to the voltage calculation unit, and the voltage enable unit is configured to enable the voltage calculation unit when the first scan signal is at a shutdown level and the second scan signal is at a conduction level; the voltage calculation unit is configured to generate the reset voltage based on the data voltage and the first initialization voltage when enabled.

[0016] Preferably, the threshold compensation module and the data writing module have different transistor types, while the threshold compensation module and the first initialization module have the same transistor type.

[0017] Preferably, the first terminal of the first initialization module is connected to the first initialization voltage, the second terminal of the first initialization module is electrically connected to the control terminal of the drive module, and the control terminal of the first initialization module is connected to the third scan signal;

[0018] Optionally, the pixel circuit further includes a storage module, a first light-emitting control module, and a second light-emitting control module. A first terminal of the first light-emitting control module is connected to a first power signal, and a second terminal of the first light-emitting control module is electrically connected to a first terminal of the driving module. An enable signal is connected to the control terminal of the first light-emitting control module. A first terminal of the second light-emitting control module is electrically connected to a second terminal of the driving module, and a second terminal of the second light-emitting control module is electrically connected to a first terminal of the light-emitting module. The enable signal is connected to the control terminal of the second light-emitting module, and a second power signal is connected to the second terminal of the light-emitting module. A first terminal of the storage module is electrically connected to a first terminal of the first light-emitting control module, and a second terminal of the storage module is electrically connected to the control terminal of the driving module.

[0019] Preferably, the pixel circuit further includes a second initialization module, the first end of the second initialization module is connected to a second initialization voltage, the second end of the second initialization module is electrically connected to the first end of the light-emitting module, and the control end of the second initialization module is connected to a fourth scanning signal.

[0020] According to another aspect of the present invention, a display panel is provided, the display panel including the pixel circuit described above.

[0021] According to another aspect of the present invention, a driving method for a pixel circuit is provided, wherein the pixel circuit is a pixel circuit as described above, and the driving method for the pixel circuit includes:

[0022] In the first initialization phase of the write frame, the control terminal of the drive module is initialized using the first initialization voltage; and in the data writing phase of the write frame, the data voltage is transmitted to the first terminal of the drive module.

[0023] A reset voltage is generated based on the data voltage and the first initialization voltage;

[0024] During the bias phase prior to the light emission phase in the holding frame, the reset voltage is transmitted to the first terminal of the driving module.

[0025] Optionally, generating the reset voltage based on the data voltage and the first initialization voltage includes:

[0026] The reset voltage is obtained by subtracting the data voltage from the first initialization voltage.

[0027] The technical solution of this invention employs a pixel circuit comprising: a driving module, a light-emitting module, a first initialization module, a data writing module, and a bias module. The data writing module is electrically connected to a first terminal of the driving module and is used to transmit a data voltage to the driving module during the data writing phase of the write frame. The driving module generates a driving current based on the voltage at its control terminal, and the light-emitting module emits light in response to the driving current. The first initialization module transmits a first initialization voltage to the control terminal of the driving module during the first initialization phase of the write frame. The bias module generates a reset voltage based on the first initialization voltage and the data voltage, and transmits the reset voltage to the first terminal of the driving module during the bias phase before the light-emitting phase in the holding frame. By setting the bias module, the bias module can generate a reset voltage based on the data voltage and the first initialization voltage, making the potential difference between the control terminal and the first terminal of the driving module closer before the light-emitting phase of the holding frame, i.e., closer to the potential difference between the control terminal and the first terminal of the driving module before the light-emitting phase of the write frame, thereby improving the flickering phenomenon of the display screen.

[0028] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of the present invention, nor is it intended to limit the scope of the invention. Other features of the invention will become readily apparent from the following description. Attached Figure Description

[0029] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0030] Figure 1 A schematic diagram of a pixel circuit structure provided in an embodiment of the present invention;

[0031] Figure 2 A schematic diagram of the circuit structure of another pixel circuit provided in an embodiment of the present invention;

[0032] Figure 3 A schematic diagram of the circuit structure of a bias module provided in an embodiment of the present invention;

[0033] Figure 4 A timing diagram of a pixel circuit provided in an embodiment of the present invention;

[0034] Figure 5 A schematic diagram of the circuit structure of another pixel circuit provided in an embodiment of the present invention;

[0035] Figure 6This is a schematic diagram of the structure of a display device provided in an embodiment of the present invention;

[0036] Figure 7 This is a flowchart of a pixel circuit driving method provided in an embodiment of the present invention. Detailed Implementation

[0037] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0038] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0039] As mentioned in the background section, display panels often experience screen flickering, particularly at low frequencies and during frequency switching. Through careful research, the inventors discovered that this problem arises from the hysteresis effect of the driving transistors in the pixel circuit. The threshold voltage of these transistors depends not only on the current bias state but also on the bias state of the previous stage. While the driving transistors have the same bias state during the write frame's illumination phase and the hold frame's illumination phase, their bias states before the write frame's illumination phase and before the hold frame's illumination phase differ. This difference causes flickering when switching from a write frame to a hold frame, and the flickering problem is more pronounced during low-frequency driving and frequency switching.

[0040] To address the aforementioned technical problems, the present invention proposes the following solutions:

[0041] Figure 1 This is a schematic diagram of a pixel circuit structure provided in an embodiment of the present invention, with reference to... Figure 1The pixel circuit includes: a driving module 101, a light-emitting module 102, a first initialization module 103, a data writing module 104, and a bias module 105; the data writing module 104 is electrically connected to the first terminal of the driving module 101, and the data writing module 104 is used to transmit a data voltage Vdata to the driving module 101 during the data writing phase of the write frame; the driving module 101 is used to generate a driving current according to the voltage of its control terminal, and the light-emitting module 102 is used to emit light in response to the driving current; the first initialization module 103 is used to transmit a first initialization voltage Vrefn1 to the control terminal of the driving module 101 during the first initialization phase of the write frame; the bias module 105 is used to generate a reset voltage according to the first initialization voltage Vrefn1 and the data voltage Vdata, and transmit the reset voltage to the first terminal of the driving module 101 during the bias phase before the light-emitting phase in the holding frame.

[0042] Specifically, the light-emitting module 102 can be, for example, an OLED (Organic Light Emitting Diode). The light-emitting module 102 is a current-driven device and needs to emit light in response to the driving current generated by the driving module 101. The specific structure and light-emitting principle of the light-emitting module 102 are well known to those skilled in the art and will not be described in detail here. A display cycle of the pixel circuit may include a write frame and a hold frame. During the first initialization phase of the write frame, the first initialization module 103 initializes the control terminal of the driving module 101, making the voltage of the control terminal of the driving module 101 Vrefn1. At this time, the voltage of the first terminal of the driving module 101 is V1. That is, the voltage difference between the control terminal and the first terminal of the driving module 101 during this phase is Vrefn1-V1. In other words, during the write frame, in the phase before the light-emitting phase, such as the first initialization phase, the potential difference between the control terminal and the first terminal of the driving module 101 is Vrefn1-V1. Before the light-emitting phase of the holding frame, the first initialization module 103 no longer initializes the control terminal of the driving module 101, and the voltage that the control terminal of the driving module 101 needs to store is close to the data voltage Vdata corresponding to the writing frame (considering the influence of leakage current and threshold compensation, the voltage of the control terminal of the driving module 101 is close to the data voltage Vdata, but may not be completely equal). The voltage of the first terminal of the driving module 101 is V1. Therefore, before the light-emitting phase of the holding frame, the potential difference between the control terminal and the first terminal of the driving module 101 is close to Vdata-V1. However, during the light-emitting phase of the writing frame and the light-emitting phase of the holding frame, the voltage difference between the control terminal and the first terminal of the driving module 101 is equal. Since the value of the voltage difference between the control terminal and the first terminal of the driving module 101 before the light-emitting phase of the writing frame is different from the value before the light-emitting phase of the holding frame, flickering occurs during low-frequency and frequency switching. In this embodiment, by setting a bias module 105, the bias module 105 can generate a reset voltage based on the data voltage Vdata and the first initialization voltage Vrefn1. This makes the potential difference between the control terminal and the first terminal of the driving module 101 closer to Vrefn1-V1 before the light emission stage of the holding frame, that is, closer to the potential difference between the control terminal and the first terminal of the driving module 101 before the light emission stage of the writing frame. This can improve the flickering phenomenon during low-frequency and frequency switching. Furthermore, since the reset voltage generated by the bias module 105 is related to the data voltage Vdata, the reset voltage changes accordingly when the data voltage Vdata changes. This allows for dynamic adjustment of the reset voltage value, resulting in weaker flickering when displaying any grayscale level in low-frequency or frequency switching states.

[0043] The pixel circuit used in this embodiment includes a driving module, a light-emitting module, a first initialization module, a data writing module, and a bias module. The data writing module is electrically connected to the first terminal of the driving module and is used to transmit a data voltage to the driving module during the data writing phase of the write frame. The driving module generates a driving current based on the voltage at its control terminal, and the light-emitting module emits light in response to the driving current. The first initialization module transmits a first initialization voltage to the control terminal of the driving module during the first initialization phase of the write frame. The bias module generates a reset voltage based on the first initialization voltage and the data voltage, and transmits the reset voltage to the first terminal of the driving module during the bias phase before the light-emitting phase in the holding frame. By setting the bias module, the bias module can generate a reset voltage based on the data voltage and the first initialization voltage, making the potential difference between the control terminal and the first terminal of the driving module closer before the light-emitting phase of the holding frame, that is, closer to the potential difference between the control terminal and the first terminal of the driving module before the light-emitting phase of the write frame, thereby improving the flickering phenomenon during low-frequency and frequency switching.

[0044] Optionally, the bias module 105 is used to subtract the first initialization voltage Vrefn1 from the data voltage Vdata to obtain the reset voltage.

[0045] Specifically, let the reset voltage be Vskip. As can be seen from the above analysis, before the light emission stage of writing the frame, the potential difference between the control terminal of the driving module 101 and the first terminal is Vrefn1-V1; before the light emission stage of holding the frame, the potential difference between the control terminal of the driving module 101 and the first terminal is approximately Vdata-V1. By setting Vskip = Vdata-Vrefn1, the potential difference between the control terminal of the driving module 101 and the first terminal is approximately Vdata-(Vdata-Vrefn1)-V1 = Vrefn1-V1, which means that the voltage difference between the control terminal of the driving module 101 and the first terminal is approximately Vrefn1-V1, thereby improving the flickering phenomenon in low-frequency and frequency switching states.

[0046] Optionally, in some embodiments, during the holding frame, the data voltage of the pixel circuit jumps to reset the first terminal of the drive module 101. In this embodiment, it is only necessary to jump the data voltage of the holding frame to the reset voltage. The bias module 105 can be understood as the internal structure of the module required to control the data voltage jump.

[0047] Optionally, in some embodiments, the duration of the bias phase is the same as the duration of the first initialization phase. This setting ensures that the transmission time of the bias voltage (voltage difference between the control terminal and the first terminal) between the control terminal and the first terminal is the same in the phase before the light emission phase of the write frame and the hold frame, thereby making the transmission effect similar and further improving the flickering phenomenon in low frequency and frequency switching states.

[0048] Optionally, in the above embodiments, such as Figure 1 As shown, the output terminal of the bias module 105 can be directly electrically connected to the first terminal of the drive module 101. In this embodiment, the bias module 105 is enabled in the holding frame, and the duration of the enable is the same as the duration of the first initialization phase of the write frame. Since the first initialization signal SN1 is always off in the holding frame, the bias module in this embodiment needs to introduce an additional enable signal. It should be noted that the start time of the enable signal in the bias phase is not limited, as long as it is before the light emission phase of the holding frame, that is, the timing with the data writing phase of the holding frame is not limited. In addition, in this embodiment, during the holding frame, the first terminal of the data writing module 104 does not input the data voltage Vdata.

[0049] In some other embodiments, optionally, Figure 2 This is a schematic diagram of the circuit structure of another pixel circuit provided in an embodiment of the present invention, with reference to... Figure 2 The bias module 105 is electrically connected to the first end of the data writing module 104, and the second end of the data writing module 104 is electrically connected to the first end of the drive module 101. The bias module 105 is used to transmit the reset voltage to the first end of the data writing module 104 during the bias phase. During the holding frame, the bias phase coincides with the data writing phase.

[0050] Specifically, both the write frame and the hold frame include a data write phase, and the data write module 104 is turned on during the data write phase. The bias module 105 is turned on during the data write phase of the hold frame, and the reset voltage output by the bias module 105 is input to the first terminal of the drive module 101 after passing through the data write module 104, ensuring that the bias phase coincides with the data write phase. That is, the bias phase begins when the data write phase begins and ends when the data write phase ends. This configuration allows the bias module to be enabled using the scan signal corresponding to the data write module without requiring an additional enable signal, reducing the number of signal lines in the display panel. It should be noted that in this embodiment, during the hold frame, the first terminal of the data write module 104 does not receive a data voltage Vdata; that is, the data line does not transmit the data voltage Vdata to the first terminal of the data write module.

[0051] Optionally, refer to Figure 1 and Figure 2 The pixel circuit also includes a threshold compensation module 106. The first terminal of the threshold compensation module 106 is electrically connected to the second terminal of the driving module 101, and the second terminal of the threshold compensation module 106 is electrically connected to the control terminal of the driving module 101. The control terminal of the threshold compensation module 106 is connected to the first scan signal SN2. The control terminal of the data writing module 104 is connected to the second scan signal SP1. The first scan signal SN2 is configured to be on during the data writing phase of the write frame and off during the holding frame. The second scan signal SP1 is configured to be on during both the data writing phase of the write frame and the data writing phase of the holding frame. The bias module 105 is configured to generate a reset voltage when the first scan signal SN2 is off and the second scan signal SP1 is on.

[0052] Specifically, the threshold compensation module 106 is used to compensate the threshold voltage of the drive module 101, so that the drive current generated by the drive module 101 is independent of the threshold voltage of the drive module 101. The first scan signal SN2 is on during the data writing phase of the write frame, so that the data voltage Vdata can be written normally to the control terminal of the drive module 101; it is off during the hold frame, and by inserting multiple hold frames, the high frequency can be converted to the low frequency. The second scan signal SP1 is on during both the data writing phase of the write frame and the data writing phase of the hold frame, so the state of the second scan signal SP1 does not need to be changed when switching from high frequency to low frequency. The bias module 105 is configured to generate a reset voltage when the first scan signal SN2 is off and the second scan signal SP1 is on. The bias module 105 does not generate a reset voltage in other states; that is, it does not generate a reset voltage when the first scan signal SN2 is off and the second scan signal is off; it does not generate a reset voltage when the first scan signal SN2 is on and the second scan signal SP1 is on; and it does not generate a reset voltage when the first scan signal SN2 is on and the second scan signal SP1 is off. This configuration ensures that the bias module 105 generates a reset voltage only during the data writing phase of the holding frame, and not during the data writing phase of the writing frame. Therefore, it does not affect the process of writing the data voltage Vdata to the control terminal of the driving module 101 during the data writing phase of the writing frame. It should be noted that the on-level described in this embodiment is the level that enables the corresponding module to conduct. The on-level may differ for different modules; for example, the on-level is low for modules using P-type transistors, while it is high for modules using N-type transistors. Similarly, the shutdown level is the level at which the corresponding module is turned on. The shutdown level may be different for different modules. For example, the shutdown level is high for modules using P-type transistors, while it is low for modules using N-type transistors.

[0053] Optionally, Figure 3 This is a schematic diagram of the circuit structure of a bias module provided in an embodiment of the present invention, with reference to... Figure 3 The bias module 15 includes a voltage calculation unit 1051 and a voltage enable unit 1052. The voltage enable unit 1052 is electrically connected to the voltage calculation unit 1051. The voltage enable unit 1051 is configured to enable the voltage calculation unit when the first scan signal SN2 is at the off level and the second scan signal SP1 is at the on level. The voltage calculation unit 1051 is configured to generate a reset voltage Vskip based on the data voltage Vdata and the first initialization voltage Vrefn1 when enabled.

[0054] Specifically, the voltage calculation unit 1051 can be a subtractor, which can only generate the reset voltage Vskip when enabled, and is in a non-operating state when disabled. The voltage calculation unit 1051 can also be a logic device, and its logical relationship can be... Where Y is the enable signal, A is the on level of the first scan signal SN2, and B is the on level of the second scan signal SP1. That is to say, the enable signal Y is enabled when the first scan signal SN2 is off and the second scan signal SP1 is on.

[0055] Optionally, continue to refer to Figure 1 and Figure 2 The first initialization module 103 has a first initialization voltage Vrefn1 connected to its first terminal, and a second terminal electrically connected to the control terminal of the drive module 101. The control terminal of the first initialization module 103 is connected to a third scan signal SN1. The pixel circuit also includes a storage module 107, a first light-emitting control module 108, a second light-emitting control module 109, and a second initialization module 110. The first terminal of the first light-emitting control module 108 is connected to a first power signal ELVDD, and the second terminal of the first light-emitting control module 108 is electrically connected to the first terminal of the drive module. The control terminal of the first light-emitting control module 108 is connected to an enable signal EM. The first terminal of the second light-emitting control module 109 is connected to the drive module 101. The second terminal of module 101 is electrically connected, the second terminal of the second light-emitting control module 109 is electrically connected to the first terminal of the light-emitting module 102, the control terminal of the second light-emitting control module 109 is connected to the enable signal EM, and the second terminal of the light-emitting module 102 is connected to the second power signal ELVSS; the first terminal of the storage module 107 is electrically connected to the first terminal of the first light-emitting control module 108, and the second terminal of the storage module 107 is electrically connected to the control terminal of the drive module 101; the first terminal of the second initialization module 110 is connected to the second initialization voltage Vrefn2, the second terminal of the second initialization module 110 is electrically connected to the first terminal of the light-emitting module 102, and the control terminal of the second initialization module 110 is connected to the fourth scan signal SP2.

[0056] Specifically, Figure 4 This is a timing diagram of a pixel circuit provided in an embodiment of the present invention. Figure 4 It can be Figure 1 or Figure 2 The timing diagram corresponding to the pixel circuit. Combined with... Figure 1 , Figure 2 and Figure 4 A display cycle of a pixel circuit includes write frames and hold frames, wherein the number of hold frames is not limited.

[0057] The write frame includes a first initialization phase t1, a data writing phase t2, a second initialization phase t3, and a light emission phase t4, taking the threshold compensation module 106 and the first initialization module 103 as having a high conduction level and the other modules as having a low conduction level as an example.

[0058] During the first initialization phase t1 of the written frame, the third scan signal SN1 is high, the first scan signal SN2 is low, the second scan signal SP1 is high, and the fourth scan signal SP2 is high. At this time, the first initialization module 103 is turned on, and the data writing module 104, the threshold compensation module 106, and the second initialization module 110 are turned off. The first initialization module 103 uses the first initialization signal Vrefn1 to initialize the control terminal of the drive module 101. During this phase, the voltage difference between the control terminal and the first terminal of the drive module 101 is Vrefn1 - V1.

[0059] During the data writing phase t2 of the write frame, the third scan signal SN1 is low, the first scan signal SN2 is high, the second scan signal SP1 is low, and the fourth scan signal SP2 is high. At this time, the first initialization module 103 is turned off, the data writing module 104 and the threshold compensation module 106 are turned on, and the second initialization module 110 is turned off. The data voltage Vdata is transmitted to the control terminal of the drive module 101 after passing through the data writing module 104, the drive module 101, and the threshold compensation module 106. When the potential difference between the control terminal and the first terminal of the drive module 101 is equal to the threshold voltage of the drive module 101, the drive module 101 is turned off, thereby completing the threshold voltage compensation of the drive module 101. After this process, the potential of the control terminal of the drive module 101 is close to the data voltage Vdata.

[0060] During the second initialization phase t3 of the written frame, the third scan signal SN1 is low, the first scan signal SN2 is low, the second scan signal SP1 is high, and the fourth scan signal SP2 is low. At this time, the second initialization module 110 is turned on, and the first initialization module 103, the data writing module 104, and the threshold compensation module 106 are turned on. The second initialization module 110 uses the second initialization signal Vrefn2 to initialize the first end of the light-emitting module 102.

[0061] During the light emission stage t4 of the written frame, the enable signal EM is at a low level, the first light emission control module 108 and the second light emission control module 109 are turned on, and the light emission module 102 emits light according to the driving current generated by the driving module 101.

[0062] The holding frame also includes the data writing phase t2, the second initialization phase t3, and the light emission phase t4;

[0063] During the data writing phase t2 of the holding frame, the third scan signal SN1 is high, the first scan signal SN2 is high, the second scan signal SP1 is low, and the fourth scan signal SP2 is high. At this time, the first initialization module 103 is off, the data writing module 104 is on, the threshold compensation module 106 is off, and the second initialization module 110 is off. Furthermore, the bias module 105 generates a reset voltage Vskip, which is transmitted to the first terminal of the drive module 101. Since the voltage at the control terminal of the write frame drive module 101 is approximately Vdata, specifically differing from Vdata by a threshold voltage, and this voltage is maintained during the holding frame, after this process, the voltage difference between the control terminal and the first terminal of the drive module 101 is approximately Vdata - Vskip - V1 = Vdata - (Vdata - Vrefn1) - V1 = Vrefn1 - V1. This voltage difference is the same as the voltage difference corresponding to the first initialization phase of the write frame, thus improving the flickering phenomenon during low-frequency and frequency switching. Specifically, during frame holding, the first terminal of the data writing module 104 does not input the data voltage Vdata, that is, the data line does not transmit the data voltage Vdata to the first terminal of the data writing module.

[0064] During the second initialization phase t3 of the holding frame, the third scan signal SN1 is low, the first scan signal SN2 is low, the second scan signal SP1 is high, and the fourth scan signal SP2 is low. At this time, the second initialization module 110 is turned on, and the first initialization module 103, the data writing module 104, and the threshold compensation module 106 are turned on. The second initialization module 110 uses the second initialization signal Vrefn2 to initialize the first end of the light-emitting module 102.

[0065] During the light emission phase t4 of the holding frame, the enable signal EM is at a low level, the first light emission control module 108 and the second light emission control module 109 are turned on, and the light emission module 102 emits light according to the driving current generated by the driving module 101.

[0066] Optionally, Figure 5 This is a schematic diagram of the circuit structure of another pixel circuit provided in an embodiment of the present invention, with reference to... Figure 5 The driving module 101 includes a first transistor T1, the first end of the first transistor T1 serves as the first end of the driving module 101, the second end of the first transistor T1 serves as the second end of the driving module 101, and the control end of the first transistor T1 serves as the control end of the driving module 101.

[0067] The data writing module 104 includes a second transistor T2. The first terminal of the second transistor T2 serves as the first terminal of the data writing module 104, the second terminal of the second transistor T2 serves as the second terminal of the data writing module 104, and the control terminal of the second transistor T2 serves as the control terminal of the data writing module 104.

[0068] The threshold compensation module 106 includes a third transistor T3. The first terminal of the third transistor T3 serves as the first terminal of the threshold compensation module 106, the second terminal of the third transistor T3 serves as the second terminal of the threshold compensation module 106, and the control terminal of the third transistor T3 serves as the control terminal of the threshold compensation module 106.

[0069] The first initialization module 103 includes a fourth transistor T4. The first terminal of the fourth transistor T4 serves as the first terminal of the first initialization module 103, the second terminal of the fourth transistor T4 serves as the second terminal of the first initialization module 103, and the control terminal of the fourth transistor T4 serves as the control terminal of the first initialization module 103.

[0070] The first light-emitting control module 108 includes a fifth transistor T5. The first terminal of the fifth transistor T5 serves as the first terminal of the first light-emitting control module 108, the second terminal of the fifth transistor T5 serves as the second terminal of the first light-emitting control module 108, and the control terminal of the fifth transistor T5 serves as the control terminal of the first light-emitting control module 108.

[0071] The second light-emitting control module 109 includes a sixth transistor T6. The first terminal of the sixth transistor T6 serves as the first terminal of the second light-emitting control module 109, the second terminal of the sixth transistor T6 serves as the second terminal of the second light-emitting control module 109, and the control terminal of the sixth transistor T6 serves as the control terminal of the second light-emitting control module 109.

[0072] The second initialization module 110 includes a seventh transistor T7. The first terminal of the seventh transistor T7 serves as the first terminal of the second initialization module 110, the second terminal of the seventh transistor T7 serves as the second terminal of the second initialization module 110, and the control terminal of the seventh transistor T7 serves as the control terminal of the second initialization module 110.

[0073] The storage module 107 includes a capacitor Cst, with the first end of the capacitor Cst serving as the first end of the storage module 107 and the second end of the capacitor Cst serving as the second end of the storage module 107.

[0074] Optionally, the threshold compensation module 106 and the first initialization module 103 use the same transistor type, which differs from the transistor type of the data writing module 104. The threshold compensation module 106 and the first initialization module 103 can be indium gallium zinc oxide (IGNOW) transistors, which have low leakage current and can mitigate the impact of leakage current on the control terminal potential of the drive module 101. The remaining transistors in the pixel circuit can be polysilicon or monocrystalline silicon transistors, offering advantages such as ease of fabrication and low cost.

[0075] This invention also provides a display panel, which includes the pixel circuit provided in any embodiment of this invention and thus has the same beneficial effects, which will not be described in detail here.

[0076] This invention also provides a display device, such as... Figure 6 As shown, Figure 6 This is a schematic diagram of a display device according to an embodiment of the present invention. The display device includes a display panel provided in this embodiment. The display device can be a mobile phone, tablet computer, MP3 player, MP4 player, smartwatch, smart helmet, personal digital assistant, video phone, or other wearable device, etc. Since the display device includes the display panel provided in this embodiment, it also has the same beneficial effects, which will not be described again here.

[0077] This invention also provides a method for driving pixel circuits, such as... Figure 7 As shown, Figure 7 This is a flowchart illustrating a pixel circuit driving method provided in an embodiment of the present invention. The pixel circuit is any pixel circuit provided in any embodiment of the present invention, and the pixel circuit driving method includes:

[0078] Step S201: In the first initialization phase of the write frame, the control terminal of the drive module is initialized using the first initialization voltage; and in the data writing phase of the write frame, the data voltage is transmitted to the first terminal of the drive module.

[0079] Specifically, a display cycle of the pixel circuit may include a write frame and a hold frame. During the first initialization stage of the write frame, the first initialization module initializes the control terminal of the drive module and writes the voltage of the control terminal of the drive module as Vrefn1. At this time, the voltage of the first terminal of the drive module is V1. That is, the voltage difference between the control terminal and the first terminal of the drive module in this stage is Vrefn1-V1. In other words, during the write frame, the potential difference between the control terminal and the first terminal of the drive module in the stage before the light emission stage is Vrefn1-V1.

[0080] Step S202: Generate a reset voltage based on the data voltage and the first initialization voltage;

[0081] In step S203, during the bias phase before the light emission phase in the holding frame, the reset voltage is transmitted to the first terminal of the drive module.

[0082] Specifically, before the light-emitting phase of the holding frame, since the first initialization module 103 no longer initializes the control terminal of the driving module, and the voltage that the control terminal of the driving module 101 needs to store is close to the data voltage Vdata corresponding to the writing frame, and the voltage of the first terminal of the driving module 101 is V1, then before the light-emitting phase of the holding frame, the potential difference between the control terminal and the first terminal of the driving module is close to Vdata-V1. However, during the light-emitting phases of the writing frame and the holding frame, the voltage difference between the control terminal and the first terminal of the driving module is equal. Therefore, it can be concluded that because the voltage difference between the control terminal and the first terminal of the driving module before the light-emitting phase of the writing frame is different from the value before the light-emitting phase of the holding frame, screen flickering occurs during low-frequency and frequency switching. In this embodiment, a reset voltage is generated based on the data voltage Vdata and the first initialization voltage Vrefn1. This ensures that before the light emission phase of the holding frame, the potential difference between the control terminal and the first terminal of the driving module is closer to Vrefn1-V1, which is closer to the potential difference between the control terminal and the first terminal of the driving module before the light emission phase of the written frame. This significantly improves the flickering phenomenon during low-frequency and frequency switching. Furthermore, since the reset voltage is related to the data voltage Vdata, the reset voltage changes accordingly when the data voltage Vdata changes. This allows for dynamic adjustment of the reset voltage value, resulting in weaker flickering when displaying any grayscale level during low-frequency or frequency switching.

[0083] The technical solution of this embodiment employs a pixel circuit driving method comprising: in the first initialization stage of the write frame, initializing the control terminal of the driving module using a first initialization voltage; and in the data writing stage of the write frame, transmitting a data voltage to the first terminal of the driving module; generating a reset voltage based on the data voltage and the first initialization voltage; and in the bias stage before the light emission stage in the holding frame, transmitting the reset voltage to the first terminal of the driving module. Generating the reset voltage based on the data voltage and the first initialization voltage makes the potential difference between the control terminal and the first terminal of the driving module closer before the light emission stage of the holding frame, i.e., closer to the potential difference between the control terminal and the first terminal of the driving module before the light emission stage of the write frame, thereby greatly improving the flickering phenomenon during low-frequency and frequency switching.

[0084] Optionally, generating a reset voltage based on the data voltage and the first initialization voltage includes:

[0085] The reset voltage is obtained by subtracting the data voltage from the first initialization voltage.

[0086] Specifically, let the reset voltage be Vskip. As can be seen from the above analysis, before the light emission stage of writing the frame, the potential difference between the control terminal of the driving module 101 and the first terminal is Vrefn1-V1; before the light emission stage of holding the frame, the potential difference between the control terminal of the driving module 101 and the first terminal is approximately Vdata-V1. By setting Vskip = Vdata-Vrefn1, the potential difference between the control terminal of the driving module 101 and the first terminal is approximately Vdata-(Vdata-Vrefn1)-V1 = Vrefn1-V1, which means that the voltage difference between the control terminal of the driving module 101 and the first terminal is approximately Vrefn1-V1, thereby greatly improving the flickering phenomenon in low frequency and frequency switching states.

[0087] It should be understood that the various forms of processes shown above can be used, with steps reordered, added, or deleted. For example, the steps described in this invention can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this invention can be achieved, and this is not limited herein.

[0088] The specific embodiments described above do not constitute a limitation on the scope of protection of this invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this invention should be included within the scope of protection of this invention.

Claims

1. A pixel circuit, characterized in that, The pixel circuit includes: a driving module, a light-emitting module, a first initialization module, a data writing module, and a bias module; The data writing module is electrically connected to the first terminal of the driver module, and the data writing module is used to transmit data voltage to the driver module during the data writing phase of the write frame. The driving module is used to generate a driving current according to the voltage at its control terminal, and the light-emitting module is used to emit light in response to the driving current; The first initialization module is used to transmit the first initialization voltage to the control terminal of the drive module during the first initialization phase of the write frame; The bias module is used to generate a reset voltage based on the first initialization voltage and the data voltage, and transmit the reset voltage to the first end of the driving module during the bias phase before the light emission phase in the holding frame. The bias module is used to subtract the first initialization voltage from the data voltage to obtain the reset voltage; when the data voltage changes, the reset voltage also changes.

2. The pixel circuit according to claim 1, characterized in that, The duration of the bias phase is the same as the duration of the first initialization phase.

3. The pixel circuit according to claim 1, characterized in that, The output terminal of the bias module is electrically connected to the first terminal of the drive module.

4. The pixel circuit according to claim 1, characterized in that, The bias module is electrically connected to the first end of the data writing module, and the second end of the data writing module is electrically connected to the first end of the driving module. The bias module is used to transmit the reset voltage to the first end of the data writing module during the bias phase. During the holding frame, the bias phase coincides with the data writing phase.

5. The pixel circuit according to claim 1, characterized in that, The pixel circuit further includes a threshold compensation module. A first terminal of the threshold compensation module is electrically connected to a second terminal of the driving module, and the second terminal of the threshold compensation module is electrically connected to a control terminal of the driving module. The control terminal of the threshold compensation module is connected to a first scan signal, and the control terminal of the data writing module is connected to a second scan signal. The first scan signal is configured to be at an on level during the data writing phase of the write frame and at an off level during the hold frame. The second scan signal is configured to be at an on level during both the data writing phase of the write frame and the data writing phase of the hold frame. The bias module is configured to generate the reset voltage when the first scan signal is at an off level and the second scan signal is at an on level.

6. The pixel circuit according to claim 5, characterized in that, The bias module includes a voltage calculation unit and a voltage enable unit; the voltage enable unit is electrically connected to the voltage calculation unit, and the voltage enable unit is configured to enable the voltage calculation unit when the first scan signal is at a shutdown level and the second scan signal is at a conduction level; the voltage calculation unit is configured to generate the reset voltage based on the data voltage and the first initialization voltage when enabled.

7. The pixel circuit according to claim 6, characterized in that, The threshold compensation module has a different transistor type than the data writing module, while the threshold compensation module has the same transistor type as the first initialization module.

8. The pixel circuit according to claim 6, characterized in that, The first terminal of the first initialization module is connected to the first initialization voltage, the second terminal of the first initialization module is electrically connected to the control terminal of the drive module, and the control terminal of the first initialization module is connected to the third scan signal.

9. The pixel circuit according to claim 6, characterized in that, The pixel circuit further includes a storage module, a first light-emitting control module, and a second light-emitting control module. A first terminal of the first light-emitting control module is connected to a first power signal, and a second terminal of the first light-emitting control module is electrically connected to a first terminal of the driving module. An enable signal is connected to the control terminal of the first light-emitting control module. A first terminal of the second light-emitting control module is electrically connected to a second terminal of the driving module, and a second terminal of the second light-emitting control module is electrically connected to a first terminal of the light-emitting module. The enable signal is connected to the control terminal of the second light-emitting module, and a second power signal is connected to the second terminal of the light-emitting module. A first terminal of the storage module is electrically connected to a first terminal of the first light-emitting control module, and a second terminal of the storage module is electrically connected to the control terminal of the driving module.

10. The pixel circuit according to claim 9, characterized in that, The pixel circuit further includes a second initialization module. The first terminal of the second initialization module is connected to a second initialization voltage, the second terminal of the second initialization module is electrically connected to the first terminal of the light-emitting module, and the control terminal of the second initialization module is connected to a fourth scanning signal.

11. A display panel, characterized in that, The display panel includes the pixel circuitry as described in any one of claims 1-10.

12. A driving method for a pixel circuit, wherein the pixel circuit is the pixel circuit according to any one of claims 1-10, characterized in that, The driving method for the pixel circuit includes: In the first initialization phase of the write frame, the control terminal of the drive module is initialized using the first initialization voltage; and in the data writing phase of the write frame, the data voltage is transmitted to the first terminal of the drive module. A reset voltage is generated based on the data voltage and the first initialization voltage; During the bias phase prior to the light emission phase in the holding frame, the reset voltage is transmitted to the first terminal of the driving module.

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