Display panel and driving method thereof

Abstract

This application discloses a display panel and its driving method. The driving method includes: during a first sub-driving cycle of a first frame displayed on the display panel, sequentially outputting a plurality of first scan signals to pixels in a plurality of odd-numbered rows of the display panel at a first frequency; and during a second sub-driving cycle of the first frame, sequentially outputting a plurality of second scan signals to pixels in a plurality of even-numbered rows of the display panel at a second frequency; wherein the second sub-driving cycle is temporally continuous with the first sub-driving cycle, and the second sub-driving cycle occurs after the first sub-driving cycle; the first frequency is greater than the second frequency; and during the first and second sub-driving cycles, data signals of the first frame are input to pixels where thin-film transistor switches are turned on under the control of the first and second scan signals. This application can improve flickering.

Description

Technical Field

[0001] This application relates to the field of display technology, specifically to a display panel and its driving method. Background Technology

[0002] Traditional AMOLED display panels typically use a 7T2C pixel circuit architecture. Although the 7T2C architecture adds drive compensation, the problem of thin-film transistor leakage current still exists. Thin-film transistor leakage current can easily lead to a decrease in display quality, especially when the AMOLED display panel switches drive frame rates. The leakage current of the thin-film transistor can cause brightness differences in the AMOLED display panel, resulting in a "flickering" phenomenon.

[0003] In addition, the threshold voltage of the driving transistor in the pixel circuit will drift over time, affecting the driving current. When the driving frame rate of the AMOLED display panel is switched, the AMOLED display panel will exhibit varying degrees of "flickering".

[0004] Therefore, it is necessary to propose a new technical solution to solve the above-mentioned technical problems. Summary of the Invention

[0005] The purpose of this application is to provide a display panel and its driving method to improve flickering.

[0006] To solve the above problems, the technical solution of this application is as follows:

[0007] In a first aspect, this application proposes a display panel driving method, comprising: during a first sub-driving cycle of a first frame displayed on the display panel, sequentially outputting a plurality of first scan signals to a plurality of odd-numbered rows of pixels on the display panel at a first frequency; during a second sub-driving cycle of the first frame, sequentially outputting a plurality of second scan signals to a plurality of even-numbered rows of pixels on the display panel at a second frequency; wherein the second sub-driving cycle is temporally continuous with the first sub-driving cycle, and the second sub-driving cycle is after the first sub-driving cycle, the first frequency is greater than the second frequency, and during the first and second sub-driving cycles, data signals of the first frame are input to pixels where thin-film transistor switches are turned on under the control of the first scan signals and the second scan signals.

[0008] In the above display panel driving method, the first frequency is an integer multiple of the second frequency.

[0009] In the above-described display panel driving method, the step of sequentially outputting a plurality of first scan signals to a plurality of odd-numbered rows of pixels on the display panel at a first frequency during a first sub-driving cycle of the first frame displayed on the display panel includes: receiving a first start signal; and, according to the first start signal, sequentially outputting a plurality of first scan signals to a plurality of odd-numbered rows of pixels on the display panel at a first frequency during a first sub-driving cycle of the first frame displayed on the display panel. The step of sequentially outputting a plurality of second scan signals to a plurality of even-numbered rows of pixels on the display panel at a second frequency during a second sub-driving cycle of the first frame includes: receiving a second start signal; and, according to the second start signal, sequentially outputting a plurality of second scan signals to a plurality of even-numbered rows of pixels on the display panel at a second frequency during a second sub-driving cycle of the first frame displayed on the display panel.

[0010] In the above-described display panel driving method, before the step of sequentially outputting a plurality of first scan signals to a plurality of odd-numbered rows of pixels of the display panel at a first frequency during the first sub-driving cycle of the first frame displayed on the display panel, the method further includes: sequentially outputting a plurality of third scan signals to a plurality of rows of pixels of the display panel at a third frequency during the driving cycle of the second frame displayed on the display panel; wherein the driving cycle of the second frame is continuous in time with the first sub-driving cycle of the first frame, the third frequency is less than or equal to the first frequency, and during the driving cycle of the second frame, the data signal of the second frame is input to the pixels in which the thin-film transistor switch is turned on under the control of the third scan signal.

[0011] In the above-described display panel driving method, the driving cycle of the first frame image further includes a first blank time period and a second blank time period, wherein the first blank time period is after the first sub-driving cycle and the second blank time period is after the second sub-driving cycle; the method further includes: during the first blank time period, sequentially outputting multiple reset signals to the pixels of multiple odd-numbered rows of the display panel at a fourth frequency, and stopping the output of the data signal of the first frame image to the pixels of multiple odd-numbered rows of the display panel; during the second blank time period, sequentially outputting multiple reset signals to the pixels of multiple even-numbered rows of the display panel at the fourth frequency, and stopping the output of the data signal of the first frame image to the pixels of multiple even-numbered rows of the display panel.

[0012] Secondly, this application proposes a display panel, comprising: a pixel array including multiple rows of pixels; and a driving circuit, the driving circuit being configured to sequentially output multiple first scan signals to multiple odd-numbered rows of pixels of the display panel at a first frequency during a first sub-driving cycle of a first frame displayed on the display panel, and to sequentially output multiple second scan signals to multiple even-numbered rows of pixels of the display panel at a second frequency during a second sub-driving cycle of the first frame; wherein the second sub-driving cycle is temporally continuous with the first sub-driving cycle, and the second sub-driving cycle is after the first sub-driving cycle, the first frequency is greater than the second frequency, and during the first and second sub-driving cycles, data signals of the first frame are input to pixels where thin-film transistor switches are turned on under the control of the first and second scan signals.

[0013] In the aforementioned display panel, the first frequency is an integer multiple of the second frequency.

[0014] In the aforementioned display panel, the driving circuit is configured to receive a first start signal and, within a first sub-driving cycle of the first frame displayed on the display panel, sequentially output a plurality of first scan signals to a plurality of odd-numbered rows of pixels on the display panel at a first frequency, based on the first start signal; and to receive a second start signal and, within a second sub-driving cycle of the first frame, sequentially output a plurality of second scan signals to a plurality of even-numbered rows of pixels on the display panel at a second frequency, based on the second start signal.

[0015] In the aforementioned display panel, the driving circuit is further configured to sequentially output multiple third scan signals to the pixels of multiple rows of the display panel at a third frequency during the driving cycle of the second frame displayed on the display panel; wherein the driving cycle of the second frame is continuous in time with the first sub-driving cycle of the first frame, the first sub-driving cycle of the first frame is after the driving cycle of the second frame, the third frequency is less than or equal to the first frequency, and during the driving cycle of the second frame, the data signal of the second frame is input to the pixel that is turned on by the thin-film transistor switch under the control of the third scan signal.

[0016] In the aforementioned display panel, the driving cycle of the first frame also includes a first blank time period and a second blank time period. The first blank time period is after the first sub-driving cycle, and the second blank time period is after the second sub-driving cycle. The driving circuit is used to sequentially output multiple reset signals to the pixels of multiple odd-numbered rows of the display panel at a fourth frequency during the first blank time period, and to stop outputting the data signal of the first frame to the pixels of multiple odd-numbered rows of the display panel. It is also used to sequentially output multiple reset signals to the pixels of multiple even-numbered rows of the display panel at the fourth frequency during the second blank time period, and to stop outputting the data signal of the first frame to the pixels of multiple even-numbered rows of the display panel.

[0017] In this application, by driving the pixels in odd-numbered rows and even-numbered rows separately, and by adjusting the driving cycle of the gate driving circuit for the pixels in odd-numbered rows and even-numbered rows, the pixels in even-numbered rows start to emit light when the brightness of the pixels in odd-numbered rows is reduced to half. Therefore, the light emitted by the pixels in even-numbered rows can be used to compensate for the brightness reduction of the pixels in odd-numbered rows caused by leakage current, thereby reducing the visual brightness difference between the pixels in odd-numbered rows and even-numbered rows and improving the flickering phenomenon. Attached Figure Description

[0018] Figure 1 This is a schematic diagram of the gate driving circuit of the display panel driving circuit of this application.

[0019] Figure 2 This is a schematic diagram of the pixel circuit of the display panel of this application.

[0020] Figure 3 This is a signal waveform diagram of the first embodiment of the display panel driving method of this application.

[0021] Figure 4 This is a brightness waveform diagram of the first embodiment of the display panel driving method of this application.

[0022] Figure 5 and Figure 6 This is a signal waveform diagram of a second embodiment of the display panel driving method of this application.

[0023] Figure 7 This is a brightness waveform diagram of a second embodiment of the display panel driving method of this application.

[0024] Figure 8 and Figure 9 This is a signal waveform diagram of the third embodiment of the display panel driving method of this application.

[0025] Figure 10 This is a brightness waveform diagram of the third embodiment of the display panel driving method of this application. Detailed Implementation

[0026] The terms used in this specification and claims have the meanings that are commonly understood by one of ordinary skill in the art to which this application pertains. The terms used in this specification and claims are for the purpose of facilitating the description and understanding of this application only, and are not intended to limit this application to the narrow interpretation of the specific terms used in the specification and claims.

[0027] The terms "first," "second," and similar terms used in this application are merely to distinguish different technical features and do not indicate any order, quantity, or importance. The term "multiple" and similar terms mean two or more unless otherwise expressly specified.

[0028] The present application will be described in detail below with reference to specific embodiments. It should be noted that the following embodiments are only used to illustrate the present application and do not limit the scope of protection of the present application.

[0029] The various embodiments provided in this application are similar, and features in different embodiments can be combined with each other.

[0030] The display panel provided in this application may be, for example, an organic light-emitting diode (OLED) display panel, a liquid crystal display (LCD) panel, a micro-LED display panel, or a mini-LED display panel. The following description uses an organic light-emitting diode display panel employing a 7T2C architecture as an example.

[0031] The first embodiment of the display panel provided in this application includes a pixel array and a driving circuit. The pixel array includes multiple rows of pixels. The driving circuit includes a gate driving circuit and a source driving circuit.

[0032] The display panel uses a progressive scan driving method.

[0033] This application optimizes the gate driving circuit of the display panel by changing the traditional 2CK driving method to a 4CK driving method. This allows each shift register in the gate driving circuit to be electrically connected to two clock signal lines (CK), and the shift registers corresponding to odd-numbered rows of pixels and even-numbered rows of pixels are connected to different clock signal lines. Therefore, odd-numbered rows of pixels and even-numbered rows of pixels can be driven separately. By adjusting the driving cycle of the gate driving circuit for odd-numbered rows and even-numbered rows of pixels, the even-numbered rows of pixels begin to emit light when the brightness of the odd-numbered rows of pixels decreases to half. Therefore, the light emitted by the even-numbered rows of pixels can compensate for the brightness attenuation of the odd-numbered rows of pixels caused by leakage current, thereby reducing the visual brightness difference between odd-numbered and even-numbered rows of pixels and improving flicker.

[0034] like Figure 1 As shown, the gate drive circuit of the drive circuit in the display panel of this application includes four clock signal lines (CK1, CK2, CK3 and CK4), a multi-level shift register (including at least Scan(n), Scan(n+1), Scan(n+2) and Scan(n+3)), and a start signal input terminal (STV).

[0035] The start signal input terminal is electrically connected to the first-stage shift register and the second-stage shift register. The first-stage shift register is electrically connected to the scan line of the pixels in the first row, and the second-stage shift register is electrically connected to the scan line of the pixels in the second row.

[0036] The nth-stage shift register (Scan(n)) is electrically connected to the first clock signal line (CK1) and the third clock signal line (CK3), and is also electrically connected to the scan line (SS1) of the pixel in the nth row. The (n+1)th-stage shift register (Scan(n+1)) is electrically connected to the second clock signal line (CK2) and the fourth clock signal line (CK4), and is also electrically connected to the scan line (SS2) of the pixel in the (n+1)th row. The (n+2)th-stage shift register (Scan(n+2)) is electrically connected to the third clock signal line (CK3) and the first clock signal line (CK1), and is also electrically connected to the scan line (SS3) of the pixel in the (n+2)th row. The (n+3)th-stage shift register (Scan(n+3)) is electrically connected to the fourth clock signal line (CK4) and the second clock signal line (CK2), and is also electrically connected to the scan line (SS4) of the pixel in the (n+3)th row.

[0037] The nth level shift register (Scan(n)) is cascaded with the (n+2)th level shift register (Scan(n+2)). The (n+1)th level shift register (Scan(n+1)) is cascaded with the (n+3)th level shift register (Scan(n+3)).

[0038] like Figure 2 As shown, the pixel circuit of the display panel of this application includes a data signal input terminal (Data), a high-level signal input terminal (ELVDD), a low-level signal input terminal (ELVSS), a light-emitting device, a first reset signal input terminal (Vint1), a second reset signal input terminal (Vint2), a first scan signal input terminal (NScan(n)), a second scan signal input terminal (PScan(n)), a third scan signal input terminal (NScan(n+10)), a light-emitting control signal input terminal (EM), a first transistor switch (T1), a second transistor switch (T2), a third transistor switch (T3), a fourth transistor switch (T4), a fifth transistor switch (T5), a sixth transistor switch (T6), a seventh transistor switch (T7), a first capacitor (Cst), and a second capacitor (Cboost).

[0039] The control terminal of the fifth transistor switch (T5) is electrically connected to the light emission control signal input terminal (EM), the input terminal of the fifth transistor switch (T5) is electrically connected to the high potential signal input terminal (ELVDD), and the output terminal of the fifth transistor switch (T5) is electrically connected to the input terminal of the first transistor switch (T1).

[0040] The control terminal of the sixth transistor switch (T6) is electrically connected to the light emission control signal input terminal (EM), the input terminal of the sixth transistor switch (T6) is electrically connected to the output terminal of the first transistor switch (T1), and the output terminal of the sixth transistor switch (T6) is electrically connected to the anode of the light-emitting device.

[0041] The cathode of the light-emitting device is electrically connected to the low-potential signal terminal (ELVSS).

[0042] The input terminal of the fourth transistor switch (T4) is electrically connected to the second reset signal input terminal (Vint2), the output terminal of the fourth transistor switch (T4) is electrically connected to the control terminal of the first transistor switch (T1), and the control terminal of the fourth transistor switch (T4) is electrically connected to the first scan signal input terminal (NScan(n)).

[0043] The control terminal of the third transistor switch (T3) is electrically connected to the third scan signal input terminal (NScan(n+10)), the input terminal of the third transistor switch (T3) is electrically connected to the output terminal of the fourth transistor switch (T4), and the output terminal of the third transistor switch (T3) is electrically connected to the output terminal of the first transistor switch (T1).

[0044] The control terminal of the seventh transistor switch (T7) is electrically connected to the second scan signal input terminal (PScan(n)), the input terminal of the seventh transistor switch (T7) is electrically connected to the first reset signal input terminal (Vint1), and the output terminal of the seventh transistor switch (T7) is electrically connected to the output terminal of the sixth transistor switch (T6).

[0045] The control terminal of the second transistor switch (T2) is electrically connected to the second scan signal input terminal (PScan(n)), the input terminal of the second transistor switch (T2) is electrically connected to the data signal input terminal (Data), and the output terminal of the second transistor switch (T2) is electrically connected to the output terminal of the fifth transistor switch (T5).

[0046] One plate of the second capacitor (Cboost) is electrically connected to the control terminal of the second transistor switch (T2), and the other plate of the second capacitor (Cboost) is electrically connected to the output terminal of the fourth transistor switch (T4).

[0047] One plate of the first capacitor (Cst) is electrically connected to the high-potential signal input terminal (ELVDD), and the other plate of the first capacitor (Cst) is electrically connected to the control terminal of the first transistor switch (T1).

[0048] The Q point of the pixel circuit is a node in the line between the output terminal of the fourth transistor switch (T4) and the control terminal of the first transistor switch (T1).

[0049] The gate driving circuit of the driving circuit is used to sequentially output a plurality of first scan signals to the pixels of a plurality of odd-numbered rows of the display panel at a first frequency, starting from the pixels of the first odd-numbered row of the display panel during the first sub-driving cycle of the first frame of the display panel.

[0050] The driving cycle of a frame includes multiple sub-driving cycles, such as a first sub-driving cycle, a second sub-driving cycle, etc. In the driving cycle of a frame, the driving circuit of the display panel drives the pixels of all rows, that is, the driving circuit provides scanning signals to the pixels of all rows.

[0051] The first sub-driving cycle is the period during which the driving circuit provides scanning signals to the pixels of the odd-numbered rows (i.e., the first row, the third row, the fifth row, ..., the 2n-1th row, etc.) of the display panel.

[0052] In the first sub-driving cycle, the driving circuit first outputs a scanning signal to the TFT gate of the first row of pixels, so that the TFT of the first row of pixels is in the conducting state. At the same time, it provides data signals corresponding to the image content to be displayed to the first row of pixels. At this time, the first row of pixels will emit light of corresponding brightness to complete the display of the image of the first row of pixels.

[0053] After outputting the scan signal to the pixels in the first row, the driving circuit then outputs the scan signal to the TFT gate of the third row of pixels, so that the TFT of the third row of pixels is in the conducting state. Then, it provides the pixels in this row with a data signal corresponding to the image content to be displayed. At this time, the pixels in the third row will emit light of corresponding brightness to complete the display of the image of the third row of pixels.

[0054] And so on, within the first sub-driving cycle, the image display of all odd-numbered rows, such as the fifth and seventh rows, is completed sequentially.

[0055] The gate driving circuit is used to sequentially output a plurality of second scan signals to a plurality of even-numbered rows of pixels on the display panel at a second frequency, starting from the first even-numbered row of pixels on the display panel during the second sub-driving cycle of the first frame.

[0056] The second sub-driving cycle is the period during which the driving circuit provides scanning signals to the pixels of the even-numbered rows (i.e., the second row, the fourth row, the sixth row, ..., the 2nth row, etc.) of the display panel.

[0057] The second sub-driving cycle begins after the first sub-driving cycle ends. In the second sub-driving cycle, the driving circuit first outputs a scan signal to the gate of the TFT of the second row of pixels, turning on the TFT of the second row of pixels. At the same time, it provides data signals corresponding to the image content to be displayed to the second row of pixels. At this time, the second row of pixels emits light of corresponding brightness to complete the display of the image of the second row of pixels.

[0058] After outputting the scan signal to the pixels in the second row, the driving circuit then outputs the scan signal to the gate of the TFT of the pixels in the fourth row, so that the TFT of the pixels in the fourth row is in the conducting state. At the same time, it provides the pixels in the fourth row with data signals corresponding to the image content to be displayed. At this time, the pixels in the fourth row emit light of corresponding brightness to complete the display of the image of the pixels in the second row.

[0059] And so on, during the second sub-driving cycle, the image display of all even-numbered rows, such as the sixth and eighth rows, is completed sequentially.

[0060] When the second sub-driving cycle ends, the image of all pixels in the first frame is displayed, and then the driving cycle for another frame begins, repeating in a loop. In this embodiment, the driving cycle for each frame (the first frame) is the same; however, the driving cycle for each frame can also be different.

[0061] Wherein, the sum of the first sub-drive cycle and the second sub-drive cycle is less than or equal to the drive cycle of the first frame, the first frequency (e.g., 30Hz) is greater than the second frequency (e.g., 15Hz), the second sub-drive cycle is greater than the first sub-drive cycle, the second sub-drive cycle is continuous with the first sub-drive cycle in time, and the second sub-drive cycle is after the first sub-drive cycle.

[0062] The source driving circuit is used to output a first data signal to the pixels of multiple rows of the display panel during the driving cycle of the first frame. That is, during the first sub-driving cycle and the second sub-driving cycle, the data signal of the first frame is input to the pixels where the thin-film transistor switches are turned on under the control of the first scan signal and the second scan signal.

[0063] The first frequency is greater than the second frequency, the first frequency is an integer multiple of the second frequency, and the second sub-drive period is an integer multiple of the first sub-drive period. For example, the first frequency is 2, 3, 4, etc., of the second frequency, and the second sub-drive period is 2, 3, 4, etc., of the first sub-drive period. The first frequency may be, for example, 30Hz, and the second frequency may be, for example, 15Hz.

[0064] The gate driving circuit is used to receive a first start signal and, in the first sub-driving cycle of the first frame displayed on the display panel, according to the first start signal, sequentially output a plurality of first scan signals to the pixels of a plurality of odd-numbered rows of the display panel at a first frequency, starting from the pixels of the first odd-numbered row of the display panel.

[0065] The gate driving circuit is used to receive a second start signal and, within a second sub-driving cycle of the first frame, to sequentially output a plurality of second scan signals to pixels of a plurality of even-numbered rows of the display panel at a second frequency, starting from the pixels of the first even-numbered row of the display panel.

[0066] The gate driving circuit is used to receive a first start signal from the timing controller of the display panel, the first start signal indicating that the first sub-driving cycle can be started.

[0067] The gate driving circuit is used to generate a first scan signal for providing to the pixels in the odd-numbered rows after receiving the first start signal.

[0068] Specifically, the gate driving circuit provides a scan signal to the gate of the thin-film transistor (TFT) of the first row of pixels during a first time period of the first sub-driving cycle, thereby turning on the TFTs of the first row of pixels. Simultaneously with providing the scan signal to the first row of pixels, the source driving circuit provides a data signal corresponding to the image content of the first row of pixels. Next, during a second time period of the first sub-driving cycle, the gate driving circuit provides a scan signal to the gate of the TFT of the third row of pixels, thereby turning on the TFTs of the third row of pixels. Simultaneously with providing the scan signal to the third row of pixels, the source driving circuit provides a data signal corresponding to the image content of the third row of pixels. And so on, during the nth time period of the first sub-driving cycle, the gate driving circuit provides a scan signal to the gate of the TFT of the (2n-1)th row of pixels, thereby turning on the TFTs of the (2n-1)th row of pixels, while the source driving circuit provides a data signal corresponding to the image content of the (2n-1)th row of pixels.

[0069] The driving circuit is used to receive a second start signal from the timing controller of the display panel, the second start signal indicating that the second sub-driving cycle can be started.

[0070] The gate driving circuit is used to generate a second scan signal for providing to the pixels in even-numbered rows after receiving the second start signal.

[0071] Specifically, the gate driving circuit provides a scan signal to the gate of the TFT of the second row of pixels during a first time period of the second sub-driving cycle, thereby turning on the TFT of the second row of pixels. Simultaneously with providing the scan signal to the second row of pixels, the source driving circuit provides a data signal corresponding to the image content of the second row of pixels. Next, during a second time period of the second sub-driving cycle, the gate driving circuit provides a scan signal to the gate of the TFT of the fourth row of pixels, thereby turning on the TFT of the fourth row of pixels. Simultaneously with providing the scan signal to the fourth row of pixels, the source driving circuit provides a data signal corresponding to the image content of the fourth row of pixels. This continues, and during the nth time period of the second sub-driving cycle, the gate driving circuit provides a scan signal to the gate of the TFT of the 2nth row of pixels, thereby turning on the TFT of the 2nth row of pixels. Simultaneously, the source driving circuit provides a data signal corresponding to the image content of the 2nth row of pixels.

[0072] After the second sub-drive cycle ends, the drive for the first frame is completed.

[0073] like Figure 3 and Figure 4 As shown, in the first sub-driving cycle, the first clock signal line (CK1), the second clock signal line (CK2), the third clock signal line (CK3), and the fourth clock signal line (CK4) are used to output a plurality of clock signals that are staggered in sequence to the gate driving circuit. The gate driving circuit generates a first scan signal for the odd-numbered rows of pixels and a second scan signal for the even-numbered rows of pixels according to the clock signals, and outputs the first scan signal and the second scan signal to the odd-numbered rows of pixels and the even-numbered rows of pixels, respectively. The data driving circuit is used to generate data signals and output them to the pixels of the pixel array of the display panel.

[0074] In this embodiment, the start signal (STV signal) for driving the pixels in the odd-numbered rows and the start signal (STV signal) for driving the pixels in the even-numbered rows are separate, and the pixels in the odd and even rows are driven at different frequencies.

[0075] The start signals (STV signals) for odd-numbered rows of pixels and even-numbered rows of pixels are independent. The driving frequency of even-numbered rows of pixels is lower (smaller) than that of odd-numbered rows. That is, the driving period of even-numbered rows of pixels is longer than that of odd-numbered rows (the driving period of even-numbered rows can be an integer multiple of the driving period of odd-numbered rows). This allows the Q-point of the pixel circuit to be reset more fully, and the data signal of the pixel circuit to be written more fully, resulting in a longer pixel emission time. For example, for odd-numbered rows of pixels, the driving circuit drives at a frequency of 30Hz (frame rate), and for even-numbered rows of pixels, it drives at a frequency of 15Hz (frame rate). In the first part of the driving cycle of each frame, the scanning and emission of all odd-numbered rows of pixels are completed (including Q-point reset and data signal writing), and the brightness waveform is as follows: Figure 4 As shown, in the latter part of the driving cycle of each frame, all even-numbered rows of pixels are scanned and illuminated (including Q-point reset and data signal writing), and the brightness waveform is as follows. Figure 4 As shown, the moment when the even-numbered rows of pixels start to emit light is exactly the alternation moment when the brightness of the pixels in the odd-numbered rows is reduced to half due to leakage current in the pixel circuit after they emit light. At this time, the brightness of the even-numbered rows of pixels can compensate for the brightness reduction of the odd-numbered rows of pixels caused by leakage current. Therefore, when switching from high frequency to low frequency, the brightness difference between each row of pixels can be reduced, the visual difference can be reduced, and the flickering phenomenon of the display panel can be improved.

[0076] The second embodiment of the display panel provided in this application is similar to the first embodiment described above, except that:

[0077] In this embodiment, the driving cycles of two consecutive frames are different, that is, the driving cycle of the first frame is different from the driving cycle of the second frame.

[0078] The gate driving circuit is used to sequentially output multiple third scan signals to the pixels of multiple rows of the display panel at a third frequency, starting from the pixels of the first row of the display panel, during the driving cycle of the second frame (odd frame) displayed on the display panel.

[0079] The second frame (odd-numbered frame) and the first frame (even-numbered frame) are two frames displayed consecutively on the display panel. Specifically, the driving cycle of the second frame (odd-numbered frame) is sequential with the first sub-driving cycle of the first frame (even-numbered frame). The second frame (odd-numbered frame) is displayed before the first frame (even-numbered frame), meaning the first sub-driving cycle of the first frame (even-numbered frame) follows the driving cycle of the second frame (odd-numbered frame). The third frequency is less than or equal to the first frequency, and may be, for example, 30Hz, 25Hz, or 20Hz. The driving cycle of the first frame (even-numbered frame) is greater than the driving cycle of the second frame (odd-numbered frame).

[0080] The source driving circuit is used to output a second data signal to the pixels of multiple rows of the display panel during the driving cycle of the second frame (odd-numbered frame). That is, during the driving cycle of the second frame (odd-numbered frame), the data signal of the second frame (odd-numbered frame) is input to the pixels where the thin-film transistor switch is turned on under the control of the third scan signal.

[0081] Before the start of the driving cycle of the second frame (odd frame), the driving circuit is used to receive a third start signal from the timing controller of the display panel, the third start signal indicating that the driving cycle of the second frame (odd frame) can be started.

[0082] Upon receiving the third start signal, the gate drive circuit begins to generate a third scan signal for providing to the pixels of the multiple rows (all rows).

[0083] Specifically, the gate driving circuit provides a scan signal to the gate of the TFT of the first row of pixels during a first time period of the driving cycle of the second frame (odd-numbered frame), so that the TFT of the first row of pixels is turned on. Simultaneously with providing the scan signal to the first row of pixels, the source driving circuit provides a data signal corresponding to the image content of the first row of pixels. Next, during a second time period of the driving cycle of the second frame (odd-numbered frame), the gate driving circuit provides a scan signal to the gate of the TFT of the second row of pixels, so that the TFT of the second row of pixels is turned on. Simultaneously with providing the scan signal to the second row of pixels, the source driving circuit provides a data signal corresponding to the image content of the second row of pixels. Similarly, during a 2n-th time period of the driving cycle of the second frame (odd-numbered frame), the gate driving circuit provides a scan signal to the gate of the TFT of the 2n-th row of pixels, so that the TFT of the 2n-th row of pixels is turned on. Simultaneously, the source driving circuit provides a data signal corresponding to the image content of the 2n-th row of pixels.

[0084] After the driving cycle of the second frame (odd frame) ends, the driving of the second frame (odd frame) is completed.

[0085] The driving cycle of the second frame (odd-numbered frame) is less than the sum of the first sub-driving cycle and the second sub-driving cycle of the first frame (even-numbered frame).

[0086] As an improvement, the driving period of the first frame (even-numbered frame) is an integer multiple of the driving period of the second frame (odd-numbered frame). For example, the driving period of the first frame (even-numbered frame) is 2 times, 3 times, 4 times, etc., the driving period of the second frame (odd-numbered frame).

[0087] like Figure 5 , Figure 6 and Figure 7As shown, in the driving cycle FP2 of the second frame (odd-numbered frame), the first clock signal line (CK1), the second clock signal line (CK2), the third clock signal line (CK3), and the fourth clock signal line (CK4) are used to output multiple clock signals that are staggered sequentially to the gate driving circuit. The gate driving circuit is used to generate multiple third scan signals for all rows of pixels according to the clock signals, and to output the multiple third scan signals sequentially to the pixels of multiple rows. The data driving circuit is used to generate data signals and output them to the pixels of the pixel array of the display panel. After the driving cycle FP2 of the second frame (odd-numbered frame) ends, the driving cycle FP1 of the first frame (even-numbered frame) begins. In the driving cycle FP1 of the first frame (even-numbered frame), the first clock signal line (CK1), the second clock signal line (CK2), the third clock signal line (CK3), and the fourth clock signal line (CK4) are used to output a plurality of clock signals that are staggered in sequence to the gate driving circuit. The gate driving circuit is used to generate a first scan signal for the odd-numbered rows of pixels and a second scan signal for the even-numbered rows of pixels according to the clock signals, and outputs the first scan signal and the second scan signal to the odd-numbered rows of pixels and the even-numbered rows of pixels respectively. The data driving circuit is used to generate data signals and output them to the pixels of the pixel array of the display panel.

[0088] In this embodiment, for the second frame (odd-numbered frames), the pixels of each line are scanned and illuminated at a frequency of 30Hz (frame frequency) (including Q-point reset and data signal writing), and the brightness waveform is as follows. Figure 7 As shown, for the first frame (even-numbered frames), the scanning and illumination of pixels in both odd and even rows are completed with a longer period (lower frame rate) (including Q-point reset and data signal writing). The brightness waveform is as follows. Figure 7 As shown, the driving period FP1 of the first frame (even-numbered frame) can be an integer multiple of the driving period FP2 of the second frame (odd-numbered frame). In the first part of the driving period FP1 of the first frame (even-numbered frame), the scanning and illumination of pixels in the odd-numbered rows are completed first (including Q-point reset and data signal writing). In the second part of the driving period FP1 of the first frame (even-numbered frame), the scanning and illumination of pixels in the even-numbered rows are completed again (including Q-point reset and data signal writing).

[0089] In this embodiment, during the driving cycle of even-numbered frames (the first frame), pixels in odd-numbered rows and pixels in even-numbered rows are driven using different start signals (STV signals). The driving cycle of even-numbered frames (the first frame) is longer than that of odd-numbered frames (the second frame). Furthermore, for even-numbered frames, pixels in even-numbered rows begin to emit light when the brightness of pixels in odd-numbered rows has decreased to half due to leakage current. That is, when the brightness of pixels in odd-numbered rows decreases to half, pixels in even-numbered rows begin to emit light. The light emitted by pixels in even-numbered rows can compensate for the brightness decrease caused by leakage current in pixels in odd-numbered rows. Thus, the average waveform of pixel brightness in odd and even rows under human vision can be considered as the waveform of pixel brightness driven at a frequency of 30Hz. In other words, through the technical solution of this application, when the frame frequency of the display panel switches from 30Hz to 15Hz, the brightness difference of the display panel can be reduced, thereby improving flickering.

[0090] The third embodiment of the display panel provided in this application is similar to the first or second embodiment described above, except that:

[0091] The driving cycle of the first frame (even-numbered frame) also includes a first blank time period and a second blank time period. The first blank time period is continuous in time with the first sub-driving cycle, and the second blank time period is continuous in time with the second sub-driving cycle. The first blank time period is after the first sub-driving cycle, and the second blank time period is after the second sub-driving cycle. The sum of the first sub-driving cycle, the second sub-driving cycle, the first blank time period, and the second blank time period is less than or equal to the driving cycle of the first frame (even-numbered frame).

[0092] The gate driving circuit is used to sequentially output multiple reset signals to the pixels of multiple odd-numbered rows of the display panel at a fourth frequency during the first blank time period. The fourth frequency is the same as the first frequency (e.g., 30Hz) or a different frequency (e.g., 20Hz, 25Hz).

[0093] The source drive circuit is used to stop outputting the data signal of the first frame (even frame) to the pixels of the multiple odd-numbered rows of the display panel during the first blank time period.

[0094] The gate driving circuit is used to sequentially output multiple reset signals to the pixels of multiple even-numbered rows of the display panel at the fourth frequency during the second blank time period, and to stop outputting the data signal of the first frame (even-numbered frame) to the pixels of multiple even-numbered rows of the display panel. The fourth frequency is the same as the second frequency (e.g., 15Hz) or a different frequency (e.g., 20Hz, 25Hz).

[0095] The source drive circuit is used to stop outputting the data signal of the first frame (even-numbered frame) to the pixels of the even-numbered rows of the display panel during the second blank time period.

[0096] During the first blank time period and the second blank time period, outputting multiple reset signals sequentially to the pixels of multiple rows of the display panel can reset the Q point of the pixel circuit of each pixel to prevent Q point leakage. Stopping the output of data signals to the pixels of multiple rows of the display panel can reduce power consumption.

[0097] like Figure 8 , Figure 9 and Figure 10 As shown, in the driving cycle FP2 of the second frame (odd-numbered frame), the first clock signal line (CK1), the second clock signal line (CK2), the third clock signal line (CK3), and the fourth clock signal line (CK4) are used to output multiple clock signals that are staggered sequentially to the gate driving circuit. The gate driving circuit is used to generate multiple third scan signals for all rows of pixels according to the clock signals, and to output the multiple third scan signals sequentially to the pixels of multiple rows. The data driving circuit is used to generate data signals and output them to the pixels of the pixel array of the display panel. After the driving cycle FP2 of the second frame (odd-numbered frame) ends, the driving cycle FP1 of the first frame (even-numbered frame) begins. In the driving cycle FP1 of the first frame (even-numbered frame), the first clock signal line (CK1), the second clock signal line (CK2), the third clock signal line (CK3), and the fourth clock signal line (CK4) are used to output a plurality of clock signals that are staggered in sequence to the gate driving circuit. The gate driving circuit is used to generate a first scan signal for the odd-numbered rows of pixels and a second scan signal for the even-numbered rows of pixels according to the clock signals, and outputs the first scan signal and the second scan signal to the odd-numbered rows of pixels and the even-numbered rows of pixels respectively. The data driving circuit is used to generate data signals and output them to the pixels of the pixel array of the display panel.

[0098] In this embodiment, by adjusting the data signal writing time (scanning time) within the driving cycle of even-numbered frames (the first frame), the pixels in odd-numbered rows and even-numbered rows can complete the data signal writing in a shorter time. This results in an additional blank time period within the driving cycle of even-numbered frames (the first frame). Figure 10 As shown in the bolded section, during this blank period, the driving circuit does not output data signals to the pixels (pixels in each row), that is, it does not write data signals to the pixels (pixels in each row), but continues to output scan signals to the pixels (pixels in each row). This allows for the reset of the Q-point and prevents leakage at the Q-point. Since there is a blank period in the driving cycle during which no data signals are output to the pixels, the power consumption of the source driving circuit can be reduced to a certain extent.

[0099] The first embodiment of the display panel driving method provided in this application includes the following steps:

[0100] During the first sub-driving cycle of the first frame displayed on the display panel, a plurality of first scan signals are sequentially output to the pixels of a plurality of odd-numbered rows of the display panel at a first frequency, starting from the pixels of the first odd-numbered row of the display panel.

[0101] The driving cycle of a frame includes multiple sub-driving cycles, such as a first sub-driving cycle, a second sub-driving cycle, etc. In the driving cycle of a frame, the driving circuit of the display panel drives the pixels of all rows, that is, the driving circuit provides scanning signals to the pixels of all rows.

[0102] The first sub-driving cycle is the period during which the driving circuit provides scanning signals to the pixels of the odd-numbered rows (i.e., the first row, the third row, the fifth row, ..., the 2n-1th row, etc.) of the display panel.

[0103] In the first sub-driving cycle, the driving circuit first outputs a scanning signal to the TFT gate of the first row of pixels, so that the TFT of the first row of pixels is in the conducting state. At the same time, it provides data signals corresponding to the image content to be displayed to the first row of pixels. At this time, the first row of pixels will emit light of corresponding brightness to complete the display of the image of the first row of pixels.

[0104] After outputting the scan signal to the pixels in the first row, the driving circuit then outputs the scan signal to the TFT gate of the third row of pixels, so that the TFT of the third row of pixels is in the conducting state. Then, it provides the pixels in this row with a data signal corresponding to the image content to be displayed. At this time, the pixels in the third row will emit light of corresponding brightness to complete the display of the image of the third row of pixels.

[0105] And so on, within the first sub-driving cycle, the image display of all odd-numbered rows, such as the fifth and seventh rows, is completed sequentially.

[0106] During the second sub-driving cycle of the first frame, a plurality of second scan signals are sequentially output to the pixels of a plurality of even-numbered rows of the display panel at a second frequency, starting from the pixels of the first even-numbered row of the display panel.

[0107] The second sub-driving cycle is the period during which the driving circuit provides scanning signals to the pixels of the even-numbered rows (i.e., the second row, the fourth row, the sixth row, ..., the 2nth row, etc.) of the display panel.

[0108] The second sub-driving cycle begins after the first sub-driving cycle ends. In the second sub-driving cycle, the driving circuit first outputs a scan signal to the gate of the TFT of the second row of pixels, turning on the TFT of the second row of pixels. At the same time, it provides data signals corresponding to the image content to be displayed to the second row of pixels. At this time, the second row of pixels emits light of corresponding brightness to complete the display of the image of the second row of pixels.

[0109] After outputting the scan signal to the pixels in the second row, the driving circuit then outputs the scan signal to the gate of the TFT of the pixels in the fourth row, so that the TFT of the pixels in the fourth row is in the conducting state. At the same time, it provides the pixels in the fourth row with data signals corresponding to the image content to be displayed. At this time, the pixels in the fourth row emit light of corresponding brightness to complete the display of the image of the pixels in the second row.

[0110] And so on, during the second sub-driving cycle, the image display of all even-numbered rows, such as the sixth and eighth rows, is completed sequentially.

[0111] When the second sub-drive cycle ends, the image of all pixels in the first frame is displayed, and then the drive cycle for another frame (e.g., the second frame) begins, and the cycle repeats.

[0112] Wherein, the sum of the first sub-drive cycle and the second sub-drive cycle is less than or equal to the drive cycle of the first frame, the first frequency (e.g., 30Hz) is greater than the second frequency (e.g., 15Hz), the second sub-drive cycle is greater than the first sub-drive cycle, the second sub-drive cycle is continuous with the first sub-drive cycle in time, and the second sub-drive cycle is after the first sub-drive cycle.

[0113] The method further includes the following steps:

[0114] During the driving cycle of the first frame, a first data signal is output to the pixels of multiple rows of the display panel. That is, during the first sub-driving cycle and the second sub-driving cycle, the data signal of the first frame is input to the pixels where the thin-film transistor switches are turned on under the control of the first scan signal and the second scan signal.

[0115] The first frequency is greater than the second frequency, the first frequency is an integer multiple of the second frequency, and the second sub-drive period is an integer multiple of the first sub-drive period. For example, the first frequency is 2, 3, 4, etc., of the second frequency, and the second sub-drive period is 2, 3, 4, etc., of the first sub-drive period. The first frequency may be, for example, 30Hz, and the second frequency may be, for example, 15Hz.

[0116] The step of sequentially outputting a plurality of first scan signals to a plurality of odd-numbered rows of pixels on the display panel at a first frequency, starting from the pixels of the first odd-numbered row of the display panel during the first sub-driving cycle of the first frame displayed on the display panel, includes:

[0117] Receive the first start signal.

[0118] During the first sub-driving cycle of the first frame displayed on the display panel, according to the first start signal, a plurality of first scan signals are sequentially output to the pixels of a plurality of odd-numbered rows of the display panel at a first frequency, starting from the pixels of the first odd-numbered row of the display panel.

[0119] The step of sequentially outputting a plurality of second scan signals to pixels in a plurality of even-numbered rows of the display panel at a second frequency, starting from the pixels in the first even-numbered row of the first frame during the second sub-driving cycle, includes:

[0120] Receive the second start signal.

[0121] During the second sub-driving cycle of the first frame, according to the second start signal, a plurality of second scan signals are sequentially output to the pixels of a plurality of even-numbered rows of the display panel at a second frequency, starting from the pixels of the first even-numbered row of the display panel.

[0122] The gate drive circuit receives a first start signal from the timing controller of the display panel, the first start signal indicating that the first sub-drive cycle can be started.

[0123] Upon receiving the first start signal, the gate drive circuit generates a first scan signal to be provided to the pixels in the odd-numbered rows.

[0124] Specifically, during a first time period of the first sub-driving cycle, the gate driving circuit provides a scan signal to the gate of the thin-film transistor (TFT) of the first row of pixels to turn on the TFTs of the first row of pixels. Simultaneously with providing the scan signal to the first row of pixels, the source driving circuit also provides a data signal corresponding to the image content of the first row of pixels. Next, during a second time period of the first sub-driving cycle, the gate driving circuit provides a scan signal to the gate of the TFT of the third row of pixels to turn on the TFTs of the third row of pixels. Simultaneously with providing the scan signal to the third row of pixels, the source driving circuit also provides a data signal corresponding to the image content of the third row of pixels. This process continues, and during the nth time period of the first sub-driving cycle, the gate driving circuit provides a scan signal to the gate of the TFT of the (2n-1)th row of pixels to turn on the TFTs of the (2n-1)th row of pixels, while the source driving circuit also provides a data signal corresponding to the image content of the (2n-1)th row of pixels.

[0125] The driving circuit receives a second start signal from the timing controller of the display panel, the second start signal indicating that the second sub-driving cycle can be started.

[0126] Upon receiving the second start signal, the gate drive circuit begins to generate a second scan signal for providing to the pixels in even-numbered rows.

[0127] Specifically, during the first time period of the second sub-driving cycle, the gate driving circuit provides a scan signal to the gate of the TFT of the second row of pixels to turn on the TFT of the second row of pixels. Simultaneously, the source driving circuit also provides a data signal corresponding to the image content of the second row of pixels to the second row of pixels. Next, during the second time period of the second sub-driving cycle, the gate driving circuit provides a scan signal to the gate of the TFT of the fourth row of pixels to turn on the TFT of the fourth row of pixels. Simultaneously, the source driving circuit also provides a data signal corresponding to the image content of the fourth row of pixels to the fourth row of pixels. This process continues, and during the nth time period of the second sub-driving cycle, the gate driving circuit provides a scan signal to the gate of the TFT of the 2nth row of pixels to turn on the TFT of the 2nth row of pixels. Simultaneously, the source driving circuit also provides a data signal corresponding to the image content of the 2nth row of pixels to the 2nth row of pixels.

[0128] After the second sub-drive cycle ends, the drive for the first frame is completed.

[0129] like Figure 3 and Figure 4As shown, in the first sub-driving cycle, the first clock signal line (CK1), the second clock signal line (CK2), the third clock signal line (CK3), and the fourth clock signal line (CK4) output multiple clock signals that are staggered in sequence to the gate driving circuit. The gate driving circuit generates a first scan signal for the odd-numbered rows of pixels and a second scan signal for the even-numbered rows of pixels according to the clock signals, and outputs the first scan signal and the second scan signal to the odd-numbered rows of pixels and the even-numbered rows of pixels, respectively. The data driving circuit generates a data signal and outputs it to the pixels of the pixel array of the display panel.

[0130] In this embodiment, the start signal (STV signal) for driving the pixels in the odd-numbered rows and the start signal (STV signal) for driving the pixels in the even-numbered rows are separate, and the pixels in the odd and even rows are driven at different frequencies.

[0131] The start signals (STV signals) for odd-numbered rows of pixels and even-numbered rows of pixels are independent. The driving frequency of even-numbered rows of pixels is lower (smaller) than that of odd-numbered rows. That is, the driving period of even-numbered rows of pixels is longer than that of odd-numbered rows (the driving period of even-numbered rows can be an integer multiple of the driving period of odd-numbered rows). This allows the Q-point of the pixel circuit to be reset more fully, and the data signal of the pixel circuit to be written more fully, resulting in a longer pixel emission time. For example, for odd-numbered rows of pixels, the driving circuit drives at a frequency of 30Hz (frame rate), and for even-numbered rows of pixels, it drives at a frequency of 15Hz (frame rate). In the first part of the driving cycle of each frame, the scanning and emission of all odd-numbered rows of pixels are completed (including Q-point reset and data signal writing), and the brightness waveform is as follows: Figure 4 As shown, in the latter part of the driving cycle of each frame, all even-numbered rows of pixels are scanned and illuminated (including Q-point reset and data signal writing), and the brightness waveform is as follows. Figure 4 As shown, the moment when the even-numbered rows of pixels start to emit light is exactly the alternation moment when the brightness of the pixels in the odd-numbered rows is reduced to half due to leakage current in the pixel circuit after they emit light. At this time, the brightness of the even-numbered rows of pixels can compensate for the brightness reduction of the odd-numbered rows of pixels caused by leakage current. Therefore, when switching from high frequency to low frequency, the brightness difference between each row of pixels can be reduced, the visual difference can be reduced, and the flickering phenomenon of the display panel can be improved.

[0132] The second embodiment of the display panel driving method provided in this application is similar to the first embodiment described above, except that:

[0133] In this embodiment, the driving cycles of two consecutive frames are different, that is, the driving cycle of the first frame is different from the driving cycle of the second frame.

[0134] Before the step of sequentially outputting a plurality of first scan signals to pixels of a plurality of odd rows of the display panel at a first frequency, starting from the pixels of the first odd row of the display panel during the first sub-driving cycle of the first frame (even-numbered frame) displayed on the display panel, the method further includes:

[0135] During the driving cycle of the second frame (odd frame) displayed on the display panel, multiple third scan signals are sequentially output to the pixels of multiple rows of the display panel at a third frequency, starting from the pixels of the first row of the display panel.

[0136] The second frame (odd-numbered frame) and the first frame (even-numbered frame) are two frames displayed consecutively on the display panel. Specifically, the driving cycle of the second frame (odd-numbered frame) is sequential with the first sub-driving cycle of the first frame (even-numbered frame). The second frame (odd-numbered frame) is displayed before the first frame (even-numbered frame), meaning the first sub-driving cycle of the first frame (even-numbered frame) follows the driving cycle of the second frame (odd-numbered frame). The third frequency is less than or equal to the first frequency, and may be, for example, 30Hz, 25Hz, or 20Hz. The driving cycle of the first frame (even-numbered frame) is greater than the driving cycle of the second frame (odd-numbered frame).

[0137] The method further includes the following steps:

[0138] During the driving cycle of the second frame (odd-numbered frame), a second data signal is output to the pixels of multiple rows of the display panel. That is, during the driving cycle of the second frame (odd-numbered frame), the data signal of the second frame (odd-numbered frame) is input to the pixels where the thin-film transistor switches are turned on under the control of the third scan signal.

[0139] Before the start of the driving cycle of the second frame (odd frame), the driving circuit receives a third start signal from the timing controller of the display panel, the third start signal indicating that the driving cycle of the second frame (odd frame) can be started.

[0140] Upon receiving the third start signal, the gate drive circuit begins to generate a third scan signal for providing to the pixels of the multiple rows (all rows).

[0141] Specifically, during the first time period of the driving cycle of the second frame (odd-numbered frames), the gate driving circuit provides a scan signal to the gate of the TFT of the first row of pixels to turn on the TFT of the first row of pixels. Simultaneously, the source driving circuit provides a data signal corresponding to the image content of the first row of pixels to the first row of pixels. Then, during the second time period of the driving cycle of the second frame (odd-numbered frames), the gate driving circuit provides a scan signal to the gate of the TFT of the second row of pixels to turn on the TFT of the second row of pixels. Simultaneously, the source driving circuit provides a data signal corresponding to the image content of the second row of pixels to the second row of pixels. This process continues, and during the 2n-th time period of the driving cycle of the second frame (odd-numbered frames), the gate driving circuit provides a scan signal to the gate of the TFT of the 2n-th row of pixels to turn on the TFT of the 2n-th row of pixels. Simultaneously, the source driving circuit provides a data signal corresponding to the image content of the 2n-th row of pixels to the 2n-th row of pixels.

[0142] After the driving cycle of the second frame (odd frame) ends, the driving of the second frame (odd frame) is completed.

[0143] The driving cycle of the second frame (odd-numbered frame) is less than the sum of the first sub-driving cycle and the second sub-driving cycle of the first frame (even-numbered frame).

[0144] As an improvement, the driving period of the first frame (even-numbered frame) is an integer multiple of the driving period of the second frame (odd-numbered frame). For example, the driving period of the first frame (even-numbered frame) is 2 times, 3 times, 4 times, etc., the driving period of the second frame (odd-numbered frame).

[0145] like Figure 5 , Figure 6 and Figure 7As shown, in the driving cycle FP2 of the second frame (odd-numbered frame), the first clock signal line (CK1), the second clock signal line (CK2), the third clock signal line (CK3), and the fourth clock signal line (CK4) output multiple clock signals that are staggered in sequence to the gate driving circuit. The gate driving circuit generates multiple third scan signals for all rows of pixels according to the clock signals and outputs the multiple third scan signals to the pixels of the multiple rows in sequence. The data driving circuit generates data signals and outputs them to the pixels of the pixel array of the display panel. After the driving cycle FP2 of the second frame (odd-numbered frame) ends, the driving cycle FP1 of the first frame (even-numbered frame) begins. In the driving cycle FP1 of the first frame (even-numbered frame), the first clock signal line (CK1), the second clock signal line (CK2), the third clock signal line (CK3), and the fourth clock signal line (CK4) output multiple clock signals that are staggered in sequence to the gate driving circuit. The gate driving circuit generates a first scan signal for the odd-numbered rows of pixels and a second scan signal for the even-numbered rows of pixels according to the clock signals, and outputs the first scan signal and the second scan signal to the odd-numbered rows of pixels and the even-numbered rows of pixels, respectively. The data driving circuit generates data signals and outputs them to the pixels of the pixel array of the display panel.

[0146] In this embodiment, for the second frame (odd-numbered frames), the pixels of each line are scanned and illuminated at a frequency of 30Hz (frame frequency) (including Q-point reset and data signal writing), and the brightness waveform is as follows. Figure 7 As shown, for the first frame (even-numbered frames), the scanning and illumination of pixels in both odd and even rows are completed with a longer period (lower frame rate) (including Q-point reset and data signal writing). The brightness waveform is as follows. Figure 7 As shown, the driving period FP1 of the first frame (even-numbered frame) can be an integer multiple of the driving period FP2 of the second frame (odd-numbered frame). In the first part of the driving period FP1 of the first frame (even-numbered frame), the scanning and illumination of pixels in the odd-numbered rows are completed first (including Q-point reset and data signal writing). In the second part of the driving period FP1 of the first frame (even-numbered frame), the scanning and illumination of pixels in the even-numbered rows are completed again (including Q-point reset and data signal writing).

[0147] In this embodiment, during the driving cycle of even-numbered frames (the first frame), pixels in odd-numbered rows and pixels in even-numbered rows are driven by different start signals (STV signals). The driving cycle of even-numbered frames (the first frame) is longer than that of odd-numbered frames (the second frame). Furthermore, for even-numbered frames, pixels in even-numbered rows begin to emit light when the brightness of pixels in odd-numbered rows has decreased to half due to leakage current. That is, when the brightness of pixels in odd-numbered rows decreases to half, pixels in even-numbered rows begin to emit light. The light emitted by pixels in even-numbered rows can compensate for the brightness decrease of pixels in odd-numbered rows caused by leakage current. Thus, the average waveform of the brightness of pixels in odd and even rows under human vision can be regarded as the waveform of pixel brightness under a frequency of 30Hz. In other words, through the technical solution of this application, when the frame frequency of the display panel is switched from 30Hz to 15Hz, the brightness difference of the display panel can be reduced, thereby improving the flicker phenomenon.

[0148] The third embodiment of the display panel driving method provided in this application is similar to the first or second embodiment described above, except that:

[0149] The driving cycle of the first frame (even-numbered frame) also includes a first blank time period and a second blank time period. The first blank time period is continuous in time with the first sub-driving cycle, and the second blank time period is continuous in time with the second sub-driving cycle. The first blank time period is after the first sub-driving cycle, and the second blank time period is after the second sub-driving cycle. The sum of the first sub-driving cycle, the second sub-driving cycle, the first blank time period, and the second blank time period is less than or equal to the driving cycle of the first frame (even-numbered frame).

[0150] The method further includes the following steps:

[0151] During the first blank time period, multiple reset signals are sequentially output to the pixels of multiple odd-numbered rows of the display panel at a fourth frequency, and the output of the data signal of the first frame (even-numbered frame) to the pixels of multiple odd-numbered rows of the display panel is stopped. The fourth frequency is the same as the first frequency (e.g., 30Hz) or a different frequency (e.g., 20Hz, 25Hz).

[0152] During the second blank time period, multiple reset signals are sequentially output to the pixels of multiple even-numbered rows of the display panel at the fourth frequency, and the output of the data signal of the first frame (even-numbered frame) to the pixels of multiple even-numbered rows of the display panel is stopped. The fourth frequency is the same as the second frequency (e.g., 15Hz) or a different frequency (e.g., 20Hz, 25Hz).

[0153] During the first blank time period and the second blank time period, outputting multiple reset signals sequentially to the pixels of multiple rows of the display panel can reset the Q point of the pixel circuit of each pixel to prevent Q point leakage. Stopping the output of data signals to the pixels of multiple rows of the display panel can reduce power consumption.

[0154] like Figure 8 , Figure 9 and Figure 10 As shown, in the driving cycle FP2 of the second frame (odd-numbered frame), the first clock signal line (CK1), the second clock signal line (CK2), the third clock signal line (CK3), and the fourth clock signal line (CK4) output multiple clock signals that are staggered in sequence to the gate driving circuit. The gate driving circuit generates multiple third scan signals for all rows of pixels according to the clock signals and outputs the multiple third scan signals to the pixels of the multiple rows in sequence. The data driving circuit generates data signals and outputs them to the pixels of the pixel array of the display panel. After the driving cycle FP2 of the second frame (odd-numbered frame) ends, the driving cycle FP1 of the first frame (even-numbered frame) begins. In the driving cycle FP1 of the first frame (even-numbered frame), the first clock signal line (CK1), the second clock signal line (CK2), the third clock signal line (CK3), and the fourth clock signal line (CK4) output multiple clock signals that are staggered in sequence to the gate driving circuit. The gate driving circuit generates a first scan signal for the odd-numbered rows of pixels and a second scan signal for the even-numbered rows of pixels according to the clock signals, and outputs the first scan signal and the second scan signal to the odd-numbered rows of pixels and the even-numbered rows of pixels, respectively. The data driving circuit generates data signals and outputs them to the pixels of the pixel array of the display panel.

[0155] In this embodiment, by adjusting the data signal writing time (scanning time) within the driving cycle of even-numbered frames (the first frame), the pixels in odd-numbered rows and even-numbered rows can complete the data signal writing in a shorter time. This results in an additional blank time period within the driving cycle of even-numbered frames (the first frame). Figure 10 As shown in the bolded section, during this blank period, the driving circuit does not output data signals to the pixels (pixels in each row), that is, it does not write data signals to the pixels (pixels in each row), but continues to output scan signals to the pixels (pixels in each row). This allows for the reset of the Q-point and prevents Q-point leakage. Since there is a blank period in the driving cycle during which no data signals are output to the pixels, the power consumption of the source driving circuit can be reduced to a certain extent.

[0156] The specific embodiments of this application have been described in detail above. The embodiments disclosed above are merely preferred embodiments of this application. Those skilled in the art can make many modifications and improvements without departing from the concept of this application. All such modifications and improvements fall within the scope of protection defined by the claims of this application.

Claims

1. A display panel driving method, characterized in that, include: During the first sub-driving cycle of the first frame displayed on the display panel, a plurality of first scan signals are sequentially output to the pixels of a plurality of odd-numbered rows of the display panel at a first frequency; During the second sub-driving cycle of the first frame, a plurality of second scan signals are sequentially output to the pixels of a plurality of even-numbered rows of the display panel at a second frequency; The second sub-driving cycle is continuous with the first sub-driving cycle in time, and the second sub-driving cycle is after the first sub-driving cycle. The first frequency is greater than the second frequency. During the first sub-driving cycle and the second sub-driving cycle, the data signal of the first frame is input to the pixel where the thin-film transistor switch is turned on under the control of the first scan signal and the second scan signal.

2. The display panel driving method as described in claim 1, characterized in that, The first frequency is an integer multiple of the second frequency.

3. The display panel driving method as described in claim 1, characterized in that, The step of sequentially outputting a plurality of first scan signals to pixels in a plurality of odd-numbered rows of the display panel at a first frequency during a first sub-driving cycle of the first frame displayed on the display panel includes: Receive the first start signal; During the first sub-driving cycle of the first frame displayed on the display panel, a plurality of first scan signals are sequentially output to the pixels of a plurality of odd-numbered rows of the display panel at a first frequency according to the first start signal. The step of sequentially outputting a plurality of second scan signals to the pixels of a plurality of even-numbered rows of the display panel at a second frequency during the second sub-driving cycle of the first frame includes: Receive the second start signal; During the second sub-driving cycle of the first frame, a plurality of second scan signals are sequentially output to the pixels of a plurality of even-numbered rows of the display panel at a second frequency according to the second start signal.

4. The display panel driving method as described in claim 1, characterized in that, Before the step of sequentially outputting a plurality of first scan signals at a first frequency to pixels in a plurality of odd-numbered rows of the display panel during the first sub-driving cycle of the first frame displayed on the display panel, the method further includes: During the driving cycle of the second frame displayed on the display panel, multiple third scan signals are sequentially output to the pixels of multiple rows of the display panel at a third frequency; Wherein, the driving cycle of the second frame is continuous in time with the first sub-driving cycle of the first frame, the third frequency is less than or equal to the first frequency, and within the driving cycle of the second frame, the data signal of the second frame is input to the pixel that is turned on by the thin-film transistor switch under the control of the third scanning signal.

5. The display panel driving method according to any one of claims 1 to 4, characterized in that, The driving cycle of the first frame also includes a first blank time period and a second blank time period. The first blank time period is after the first sub-driving cycle, and the second blank time period is after the second sub-driving cycle. The method further includes: During the first blank time period, multiple reset signals are sequentially output to the pixels of multiple odd-numbered rows of the display panel at a fourth frequency, and the output of the data signal of the first frame of the image to the pixels of multiple odd-numbered rows of the display panel is stopped. During the second blank time period, multiple reset signals are sequentially output to the pixels of multiple even-numbered rows of the display panel at the fourth frequency, and the output of the data signal of the first frame image to the pixels of multiple even-numbered rows of the display panel is stopped.

6. A display panel, characterized in that, include: A pixel array, consisting of multiple rows of pixels; as well as The driving circuit is configured to sequentially output a plurality of first scan signals to a plurality of odd-numbered rows of pixels on the display panel at a first frequency during a first sub-driving cycle of a first frame of the display panel, and to sequentially output a plurality of second scan signals to a plurality of even-numbered rows of pixels on the display panel at a second frequency during a second sub-driving cycle of the first frame of the display panel. The second sub-driving cycle is continuous with the first sub-driving cycle in time, and the second sub-driving cycle is after the first sub-driving cycle. The first frequency is greater than the second frequency. During the first sub-driving cycle and the second sub-driving cycle, the data signal of the first frame is input to the pixel where the thin-film transistor switch is turned on under the control of the first scan signal and the second scan signal.

7. The display panel as described in claim 6, characterized in that, The first frequency is an integer multiple of the second frequency.

8. The display panel as described in claim 6, characterized in that, The driving circuit is configured to receive a first start signal and, within a first sub-driving cycle of the first frame displayed on the display panel, sequentially output a plurality of first scan signals to a plurality of odd-numbered rows of pixels on the display panel at a first frequency according to the first start signal; and to receive a second start signal and, within a second sub-driving cycle of the first frame, sequentially output a plurality of second scan signals to a plurality of even-numbered rows of pixels on the display panel at a second frequency according to the second start signal.

9. The display panel as described in claim 6, characterized in that, The driving circuit is also used to output multiple third scan signals to the pixels of multiple rows of the display panel at a third frequency during the driving cycle of the second frame displayed on the display panel. Wherein, the driving cycle of the second frame is continuous in time with the first sub-driving cycle of the first frame, the first sub-driving cycle of the first frame is after the driving cycle of the second frame, the third frequency is less than or equal to the first frequency, and within the driving cycle of the second frame, the data signal of the second frame is input to the pixel that is turned on by the thin-film transistor switch under the control of the third scanning signal.

10. The display panel as described in any one of claims 6 to 9, characterized in that, The driving cycle of the first frame also includes a first blank time period and a second blank time period. The first blank time period is after the first sub-driving cycle, and the second blank time period is after the second sub-driving cycle. The driving circuit is configured to sequentially output multiple reset signals to the pixels of multiple odd-numbered rows of the display panel at a fourth frequency during the first blank time period, and to stop outputting the data signal of the first frame image to the pixels of multiple odd-numbered rows of the display panel; and to sequentially output multiple reset signals to the pixels of multiple even-numbered rows of the display panel at the fourth frequency during the second blank time period, and to stop outputting the data signal of the first frame image to the pixels of multiple even-numbered rows of the display panel.

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