Driving chip, display panel and driving method thereof

Abstract

The application provides a driving chip, a display panel and a driving method thereof. The driving chip comprises a voltage adjustment module configured to receive a first voltage signal output by a power module and adjust the first voltage signal to generate a second voltage signal (smaller than the first voltage signal) at at least one gray scale value; a gamma module configured to generate a plurality of first gamma reference voltages according to the first voltage signal or generate a plurality of second gamma reference voltages according to the second voltage signal; and a buffer module configured to output a target data signal (generated according to the plurality of first gamma reference voltages or the plurality of second gamma reference voltages) to a corresponding data line, and further configured to receive the second voltage signal, generate a current signal according to the second voltage signal and transmit the current signal to the corresponding data line, thereby reducing the power consumption of the driving chip and the display panel.

Description

Technical Field

[0001] This invention relates to the field of display technology, and more particularly to the manufacture of display devices, specifically to driver chips, display panels, and driving methods thereof. Background Technology

[0002] With the further improvement of energy efficiency standards, energy consumption indicators have also increased.

[0003] In the panel industry, overall power consumption targets also need to be reduced significantly. Therefore, low-power technologies and algorithms will be a mandatory requirement for next-generation driver chips. To meet energy consumption standards, it is necessary to optimize the power consumption of driver chips and enhance the competitiveness of panel products. Summary of the Invention

[0004] The purpose of this invention is to provide a driver chip, a display panel, and a driving method thereof, so as to reduce the power consumption of existing driver chips and display panels containing driver chips.

[0005] This invention provides a driver chip for use in a display panel, the display panel including multiple data lines and multiple sub-pixels, the driver chip being electrically connected to the multiple sub-pixels through the multiple data lines to drive the multiple sub-pixels to emit light, including:

[0006] The power module is used to generate the first voltage signal;

[0007] A voltage adjustment module, electrically connected to the power supply module, is used to receive the first voltage signal and adjust the first voltage signal to generate a second voltage signal at at least one grayscale value, wherein the value of the second voltage signal is less than the value of the first voltage signal.

[0008] The gamma module is electrically connected to the power module to receive the first voltage signal and generate a plurality of first gamma reference voltages based on the first voltage signal, or is electrically connected to the voltage adjustment module to receive the second voltage signal and generate a plurality of second gamma reference voltages based on the second voltage signal.

[0009] A buffer module is electrically connected to the gamma module and the corresponding data line, and is used to output a target data signal to the corresponding data line. The target data signal is generated based on a plurality of first gamma reference voltages or a plurality of second gamma reference voltages.

[0010] The buffer module is also electrically connected to the voltage adjustment module and the corresponding data line, and is used to receive the second voltage signal, generate a current signal according to the second voltage signal, and transmit the current signal to the corresponding data line.

[0011] In one embodiment, the voltage adjustment module is used to adjust the first voltage signal to generate the second voltage signal at a certain grayscale value, and the driver chip further includes:

[0012] The judgment module is electrically connected to the voltage adjustment module and is used to acquire the image signal of the sub-pixel and generate a first control signal when the image signal is within the target range. The image signal is related to the grayscale value.

[0013] The voltage adjustment module is used to adjust the first voltage signal according to the first control signal to generate the second voltage signal;

[0014] The gamma module is electrically connected to the voltage adjustment module to receive the second voltage signal and generate a plurality of second gamma reference voltages based on the second voltage signal. The target data signal is generated based on the plurality of second gamma reference voltages.

[0015] In one embodiment, the image signal is an initial data signal of the sub-pixel, and the target range is a range of a minimum value greater than the absolute value of the initial data signal and a maximum value less than the absolute value of the initial data signal, wherein the initial data signal is generated based on a plurality of first gamma reference voltages.

[0016] In one embodiment, the initial data signal is an analog signal, and the judgment module includes at least one comparator, the comparator comprising:

[0017] The comparison input is used to load the initial data signal;

[0018] A comparison reference end is used to load the target signal corresponding to the target range;

[0019] The comparison output is used to generate a signal to be processed based on the initial data signal and the target signal;

[0020] The judgment module may further include a processing module electrically connected between the comparison output terminal and the voltage adjustment module, the processing module being used to generate the first control signal based on the signal to be processed.

[0021] In one embodiment, the image signal is the grayscale signal of the sub-pixel, and the target range is a range greater than the minimum value of the grayscale signal and less than the maximum value of the grayscale signal;

[0022] The target data signal is generated based on one of a plurality of first gamma reference voltages, a plurality of second gamma reference voltages, and the grayscale signal.

[0023] In one embodiment, the grayscale signal is a digital signal, comprising a plurality of grayscale data arranged sequentially, each grayscale data being equal to 0 or 1, and the judgment module comprising:

[0024] Multiple input terminals are used to load multiple grayscale data respectively;

[0025] The output terminal is used to output the first control signal when the grayscale signal is within the target range.

[0026] In one embodiment, the voltage adjustment module includes:

[0027] A logic module includes a logic input terminal and multiple logic output terminals. The logic input terminal is electrically connected to the judgment module. The logic module is used to generate a third control signal based on the first control signal. The third control signal includes multiple control voltages arranged in sequence. The multiple logic output terminals are respectively loaded with the multiple control voltages.

[0028] A resistor string includes multiple resistors connected in series. The first end of the resistor string is electrically connected to the power module to load the first voltage signal, and the second end of the resistor string is grounded.

[0029] Multiple switching elements are provided, each of which includes a switch input terminal, a switch output terminal, and a switch control terminal. Each switch input terminal is electrically connected between the first terminal and an adjacent resistor, or between two adjacent resistors. The multiple switch control terminals are respectively electrically connected to multiple logic output terminals to respectively load multiple control voltages. The multiple switch output terminals are all electrically connected to the buffer module.

[0030] In one embodiment, the voltage adjustment module is used to adjust the first voltage signal to generate the second voltage signal at each grayscale value, the gamma module is electrically connected to the power module to receive the first voltage signal and generate a plurality of first gamma reference voltages based on the first voltage signal, and the target data signal is generated based on the plurality of first gamma reference voltages.

[0031] The present invention also provides a display panel, including a panel body and a driving chip as described above, electrically connected to the panel body.

[0032] This invention provides a driving method for a display panel, executed by any of the driving chips described above, to control the brightness of the light emitted by a plurality of sub-pixels, comprising:

[0033] The voltage adjustment module receives a first voltage signal output by the power module, and adjusts the first voltage signal to generate a second voltage signal at at least one grayscale value, wherein the value of the second voltage signal is less than the value of the first voltage signal;

[0034] The gamma module receives the first voltage signal and generates multiple first gamma reference voltages based on the first voltage signal, or receives the second voltage signal and generates multiple second gamma reference voltages based on the second voltage signal.

[0035] The buffer module outputs a target data signal to the corresponding data line, and the target data signal is generated based on a plurality of first gamma reference voltages or a plurality of second gamma reference voltages.

[0036] The buffer module receives the second voltage signal, generates a current signal based on the second voltage signal, and transmits the current signal to the corresponding data line.

[0037] This invention provides a driver chip, a display panel, and a driving method thereof. The driver chip is configured to include: a voltage adjustment module electrically connected to the power supply module, for receiving a first voltage signal and adjusting the first voltage signal to generate a second voltage signal at at least one grayscale value, wherein the value of the second voltage signal is less than the value of the first voltage signal; a gamma module electrically connected to the power supply module for receiving the first voltage signal and generating multiple first gamma reference voltages based on the first voltage signal, or electrically connected to the voltage adjustment module for receiving the second voltage signal and generating multiple second gamma reference voltages based on the second voltage signal; a buffer module electrically connected to the gamma module and the corresponding data line, for outputting a target data signal to the corresponding data line, wherein the target data signal is generated based on multiple first gamma reference voltages or multiple second gamma reference voltages; and the buffer module is also electrically connected to the voltage adjustment module and the corresponding data line for receiving the second voltage signal, generating a current signal based on the second voltage signal, and transmitting the current signal to the corresponding data line. The buffer module can generate a smaller current signal based on a smaller second voltage signal and transmit it to the corresponding data line, thereby reducing the power consumption of the driver chip and the display panel. Attached Figure Description

[0038] The present invention will be further described below with reference to the accompanying drawings. It should be noted that the accompanying drawings described below are merely for illustrating some embodiments of the present invention. Those skilled in the art can obtain other drawings based on these drawings without any creative effort.

[0039] Figures 1 to 4 A module diagram of a driver chip provided in an embodiment of the present invention.

[0040] Figure 5 A block diagram of a display panel provided in an embodiment of the present invention.

[0041] Figure 6 A flowchart of a display panel driving method provided in an embodiment of the present invention. Detailed Implementation

[0042] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the scope of protection of the present invention.

[0043] In the description of this invention, the terms "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Therefore, features defined with "first" or "second" may explicitly or implicitly include one or more of the stated features. Furthermore, it should be noted that the accompanying drawings only provide structures closely related to the invention, omitting some details less relevant to the invention. The purpose is to simplify the drawings and make the inventive points clear at a glance, not to indicate that the actual device is identical to the accompanying drawings. Figure 1 It is identical, but this is not a limitation of the actual device.

[0044] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of the invention. The appearance of this phrase at various points in the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0045] The present invention provides a driver chip, which may include, but is not limited to, the following embodiments and combinations thereof.

[0046] In one embodiment, a driver chip is applied to a display panel, the display panel including multiple data lines and multiple sub-pixels, the driver chip being electrically connected to the multiple sub-pixels via the multiple data lines to drive the multiple sub-pixels to emit light; such as Figure 1As shown, the driver chip 100 includes: a power supply module 30 for generating a first voltage signal VAA; a voltage adjustment module 20 electrically connected to the power supply module 30 for receiving the first voltage signal VAA and adjusting the first voltage signal VAA at at least one grayscale value to generate a second voltage signal VAA', wherein the value of the second voltage signal VAA' is less than the value of the first voltage signal VAA; and a gamma module 50 electrically connected to the power supply module 30 for receiving the first voltage signal VAA and generating a plurality of first gamma reference voltages GM1 based on the first voltage signal VAA, or electrically connected to the voltage adjustment module 20 for receiving the second gamma reference voltage GM1. The voltage signal VAA' is used to generate multiple second gamma reference voltages GM2 based on the second voltage signal VAA'; a buffer module 40 is electrically connected to the gamma module 50 and the corresponding data line, and is used to output a target data signal to the corresponding data line, wherein the target data signal is generated based on multiple first gamma reference voltages GM1 or multiple second gamma reference voltages GM2; wherein, the buffer module 40 is also electrically connected to the voltage adjustment module 20 and the corresponding data line, and is used to receive the second voltage signal VAA', generate a current signal I2 based on the second voltage signal VAA', and transmit the current signal I2 to the corresponding data line.

[0047] For ease of description, this example illustrates the arrangement of multiple sub-pixels along rows and columns in a display panel. The display panel may also include multiple gate lines, each gate line electrically connected to multiple sub-pixels in the same row. Each gate line transmits a corresponding gate signal to the corresponding row of sub-pixels, and the multiple rows of sub-pixels are turned on sequentially under the action of the corresponding multiple gate signals. Each data line is electrically connected to multiple sub-pixels in the same column, and each data line transmits a corresponding data string signal to the corresponding column of sub-pixels. The data string signal includes multiple data signals corresponding to the corresponding multiple sub-pixels and arranged sequentially. Each data signal has a corresponding data voltage. In conjunction with the sequential turning on of multiple rows of sub-pixels, the multiple data voltages of multiple data lines corresponding to multiple sub-pixels in the same row can be simultaneously transmitted to the corresponding row of sub-pixels. In this way, multiple rows of sub-pixels are turned on sequentially, and each row of sub-pixels is loaded with a corresponding data voltage during the turning-on phase to emit light of a corresponding brightness.

[0048] Based on the above discussion, the driving chip in this embodiment may include at least a source driving module, which may include multiple buffer modules 40 as described above. Each buffer module 40 may be electrically connected to a corresponding source line in a corresponding time period. Furthermore, each source line may be electrically connected to different data lines at different times. That is, each buffer module 40 may output a data voltage corresponding to one of the sub-pixels at each time (e.g., equal to the second data signal data2 in a certain state) to be transmitted to the corresponding sub-pixel through the corresponding source line and the corresponding data line.

[0049] In other cases, the voltage adjustment module 20 can also output a first voltage signal VAA. That is, the voltage adjustment module 20 only serves to transmit the first voltage signal VAA output by the power supply module 30. Correspondingly, in this case, the buffer module 40 can also generate a corresponding first current I1 (greater than the aforementioned current signal I2) based on the first voltage signal VAA and transmit it to the corresponding data line. This invention aims to illustrate the possibility that the voltage adjustment module 20 can output a second voltage signal VAA' to cause the buffer module 40 to generate a smaller current signal I2.

[0050] Understandably, by setting a voltage adjustment module 20 electrically connected between the power module 30 and the buffer module 40 in this invention, the first voltage signal VAA output by the power module 30 can be adjusted to generate a second voltage signal VAA' acting on the buffer module 40. This not only ensures that the power module 30 still outputs the first voltage signal VAA to act on other modules to maintain the other functions of the driver chip 100, but also allows the second voltage signal VAA' with a smaller voltage value to act on the buffer module 40, so that the buffer module 40 generates a smaller current signal I2. Thus, it can be considered that the power consumption of the driver chip 100 is reduced, and correspondingly, the power consumption of the entire display panel is also reduced.

[0051] In one embodiment, such as Figure 2As shown, the voltage adjustment module 20 is used to adjust the first voltage signal VAA to generate the second voltage signal VAA' under a certain grayscale value. The driver chip 100 further includes: a judgment module 10, electrically connected to the voltage adjustment module 20, used to acquire the image signal sig of the sub-pixel, and generate a first control signal con1 when the image signal sig is within the target range. The image signal sig is related to the grayscale value of the sub-pixel's emission (i.e., related to its brightness). The voltage adjustment module 20 is used to adjust the first voltage signal VAA to generate the second voltage signal VAA' according to the first control signal con1. The gamma module 50 is electrically connected to the voltage adjustment module 20 to receive the second voltage signal VAA' and generate a plurality of second gamma reference voltages GM2 according to the second voltage signal VAA'. The target data signal is generated according to the plurality of second gamma reference voltages GM2.

[0052] Specifically, the first voltage signal VAA generated by the power supply module 30 acts on the buffer module 40 to generate a corresponding first current I1. Based on this, this embodiment also provides a voltage adjustment module 20 electrically connected to the buffer module 40 and a judgment module 10 electrically connected to the voltage adjustment module 20. The judgment module 10 is used to obtain the image signal sig of the sub-pixel, and when the image signal sig is within the target range (that is, under the corresponding partial grayscale value), it generates a first control signal con1. This first control signal con1 can be used by the voltage adjustment module 20 to adjust the first voltage signal VAA generated by the power supply module 30 to generate a second voltage signal VAA' that is smaller than the first voltage signal VAA. Correspondingly, the current signal I2 generated by the buffer module 40 based on the smaller second voltage signal VAA' is also smaller, which can be less than the first current I1. Thus, it can be considered that the power consumption of the driver chip 100 has been reduced, and correspondingly, the power consumption of the entire display panel has also been reduced.

[0053] Understandably, by adding the voltage adjustment module 20 and the judgment module 10 in this embodiment, a first control signal con1 can be generated at least when the image signal sig is within the target range. Furthermore, the first control signal con1 adjusts the larger first voltage signal VAA to a smaller second voltage signal VAA', causing the current output by the buffer module 40 to change from a larger first current I1 to a smaller current signal I2, thereby reducing the power consumption of the driver chip 10 and the corresponding display panel. Here, the target range is not limited; it can be understood that in this embodiment, the range of the image signal sig (related to the brightness of the sub-pixel emission) that can be used to reduce power consumption is limited. That is, power consumption is not reduced (i.e., a smaller second voltage signal VAA' is generated) at any brightness level of the sub-pixel emission, thus balancing optimal display parameters and lower power consumption of the display panel.

[0054] Furthermore, in this embodiment, both the gamma module 50 and the buffer module 40 are electrically connected to the voltage adjustment module 20, which can reduce the need to differentiate the source of the signals acquired by the gamma module 50 and the buffer module 40, thereby reducing the types of signals, reducing the number of pins, and lowering the cost of the driver chip 100.

[0055] In one embodiment, such as Figure 2 As shown, the image signal sig is the initial data signal data1 of the sub-pixel, and the target range is the range of the minimum value greater than the absolute value of the initial data signal data1 and the maximum value less than the absolute value of the initial data signal data1. The initial data signal data1 is generated based on a plurality of first gamma reference voltages GM1 (that is, based on the first voltage signal VAA).

[0056] It should be noted that the target data signal output by the buffer module 40 can be equal to the initial data signal data1 generated based on multiple first gamma reference voltages GM1, or it can be equal to the non-initial data signal data2 generated based on multiple second gamma reference voltages GM2. The initial data signal data1 acquired by the judgment module 10 can be understood as follows: when the grayscale value corresponding to each sub-pixel is transmitted to the gamma module 50, the gamma module 50 can by default generate multiple first gamma reference voltages GM1 (it can be assumed that the voltage adjustment module 20 has not yet received the first control signal con1 at this time, and therefore cannot adjust the first voltage signal VAA to generate the second voltage signal VAA'), so that the driver chip 100 can generate the initial data signal data1 corresponding to that sub-pixel based on this, and transmit this initial data signal data1 to the judgment module 10 for it to determine whether to generate the first control signal con1. In this embodiment, the image signal sig is the initial data signal data1 of the sub-pixel. When the initial data signal data1 is within the target range, since the voltage adjustment module 20 has generated the second voltage signal VAA', the gamma module 50 will also generate multiple second gamma reference voltages GM2 accordingly, so that the final target data signal is equal to the non-initial data signal data2. That is, whether the non-initial data signal data2 will be generated needs to be determined based on the initial data signal data1.

[0057] Furthermore, such as Figure 2 As shown, in this embodiment, the judgment module 10 is also used to generate a second control signal con2 when the initial data signal data1 is outside the target range. Correspondingly, the voltage adjustment module 20 is also used to directly output a first voltage signal VAA according to the second control signal con2. Correspondingly, the buffer module 40 can also generate a first current I1 under the action of the first voltage signal VAA, that is, maintain the original first current I1. Correspondingly, the gamma module 50 also receives the first voltage signal VAA at this time. Similarly, the final target data signal is equal to the initial data signal data1.

[0058] It should be noted that the statement "the initial data signal data1 is generated based on the first voltage signal VAA, and the non-initial data signal data2 is generated based on the second voltage signal VAA'" can be understood as follows: regardless of whether the buffer module 40 is acted upon by the first voltage signal VAA or the second voltage signal VAA', it maintains the output of the initial data signal data1, and the only effect is on the magnitude of its output current. However, for the module that generates the target data signal, it can generate the initial data signal data1 or the non-initial data signal data2 based on the first voltage signal VAA or the second voltage signal VAA' to serve as the target data signal.

[0059] Furthermore, such as Figure 3 As shown, the driver chip 100 further includes a voltage conversion module 60, electrically connected to the gamma module 50, for generating the initial data signal data1 based on a plurality of first gamma reference voltages GM1, or for generating the non-initial data signal data2 based on a plurality of second gamma reference voltages GM2. That is, the voltage conversion module 60 here functions to "generate the initial data signal data1 or the non-initial data signal data2 as the target data signal based on the first voltage signal VAA or the second voltage signal VAA'".

[0060] Based on the above discussion, the first voltage signal VAA or the second voltage signal VAA' generated by the voltage adjustment module 20 can be considered as the basis for generating multiple gamma reference voltages. Specifically, it can be understood as the upper limit of multiple gamma reference voltages, with a corresponding lower limit of 0. Since the second voltage signal VAA' is less than the first voltage signal VAA, if the multiple gamma reference voltages are generated in the same way, then the multiple second gamma reference voltages GM2 can also be considered less than the multiple first gamma reference voltages GM1.

[0061] The number of gamma reference voltages is generally much smaller than the number of all data voltages (which correspond to all grayscale values ​​(integers)). Therefore, the voltage conversion module 60 can further generate corresponding data voltages based on the multiple corresponding gamma reference voltages and the grayscale values ​​corresponding to the sub-pixels. That is, the upper limit of the data voltage is the first voltage signal VAA or the second voltage signal VAA', and the lower limit is 0. In other words, when the voltage adjustment module 20 outputs the first voltage signal VAA and the second voltage signal VAA' respectively, the target data voltages generated by the voltage conversion module 60 corresponding to the same grayscale value are equal to the initial data signal data1 and the non-initial data signal data2 respectively.

[0062] Based on the above discussion, the value of the initial data signal data1 and the value of the non-initial data signal data2 in this embodiment can be understood as two possible values ​​of the data voltage. Furthermore, for the liquid crystal panel, considering the polarity reversal, the initial data signal data1 (i.e., the original value of the data voltage) has a certain range. The value of the initial data signal data1 can be greater than or equal to 0, or less than or equal to 0. Therefore, the difference between the value of the initial data signal data1 and 0 can be represented by the "absolute value of the initial data signal data1". Thus, the maximum and minimum values ​​of the "absolute value of the initial data signal data1" are non-zero numbers and 0, respectively. Furthermore, for the liquid crystal panel, two types, normally white or normally black, can be considered. That is, when the absolute value of the initial data signal data1 is equal to 0, the brightness of the liquid crystal panel is at its maximum or minimum value.

[0063] Based on the above discussion, the target range in this embodiment is the range between the minimum value greater than the absolute value of the initial data signal data1 and the maximum value less than the absolute value of the initial data signal data1. That is, the target range is any value other than the maximum and minimum values ​​of the absolute value of the initial data signal data1. Conversely, in this embodiment, when the initial data signal data1 is at its maximum absolute value (a non-zero value, either positive or negative) or minimum absolute value (equal to 0), that is, when the brightness of the display panel is at its maximum or minimum value (determined according to the two types of constant white or constant black), the voltage adjustment module 20 still outputs a relatively large first voltage signal VAA.

[0064] Following the above discussion, and considering that "the initial data signal data1 is generated based on the first voltage signal VAA" and "the image signal sig is related to the brightness of the sub-pixel's emission," it can be seen that when the initial data signal data1 is used to control the brightness of the display panel, theoretically at either the maximum or minimum value, in this embodiment, the control voltage adjustment module 20 is set to directly output a larger first voltage signal VAA to ensure that the corresponding sub-pixel is still affected by the initial data signal data1 to maintain the emission at the maximum or minimum brightness.

[0065] For LCD panels, there are two parameters: transmittance and contrast ratio. Transmittance is equal to Lmax / LB, and contrast ratio is equal to Lmax / Lmin. Lmax and Lmin represent the maximum and minimum brightness of the sub-pixels or the display panel (including all sub-pixels), respectively, and LB represents the backlight brightness of the display panel. As discussed above, in this embodiment, when the initial data signal data1 is used to control the brightness of the display panel to its theoretical maximum and minimum values, the display panel can indeed maintain the maximum and minimum brightness. That is, the display panel can still have constant transmittance and contrast ratio, which can ensure the stability of the transmittance and contrast ratio of the display panel (with better display parameters), so as to improve the image quality of the display panel while reducing power consumption.

[0066] In one embodiment, such as Figure 4 As shown, the initial data signal data1 is an analog signal. The judgment module 10 includes at least one comparator (which may include a first comparator 101 and a second comparator 102). The comparator (either the first comparator 101 or the second comparator 102) includes: a comparison input terminal A1 for loading the initial data signal data1; a comparison reference terminal (including but not limited to A21 and A22) for loading the target signal corresponding to the target range; and a comparison output terminal (including but not limited to A31 and A32) for generating a signal to be processed based on the initial data signal data1 and the target signal. The judgment module 10 may also include a processing module 103 electrically connected between the comparison output terminal and the voltage adjustment module 20. The processing module 103 is used to generate the first control signal con1 based on the signal to be processed.

[0067] in, Figure 4 Taking the initial data signal data1 (generated based on the corresponding grayscale signal and the first gamma reference voltage GM1 generated by the gamma module 50 by default) as an example, with the image signal sig as the sub-pixel, as discussed above, the target range is the range between the minimum value greater than the absolute value of the initial data signal data1 and the maximum value less than the absolute value of the initial data signal data1. Therefore, the target signal here can be set to include a first target signal and a second target signal, which can be the minimum and maximum absolute values ​​of the initial data signal data1, respectively. Furthermore, as discussed above, the gamma reference voltage can have an upper limit and a lower limit (which can be 0). Here, multiple gamma reference voltages are taken as Gamma1 to Gamma14, and the gamma reference voltage has a lower limit Gamma1 and an upper limit Gamma14. These can also be set as the first target signal and the second target signal, respectively.

[0068] Specifically, the comparison input terminals A1 of the first comparator 101 and the second comparator 102 are shorted and both are loaded with the initial data signal data1. According to the working principle of the comparators, if the initial data signal data1 is equal to the first target signal, then A31 can output the corresponding first value (otherwise it can output the second value). If the initial data signal data1 is equal to the second target signal, then A32 can output the corresponding first value (otherwise it can output the second value). The side where A31 and A32 both output the corresponding first value is called the comparison output terminal outputting the signal to be processed. Furthermore, the processing module 103 can generate a first control signal con1 according to the signal to be processed, so that the voltage adjustment module 20 generates a smaller second voltage signal VAA', thereby reducing the power consumption of the driver chip 100 and the display panel.

[0069] In one embodiment, such as Figure 3 As shown, the image signal sig is the grayscale signal gam of the sub-pixel, and the target range is the range greater than the minimum value of the grayscale signal gam and less than the maximum value of the grayscale signal gam. The target data signal is generated based on one of multiple first gamma reference voltages GM1, multiple second gamma reference voltages GM2, and the grayscale signal. As discussed above, each sub-pixel can have a corresponding grayscale signal gam and a corresponding data voltage. Specifically, the voltage conversion module 60 can generate the corresponding data voltage based on the grayscale value of the sub-pixel using multiple corresponding gamma reference voltages. For example, when the multiple reference voltages are multiple first gamma reference voltages GMA1 (generated based on the first voltage signal VAA), the target data voltage is equal to the initial data signal data1. Similarly, when the multiple reference voltages are multiple second gamma reference voltages GMA2 (generated based on the second voltage signal VAA'), the target data voltage is equal to the non-initial data signal data2.

[0070] Understandably, in this embodiment, the grayscale signal gam, generated prior to the initial data signal data1 and corresponding to it, is used as the aforementioned image signal sig. Since the two are in one-to-one correspondence, and the grayscale signal gam can only be greater than or equal to 0, the target range is the range greater than the minimum value (equal to 0) of the grayscale signal gam and less than the maximum value (e.g., 255) of the grayscale signal gam; unlike... Figure 4 As shown, since the image signal sig is the grayscale signal gam of the sub-pixel (generally generated by the timing control module), the judgment module 10 is not electrically connected to the buffer module 40 used for output data voltage, but can be electrically connected to, for example, the timing control module.

[0071] Similarly, as discussed above, such as Figure 3As shown, the driver chip 100 also includes a gamma module 50 and a voltage conversion module 60 as described above. The voltage conversion module 60 is specifically used to generate the initial data signal based on a plurality of first gamma reference voltages GMA1 and the grayscale signal gam, or to generate the non-initial data signal based on a plurality of second gamma reference voltages GMA2 and the grayscale signal gam.

[0072] In one embodiment, the grayscale signal gam is a digital signal, comprising a plurality of grayscale data arranged sequentially, each of the grayscale data being equal to 0 or 1, different from... Figure 4 As shown, Figure 3 As shown, the judgment module 10 at this time includes: multiple judgment input terminals for loading multiple grayscale data respectively; and a judgment output terminal for outputting the first control signal con1 when the grayscale signal gam is within the target range.

[0073] Specifically, the number of judgment input terminals can be equal to the number of grayscale data in the grayscale signal gam. Here, we take the grayscale signal gam as a binary signal as an example. That is, each judgment input terminal is loaded with 0 or 1. Furthermore, for example, each judgment input terminal can be connected to a sub-judgment device (which may include, but is not limited to, gate circuits). The multiple sub-judgment output terminals corresponding to multiple sub-judgment devices can be electrically connected to another gate circuit, and the output terminal of the gate circuit can be used as the above-mentioned judgment output terminal.

[0074] Understandably, in this embodiment, it is equivalent to directly identifying the grayscale signal gam (digital signal) used to generate the simulated data voltage (corresponding signal) before generating the simulated data voltage (corresponding signal). The same "outputting the first control signal con1 when the grayscale signal gam is within the target range" can be achieved by reasonably setting the structure of the judgment module 10.

[0075] In one embodiment, such as Figure 4As shown, the voltage adjustment module 20 includes: a logic module 201, including a logic input terminal and multiple logic output terminals. The logic input terminal is electrically connected to the judgment module 10. The logic module 201 is used to generate a third control signal based on the first control signal con1. The third control signal includes multiple control voltages arranged in sequence (taking four control voltages V1, V2, V3, and V4 as an example). The multiple logic output terminals are respectively loaded with multiple control voltages. A voltage divider module 202 includes: a resistor string, including multiple resistors connected in series (the number is equal to the number of control voltages, taking R1, R2, R3, and R4 as an example). The first end of the resistor string is electrically connected to the first control input terminal. The first voltage signal VAA is loaded by connecting to the power module 30, and the second end of the resistor string is grounded; a plurality of switching elements (the number of which is equal to the number of control voltages, here Q1, Q2, Q3, and Q4 are used as an example), each of the switching elements includes a switch input terminal, a switch output terminal, and a switch control terminal, each of the switch input terminals is electrically connected between the first terminal and the adjacent resistor (for the resistor R1 closest to the first terminal), or between two adjacent resistors (for the remaining resistors R2, R3, and R4), the plurality of switch control terminals are electrically connected to the plurality of logic output terminals respectively to load the plurality of control voltages respectively, and the plurality of switch output terminals are all electrically connected to the buffer module 40.

[0076] in, Figure 4 The diagram only illustrates the case where the image signal sig is within the target range, i.e., the first control signal con1 is generated. Therefore, the logic module 201 generates a third control signal based on the first control signal con1. The third control signal satisfies the condition that multiple control voltages can control multiple switching elements respectively, so that multiple switch outputs can adjust a larger first voltage signal VAA to generate a smaller second voltage signal VAA'. Here, the multiple switching elements can essentially be multiple switching transistors. The switch control terminal is the gate of the corresponding switching transistor, the switch input terminal can be one of the source or drain of the switching transistor, and the switch output terminal can be the other of the source or drain of the switching transistor. In this embodiment, the setting of the number of gears (i.e., the number of resistors) and the value of VAA' corresponding to each gear (i.e., the value of the resistor) are not limited.

[0077] Specifically, such as Figure 4 As shown, based on the number of switching transistors being 4, the voltage divider module 202 can reduce the first voltage signal VAA by the following four levels (the number of levels can be equal to the number of switching transistors):

[0078] In the first gear, the VAA voltage remains unchanged. The logic module 201 needs to control Q1 to turn on and Q2, Q3, and Q4 to turn off. At this time, the output of the voltage adjustment module 20 is equivalent to being electrically connected to the first end of the resistor string. The voltage at this node is equal to the value of the first voltage signal VAA, so it can be considered that the first voltage signal VAA is still being output.

[0079] In the second gear, VAA' = VAA * (R2 + R3 + R4) / (R1 + R2 + R3 + R4), logic module 201 needs to control Q2 to be turned on and Q1, Q3, and Q4 to be turned off. At this time, the output of voltage adjustment module 20 is equivalent to being electrically connected between R1 and R2 in the resistor string. The voltage at this node is equivalent to the voltage division of "R2 + R3 + R4" in VAA.

[0080] The third level, VAA' = VAA * (R3 + R4) / (R1 + R2 + R3 + R4), requires logic module 201 to control Q3 to be turned on and Q1, Q2, and Q4 to be turned off. At this time, the output of voltage adjustment module 20 is equivalent to being electrically connected between R2 and R3 in the resistor string. The voltage at this node is equivalent to the voltage division of "R3 + R4" in VAA.

[0081] In the fourth gear, VAA' = VAA * R4 / (R1 + R2 + R3 + R4), logic module 201 needs to control Q4 to be turned on, while Q1, Q2, and Q3 are all turned off. At this time, the output of voltage adjustment module 20 is equivalent to being electrically connected between R3 and R4 in the resistor string. The voltage at this node is equivalent to the voltage division of "R4" in VAA.

[0082] It should be noted that in this embodiment, there is no limitation on whether the second voltage signals VAA' corresponding to image signals sig that are within the target range but have different values ​​are equal. For example, the second voltage signals VAA' corresponding to any image signal sig within the target range can be set to be equal, such as being equal to at least one of the second, third, and fourth levels. Alternatively, the second voltage signals VAA' corresponding to image signals sig with different values ​​within the target range can be set to be unequal. For example, the second voltage signals VAA' corresponding to image signals sig that are in the second, third, and fourth intervals can be respectively corresponding to the second, third, and fourth levels.

[0083] In other embodiments, such as Figure 1As shown by the dashed line, the voltage adjustment module 20 is used to adjust the first voltage signal VAA to generate the second voltage signal VAA' at each grayscale value. The gamma module 50 is electrically connected to the power supply module 30 to receive the first voltage signal VAA and generate a plurality of first gamma reference voltages GM1 based on the first voltage signal VAA. Each target data signal generates GM1 based on the plurality of first gamma reference voltages.

[0084] Understandably, in this embodiment, since the gamma module 50 is electrically connected to the power supply module 30, unlike the buffer module 40 which is electrically connected to the voltage adjustment module 20, regardless of the image signal, that is, at each gray level value, the gamma module 50 can generate multiple first gamma reference voltages GM1 based on the first voltage signal VAA, so that the final target data signal can be always equal to the initial data signal data1 of the sub-pixel, so as to avoid the target data signal being equal to the lower non-initial data signal data2, and to ensure that the brightness of the sub-pixel is not reduced due to whether the second voltage signal VAA' is output.

[0085] The present invention also provides a display panel, such as Figure 5 As shown, the display panel 1 may include a panel body 70 and a driver chip 100 electrically connected to the panel body 70 as described above. As discussed above, in conjunction with... Figures 3 to 5 As shown, the buffer module 40 can control whether a non-initial data signal data2 is generated based on the grayscale signal gam, depending on whether the voltage divider module 202 outputs a second voltage signal VAA', i.e., whether the gamma module 50 generates multiple second gamma reference voltages GM2. Simultaneously, it can also determine whether the buffer module 40 outputs a smaller second current I2. It should be noted that for each sub-pixel in each frame, the voltage adjustment module 20 can first output a first voltage signal VAA or a second voltage signal VAA' based on its corresponding image signal sig (initial data signal data1 or grayscale signal gam), and then electrically connect the buffer module 40 to the panel body 70 to transmit the final data voltage. Before this, the buffer module 40 can be disconnected from the panel body 70 to prevent increased power consumption of the display panel 1.

[0086] The present invention also provides a driving method for a display panel, for execution by a driving chip as described above, to control the brightness of the light emitted by a plurality of said sub-pixels, such as... Figure 6 As shown, the steps may include, but are not limited to, the following:

[0087] S1, the voltage adjustment module receives the first voltage signal output by the power module, and adjusts the first voltage signal to generate a second voltage signal at at least one grayscale value, wherein the value of the second voltage signal is less than the value of the first voltage signal;

[0088] Specifically, as can be referred to in the above description, the voltage adjustment module 20 can be electrically connected to the power supply module 30 to execute S1;

[0089] S2, the gamma module receives the first voltage signal and generates a plurality of first gamma reference voltages based on the first voltage signal, or receives the second voltage signal and generates a plurality of second gamma reference voltages based on the second voltage signal;

[0090] Specifically, as can be seen from the above description, the gamma module 50 can be electrically connected to the power module 30 to execute S2;

[0091] S3, the buffer module outputs a target data signal to the corresponding data line, the target data signal being generated based on a plurality of first gamma reference voltages or a plurality of second gamma reference voltages;

[0092] Specifically, as can be seen from the above description, the buffer module 40 can be electrically connected to the gamma module 50 and the corresponding data line to execute S3;

[0093] S4, the buffer module receives the second voltage signal, generates a current signal based on the second voltage signal, and transmits the current signal to the corresponding data line.

[0094] Specifically, as can be seen from the above description, the buffer module 40 can also be electrically connected to the voltage adjustment module 20 and the corresponding data line to execute S4.

[0095] Furthermore, the above-mentioned display panel driving method may also include, but is not limited to, the following steps:

[0096] S5, the judgment module acquires the image signal of the sub-pixel, and generates a first control signal when the image signal is within the target range, wherein the image signal is related to the brightness of the light emitted by the sub-pixel;

[0097] Specifically, as can be referred to in the above description, the judgment module 10 can be electrically connected to the voltage adjustment module 20 to execute S5, and S5 can be located before S1;

[0098] S101, the voltage adjustment module adjusts the first voltage signal according to the first control signal to generate the second voltage signal;

[0099] Specifically, S101 can be understood as a refinement of S1 based on S5.

[0100] This invention provides a driver chip, a display panel, and a driving method thereof. The driver chip is configured to include: a voltage adjustment module electrically connected to the power supply module, for receiving a first voltage signal and adjusting the first voltage signal to generate a second voltage signal at at least one grayscale level, wherein the value of the second voltage signal is less than the value of the first voltage signal; a gamma module electrically connected to the power supply module for receiving the first voltage signal and generating multiple first gamma reference voltages based on the first voltage signal, or electrically connected to the voltage adjustment module for receiving the second voltage signal and generating multiple second gamma reference voltages based on the second voltage signal; a buffer module electrically connected to the gamma module and the corresponding data line, for outputting a target data signal to the corresponding data line, wherein the target data signal is generated based on multiple first gamma reference voltages or multiple second gamma reference voltages; and the buffer module is also electrically connected to the voltage adjustment module and the corresponding data line for receiving the second voltage signal, generating a current signal based on the second voltage signal, and transmitting the current signal to the corresponding data line. The buffer module can generate a smaller current signal based on a smaller second voltage signal and transmit it to the corresponding data line, thereby reducing the power consumption of the driver chip and the display panel.

[0101] The driving chip, display panel, and driving method provided in the embodiments of the present invention have been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of the present invention. The descriptions of the above embodiments are only for the purpose of helping to understand the technical solutions and core ideas of the present invention. Those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. These modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A driver chip, applied to a display panel, the display panel including multiple data lines and multiple sub-pixels, the driver chip being electrically connected to the multiple sub-pixels via the multiple data lines to drive the multiple sub-pixels to emit light, characterized in that, include: The power module is used to generate the first voltage signal; A voltage adjustment module, electrically connected to the power supply module, is used to receive the first voltage signal and adjust the first voltage signal to generate a second voltage signal at at least one grayscale value, wherein the value of the second voltage signal is less than the value of the first voltage signal. The gamma module is electrically connected to the power module to receive the first voltage signal and generate a plurality of first gamma reference voltages based on the first voltage signal, or is electrically connected to the voltage adjustment module to receive the second voltage signal and generate a plurality of second gamma reference voltages based on the second voltage signal. A buffer module is electrically connected to the gamma module and the corresponding data line, and is used to output a target data signal to the corresponding data line. The target data signal is generated based on a plurality of first gamma reference voltages or a plurality of second gamma reference voltages. The buffer module is also electrically connected to the voltage adjustment module and the corresponding data line, and is used to receive the second voltage signal, generate a current signal according to the second voltage signal, and transmit the current signal to the corresponding data line. The voltage adjustment module is used to adjust the first voltage signal to generate the second voltage signal under certain grayscale values, and the driver chip further includes: The judgment module is electrically connected to the voltage adjustment module and is used to acquire the image signal of the sub-pixel and generate a first control signal when the image signal is within the target range. The image signal is related to the grayscale value. The voltage adjustment module is used to adjust the first voltage signal according to the first control signal to generate the second voltage signal; The gamma module is electrically connected to the voltage adjustment module to receive the second voltage signal and generate a plurality of second gamma reference voltages based on the second voltage signal. The target data signal is generated based on the plurality of second gamma reference voltages.

2. The driver chip as described in claim 1, characterized in that, The image signal is the initial data signal of the sub-pixel, and the target range is the range of the minimum value greater than the absolute value of the initial data signal and the maximum value less than the absolute value of the initial data signal. The initial data signal is generated based on a plurality of first gamma reference voltages.

3. The driver chip as described in claim 2, characterized in that, The initial data signal is an analog signal, and the judgment module includes at least one comparator, the comparator including: The comparison input is used to load the initial data signal; A comparison reference end is used to load the target signal corresponding to the target range; The comparison output is used to generate a signal to be processed based on the initial data signal and the target signal; The judgment module may further include a processing module electrically connected between the comparison output terminal and the voltage adjustment module, the processing module being used to generate the first control signal based on the signal to be processed.

4. The driver chip as described in claim 1, characterized in that, The image signal is the grayscale signal of the sub-pixel, and the target range is the range greater than the minimum value of the grayscale signal and less than the maximum value of the grayscale signal. The target data signal is generated based on one of a plurality of first gamma reference voltages, a plurality of second gamma reference voltages, and the grayscale signal.

5. The driver chip as described in claim 4, characterized in that, The grayscale signal is a digital signal, comprising multiple grayscale data arranged sequentially, each grayscale data being equal to 0 or 1. The judgment module includes: Multiple input terminals are used to load multiple grayscale data respectively; The output terminal is used to output the first control signal when the grayscale signal is within the target range.

6. The driver chip as described in claim 1, characterized in that, The voltage adjustment module includes: A logic module includes a logic input terminal and multiple logic output terminals. The logic input terminal is electrically connected to the judgment module. The logic module is used to generate a third control signal based on the first control signal. The third control signal includes multiple control voltages arranged in sequence. The multiple logic output terminals are respectively loaded with the multiple control voltages. A resistor string includes multiple resistors connected in series. The first end of the resistor string is electrically connected to the power module to load the first voltage signal, and the second end of the resistor string is grounded. Multiple switching elements are provided, each of which includes a switch input terminal, a switch output terminal, and a switch control terminal. Each switch input terminal is electrically connected between the first terminal and an adjacent resistor, or between two adjacent resistors. The multiple switch control terminals are respectively electrically connected to multiple logic output terminals to respectively load multiple control voltages. The multiple switch output terminals are all electrically connected to the buffer module.

7. The driver chip as described in claim 1, characterized in that, The voltage adjustment module is used to adjust the first voltage signal to generate the second voltage signal at each grayscale value. The gamma module is electrically connected to the power supply module to receive the first voltage signal and generate a plurality of first gamma reference voltages based on the first voltage signal. The target data signal is generated based on the plurality of first gamma reference voltages.

8. A display panel, characterized in that, It includes a panel body and a driver chip as described in any one of claims 1 to 7, which is electrically connected to the panel body.

9. A driving method for a display panel, characterized in that, For execution by the driver chip as described in any one of claims 1 to 7, to control the brightness of the light emitted by the plurality of said sub-pixels, including: The voltage adjustment module receives a first voltage signal output by the power module, and adjusts the first voltage signal to generate a second voltage signal at at least one grayscale value, wherein the value of the second voltage signal is less than the value of the first voltage signal; The gamma module receives the first voltage signal and generates multiple first gamma reference voltages based on the first voltage signal, or receives the second voltage signal and generates multiple second gamma reference voltages based on the second voltage signal. The buffer module outputs a target data signal to the corresponding data line, and the target data signal is generated based on a plurality of first gamma reference voltages or a plurality of second gamma reference voltages. The buffer module receives the second voltage signal, generates a current signal based on the second voltage signal, and transmits the current signal to the corresponding data line.

Images