Method, apparatus, system, device and medium for testing data retention performance

Abstract

A test method and device for data retention performance, an electronic device, and a storage medium. The method comprises: obtaining first and second corresponding relationship information of a to-be-tested memory; calculating, based on a preset number of failed bits index, a threshold voltage variation range corresponding to a non-failed storage unit before baking of the to-be-tested memory; determining, based on the threshold voltage variation range corresponding to the non-failed storage unit before baking of the to-be-tested memory and the second corresponding relationship information, a total number of tail storage units after baking of the to-be-tested memory; and determining, based on the total number of tail storage units after baking of the to-be-tested memory, the data retention performance of the to-be-tested memory. The above scheme can test the data retention performance of any memory on the same technical platform.

Description

Technical Field

[0001] This invention relates to the field of memory technology, and more specifically to a method, apparatus, electronic device, and storage medium for testing data retention performance. Background Technology

[0002] NAND flash memory can be used as a device for storing large amounts of data. Data retention performance is one of the important indicators for evaluating the reliability of NAND flash memory. Data retention performance refers to the ability of NAND flash memory to retain data without loss after data is written to it.

[0003] NAND Flash comprises a memory array, which contains a large number of memory cells arranged in an array. In the prior art, the data retention performance of NAND Flash is typically tested based on the threshold voltage Vt of the memory cells.

[0004] In practical applications, different NAND Flash chips may have different processes and operation methods. The operation methods can include writing, reading and deleting methods, which leads to different distributions of the threshold voltage Vt of the memory cells for different NAND Flash chips.

[0005] Currently, when testing the data retention performance of NAND Flash based on the threshold voltage Vt of the storage cell, it is necessary to consider specific processes and operating methods to determine the data retention performance of NAND Flash. There is no unified testing scheme to quantitatively test the data retention performance of different capacities or different NAND Flash products on the same platform. This is very detrimental to the comparison and optimization of NAND Flash during the product process optimization and improvement stage. Furthermore, there is no unified evaluation standard to determine the data retention performance of NAND Flash during the mass production stage. Summary of the Invention

[0006] The problem this invention aims to solve is: how to uniformly test the data retention performance of memory.

[0007] To address the aforementioned problems, this invention provides a method for testing data retention performance. The method includes: acquiring first and second correspondence information of the memory under test; wherein the first correspondence information is the correspondence between the threshold voltage of the memory cells and the number of memory cells before baking the memory under test; the second correspondence information is the correspondence between the threshold voltage of the memory cells and the number of memory cells after baking the memory under test; calculating the threshold voltage variation range corresponding to the non-failed memory cells before baking the memory under test based on a preset failure bit index; the preset failure bit index is used to characterize the number of failed memory cells in the memory under test; determining the total number of tail bits of memory cells after baking the memory under test based on the threshold voltage variation range corresponding to the non-failed memory cells before baking the memory under test and the second correspondence information; and determining the data retention performance of the memory under test based on the total number of tail bits of memory cells after baking the memory under test.

[0008] This invention also provides a data retention performance testing apparatus, comprising: an acquisition unit, adapted to acquire first correspondence information and second correspondence information of a memory under test; wherein the first correspondence information is the correspondence information between the threshold voltage of the memory cell and the number of memory cells before baking the memory under test; the second correspondence information is the correspondence information between the threshold voltage of the memory cell and the number of memory cells after baking the memory under test; a calculation unit, adapted to calculate, based on a preset failure bit index, the threshold voltage change range corresponding to the non-failed memory cells before baking the memory under test; the preset failure bit index is used to characterize the number of failed memory cells in the memory under test; a first determination unit, adapted to determine, based on the threshold voltage change range corresponding to the non-failed memory cells before baking the memory under test and the second correspondence information, the total number of tail bits of memory cells after baking the memory under test; and a second determination unit, adapted to determine the data retention performance of the memory under test based on the total number of tail bits of memory cells after baking the memory under test.

[0009] This invention also provides a testing system, which includes the above-described data retention performance testing device and a memory to be tested; the data retention performance testing device is connected to the memory to be tested and is adapted to test the data retention performance of the memory to be tested.

[0010] This invention also provides a computer-readable storage medium having a computer program stored thereon, the computer program being executed by a processor to implement the steps of any of the methods described above.

[0011] This invention also provides an electronic device, including a memory and a processor, wherein the memory stores a computer program that can run on the processor, and the processor executes the steps of any of the methods described above when running the computer program.

[0012] Compared with the prior art, the technical solution of the embodiments of the present invention has the following advantages:

[0013] By applying the scheme of this invention, after obtaining the first and second correspondence information, the threshold voltage change range corresponding to the non-failed memory cells before baking the memory under test is first calculated. Then, based on the threshold voltage change range and the second correspondence information, the total number of tail memory cells after baking the memory under test is determined. Finally, based on the total number of tail memory cells after baking the memory under test, the data retention performance of the memory under test is determined. The entire testing process does not require specific processes or operating methods. The data retention performance of the memory under test can be determined based on the total number of tail memory cells after baking. Therefore, it can be used as a unified testing scheme to quantitatively test the data retention performance of NAND Flash, suitable for testing the data retention performance of NAND Flash with different capacities or products on the same technology platform. Attached Figure Description

[0014] Figure 1 This is a schematic diagram of the curve showing the change in the number of memory cells under test as a function of the threshold voltage of the memory cells;

[0015] Figure 2 This is a schematic diagram of the curve showing the change in the number of memory cells as a function of the threshold voltage of the memory cells in another type of memory under test.

[0016] Figure 3 This is a flowchart of a data retention performance testing method according to an embodiment of the present invention;

[0017] Figure 4 This is a schematic diagram of a preset failure number index in an embodiment of the present invention;

[0018] Figure 5 This is a schematic diagram illustrating the principle of a data retention performance test in an embodiment of the present invention;

[0019] Figure 6 This is a schematic diagram illustrating how to determine the total number of tail memory cells after baking the memory to be tested, according to an embodiment of the present invention.

[0020] Figure 7 This is a schematic diagram of the structure of a testing system according to an embodiment of the present invention. Detailed Implementation

[0021] Currently, when testing the data retention performance of NAND Flash based on the threshold voltage Vt of the storage cell, the following two methods are mainly used:

[0022] The first type, referring to Figure 1 The difference between the first peak value Vt1 and the second peak value Vt2, i.e., Vt1-Vt2, is calculated. Here, the first peak value Vt1 refers to the threshold voltage Vt value corresponding to the maximum number of memory cells before the memory under test is baked. The second peak value Vt2 refers to the threshold voltage Vt value corresponding to the maximum number of memory cells after the memory under test is baked. The number of memory cells is represented by bit count.

[0023] The second method, refer to Figure 2 The number of failed memory cells is calculated. A read verification voltage V1 can be set, and the number of memory cells in the memory under test that are below this read verification voltage V1 after baking is accumulated and summed as the number of failed memory cells. Specifically, when the memory cell threshold voltage is equal to the read verification voltage V1, the corresponding number of memory cells is H1, and the sum of the number of all memory cells that are less than or equal to H1 is the number of failed memory cells.

[0024] When using the first method described above to determine the data retention performance of NAND Flash, since both the first threshold voltage peak and the second threshold voltage peak are related to the manufacturing process and operating method, after obtaining the difference between the first threshold voltage peak and the second threshold voltage peak, it is also necessary to analyze the impact of the manufacturing process and operating method on this difference. Furthermore, different NAND Flashes have different impacts on this difference, so it is not possible to directly determine the data retention performance of NAND Flashes of different products or capacities based on this difference.

[0025] When using the second method described above to determine the data retention performance of NAND Flash, the number of failed memory cells is related to the read verification voltage. However, different NAND Flash products have different read verification voltages, so it is impossible to obtain the number of failed memory cells based on the same read verification voltage.

[0026] Whether using the first or second method to determine the data retention performance of NAND Flash, it is necessary to combine specific processes and operating methods to determine the data retention performance of NAND Flash. It cannot be used as a unified test method to quantitatively test the data retention performance of NAND Flash.

[0027] To address this issue, this invention provides a method for testing data retention performance. Applying this method, after obtaining first and second correspondence information, the method first calculates the threshold voltage variation range corresponding to the non-failed memory cells before baking the memory under test. Then, based on this threshold voltage variation range and the second correspondence information, the total number of tail memory cells after baking the memory under test is determined. Finally, based on the total number of tail memory cells after baking the memory under test, the data retention performance of the memory under test is determined. The entire testing process does not require specific processes or operating methods. The data retention performance of the memory under test can be determined based on the total number of tail memory cells after baking. Therefore, it can be used as a unified testing scheme to quantitatively test the data retention performance of NAND Flash, suitable for testing the data retention performance of different NAND Flash chips on the same technology platform.

[0028] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0029] Reference Figure 3 This invention provides a method for testing data retention performance, which may include the following steps:

[0030] Step 31: Obtain the first and second correspondence information of the memory to be tested.

[0031] Wherein, the first correspondence information is the correspondence information between the threshold voltage of the memory cell and the number of memory cells before the memory under test is baked; the second correspondence information is the correspondence information between the threshold voltage of the memory cell and the number of memory cells after the memory under test is baked.

[0032] In practice, after writing data to the memory under test, a first read is performed, at which point the first correspondence can be obtained. After the first read, the memory under test is baked, and then a second read is performed, at which point the second correspondence can be obtained.

[0033] In practice, the first and second correspondence information can have various forms of representation. For example, refer to... Figure 4 The first correspondence information can be the curve 41 showing the change of the number of storage cells with the threshold voltage Vt of the storage cells before baking the memory to be tested, and the second correspondence information can be the curve 42 showing the change of the number of storage cells with the threshold voltage Vt of the storage cells after baking the memory to be tested.

[0034] In other embodiments, the first and second correspondence information can also be in tabular form. This is not limited here, as long as it can represent the number of memory cells corresponding to different threshold voltages.

[0035] Step 32: Based on the preset failure bit index, calculate the threshold voltage change range corresponding to the non-failed memory cells before baking the memory to be tested.

[0036] The preset failure number index is used to characterize the number of failed memory cells in the memory under test before baking the memory under test.

[0037] The inventors discovered that data retention performance issues cause an abnormal change in the number of memory cells following baking of the tested memory, as the cell threshold voltage changes. (Refer to...) Figure 4 Compared to before baking, because the memory requires data retention, the slope of curve 42, which shows the change in the number of memory cells as a function of the memory cell threshold voltage, decreases at the end (as shown in region A). Except at the end, the differences in the distribution of curves 41 and 42 before and after baking are mainly caused by the memory program.

[0038] Based on this, in embodiments of the present invention, in order to eliminate the differences in the distribution of the threshold voltage Vt of the memory cells caused by the memory program, the number of memory cells at the tail position is used as an indicator of the data retention performance of the memory under test. Specifically, the curve of the number of memory cells in the memory under test as a function of the threshold voltage of the memory cells can be divided into two parts: one part is the ideal distribution curve excluding the tail position, and the other part is the curve at the tail position. Thus, the data situation with a slight offset can be used as an indicator of the data retention performance of the memory. The critical threshold voltage value between the ideal distribution curve and the tail position curve can be determined by the curve of the number of memory cells as a function of the threshold voltage of the memory cells before baking.

[0039] In practical implementation, the ideal distribution curve can be the entire curve of the change in the number of memory cells as a function of the threshold voltage of the memory cells before baking. In this case, half of the range of change in the threshold voltage of the memory cells before baking can be taken as the range of change in the threshold voltage of the memory cells after baking, from the maximum number of memory cells to the tail boundary. (Refer to...) Figure 4Assuming the minimum threshold voltage of the memory cell before baking is V2, then half of the range of threshold voltage variation of the memory cell before baking = the threshold voltage of the largest memory cell Vt1 - the minimum threshold voltage of the memory cell before baking V2, which is (Vt1 – V2). The threshold voltage of the memory cell tail boundary after baking = Vt2 - (Vt1 – V2). Based on the curve 42 showing the change in the number of memory cells with the threshold voltage of the memory cell after baking, given the threshold voltage of the memory cell tail boundary after baking, the corresponding number of memory cells can be determined. Therefore, the data retention performance of the memory under test can be determined based on the number of memory cells at the tail.

[0040] In practice, when reading the memory to be tested, the voltage value of the memory cell may not be read due to factors such as noise and process. The memory cell whose voltage value cannot be read is called the failed memory cell, and the number of failed memory cells is called the number of failed bits.

[0041] In one embodiment of the present invention, considering that the curve of the number of storage cells as a function of the threshold voltage of the storage cells before baking may be affected by a variety of factors and fail, a preset failure bit index can be set. The preset failure bit index is used to characterize the number of failed storage cells in the memory to be tested, thereby obtaining an ideal distribution curve based on the preset failure bit index.

[0042] In practice, the specific value of the preset failure bit index can be obtained through a limited number of experiments. Before baking the memory under test, the portion of the curve showing the change in the number of memory cells as a function of the memory cell threshold voltage, excluding the failed memory cells, represents the ideal state curve, thereby optimizing the ideal state distribution curve.

[0043] For example, refer to Figure 4 The preset failure bit index can be set to 50, then the horizontal coordinate values ​​on curve 41 are Vt1_L50 and Vt1_R50, respectively, and the horizontal coordinate values ​​on curve 42 are Vt2_L50 and Vt2_R50, respectively. That is to say, the threshold voltage range corresponding to the non-failed memory cell on curve 41 is [Vt1_L50, Vt1_R50], and the threshold voltage range corresponding to the non-failed memory cell on curve 42 is [Vt2_L50, Vt2_R50].

[0044] Step 33: Based on the threshold voltage change range of the non-failed memory cells before the memory under test is baked, and the second correspondence information, determine the total number of tail memory cells after the memory under test is baked.

[0045] In practice, based on the threshold voltage variation range of the non-failed memory cells before baking the memory under test, and the threshold voltage value corresponding to the maximum number of memory cells after baking the memory under test, the threshold voltage value corresponding to the tail bit boundary after baking the memory under test can be determined first, and then the total number of tail bit memory cells after baking the memory under test can be determined based on the threshold voltage value corresponding to the tail bit boundary after baking the memory under test.

[0046] In a specific implementation, the difference between the threshold voltage value corresponding to the maximum number of memory cells after baking the memory under test and half of the threshold voltage change of the non-failed memory cells before baking the memory under test can be used as the threshold voltage value corresponding to the tail bit boundary after baking the memory under test.

[0047] Reference Figure 5 Before baking the memory under test, the threshold voltage range corresponding to the non-failed memory cells is [Vt1_L50, Vt1_R50], and half of its change is (Vt1_R50-Vt1_L50) / 2. Taking half of the change in threshold voltage corresponding to the non-failed memory cells before baking the memory under test as the change between the threshold voltage value corresponding to the tail boundary and the threshold voltage value corresponding to the maximum number of memory cells after baking the memory under test, the threshold voltage value corresponding to the tail boundary can be obtained as Vt2-(Vt1_R50-Vt1_L50) / 2.

[0048] After determining the threshold voltage value corresponding to the tail bit boundary after baking the memory under test, the number of memory cells corresponding to the tail bit boundary after baking the memory under test can be obtained as FBC by using the correspondence between the threshold voltage after baking the memory under test and the number of memory cells.

[0049] Reference Figure 6 The cumulative sum of the number of memory cells whose number of storage cells after baking is less than or equal to the FBC, AFBC, is taken as the total number of tail-bit storage cells after baking the memory under test. Figure 6 It can be seen that the change in the number of storage cells after the memory under test is baked with respect to the threshold voltage of the storage cells can be divided into two parts: one part is the tail storage cell, and the other part is the other storage cells except for the tail storage cell.

[0050] Step 34: Determine the data retention performance of the memory under test based on the total number of tail memory cells after baking the memory under test.

[0051] In practice, the total number of tail memory cells after the memory under test is baked can be normalized, and the normalization result can be used as an indicator of the data retention performance of the test memory.

[0052] Specifically, the quotient between the total number of tail bits after baking the memory under test and the total number of memory cells under test can be used as the indicator FP for testing the memory's data retention performance, where FP = AFBC / totalbits, and total bits represents the total number of tail bits after baking the memory under test.

[0053] As can be seen from the above, the data retention performance testing method in this embodiment of the invention can eliminate the distribution difference of the memory cell threshold voltage before and after baking caused by factors such as process and operation method. Furthermore, the distribution of the memory cell threshold voltage after baking can be optimized by adjusting the preset failure bit index, thereby improving the test sensitivity and enabling the index FP of the test memory to more accurately characterize the data retention performance of the memory under test.

[0054] To enable those skilled in the art to better understand and implement the present invention, the apparatus, testing system, electronic device, and computer-readable storage medium corresponding to the above method are described in detail below.

[0055] Reference Figure 7 This invention also provides a data retention performance testing device 70, which may include: an acquisition unit 71, a calculation unit 72, a first determination unit 73, and a second determination unit 74. Wherein:

[0056] The acquisition unit 71 is adapted to acquire first correspondence information and second correspondence information of the memory under test; wherein, the first correspondence information is the correspondence information between the threshold voltage of the memory cell and the number of memory cells before baking the memory under test; and the second correspondence information is the correspondence information between the threshold voltage of the memory cell and the number of memory cells after baking the memory under test.

[0057] The calculation unit 72 is adapted to calculate the threshold voltage change range corresponding to the non-failed memory cells before baking the memory under test, based on a preset failure number index; the preset failure number index is used to characterize the number of failed memory cells in the memory under test.

[0058] The first determining unit 73 is adapted to determine the total number of tail bit memory cells after baking the memory under test based on the threshold voltage change range corresponding to the memory cells that have not failed before the memory under test is baked, and the second correspondence information.

[0059] The second determining unit 74 is adapted to determine the data retention performance of the memory under test based on the total number of tail bit storage cells after baking the memory under test.

[0060] In one embodiment of the present invention, the first determining unit 73 may include: a first calculation subunit 731 and a second calculation subunit 732, wherein:

[0061] The first calculation subunit 731 is adapted to determine the threshold voltage value corresponding to the tail bit boundary after baking the memory under test based on the threshold voltage change range corresponding to the non-failed memory cells before baking the memory under test, and the threshold voltage value corresponding to the maximum number of memory cells after baking the memory under test.

[0062] The second calculation subunit 732 is adapted to determine the total number of tail bit storage cells after baking the memory under test based on the threshold voltage value corresponding to the tail bit boundary after baking the memory under test.

[0063] In one embodiment of the present invention, the second determining unit 74 is adapted to perform a normalization operation on the total number of tail memory cells after the memory under test is baked, and to determine the data retention performance of the memory under test based on the result of the normalization operation.

[0064] Reference Figure 7 The present invention also provides a testing system, which may include the data retention performance testing device 70 described above and a memory under test 80; the data retention performance testing device 70 is connected to the memory under test 80 and is adapted to test the data retention performance of the memory under test 80.

[0065] In specific implementations, the memory to be tested 80 includes, but is not limited to, NAND Flash.

[0066] This invention also provides a computer-readable storage medium having a computer program stored thereon, the computer program being executed by a processor to implement the steps of any of the above methods.

[0067] In specific implementations, the computer-readable storage medium may include ROM, RAM, disk, or optical disk, etc.

[0068] This invention also provides an electronic device, which includes a memory and a processor. The memory stores a computer program that can run on the processor. The processor executes the steps of any of the methods described above when running the computer program.

[0069] Regarding the modules / units included in the various devices and products described in the above embodiments, they can be software modules / units, hardware modules / units, or a combination of both. For example, for various devices and products applied to or integrated into a chip, all of their modules / units can be implemented using hardware methods such as circuits, or at least some modules / units can be implemented using software programs that run on a processor integrated within the chip, while the remaining (if any) modules / units can be implemented using hardware methods such as circuits; for various devices and products applied to or integrated into a chip module, all of their modules / units can be implemented using hardware methods such as circuits, and different modules / units can be located in the same component (e.g., chip, circuit module, etc.) or different components of the chip module, or at least some modules / units can be implemented using hardware methods such as circuits. The components can be implemented using software programs that run on the processor integrated within the chip module. The remaining (if any) modules / units can be implemented using hardware methods such as circuits. For various devices and products applied to or integrated into the terminal, each of its components / units can be implemented using hardware methods such as circuits. Different modules / units can be located in the same component (e.g., chip, circuit module, etc.) or in different components within the terminal. Alternatively, at least some modules / units can be implemented using software programs that run on the processor integrated within the terminal, while the remaining (if any) modules / units can be implemented using hardware methods such as circuits.

[0070] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A method for testing data retention performance, characterized in that, include: Obtain first and second correspondence information of the memory under test; wherein, the first correspondence information is the correspondence information between the threshold voltage of the memory cell and the number of memory cells before baking the memory under test; and the second correspondence information is the correspondence information between the threshold voltage of the memory cell and the number of memory cells after baking the memory under test. Based on a preset failure number index, the threshold voltage variation range corresponding to the non-failed memory cells before baking the memory under test is calculated; the preset failure number index is used to characterize the number of failed memory cells in the memory under test before baking the memory under test. Based on the threshold voltage variation range of the non-failed memory cells before the memory under test is baked, and the second correspondence information, the total number of tail memory cells after the memory under test is determined. The data retention performance of the memory under test is determined based on the total number of tail memory cells after baking the memory under test. The step of determining the total number of tail bits of the memory under test after baking, based on the threshold voltage variation range corresponding to the non-failed memory cells before baking the memory under test and the second correspondence information, includes: determining the threshold voltage value corresponding to the tail bit boundary after baking the memory under test based on the threshold voltage variation range corresponding to the non-failed memory cells before baking the memory under test and the threshold voltage value corresponding to the maximum number of memory cells after baking the memory under test; and determining the total number of tail bits of the memory under test after baking based on the threshold voltage value corresponding to the tail bit boundary after baking the memory under test.

2. The data retention performance testing method as described in claim 1, characterized in that, The determination of the threshold voltage value corresponding to the tail bit boundary after baking the memory under test, based on the threshold voltage variation range corresponding to the non-failed memory cells before baking the memory under test, and the threshold voltage value corresponding to the maximum number of memory cells after baking the memory under test, includes: The difference between the threshold voltage value corresponding to the maximum number of memory cells after baking the memory under test and half of the threshold voltage change corresponding to the non-failed memory cells before baking the memory under test is taken as the threshold voltage value corresponding to the tail bit boundary after baking the memory under test.

3. The data retention performance testing method as described in claim 1, characterized in that, The determination of the data retention performance of the memory under test based on the total number of tail memory cells after baking includes: Perform a normalization operation on the total number of tail memory cells after the memory under test is baked; Based on the result of the normalization operation, the data retention performance of the memory under test is determined.

4. A data retention performance testing device, characterized in that, include: The acquisition unit is adapted to acquire a first correspondence information and a second correspondence information of the memory under test; wherein, the first correspondence information is the correspondence information between the threshold voltage of the memory cell and the number of memory cells before the memory under test is baked; and the second correspondence information is the correspondence information between the threshold voltage of the memory cell and the number of memory cells after the memory under test is baked. The calculation unit is adapted to calculate the threshold voltage change range corresponding to the non-failed memory cells before baking the memory under test, based on a preset failure number index; the preset failure number index is used to characterize the number of failed memory cells in the memory under test. The first determining unit is adapted to determine the total number of tail bit memory cells after baking the memory under test based on the threshold voltage change range corresponding to the memory cells that have not failed before the memory under test is baked, and the second correspondence information. The second determining unit is adapted to determine the data retention performance of the memory under test based on the total number of tail bit storage cells after baking the memory under test; The first determining unit includes: a first calculation subunit, adapted to determine the threshold voltage value corresponding to the tail bit boundary after baking the memory under test based on the threshold voltage change range corresponding to the non-failed memory cells before baking the memory under test, and the threshold voltage value corresponding to the maximum number of memory cells after baking the memory under test; and a second calculation subunit, adapted to determine the total number of tail bit memory cells after baking the memory under test based on the threshold voltage value corresponding to the tail bit boundary after baking the memory under test.

5. The data retention performance testing apparatus as described in claim 4, characterized in that, The second determining unit is adapted to perform a normalization operation on the total number of tail memory cells after the memory under test is baked, and to determine the data retention performance of the memory under test based on the result of the normalization operation.

6. A testing system, characterized in that, The device includes the data retention performance testing apparatus as described in any one of claims 4 to 5, and a memory to be tested; the data retention performance testing apparatus is connected to the memory to be tested and is adapted to test the data retention performance of the memory to be tested.

7. A computer-readable storage medium having a computer program stored thereon, characterized in that, The computer program is executed by a processor to implement the steps of the method according to any one of claims 1 to 3.

8. An electronic device comprising a memory and a processor, wherein the memory stores a computer program capable of running on the processor, characterized in that, When the processor runs the computer program, it performs the steps of the method according to any one of claims 1 to 3.

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