CMOS devices and their fabrication methods

Abstract

This application relates to the field of semiconductor technology and discloses a CMOS device and its fabrication method. The CMOS device includes stacked N-type transistors and P-type transistors; the channels of the N-type transistors and P-type transistors are both annular channels; the gates of the N-type transistors and P-type transistors are located in vias penetrating the annular channels of the N-type transistors and P-type transistors; the N-type transistors and P-type transistors share the same gate.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and more particularly to a CMOS device and a method for fabricating the same. Background Technology

[0002] Thin-film integrated circuits (TFT-ICs) are becoming increasingly important in emerging fields such as flexible displays, the Internet of Things (IoT), and wearable electronics. However, due to the lack of high-performance P-type oxide devices, most oxide ICs use only single-level logic circuits with N-type devices. Single-level logic circuits suffer from low robustness, high power consumption, and large layout area. Taking a single-level inverter as an example, achieving rail-to-rail output requires sacrificing area.

[0003] Traditional oxide CMOS structures are based on planar FET manufacturing processes, connecting N-type FET devices and P-type FET devices through metal traces, or using only a single-level logic circuit of an N-type FET device to achieve complementary logic functions. This results in a large layout area, relatively complex processes, and difficulty in achieving high-density integration. Summary of the Invention

[0004] This application provides a CMOS device and a method for fabricating it. The CMOS device of this application has a three-dimensional vertical common gate structure, which can improve the integration density.

[0005] This application provides a CMOS device, including:

[0006] Stacked N-type and P-type transistors;

[0007] Both the N-type transistor and the P-type transistor have annular channels.

[0008] The gates of the N-type transistor and the P-type transistor are located within vias that penetrate the annular channel of the N-type transistor and the annular channel of the P-type transistor; the N-type transistor and the P-type transistor share the same gate.

[0009] In some embodiments, the annular channel of the N-type transistor is made of N-type oxide semiconductor material, and the annular channel of the P-type transistor is made of P-type oxide semiconductor material.

[0010] In some embodiments, the N-type oxide semiconductor material is a metal oxide containing indium, gallium, or zinc; and the P-type oxide semiconductor material is a metal oxide containing tin or copper.

[0011] In some embodiments, the N-type transistor includes:

[0012] Grounding layer;

[0013] First dielectric layer;

[0014] First metal layer;

[0015] First annular channel;

[0016] First gate oxide layer;

[0017] Gate;

[0018] The P-type transistor includes:

[0019] First metal layer;

[0020] Second dielectric layer;

[0021] Second metal layer;

[0022] Second ring channel;

[0023] Second gate oxide layer;

[0024] Gate;

[0025] Wherein, the grounding layer is embedded in the first dielectric layer; a first through hole is provided in the first dielectric layer on the grounding layer; the top of the first through hole is provided with the first metal layer; and the inner periphery of the first through hole is provided with the first annular channel.

[0026] The first metal layer is embedded in the second dielectric layer; a second through-hole is provided in the second dielectric layer on the first metal layer; the second metal layer is provided at the top of the second through-hole; a second annular channel is provided around the inner periphery of the second through-hole;

[0027] The first gate oxide layer and the second gate oxide layer are disposed around the inner side of the third via; the inner side of the first gate oxide layer and the second gate oxide layer is filled with the columnar gate; the third via is located on the ground layer and penetrates the first dielectric layer, the first metal layer, the second dielectric layer, the second metal layer, the third dielectric layer, the first via, and the second via.

[0028] In some embodiments, the CMOS device further includes:

[0029] Substrate; the substrate is a flexible substrate;

[0030] The N-type transistor is located on the flexible substrate.

[0031] In some embodiments, the vertical projections of the first via and the second via on the ground layer coincide.

[0032] In some embodiments, the CMOS device further includes:

[0033] Third dielectric layer;

[0034] The second metal layer is embedded in the third dielectric layer;

[0035] The third via extends upward and penetrates the third dielectric layer; the second gate oxide layer and the gate extend to a predetermined area at the top of the third via.

[0036] In some embodiments, the CMOS device further includes a first through-hole interconnect structure;

[0037] The first via interconnect structure is located on the ground layer and penetrates the first dielectric layer, the second dielectric layer and the third dielectric layer; it is used to connect the GND electrode to the ground layer.

[0038] In some embodiments, the CMOS device further includes a second through-hole interconnect structure;

[0039] The second via interconnect structure is located on the second metal layer and penetrates the third dielectric layer; it is used to connect the input electrode to the second metal layer.

[0040] In some embodiments, the CMOS device further includes a third via interconnect structure;

[0041] The third via interconnect structure is located on the first metal layer, penetrates the second dielectric layer and the third dielectric layer, and is used to connect the output electrode to the first metal layer.

[0042] This application provides a method for fabricating a CMOS device, including:

[0043] Forming N-type and P-type transistors;

[0044] The formation of N-type transistors and P-type transistors includes:

[0045] The following layers are formed sequentially from bottom to top: ground layer, first dielectric layer, first metal layer, second dielectric layer, second metal layer, and third dielectric layer;

[0046] A first via is formed, the first via being located between the ground layer and the first metal layer; a first oxide is deposited around the inner periphery of the first via;

[0047] A second via is formed, the second via being located between the first metal layer and the second metal layer; a second oxide is deposited around the inner periphery of the second via;

[0048] A third via is formed, the third via being located on the ground layer and penetrating the first dielectric layer, the first metal layer, the second dielectric layer, the second metal layer, the third dielectric layer, the first via deposited with the first oxide, and the second via deposited with the second oxide;

[0049] A third oxide is deposited around the inner side of the third through-hole to form a gate oxide layer;

[0050] Conductive material is deposited around the inner side of the gate oxide layer to form the common gate of the N-type transistor and the P-type transistor.

[0051] In some embodiments, a first through-hole interconnect structure, a second through-hole interconnect structure, and a third through-hole interconnect structure are formed;

[0052] The first via interconnect structure is located on the ground layer and penetrates the first dielectric layer, the second dielectric layer, and the third dielectric layer; it is used to connect the GND electrode to the ground layer.

[0053] The second via interconnect structure is located on the second metal layer and penetrates the third dielectric layer; it is used to connect the input electrode to the second metal layer.

[0054] The third via interconnect structure is located on the first metal layer, penetrates the second dielectric layer and the third dielectric layer, and is used to connect the output electrode to the first metal layer.

[0055] Other features and advantages of this application will be set forth in the following description, and will be apparent in part from the description, or may be learned by practicing the application. Other advantages of this application can be realized and obtained by means of the solutions described in the description and the accompanying drawings. Attached Figure Description

[0056] The accompanying drawings are used to provide an understanding of the technical solutions of this application and constitute a part of the specification. They are used together with the embodiments of this application to explain the technical solutions of this application and do not constitute a limitation on the technical solutions of this application.

[0057] Figure 1 This is a schematic diagram of a CMOS device according to an embodiment of this application;

[0058] Figure 2 This is a schematic diagram of the second step in the CMOS device fabrication process according to an embodiment of this application;

[0059] Figure 3 This is a schematic diagram of the second step in the CMOS device fabrication process according to an embodiment of this application;

[0060] Figure 4 This is a schematic diagram of the third step in the CMOS device fabrication process according to an embodiment of this application;

[0061] Figure 5 This is a schematic diagram of the fourth step in the CMOS device fabrication process according to an embodiment of this application;

[0062] Figure 6This is a schematic diagram of the fourth step in the CMOS device fabrication process according to an embodiment of this application;

[0063] Figure 7 This is a schematic diagram of the fifth step in the CMOS device fabrication process according to an embodiment of this application;

[0064] Figure 8 This is a schematic diagram of the sixth step in the CMOS device fabrication process according to an embodiment of this application;

[0065] Figure 9 This is a schematic diagram of the sixth step in the CMOS device fabrication process according to an embodiment of this application;

[0066] Figure 10 This is a schematic diagram of the seventh step in the CMOS device fabrication process according to an embodiment of this application;

[0067] Figure 11 This is a schematic diagram of the seventh step in the CMOS device fabrication process according to an embodiment of this application;

[0068] Figure 12 This is a schematic diagram of the eighth step in the CMOS device fabrication process according to an embodiment of this application. Detailed Implementation

[0069] This application provides a CMOS device, the CMOS device comprising: stacked N-type transistors and P-type transistors;

[0070] Both the N-type transistor and the P-type transistor have annular channels.

[0071] The gates of the N-type transistor and the P-type transistor are located within vias penetrating the annular channels of the N-type and P-type transistors, respectively; the N-type and P-type transistors share the same gate. This shared gate can be understood as being connected to different regions of a conductive structure, each region being the effective gate region of the corresponding transistor. For example, the gate extends along a direction perpendicular to the substrate, and the semiconductor layers or channels of the two transistors are located in different regions of the gate sidewall, spaced apart from the gate.

[0072] The annular channel can be understood as the semiconductor layer having a ring-shaped structure, surrounding the gate.

[0073] exist Figure 1 In this configuration, N-type transistor 10 is stacked at the bottom and P-type transistor 20 is stacked on top. Alternatively, P-type transistors can be stacked at the bottom and N-type transistors at the top. To accommodate this variation, those skilled in the art can make adaptive changes where necessary, which will not be elaborated here.

[0074] In one exemplary embodiment, with Figure 1For example, the N-type transistor 10 includes:

[0075] Grounding layer 11;

[0076] First dielectric layer 15;

[0077] First metal layer 16;

[0078] First annular channel 12;

[0079] First gate oxide layer 13;

[0080] Gate 14;

[0081] in,

[0082] The P-type transistor 20 includes:

[0083] First metal layer 16;

[0084] Second dielectric layer 19;

[0085] Second metal layer 21;

[0086] Second annular channel 18;

[0087] Second gate oxide layer 17;

[0088] Gate 14;

[0089] Wherein, the grounding layer 11 is embedded in the first dielectric layer 15; the first dielectric layer 15 on the grounding layer 11 is provided with a first through hole; the top of the first through hole is provided with the first metal layer 16; the inner periphery of the first through hole is provided with the first annular channel 12.

[0090] The first metal layer is embedded in the second dielectric layer 19; a second through hole is provided in the second dielectric layer 22 on the first metal layer 16; the second metal layer 21 is provided at the top of the second through hole; a second annular channel 18 is provided around the inner side of the second through hole;

[0091] The first gate oxide layer 13 and the second gate oxide layer 17 are disposed around the inner periphery of the third via; the inner sides of the first gate oxide layer 13 and the second gate oxide layer 17 are filled with the columnar gate 14; the third via is located on the ground layer 11 and penetrates the first dielectric layer 15, the first metal layer 16, the second dielectric layer 19, the second metal layer 21, the third dielectric layer, the first via, and the second via.

[0092] In one exemplary embodiment, the N-type transistor includes a source, a drain, and a gate; the P-type transistor includes a source, a drain, and a gate; the drain of the N-type transistor and the drain of the P-type transistor are connected; the gate of the N-type transistor and the gate of the P-type transistor are connected. A first metal layer serves as the drain of the N-type transistor and the drain of the P-type transistor, a second metal layer serves as the source of the P-type transistor, and a ground layer serves as the source of the N-type transistor.

[0093] In one exemplary embodiment, in the CMOS device, the source of the P-type transistor is connected to an external VDD terminal, the source of the N-type transistor is grounded, the drain of the N-type transistor and the drain of the P-type transistor are connected as an output terminal, and the gate of the N-type transistor and the gate of the P-type transistor are connected as an input terminal.

[0094] In one exemplary embodiment, the annular channel of the N-type transistor is made of N-type oxide semiconductor material, and the annular channel of the P-type transistor is made of P-type oxide semiconductor material.

[0095] In one exemplary embodiment, the N-type oxide semiconductor material is a metal oxide containing indium, gallium, or zinc; and the P-type oxide semiconductor material is a metal oxide containing tin or copper.

[0096] In one exemplary embodiment, the CMOS device further includes:

[0097] Substrate; the substrate may be a flexible substrate;

[0098] The N-type transistor is located on the flexible substrate.

[0099] In one exemplary embodiment, the vertical projections of the first via and the second via on the ground layer coincide.

[0100] In one exemplary embodiment, the CMOS device further includes: a third dielectric layer;

[0101] The second metal layer is embedded in the third dielectric layer;

[0102] The third via extends upward and penetrates the third dielectric layer; the second gate oxide layer and the gate extend to a predetermined area at the top of the third via.

[0103] In one exemplary embodiment, the CMOS device further includes:

[0104] First through-hole interconnect structure;

[0105] The first via interconnect structure is located on the ground layer and penetrates the first dielectric layer, the second dielectric layer and the third dielectric layer; it is used to connect the GND electrode to the ground layer.

[0106] In one exemplary embodiment, the CMOS device further includes:

[0107] Second through-hole interconnect structure;

[0108] The second via interconnect structure is located on the second metal layer and penetrates the third dielectric layer; it is used to connect the input electrode to the second metal layer.

[0109] In one exemplary embodiment, the CMOS device further includes:

[0110] Third through-hole interconnect structure;

[0111] The third via interconnect structure is located on the first metal layer, penetrates the second dielectric layer and the third dielectric layer, and is used to connect the output electrode to the first metal layer.

[0112] Among them, the through-hole interconnect structure can be a through hole, and in terms of process, tungsten plugs or tungsten through holes can be used as the through-hole interconnect structure.

[0113] In one exemplary embodiment, the N-type transistor is an N-type field-effect transistor;

[0114] The P-type transistor is a P-type field-effect transistor.

[0115] The N-type transistor of this application embodiment includes: a ground layer; a first dielectric layer; a first metal layer; a first annular channel; a first gate oxide layer; and a gate. The P-type transistor includes: a first metal layer; a second dielectric layer; a second metal layer; a second annular channel; a second gate oxide layer; and a gate. The ground layer is embedded in the first dielectric layer. A first via is formed in the first dielectric layer on the ground layer. The first metal layer is disposed at the top of the first via. A first annular channel is formed around the inner periphery of the first via. The first metal layer is embedded in the second dielectric layer. A second via is formed in the second dielectric layer on the first metal layer. The second metal layer is disposed at the top of the second via. A second annular channel is formed around the inner periphery of the second via. The first gate oxide layer and the second gate oxide layer are disposed around the inner periphery of a third via. A columnar gate is filled inside the first gate oxide layer and the second gate oxide layer. The third via is located on the ground layer and penetrates the first dielectric layer, the first metal layer, the second dielectric layer, the second metal layer, the third dielectric layer, the first via, and the second via. In this CMOS device, the N-type transistors and P-type transistors are stacked vertically. The N-type and P-type transistors employ a ring-channel structure and share a common gate, forming a common-gate ring-channel device structure. This structure enables complementary CFETs, offering area advantages and effectively improving integration density. It can be widely used in large-scale flexible integrated circuits, such as those in wearable devices, to construct various logic function circuits.

[0116] This application provides a method for fabricating a CMOS device, including:

[0117] Forming N-type and P-type transistors;

[0118] The formation of N-type transistors and P-type transistors includes:

[0119] The following layers are formed sequentially from bottom to top: ground layer, first dielectric layer, first metal layer, second dielectric layer, second metal layer, and third dielectric layer;

[0120] A first via is formed, the first via being located between the ground layer and the first metal layer; a first oxide is deposited around the inner periphery of the first via;

[0121] A second via is formed, the second via being located between the first metal layer and the second metal layer; a second oxide is deposited around the inner periphery of the second via;

[0122] A third via is formed, the third via being located on the ground layer and penetrating the first dielectric layer, the first metal layer, the second dielectric layer, the second metal layer, the third dielectric layer, the first via deposited with the first oxide, and the second via deposited with the second oxide;

[0123] A third oxide is deposited around the inner side of the third through-hole to form a gate oxide layer;

[0124] Conductive material is deposited around the inner side of the gate oxide layer to form the common gate of the N-type transistor and the P-type transistor.

[0125] In one exemplary embodiment, the method for fabricating the CMOS device further includes:

[0126] Forming a first through-hole interconnect structure, a second through-hole interconnect structure, and a third through-hole interconnect structure;

[0127] The first via interconnect structure is located on the ground layer and penetrates the first dielectric layer, the second dielectric layer, and the third dielectric layer; it is used to connect the GND electrode to the ground layer.

[0128] The second via interconnect structure is located on the second metal layer and penetrates the third dielectric layer; it is used to connect the input electrode to the second metal layer.

[0129] The third via interconnect structure is located on the first metal layer, penetrates the second dielectric layer and the third dielectric layer, and is used to connect the output electrode to the first metal layer.

[0130] In one exemplary embodiment, the first oxide is an N-type oxide, such as IGZO, In2O3, ZnO, etc.

[0131] In one exemplary embodiment, the second oxide is a p-type oxide, such as SnO, Cu2O3, etc.

[0132] In one exemplary embodiment, the third oxide is a gate oxide such as SiO2, HfO2, or AL2O3.

[0133] In one exemplary embodiment, the first dielectric layer, the second dielectric layer, and the third dielectric layer may be composed of SiO2.

[0134] In one exemplary embodiment, the gate material can be Poly, TiN, TiW, ITO, etc.

[0135] In one exemplary embodiment, the first metal layer, the second metal layer, and the third metal layer may be made of materials such as Ti, Al, ITO, etc.

[0136] Complementary circuits combining N-type and P-type transistors offer advantages such as lower power consumption, stronger noise immunity, rail-to-rail output, and more efficient circuit design. In the Complementary Field-Effect Transistor (CFET) device structure, the nFET and pFET share a common gate electrode as the signal input and a common drain electrode as the signal output. The source electrodes are grounded and powered, respectively. The complementary all-around gate device structure, composed of vertically stacked N and P transistors, differs from traditional transistors in that the P-type oxide transistor and N-type oxide transistor employ a ring-channel structure; the P-type oxide transistor and N-type oxide transistor are stacked together with a common gate to form a complementary CFET. The CFET possesses complete CMOS transistor functionality.

[0137] Complementary CFETs (Complementary Field-Effect Transistors) are achieved using a common-gate ring-channel device structure employing P-type oxide semiconductors (such as SnO or Cu2O3) and N-type oxide semiconductors (such as IGZO, In2O3, or ZnO). This ring-channel design, being a fully encircling channel, offers area advantages and effectively improves integration density. It can be widely used in large-scale flexible integrated circuits, such as those in wearable devices, to construct various logic function circuits.

[0138] The following example, using the specific fabrication process of a CFET, illustrates the fabrication method of the aforementioned CMOS device.

[0139] The fabrication process of the CFET in this application embodiment includes the following steps:

[0140] Step 1: Provide a flexible substrate.

[0141] Step 2: Fabricate the bottom electrode (i.e., the GND electrode, located on the aforementioned grounding layer) on the flexible substrate (e.g.) Figure 2 As shown); an insulating dielectric is deposited on the bottom electrode and the substrate not covered by the bottom electrode to form a first dielectric layer, and CMP planarization is performed (as shown). Figure 3 (As shown).

[0142] Step 3: Etch the insulating dielectric (SiO2) on the bottom electrode to form the first via; deposit N-type oxide within the first via and perform CMP planarization (e.g., Figure 4 (As shown).

[0143] Step 4: Fabricate the output electrode at the top of the first through-hole (e.g., Figure 5 As shown), an insulating dielectric is deposited on the output electrode and the first dielectric layer not covered by the output electrode to form a second dielectric layer, and CMP planarization is performed (e.g. Figure 6 (As shown).

[0144] In this process, the output electrode is typically fabricated by depositing metal electrode material, followed by photolithography and etching to form the desired electrode pattern.

[0145] Step 5: Etch the insulating dielectric on the output electrode to form a second via; deposit P-type oxide within the second via; perform CMP planarization (e.g., ...). Figure 7 (As shown).

[0146] Step 6: Fabricate a VDD electrode at the top of the second through-hole (e.g., Figure 8 As shown); an insulating dielectric is deposited on the VDD electrode to form a third dielectric layer, and CMP planarization is performed (e.g. Figure 9 (As shown).

[0147] Step 7: Etch the first dielectric layer, the second dielectric layer, the third dielectric layer, the VDD electrode, and the output electrode to form a third via on the bottom electrode surface that penetrates the first dielectric layer, the second dielectric layer, the third dielectric layer, the VDD electrode, and the output electrode (e.g., ...). Figure 10 As shown), gate oxide material is deposited inside the third via to form a gate oxide layer; metal material is deposited inside the gate oxide layer to form a common gate electrode (VIN electrode) (as shown). Figure 11 (As shown).

[0148] Step 8: Lead out the GND electrode, VIN electrode, and VDD electrode (e.g. Figure 12 (As shown).

[0149] The insulating medium can be SiO2, the N-type oxide can be IGZO, In2O3, ZnO, and the P-type oxide can be SnO, Cu2O3, etc.

[0150] The wafer manufacturing process mainly includes seven independent processes: photolithography, etching, thin film growth, diffusion, ion implantation, chemical mechanical polishing, and metallization. Chemical mechanical polishing (CMP) refers to the efficient removal of excess material on the wafer surface and global nanoscale planarization through the synergistic effect of chemical etching and mechanical grinding.

[0151] The above Figures 2-12 In the diagram, 110 represents the substrate, 120 represents the bottom electrode, 130 represents the first dielectric layer, 140 represents the first via, 150 represents the output electrode, 160 represents the second dielectric layer, 170 represents the second via, 180 represents the VDD electrode, 190 represents the third dielectric layer, 200 represents the third via, 210 represents the gate oxide layer, and 220 represents the gate electrode.

[0152] Following the above fabrication steps, a common-gate ring-channel device structure can be formed, realizing a complementary CFET, which has an area advantage and can effectively improve the integration density.

[0153] This application describes several embodiments, but these descriptions are exemplary and not restrictive, and it will be apparent to those skilled in the art that many more embodiments and implementations are possible within the scope of the embodiments described herein. Although many possible combinations of features are shown in the drawings and discussed in the detailed description, many other combinations of the disclosed features are also possible. Unless specifically limited, any feature or element of any embodiment may be used in combination with, or may replace, any feature or element of any other embodiment.

[0154] Any feature shown and / or discussed in this application may be implemented individually or in any suitable combination.

[0155] Furthermore, in describing representative embodiments, the specification may have presented methods and / or processes as a specific sequence of steps. However, the method or process should not be limited to the specific order of steps described herein, to the extent that it does not depend on such a specific order. Other sequences of steps are possible, as will be understood by those skilled in the art.

[0156] It will be understood by those skilled in the art that all or some of the steps, systems, or apparatuses disclosed above, and their functional modules / units, can be implemented as software, firmware, hardware, or suitable combinations thereof. In hardware implementations, the division between functional modules / units mentioned above does not necessarily correspond to the division of physical components; for example, a physical component may have multiple functions, or a function or step may be performed collaboratively by several physical components. Some or all components may be implemented as software executed by a processor, such as a digital signal processor or microprocessor, or as hardware, or as an integrated circuit, such as an application-specific integrated circuit (ASIC). Such software may be distributed on a computer-readable medium, which may include computer storage media (or non-transitory media) and communication media (or transient media). As is known to those skilled in the art, the term computer storage media includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information (such as computer-readable instructions, data structures, program modules, or other data). Computer storage media include, but are not limited to, RAM, ROM, EEPROM, flash memory or other memory technologies, CD-ROM, digital versatile disc (DVD) or other optical disc storage, magnetic cartridges, magnetic tape, disk storage or other magnetic storage devices, or any other medium that can be used to store desired information and can be accessed by a computer. Furthermore, it is well known to those skilled in the art that communication media typically contain computer-readable instructions, data structures, program modules, or other data in modulated data signals such as carrier waves or other transmission mechanisms, and may include any information delivery medium.

Claims

1. A CMOS device, characterized in that, include: Stacked N-type and P-type transistors; Both the N-type transistor and the P-type transistor have annular channels. The gates of the N-type transistor and the P-type transistor are located within vias that penetrate the annular channel of the N-type transistor and the annular channel of the P-type transistor; the N-type transistor and the P-type transistor share the same gate. The N-type transistor includes: a ground layer; a first dielectric layer; a first metal layer; a first annular channel; a first gate oxide layer; and a gate. The P-type transistor includes: a first metal layer; a second dielectric layer; a second metal layer; a second annular channel; a second gate oxide layer; and a gate. The ground layer is embedded in the first dielectric layer. A first via is formed in the first dielectric layer on the ground layer. The first metal layer is formed at the top of the first via. The first annular channel is formed around the inner periphery of the first via. The first metal layer is embedded in the second dielectric layer; a second through-hole is provided in the second dielectric layer on the first metal layer; the second metal layer is provided at the top of the second through-hole; a second annular channel is provided around the inner periphery of the second through-hole; The first gate oxide layer and the second gate oxide layer are disposed around the inner side of the third via; the inner side of the first gate oxide layer and the second gate oxide layer is filled with the columnar gate; the third via is located on the ground layer and penetrates the first dielectric layer, the first metal layer, the second dielectric layer, the second metal layer, the third dielectric layer, the first via, and the second via.

2. The CMOS device according to claim 1, characterized in that, The annular channel of the N-type transistor is made of N-type oxide semiconductor material, and the annular channel of the P-type transistor is made of P-type oxide semiconductor material.

3. The CMOS device according to claim 2, characterized in that, The N-type oxide semiconductor material is a metal oxide containing indium, gallium, or zinc; the P-type oxide semiconductor material is a metal oxide containing tin or copper.

4. The CMOS device according to claim 1, characterized in that, The CMOS device further includes: Substrate; the substrate is a flexible substrate; The N-type transistor is located on the flexible substrate.

5. The CMOS device according to claim 1, characterized in that, The vertical projections of the first through hole and the second through hole on the grounding layer coincide.

6. The CMOS device according to claim 5, characterized in that, The CMOS device further includes: A third dielectric layer; a second metal layer embedded in the third dielectric layer; a third via extending upward and penetrating the third dielectric layer; a second gate oxide layer and a gate electrode extending to a predetermined region at the top of the third via.

7. The CMOS device according to claim 6, characterized in that, The CMOS device further includes a first through-hole interconnect structure; The first via interconnect structure is located on the ground layer and penetrates the first dielectric layer, the second dielectric layer and the third dielectric layer; it is used to connect the GND electrode to the ground layer.

8. The CMOS device according to claim 6 or 7, characterized in that, The CMOS device further includes a second through-hole interconnect structure; The second via interconnect structure is located on the second metal layer and penetrates the third dielectric layer; it is used to connect the input electrode to the second metal layer.

9. The CMOS device according to claim 8, characterized in that, The CMOS device also includes a third through-hole interconnect structure; The third via interconnect structure is located on the first metal layer, penetrates the second dielectric layer and the third dielectric layer, and is used to connect the output electrode to the first metal layer.

10. A method for fabricating a CMOS device, applied to the CMOS device according to any one of claims 1-9, characterized in that, Forming N-type and P-type transistors; The formation of N-type transistors and P-type transistors includes: The following layers are formed sequentially from bottom to top: ground layer, first dielectric layer, first via, first metal layer, second dielectric layer, second via, second metal layer, third dielectric layer, and third via; The first via is located between the ground layer and the first metal layer; a first oxide is deposited around the inner periphery of the first via; The second via is located between the first metal layer and the second metal layer; a second oxide is deposited around the inner periphery of the second via; The third via is located on the ground layer and penetrates the first dielectric layer, the first metal layer, the second dielectric layer, the second metal layer, the third dielectric layer, the first via deposited with the first oxide, and the second via deposited with the second oxide. A third oxide is deposited around the inner side of the third through-hole to form a gate oxide layer; Conductive material is deposited around the inner side of the gate oxide layer to form the common gate of the N-type transistor and the P-type transistor.

11. The manufacturing method according to claim 10, characterized in that, Also includes: Forming a first through-hole interconnect structure, a second through-hole interconnect structure, and a third through-hole interconnect structure; The first via interconnect structure is located on the ground layer and penetrates the first dielectric layer, the second dielectric layer, and the third dielectric layer; it is used to connect the GND electrode to the ground layer. The second via interconnect structure is located on the second metal layer and penetrates the third dielectric layer; it is used to connect the input electrode to the second metal layer. The third via interconnect structure is located on the first metal layer, penetrates the second dielectric layer and the third dielectric layer, and is used to connect the output electrode to the first metal layer.

Images