Display panel and design method thereof

Abstract

The application discloses a display panel and a design method thereof. The display panel has a first display area and a second display area, and the first display area and the second display area are respectively provided with power supply wires and signal wires. The first display area comprises a plurality of first sub-pixels, and the first sub-pixels are respectively electrically connected with the power supply wires and the signal wires. The second display area comprises a plurality of second sub-pixels, and the second sub-pixels are respectively electrically connected with the power supply wires and the signal wires. In the second display area, the orthographic projection of the signal wires and the orthographic projection of the power supply wires at least partially overlap. When the display panel works, the current difference between the first current value flowing through the thin film transistor of the first sub-pixel and the second current value flowing through the thin film transistor of the second sub-pixel is less than a preset threshold value. The display panel can improve the problem of uneven brightness and improve the display effect.

Description

Technical Field

[0001] This application relates to the field of display technology, specifically to a display panel and its design method. Background Technology

[0002] Mini / Micro-LED (MLED) display technology has entered a stage of accelerated development in recent years. MLED has the characteristics of high contrast and high color rendering performance, and can be used in small and medium-sized high value-added display applications, thus becoming a hot spot for major panel manufacturers.

[0003] However, due to the narrow bezel size limitation of the MLED panel, the fan-out traces must be placed within the AA area. Placing them outside the display area would result in excessively large LED spacing at the bezel, causing the fan-out traces to overlap with the power traces within the display area, leading to parasitic capacitance. The fan-out traces are typically data signal lines. When the LEDs are lit, the pixel at the overlap with the fan-out trace experiences a voltage increase due to the parasitic capacitance between the power and data signal lines. This increases the current flowing through the LED in that pixel. Consequently, given the same data signal, the data voltage at the pixel overlapping with the fan-out trace is higher than that at pixels not overlapping, resulting in higher brightness at the overlapping pixels and uneven brightness across the display panel.

[0004] Therefore, how to solve the problem of uneven brightness on the display panel is an urgent issue that needs to be addressed. Summary of the Invention

[0005] This application provides a display panel and its design method, which can improve the problem of uneven brightness in the display panel and enhance the display effect.

[0006] In a first aspect, this application provides a display panel having a first display area and a second display area. Both the first and second display areas are provided with power lines and signal lines. The first display area includes a plurality of first sub-pixels, which are electrically connected to the power lines and the signal lines respectively. The second display area includes a plurality of second sub-pixels, which are electrically connected to the power lines and the signal lines respectively. In the second display area, the orthographic projection of the signal lines and the orthographic projection of the power lines at least partially overlap. When the display panel is in operation, the current difference between a first current value flowing through the thin-film transistor of the first sub-pixel and a second current value flowing through the thin-film transistor of the second sub-pixel is less than a preset threshold.

[0007] Optionally, in some embodiments of this application, the channel width-to-length ratios of the thin-film transistors corresponding to the first sub-pixel and the second sub-pixel are not equal.

[0008] Optionally, in some embodiments of this application, the channel length of the thin-film transistor of the second sub-pixel is greater than the channel length of the thin-film transistor of the first sub-pixel.

[0009] Optionally, in some embodiments of this application, the channel width of the thin-film transistor of the second sub-pixel is equal to the channel width of the thin-film transistor of the first sub-pixel.

[0010] Optionally, in some embodiments of this application, the channel width of the thin-film transistor of the second sub-pixel is smaller than the channel width of the thin-film transistor of the first sub-pixel.

[0011] Optionally, in some embodiments of this application, the first current value is equal to the second current value.

[0012] On the other hand, embodiments of this application provide a design method for a display panel, the method comprising: providing a reference display panel having a first display area and a second display area disposed adjacent to each other, the first display area including a plurality of first sub-pixels, and the second display area including a plurality of second sub-pixels; acquiring a first current value of a thin-film transistor flowing through the first sub-pixel and a second current value of a thin-film transistor flowing through the second sub-pixel when the reference display panel is in operation, and calculating a current difference between the first current value and the second current value; calculating a target channel width-to-length ratio of the thin-film transistor of the second sub-pixel when the current difference is less than a preset threshold; and designing a target display panel according to the target channel width-to-length ratio, wherein the channel width-to-length ratio of the thin-film transistor of the second sub-pixel of the target display panel is equal to the target channel width-to-length ratio.

[0013] Optionally, in some embodiments of this application, the step of calculating the target channel width-to-length ratio of the thin-film transistor of the second sub-pixel when the current difference is less than a preset threshold specifically includes: adjusting the initial channel length of the thin-film transistor of the second sub-pixel according to the current difference; and obtaining the current channel width-to-length ratio of the thin-film transistor of the second sub-pixel as the target channel width-to-length ratio of the thin-film transistor of the second sub-pixel when the current difference is less than the preset threshold.

[0014] Optionally, in some embodiments of this application, the step of designing a target display panel according to the target channel aspect ratio, wherein the channel aspect ratio of the thin-film transistor of the second sub-pixel of the target display panel is equal to the target channel aspect ratio, specifically includes: obtaining the target channel aspect ratio of the thin-film transistor of the second sub-pixel in full grayscale; determining the ratio of the number of each target channel aspect ratio to the total number of multiple target channel aspect ratios; and fabricating the thin-film transistor of the second sub-pixel of the target display panel according to the target channel aspect ratio with the highest ratio.

[0015] Optionally, in some embodiments of this application, the step of designing a target display panel according to the target channel width-to-length ratio, wherein the channel width-to-length ratio of the thin-film transistor of the second sub-pixel of the target display panel is equal to the target channel width-to-length ratio, specifically includes: obtaining the target channel width-to-length ratio of the thin-film transistor of the second sub-pixel in full grayscale; obtaining the change in each target channel width-to-length ratio with respect to the corresponding initial channel width-to-length ratio, and obtaining the average of multiple changes; and fabricating the thin-film transistor of the second sub-pixel of the target display panel based on the target channel width-to-length ratio calculated from the initial channel width-to-length ratio and the average of the changes.

[0016] This application provides a display panel and its design method. The display panel has a first display area and a second display area, both of which are provided with power lines and signal lines. The first display area includes a plurality of first sub-pixels, which are electrically connected to the power lines and the signal lines respectively. The second display area includes a plurality of second sub-pixels, which are electrically connected to the power lines and the signal lines respectively. In the second display area, the orthographic projection of the signal lines and the orthographic projection of the power lines at least partially overlap. When the display panel is operating, the current difference between the first current value flowing through the thin-film transistor of the first sub-pixel and the second current value flowing through the thin-film transistor of the second sub-pixel is less than a preset threshold. By controlling the second current value flowing through the second sub-pixels, this display panel can improve the problem of uneven brightness and enhance the display effect. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. The accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 This is a schematic diagram of the structure of a reference display panel provided in an embodiment of this application;

[0019] Figure 2 This is a top view of the reference display panel provided in the embodiments of this application;

[0020] Figure 3 This is an equivalent circuit diagram of the first sub-pixel provided in an embodiment of this application;

[0021] Figure 4 This is an equivalent circuit diagram of the second sub-pixel provided in an embodiment of this application;

[0022] Figure 5 This is a schematic diagram illustrating uneven brightness of a reference display panel provided in an embodiment of this application;

[0023] Figure 6 This is a flowchart illustrating the design method of the first display panel provided in the embodiments of this application;

[0024] Figure 7 This is a graph showing the relationship between the threshold voltage and channel length, and the current and channel length of the thin-film transistor provided in the embodiments of this application.

[0025] Figure 8 This is a flowchart illustrating a second display panel design method provided in an embodiment of this application;

[0026] Figure 9 yes Figure 6 One of the flowcharts for the sub-steps in step S20;

[0027] Figure 10 yes Figure 6 The second flowchart of the sub-steps in step S20;

[0028] Figure 11 yes Figure 6 One of the flowcharts for the sub-steps in step S30;

[0029] Figure 12 yes Figure 6 The second flowchart of the sub-steps in step S30;

[0030] Figure 13 yes Figure 6 A schematic diagram of the first type of sub-step in step S40;

[0031] Figure 14 yes Figure 6 The second process diagram of the sub-step S40. Detailed Implementation

[0032] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0033] This application provides a display panel and its design method. The design method improves the problem of uneven brightness in the display panel and enhances the display effect. Detailed descriptions follow. It should be noted that the order of description of the following embodiments is not intended to limit the preferred order of the embodiments. Furthermore, in the description of this application, the term "comprising" means "including but not limited to". The terms "first", "second", "third", etc., are used merely as identifiers to distinguish different objects, not to describe a specific order.

[0034] Please see Figures 1 to 5 , Figure 1 This is a schematic diagram of the structure of a reference display panel provided in an embodiment of this application; Figure 2 This is a top view of the reference display panel provided in the embodiments of this application; Figure 3 This is an equivalent circuit diagram of the first sub-pixel provided in an embodiment of this application; Figure 4 This is an equivalent circuit diagram of the second sub-pixel provided in an embodiment of this application; Figure 5 This is a schematic diagram illustrating uneven brightness of a reference display panel provided in an embodiment of this application.

[0035] In the embodiments of this application, such as Figure 1 and Figure 2 As shown, the first display area 10 of the reference display panel includes a plurality of first sub-pixels 11, power lines 30, and signal lines 40, with the first sub-pixels 11 electrically connected to the power lines 30 and signal lines 40 respectively; the second display area 20 includes a plurality of second sub-pixels 21, power lines 30, and signal lines 40, with the second sub-pixels 21 electrically connected to the power lines 30 and signal lines 40 respectively, wherein, in the second display area 20, the orthographic projection of the signal lines 40 and the orthographic projection of the power lines 30 at least partially overlap; wherein, when the display panel is working, the current difference between the first current value of the thin-film transistor flowing through the first sub-pixel 11 and the second current value of the thin-film transistor flowing through the second sub-pixel 21 is less than a preset threshold.

[0036] In this embodiment, the power supply trace 30 includes a first power supply line VDD for providing a constant high voltage level and a second power supply line VSS for providing a constant low voltage level. The power supply trace 30 extends along a first direction Y, which can be either the width direction or the length direction of the display panel. Figure 1Taking the first direction Y as the width direction of the display panel as an example; the signal trace 40 includes a data signal line Data, and the signal trace 40 includes a first connecting segment 41 extending along the first direction Y and a second connecting segment 42 extending along the second direction X. The first connecting segment 41 is located in the first display area 10 and extends to the second display area 20, and the second connecting segment 42 is located in the second display area 20. The orthographic projection of the second connecting segment 42 at least partially overlaps with the orthographic projection of the power trace 30. Therefore, parasitic capacitances Cdd and Cds are generated between the power trace 30 and the second connecting segment 42 of the signal trace 40. Correspondingly, the second direction X can be the width direction or the length direction of the display panel. Figure 1 Taking the second direction X as the width direction of the display panel as an example.

[0037] In this embodiment, the channel width-to-length ratios of the thin-film transistors corresponding to the first sub-pixel and the second sub-pixel are not equal. Specifically, the channel length of the thin-film transistor of the second sub-pixel is greater than the channel length of the thin-film transistor of the first sub-pixel. Further, the channel width of the thin-film transistor of the second sub-pixel is equal to the channel width of the thin-film transistor of the first sub-pixel.

[0038] In this embodiment, the channel width-to-length ratios of the thin-film transistors corresponding to the first sub-pixel and the second sub-pixel are not equal. Specifically, the channel width of the thin-film transistor of the second sub-pixel is smaller than the channel width of the thin-film transistor of the first sub-pixel. Further, the channel width of the thin-film transistor of the second sub-pixel may or may not be equal to the channel width of the thin-film transistor of the first sub-pixel, as long as the current difference between the first current value flowing through the thin-film transistor of the first sub-pixel 11 and the second current value flowing through the thin-film transistor of the second sub-pixel 21 is less than a preset threshold when the display panel is working.

[0039] Preferably, by setting the channel width-to-length ratio of the thin-film transistors corresponding to the first sub-pixel and the second sub-pixel to be unequal, the preset threshold is 0, that is, the first current value is equal to the second current value.

[0040] Specifically, such as Figure 3As shown, the first sub-pixel 11 includes a first transistor T1, a second transistor T2, a third transistor T3, a capacitor C, and a switch SW1. The gate of the first transistor T1 is electrically connected to the scan signal line scan, one of the source and drain of the first transistor T1 is electrically connected to the data signal line Data, and the other of the source and drain of the first transistor T1 is electrically connected to the first node G. The gate of the second transistor T2 is electrically connected to the first node G, and one of the source and drain of the second transistor T2 is electrically connected to the first power supply line VDD. The second transistor... One of the source and drain of transistor T2 is electrically connected to the second node S; one end of capacitor C is electrically connected to the first node G, and the other end of capacitor C is electrically connected to the second node S; the gate of the third transistor T3 is electrically connected to the sensing signal line Sensing; one of the source and drain of the second transistor T2 is electrically connected to one end of switch SW1, and the other end of the source and drain of the second transistor T2 is electrically connected to the second node S; one end of switch SW1 is also electrically connected to the ADC circuit, and the other end of switch SW1 is electrically connected to the reference signal line Vref.

[0041] like Figure 4 As shown, the second sub-pixel 21 has the same structure as the first sub-pixel 11. However, there is a parasitic capacitance Cdd between the first power supply terminal VDD of the second sub-pixel 21 and the data signal line Data; there is a parasitic capacitance Cds between the second power supply terminal VSS of the second sub-pixel 21 and the data signal line Data.

[0042] This configuration causes the second sub-pixel 21, located near the second connection segment 42 of the signal trace 40, to experience an increased potential due to the parasitic capacitances Cdd and Cds between the power supply trace 30 and the second connection segment 42 of the signal trace 40. This results in an increase in the data voltage Vdata on the second connection segment 42 of the signal trace 40 due to coupling, leading to an increase in the current flowing through the second sub-pixel 21. This, in turn, causes... Figure 5 As shown, when given the same data signal Data, the data voltage Vdata of the second sub-pixel 21 closer to the second connection segment 42 of the signal trace 40 is higher than that of the first sub-pixel 11 farther from the second connection segment 42 of the signal trace 40. That is, the brightness of the second sub-pixel 21 closer to the second connection segment 42 of the signal trace 40 is higher than that of the first sub-pixel 11 farther from the second connection segment 42 of the signal trace 40, which leads to uneven brightness of the display panel.

[0043] To address the aforementioned issues, the display panel design method provided in this application, by designing the thin-film transistors of the first sub-pixel and the second sub-pixel, can control the current flowing through the second sub-pixel 21, thereby improving the uneven brightness problem of the display panel and enhancing the display effect.

[0044] Please see Figure 6 , Figure 6 This is a flowchart illustrating a first method for designing a display panel according to an embodiment of this application. This application provides a method for designing a display panel, such as... Figure 6 As shown, the design method for the display panel includes:

[0045] S10. A reference display panel is provided, the reference display panel having a first display area 10 and a second display area 20 arranged adjacent to each other, the first display area 10 including a plurality of first sub-pixels 11; the second display area 20 including a plurality of second sub-pixels 21.

[0046] Specifically, the thin-film transistors of the first sub-pixel 11 and the second sub-pixel 21 have an initial channel width-to-length ratio. Since the brightness of the second sub-pixel of the first sub-pixel is primarily related to the current flowing through the sub-pixel, while the reference... Figure 7 , Figure 7 This is a graph showing the relationship between the threshold voltage and channel length of the thin-film transistor (TFT) and the current and channel length, as provided in the embodiments of this application. The current flowing through the sub-pixel is related to the threshold voltage of the TFT; therefore, this application can adjust the brightness of the display panel by changing the current flowing through the sub-pixel and thus adjusting the threshold voltage of the TFT.

[0047] S20. Obtain the first current value of the thin-film transistor flowing through the first sub-pixel 11 and the second current value of the thin-film transistor flowing through the second sub-pixel 21 when the reference display panel is working, and calculate the current difference between the first current value and the second current value.

[0048] In this embodiment, the second sub-pixel 21 in the second display area 20 is affected by the parasitic capacitances Cdd and Cds between the second connection segment 42 of the power supply line 30 and the signal line 40, causing the second current value to be greater than the first current value, and the brightness of the second display area 20 to be higher than that of the first display area 10. Therefore, by obtaining the second current value and comparing it with the first current value, the current difference between the first current value and the second current value is obtained to determine the magnitude of the influence of the parasitic capacitances Cdd and Cds on the second sub-pixel 21. Then, by reducing the second current value of the second sub-pixel 21, the second current value is made to be consistent with the first current value, so as to achieve the same brightness between the first sub-pixel 11 and the second sub-pixel 21.

[0049] S30. When the current difference is less than a preset threshold, obtain the target channel width-to-length ratio of the thin-film transistor of the second sub-pixel 21.

[0050] In this embodiment, the relationship between the current value I and the channel width-to-length ratio W / L of the thin-film transistor is as follows:

[0051]

[0052] Where I represents the second current value, μ represents the mobility, Cox represents the capacitance of the thin-film transistor, W represents the channel width of the thin-film transistor, L represents the channel length of the thin-film transistor, Vgs represents the gate-source voltage of the thin-film transistor, and Vth represents the threshold voltage of the thin-film transistor.

[0053] In this embodiment, the current difference ΔI between the first current value I1 and the second current value I2 is I2-I1. Based on the current difference ΔI, the channel width-to-length ratio change ΔW / L of the thin-film transistor of the second sub-pixel 21 is obtained. Let the initial channel width-to-length ratio of the thin-film transistor corresponding to the second sub-pixel 21 be W1 / L1, and the target channel width-to-length ratio of the thin-film transistor corresponding to the second sub-pixel 21 be W2 / L2. Then the channel width-to-length ratio change ΔW / L is W1 / L1-W2 / L2.

[0054] For example, if the initial channel width-to-length ratio W1 / L1 is 1 / 10 and the change in channel width-to-length ratio ΔW / L is 1 / 30, then the calculated target channel width-to-length ratio W2 / L2 is 1 / 15.

[0055] In this embodiment, the second current value of the second sub-pixel 21 in the second display area 20 is reduced by decreasing the aspect ratio of the thin-film transistor in the second sub-pixel 21 and increasing the threshold voltage of the driving thin-film transistor in the second sub-pixel 21. The threshold voltage of the driving thin-film transistor is affected by the process and device design. Once the process is determined, the threshold voltage can be adjusted by optimizing the design of the second sub-pixel 21 in the second display area 20. In this embodiment, the threshold voltage of the driving thin-film transistor is adjusted by adjusting the channel length and / or channel width, i.e., adjusting the aspect ratio of the channel. Preferably, the channel length of the driving thin-film transistor is adjusted to regulate the threshold voltage of the driving thin-film transistor. The larger the channel length of the driving thin-film transistor, the higher the threshold voltage. Therefore, as... Figure 7 As shown, by slightly increasing the channel length of the driving transistor in the second sub-pixel 21 of the second display area 20, its channel aspect ratio can be reduced and its threshold voltage can be increased, thereby reducing the current flowing through the second sub-pixel 21 in the second display area 20. This will make the brightness of the second display area 20 and the first sub-pixel 11 in the first display area 10 more consistent, thus improving the problem of uneven brightness in the display panel.

[0056] After calculating the target channel width-to-length ratio of the thin-film transistor of the second sub-pixel, step S40 is executed to design the target display panel according to the target channel width-to-length ratio, wherein the channel width-to-length ratio of the thin-film transistor of the second sub-pixel of the target display panel is equal to the target channel width-to-length ratio.

[0057] In this embodiment, the channel width-to-length ratio of the thin-film transistor corresponding to the second sub-pixel 21 is adjusted from W1 / L1 to W2 / L2. Subsequently, the thin-film transistors corresponding to the second sub-pixel 21 are fabricated according to the target channel width-to-length ratio W2 / L2. At the same time, the thin-film transistors corresponding to the first sub-pixel 11 are fabricated according to the initial channel width-to-length ratio W1 / L1, resulting in an improved display panel.

[0058] It should be noted that the reference display panel is the same model as the display panel finally manufactured in the embodiment of the present invention. Except for the difference in the width-to-length ratio of the channel of the thin-film transistor in the second display area 20, the other parameters, dimensions, materials, etc. are the same.

[0059] Please see Figure 8 , Figure 8 This is a flowchart illustrating a second display panel design method provided in an embodiment of this application. Figure 8 As shown, before step S20, step S00 is also included:

[0060] S00. Determine the initial channel width-to-length ratio of the thin-film transistor of the first sub-pixel 11 in the reference display panel, wherein the initial channel width-to-length ratio of the thin-film transistor of the first sub-pixel 11 is equal to the initial channel width-to-length ratio of the thin-film transistor of the second sub-pixel 21.

[0061] Specifically, after selecting the reference display panel, it is necessary to first determine the initial channel width-to-length ratio of the thin-film transistor of the first sub-pixel 11 and the initial channel width-to-length ratio of the thin-film transistor of the second sub-pixel 21 in the reference display panel.

[0062] The initial channel width-to-length ratio of the thin-film transistor in the first sub-pixel 11 and the initial channel width-to-length ratio of the thin-film transistor in the second sub-pixel 21 can be obtained by reading the design manual of the reference display panel. Alternatively, the reference display panel can be powered on, and the initial channel width-to-length ratio of the thin-film transistor in the first sub-pixel 11 can be calculated by detecting the current flowing through the thin-film transistor in the first sub-pixel 11.

[0063] Optionally, the initial channel width-to-length ratio of the thin-film transistor of the first sub-pixel 11 and the initial channel width-to-length ratio of the thin-film transistor of the second sub-pixel 21 may be equal or unequal, and this application does not impose any specific limitation.

[0064] Please see Figure 9 , Figure 9 yes Figure 6 One of the flowcharts for the sub-steps of step S20. Step S20 specifically includes:

[0065] S2011. Obtain the first current value and the second current value corresponding to the first sub-pixel 11 and the second sub-pixel 21 under the preset grayscale, respectively.

[0066] In this embodiment, the preset grayscale can take one or more values ​​between 0 and 255. Specifically, the second current value I2 of the second sub-pixel 21 is greater than the first current value I1 of the first sub-pixel 11.

[0067] S2012. Subtract the first current value from the second current value to obtain the current difference between the first current value and the second current value.

[0068] In this embodiment of the application, the current difference ΔI = I2 - I1, and the channel width-to-length ratio change ΔW / L calculated based on the current difference ΔI is a positive value. In addition, since the target channel width-to-length ratio W2 / L2 is equal to the initial channel width-to-length ratio W1 / L1 minus the channel width-to-length ratio change ΔW / L, the target channel width-to-length ratio W2 / L2 is less than the initial channel width-to-length ratio W1 / L1.

[0069] As one specific embodiment of this application, please refer to Figure 10 , Figure 10 yes Figure 6 The second flowchart illustrates the sub-steps of step S20. Step S20 specifically includes:

[0070] S2021. Obtain multiple first current values ​​corresponding to the first sub-pixel 11 in full grayscale and multiple second current values ​​corresponding to the second sub-pixel 21 in full grayscale.

[0071] In this embodiment of the application, multiple first current values ​​corresponding to the first sub-pixel 11 at gray levels 0 to 255 can be obtained respectively, and correspondingly, multiple second current values ​​corresponding to the second sub-pixel 21 at gray levels 0 to 255 can be obtained.

[0072] S2022. Subtract the first current value from the second current value under the same gray level to obtain multiple current difference values ​​corresponding to the first current value and the second current value under the full gray level.

[0073] In this embodiment, the current difference between the first current value and the second current value at the same gray level is obtained, thereby obtaining the influence of the parasitic capacitances Cdd and Cds between the second connection segment 42 of the power supply trace 30 and the signal trace 40 at different gray levels on the second current value of the second sub-pixel 21.

[0074] Please see Figure 11 , Figure 11 yes Figure 6 One of the flowcharts for the sub-steps of step S30. Step S30 specifically includes:

[0075] S3011. Adjust the initial channel width of the thin-film transistor of the second sub-pixel 21 according to the current difference.

[0076] Specifically, the current difference ΔI between the first current value I1 and the second current value I2 is I2-I1. Based on the current difference ΔI, the change in the channel width-to-length ratio ΔW / L of the thin-film transistor of the second sub-pixel 21 is obtained. Let the initial channel width-to-length ratio of the thin-film transistor corresponding to the second sub-pixel 21 be W1 / L1, and the target channel width-to-length ratio of the thin-film transistor corresponding to the second sub-pixel 21 be W2 / L2. Then the change in the channel width-to-length ratio ΔW / L is W1 / L1-W2 / L2.

[0077] S3012. When the current difference is less than a preset threshold, the current channel width-to-length ratio of the thin-film transistor of the second sub-pixel 21 is obtained as the target channel width-to-length ratio of the thin-film transistor of the second sub-pixel 21.

[0078] In this embodiment, preferably, the preset threshold is 0, that is, the first current value of the first sub-pixel 11 is equal to the second current value of the second sub-pixel 21, and thus the brightness of the first sub-pixel 11 is consistent with the brightness of the second sub-pixel 21. Further, the preset threshold may not be 0, as long as the current difference between the first and second current values ​​does not cause a significant brightness difference between the first sub-pixel 11 and the second sub-pixel 21.

[0079] In this embodiment of the application, after calculating the change in the channel width-to-length ratio of the thin-film transistor corresponding to the second sub-pixel 21, it is necessary to determine the channel length and channel width of the thin-film transistor corresponding to the second sub-pixel 21 based on the change in the channel width-to-length ratio.

[0080] Specifically, the channel length of the thin-film transistor (TFT) can be adjusted according to the change in the channel width-to-length ratio, or the channel width can be adjusted, or both the channel length and channel width can be adjusted simultaneously. Preferably, the channel length of the TFT is adjusted according to the change in the channel width-to-length ratio.

[0081] When adjusting only the channel length of the thin-film transistor (TFT) is determined based on the change in the channel width-to-length ratio, the channel width of the TFT remains unchanged. The channel length of the TFT corresponding to the second sub-pixel 21 is obtained based on the initial channel width and the change in the channel width-to-length ratio. When adjusting only the channel width of the TFT is determined based on the change in the channel width-to-length ratio, the channel length of the TFT remains unchanged. The channel width of the TFT corresponding to the first sub-pixel 11 is obtained based on the initial channel length and the change in the channel width-to-length ratio. When adjusting both the channel length and channel width of the TFT is determined based on the change in the channel width-to-length ratio, corresponding adjustments are made to the initial channel length and initial channel width so that the ratio of the adjusted channel width to the channel length is equal to the target channel width-to-length ratio.

[0082] For example, if the initial channel width-to-length ratio W1 / L1 is 1 / 10 and the channel width-to-length ratio change ΔW / L is 1 / 30, then the calculated target channel width-to-length ratio W2 / L2 is 1 / 15. The initial channel width of the thin-film transistor is 1 micrometer and the initial channel length is 10 micrometers. If only the channel length of the thin-film transistor is adjusted, the channel length of the thin-film transistor needs to be adjusted from the initial channel length of 10 micrometers to 15 micrometers, while the channel width of the thin-film transistor remains 1 micrometer.

[0083] Please see Figure 12 , Figure 12 yes Figure 6 The second flowchart illustrates the sub-steps of step S30. Step S30 specifically includes:

[0084] S3021. Adjust the initial channel length of the thin-film transistor of the second sub-pixel 21 according to the current difference.

[0085] In one specific implementation, the current difference ΔI between the first current value I1 and the second current value I2 is I2-I1. Based on the current difference ΔI, the change in the channel width-to-length ratio ΔW / L of the thin-film transistor of the second sub-pixel 21 is obtained. Let the initial channel width-to-length ratio of the thin-film transistor corresponding to the second sub-pixel 21 be W1 / L1, and the target channel width-to-length ratio of the thin-film transistor corresponding to the second sub-pixel 21 be W2 / L2. Then the change in the channel width-to-length ratio ΔW / L is W1 / L1-W2 / L2. Specifically, the width of the thin-film transistor of the second sub-pixel 21 is kept constant, that is, W1=W2. Therefore, it is only necessary to adjust L2 to L1+L.

[0086] S3022. When the current difference is less than a preset threshold, the current channel length of the thin film transistor of the second sub-pixel 21 is obtained as the target channel length of the thin film transistor of the second sub-pixel 21.

[0087] Specifically, the preset threshold can be 0 or not. It is only necessary to adjust the channel length of the thin film transistor of the second sub-pixel 21 so that the second current flowing through the driving thin film transistor of the second sub-pixel 21 does not cause a significant difference between the brightness of the second sub-pixel 21 and the brightness of the first sub-pixel 11. Therefore, when the corresponding current difference makes the brightness of the first sub-pixel 11 and the brightness of the second sub-pixel 21 tend to be consistent, the channel length of the thin film transistor of the second sub-pixel 21 is the target channel length of the thin film transistor of the second sub-pixel 21.

[0088] In this embodiment, the target channel length of the thin-film transistor in the second sub-pixel 21 is greater than the initial channel length of the thin-film transistor in the second sub-pixel 21. That is, by slightly increasing the channel length of the driving transistor in the second sub-pixel 21 of the second display area 20, its channel aspect ratio is reduced and its threshold voltage is increased, thereby reducing the current flowing through the second sub-pixel 21 in the second display area 20. This makes the brightness of the second display area 20 and the first sub-pixel 11 in the first display area 10 more consistent, thereby improving the problem of uneven brightness in the display panel.

[0089] In this embodiment, by testing the first current value of the first sub-pixel 11 in the first display area 10 of the reference display panel and the second current value of the second sub-pixel 21 in the second display area 20 of the reference display panel, the change in the channel width-to-length ratio of the thin-film transistor corresponding to the second sub-pixel 21 is calculated. This determines the change in current flowing through the thin-film transistor corresponding to the second sub-pixel 21 when the second display area 20 of the reference display panel is subjected to coupling. The target channel width-to-length ratio is calculated based on the difference between the initial channel width-to-length ratio and the change in channel width-to-length ratio. The channel length and / or channel width of the thin-film transistor corresponding to the second sub-pixel 21 are determined. Then, the thin-film transistor of the second sub-pixel 21 in the second display area 20 of the display panel is remade according to the determined channel length and channel width. This adjusts the channel width-to-length ratio of the thin-film transistor corresponding to the second sub-pixel 21 in the second display area 20 of the display panel. By adjusting the channel width-to-length ratio, the brightness of the second display area 20 is reduced. This makes the brightness of the first display area 10 and the second display area 20 more uniform under the existing narrow bezel technology, thereby improving the display effect of the display panel.

[0090] Please see Figure 13 , Figure 13 yes Figure 6 The first flowchart illustrates the sub-step of step S40. Step S40 specifically includes:

[0091] S4011, Obtain the target channel width-to-length ratio of the thin-film transistor of the second sub-pixel 21 under full grayscale.

[0092] In this embodiment, the target channel width-to-length ratio of the thin-film transistors of the second sub-pixel 21 at gray levels 0 to 255 is obtained through simulation testing. Specifically, the target channel length of the thin-film transistors of the second sub-pixel 21 at gray levels 0 to 255 is obtained.

[0093] S4012. Determine the ratio of the number of width-to-length ratios of each target channel to the total number of width-to-length ratios of multiple target channels.

[0094] In this embodiment of the application, the target channel lengths corresponding to the thin film transistors of the second sub-pixel 21 at different gray levels are summarized and compared to obtain the proportion of different target channel length values ​​in all target channel length values.

[0095] S4013. Fabricate the thin-film transistor of the second sub-pixel 21 based on the target channel width-to-length ratio with the highest ratio.

[0096] In this embodiment, the target channel length value with the highest percentage is selected from the calculated target channel length values ​​corresponding to the thin-film transistors of the second sub-pixel 21 at different gray levels as the final target channel length value of the thin-film transistor of the second sub-pixel 21. This setting ensures that the target channel length value of the thin-film transistor of the second sub-pixel 21 can satisfy the requirement that the first current value and the second current value tend to be consistent across as many gray levels as possible.

[0097] Furthermore, after determining the channel length and channel width of the thin-film transistor corresponding to each second sub-pixel 21, the thin-film transistor corresponding to each second sub-pixel 21 in the second display area 20 is fabricated according to the determined channel length and channel width during the subsequent fabrication of the display panel.

[0098] Please see Figure 14 , Figure 14 yes Figure 6 The second flowchart illustrates the sub-step of step S40. Step S40 specifically includes:

[0099] S4021. Obtain the target channel width-to-length ratio of the thin-film transistor of the second sub-pixel 21 under full grayscale.

[0100] S4022. Obtain the change in each target channel width-to-length ratio and the corresponding initial channel width-to-length ratio, and obtain the average of multiple changes;

[0101] S4023. The thin-film transistor of the second sub-pixel 21 of the target display panel is fabricated based on the target channel width-to-length ratio calculated from the initial channel width-to-length ratio and the average of the changes.

[0102] On the other hand, this application provides a display panel manufactured using the display panel design method described above. Specifically, the display panel includes a first display area 10 and a second display area 20. Both the first display area 10 and the second display area 20 include power lines 30 and signal lines 40. The first display area 10 includes a plurality of first sub-pixels 11, which are electrically connected to the power lines 30 and the signal lines 40 respectively. The second display area 20 includes a plurality of second sub-pixels 21, which are electrically connected to the power lines 30 and the signal lines 40 respectively. In the second display area 20, the orthographic projection of the signal lines 40 and the orthographic projection of the power lines 30 at least partially overlap. When the display panel is working, the current difference between the first current value of the thin-film transistor flowing through the first sub-pixel 11 and the second current value of the thin-film transistor flowing through the second sub-pixel 21 is less than a preset threshold.

[0103] In the embodiments of this application, the channel width-to-length ratio of the thin-film transistors corresponding to the first sub-pixel 11 and the second sub-pixel 21 is not equal.

[0104] In this embodiment, the channel length of the thin-film transistor of the second sub-pixel 21 is greater than the channel length of the thin-film transistor of the first sub-pixel 11.

[0105] This application provides a display panel and its design method. The design method of the display panel can improve the problem of uneven brightness in the display panel and improve the display effect by adjusting the channel width-to-length ratio of the thin film transistor of the second sub-pixel 21 to control the second current value flowing through the second sub-pixel 21.

[0106] The above provides a detailed description of a display panel and its design method provided by the embodiments of this application. Specific examples have been used to illustrate the principles and implementation methods of this application. The description of the above embodiments is only for the purpose of helping to understand the method and core ideas of this application. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of this application. Therefore, the content of this specification should not be construed as a limitation of this application.

Claims

1. A display panel, characterized in that, The display panel has a first display area and a second display area, and both the first display area and the second display area are provided with power lines and signal lines; The first display area includes a plurality of first sub-pixels, and the first sub-pixels are electrically connected to the power supply line and the signal line respectively; The second display area includes a plurality of second sub-pixels, which are electrically connected to the power supply trace and the signal trace, respectively. The signal trace includes a first connecting segment extending along a first direction and a second connecting segment extending along a second direction. The first connecting segment is located in the first display area and extends into the second display area. The power trace extends along the first direction. The second connecting segment is located in the second display area, and the orthographic projection of the second connecting segment at least partially overlaps with the orthographic projection of the power trace. The second connecting segment is not located in the first display area. When the display panel is working, the difference between the first current value flowing through the thin-film transistor of the first sub-pixel and the second current value flowing through the thin-film transistor of the second sub-pixel is less than a preset threshold, and the channel width-to-length ratio of the thin-film transistor corresponding to the first sub-pixel is greater than the channel width-to-length ratio of the thin-film transistor corresponding to the second sub-pixel.

2. The display panel according to claim 1, characterized in that, The channel length of the thin-film transistor of the second sub-pixel is greater than the channel length of the thin-film transistor of the first sub-pixel.

3. The display panel according to claim 2, characterized in that, The channel width of the thin-film transistor of the second sub-pixel is equal to the channel width of the thin-film transistor of the first sub-pixel.

4. The display panel according to claim 1, characterized in that, The channel width of the thin-film transistor of the second sub-pixel is smaller than the channel width of the thin-film transistor of the first sub-pixel.

5. The display panel according to claim 2, characterized in that, The first current value is equal to the second current value.

6. A design method for manufacturing the display panel according to any one of claims 1 to 5, characterized in that, The method includes: A reference display panel is provided, the reference display panel having a first display area and a second display area arranged adjacent to each other, the first display area including a plurality of first sub-pixels, and the second display area including a plurality of second sub-pixels; The first current value of the thin-film transistor flowing through the first sub-pixel and the second current value of the thin-film transistor flowing through the second sub-pixel are obtained when the reference display panel is working, and the current difference between the first current value and the second current value is calculated. Calculate the target channel width-to-length ratio of the thin-film transistor of the second sub-pixel when the current difference is less than a preset threshold; The target display panel is designed according to the target channel width-to-length ratio, wherein the channel width-to-length ratio of the thin-film transistor of the second sub-pixel of the target display panel is equal to the target channel width-to-length ratio.

7. The display panel design method according to claim 6, characterized in that, The step of calculating the target channel width-to-length ratio of the thin-film transistor of the second sub-pixel when the current difference is less than a preset threshold specifically includes: Based on the current difference, the initial channel length of the thin-film transistor of the second sub-pixel is adjusted; When the current difference is less than a preset threshold, the current channel width-to-length ratio of the thin-film transistor of the second sub-pixel is obtained as the target channel width-to-length ratio of the thin-film transistor of the second sub-pixel.

8. The display panel design method according to claim 6, characterized in that, The step of designing the target display panel according to the target channel width-to-length ratio, wherein the channel width-to-length ratio of the thin-film transistor of the second sub-pixel of the target display panel is equal to the target channel width-to-length ratio, specifically includes: The target channel width-to-length ratio of the thin-film transistor of the second sub-pixel is obtained in full grayscale. Determine the ratio of the number of each of the target channel width-to-length ratios to the total number of the plurality of target channel width-to-length ratios; The thin-film transistor of the second sub-pixel of the target display panel is made according to the target channel width-to-length ratio with the highest ratio.

9. The display panel design method according to claim 6, characterized in that, The step of designing the target display panel according to the target channel width-to-length ratio, wherein the channel width-to-length ratio of the thin-film transistor of the second sub-pixel of the target display panel is equal to the target channel width-to-length ratio, specifically includes: The target channel width-to-length ratio of the thin-film transistor of the second sub-pixel is obtained in full grayscale. Obtain the change in each target channel width-to-length ratio relative to the corresponding initial channel width-to-length ratio, and then obtain the average of the multiple changes. The thin-film transistor of the second sub-pixel of the target display panel is fabricated based on the target channel width-to-length ratio calculated from the initial channel width-to-length ratio and the average of the changes.

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