Display panel and display device

Abstract

The embodiment of the present invention discloses a display panel and a display device, wherein the display panel includes a substrate, a thin film transistor layer, the thin film transistor layer includes a first thin film transistor, a first conductor layer and a fan-out line, the first fan-out sub-segment of the fan-out line and the first gate of the first thin film transistor have a first overlapping portion in their orthographic projection on the substrate, the orthographic projection of the first conductor layer on the substrate at least partially overlaps with the first overlapping portion, the spacing between a side of a first shielding portion close to the first gate and the first gate is greater than the spacing between a side of the first shielding portion close to the first fan-out sub-segment and the first fan-out sub-segment, and the present invention improves the parasitic capacitance between the first gate and the first fan-out sub-segment by setting the first shielding portion, and at the same time, sets the spacing between a side of the first shielding portion close to the first gate and the first gate to be larger, thereby avoiding the parasitic capacitance between the first shielding portion and the first gate interfering with the signal received by the first gate, thereby improving the display quality of the display panel.

Description

Technical Field

[0001] The present invention relates to the field of display, and in particular to a display panel and a display device. Background Art

[0002] Although the FIAA (Fanout In AA, fan-out routing is located in the display area) technology can reduce the width of the lower frame to a certain extent, in order to reduce the process difficulty and cost, the fan-out routing introduced by the driver chip end in the display area and the data line in the display area can be designed with the same metal (such as SD1) in the horizontal direction, and the fan-out routing in the display area can be designed with another metal (such as SD2) in the vertical direction, so as to achieve the same signal transmission effect while reducing costs and achieving a simple routing design. However, in the display panel obtained in this way, there is an overlap between the gate of the thin film transistor in the display area and the fan-out routing in the thickness direction of the display panel, thereby generating parasitic capacitance, causing interference to the data signal Data, and causing display abnormalities.

[0003] Therefore, a display panel and a display device are urgently needed to solve the above technical problems. Summary of the invention

[0004] The present invention provides a display panel and a display device, which can alleviate the technical problem of display abnormality caused by the overlap of a fan-out wiring in a display area and a gate of a thin film transistor in the display area.

[0005] The present invention provides a display panel, including a display area, wherein the display panel includes:

[0006] substrate;

[0007] A thin film transistor layer, located on one side of the substrate, comprising a first thin film transistor located in the display area and a fan-out line located in the display area;

[0008] The first thin film transistor includes a first gate;

[0009] The fan-out line comprises a first fan-out sub-segment, the first fan-out sub-segment is located at a side of the first gate away from the substrate, and an orthographic projection of the first fan-out sub-segment on the substrate has a first overlapping portion with an orthographic projection of the first gate on the substrate;

[0010] The thin film transistor layer further includes a first conductor layer, the first conductor layer is located between the first gate and the first fan-out sub-segment, the first thin film transistor further includes a first shielding portion located in the first conductor layer, and an orthographic projection of the first shielding portion on the substrate at least partially overlaps with the first overlapping portion;

[0011] The distance between a side of the first shielding portion close to the first gate and a side of the first gate close to the first shielding portion is greater than the distance between a side of the first shielding portion close to the first fan-out sub-segment and a side of the first fan-out sub-segment close to the first shielding portion.

[0012] Preferably, the first overlapping portion is located within the orthographic projection of the first shielding portion on the substrate.

[0013] Preferably, the first shielding portion is electrically connected to a constant voltage signal terminal of the display panel.

[0014] Preferably, a ratio of a distance between a side of the first shielding portion close to the first gate and a side of the first gate close to the first shielding portion to a distance between a side of the first shielding portion close to the first fan-out sub-segment and a side of the first fan-out sub-segment close to the first shielding portion is greater than 1;

[0015] A ratio of a distance between a side of the first shielding portion close to the first gate and a side of the first gate close to the first shielding portion to a distance between a side of the first shielding portion close to the first fan-out sub-segment and a side of the first fan-out sub-segment close to the first shielding portion is less than or equal to 5.5.

[0016] Preferably, a distance between a side of the first shielding portion close to the first gate and a side of the first gate close to the first shielding portion is greater than or equal to 300 nanometers, and a distance between a side of the first shielding portion close to the first gate and a side of the first gate close to the first shielding portion is less than or equal to 1100 nanometers;

[0017] A distance between a side of the first shielding portion close to the first fan-out sub-segment and a side of the first fan-out sub-segment close to the first shielding portion is greater than or equal to 200 nanometers, and a distance between a side of the first shielding portion close to the first fan-out sub-segment and a side of the first fan-out sub-segment close to the first shielding portion is less than or equal to 800 nanometers.

[0018] Preferably, the display panel further comprises a plurality of data lines located in the display area, and the data lines are connected to the first fan-out sub-segment;

[0019] The fan-out line further includes a second fan-out sub-segment, the first fan-out sub-segment extends along a first direction, the second fan-out sub-segment extends along a second direction, the data line extends along the second direction, and the first direction intersects the second direction;

[0020] The second fan-out sub-segment is located at a side of the first fan-out sub-segment away from the substrate.

[0021] Preferably, the first thin film transistor further comprises a first active layer and a first source-drain electrode layer, the first active layer is located on a side of the first gate electrode close to the substrate, and the first fan-out sub-segment is arranged on the same layer as the first source-drain electrode layer;

[0022] The thin film transistor layer further includes a first insulating layer and a second insulating layer, wherein the first insulating layer is spaced between the first gate and the first conductor layer, and the second insulating layer is spaced between the first conductor layer and the first fan-out sub-segment;

[0023] The thickness of the first insulating layer is greater than the thickness of the second insulating layer.

[0024] Preferably, the thin film transistor layer further includes a second thin film transistor located in the display area, and the second thin film transistor is electrically connected to the first thin film transistor;

[0025] The second thin film transistor includes a second active layer, a second gate, a third gate, and a second source and drain electrode layer. The second active layer is located on a side of the first active layer away from the substrate, the second gate is arranged on the same layer as the first shielding portion, the second source and drain electrode layer is arranged on the same layer as the first source and drain electrode layer, and the third gate is located on a side of the second active layer close to the substrate.

[0026] Preferably, the first insulating layer includes a first insulating sublayer, a second insulating sublayer, and a third insulating sublayer, the first insulating sublayer is located between the first gate and the third gate, the second insulating sublayer is located between the third gate and the second active layer, and the third insulating sublayer is located between the second active layer and the first conductor layer.

[0027] Preferably, the thin film transistor layer includes a first type of thin film transistor, a second type of thin film transistor, a third type of thin film transistor, a fourth type of thin film transistor, a fifth type of thin film transistor, a sixth type of thin film transistor, a seventh type of thin film transistor and an eighth type of thin film transistor located in the display area;

[0028] The source and drain of the first type of thin film transistor are electrically connected between the second node and the third node, and the gate of the first type of thin film transistor is electrically connected to the first node;

[0029] One of the source and the drain of the second type of thin film transistor is electrically connected to the second node, the other of the source and the drain of the second type of thin film transistor receives a data signal, and the gate of the second type of thin film transistor receives a first scan signal;

[0030] The source and drain of the third type of thin film transistor are electrically connected between the first node and the third node, and the gate of the third type of thin film transistor receives a second scanning signal;

[0031] One of the source and the drain of the fourth type of thin film transistor is electrically connected to the first node, the other of the source and the drain of the fourth type of thin film transistor receives a first reset signal, and the gate of the fourth type of thin film transistor receives a third scan signal;

[0032] The source and drain of the fifth type of thin film transistor are electrically connected between the first power supply terminal and the second node, and the gate of the fifth type of thin film transistor receives a light emitting control signal;

[0033] The source and drain of the sixth type of thin film transistor are electrically connected between the third node and the light emitting device, and the gate of the sixth type of thin film transistor receives a light emitting control signal;

[0034] One of the source and the drain of the seventh type of thin film transistor is electrically connected to the light emitting device, the other of the source and the drain of the seventh type of thin film transistor receives a second reset signal, and the gate of the seventh type of thin film transistor receives a fourth scan signal;

[0035] One of the source and the drain of the eighth thin film transistor is electrically connected to the second node, the other of the source and the drain of the eighth thin film transistor receives a third reset signal, and the gate of the eighth thin film transistor receives a fifth scan signal;

[0036] Among them, the seventh type of thin film transistor and / or the eighth type of thin film transistor is selected from the first thin film transistor, and the third type of thin film transistor and / or the fourth type of thin film transistor is selected from the second thin film transistor.

[0037] The present invention further provides a display device, comprising the display panel as described above.

[0038] The present invention improves the parasitic capacitance between the first gate and the first fan-out sub-segment by setting the first shielding portion. At the same time, a larger distance is set between the side of the first shielding portion close to the first gate and the first gate, thereby avoiding the parasitic capacitance between the first shielding portion and the first gate interfering with the signal received by the first gate, thereby improving the display quality of the display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without paying any creative work.

[0040] Figure 1 is a schematic diagram of display abnormality of a display panel in the prior art;

[0041] Figure 2 This is a first principle schematic diagram of display abnormality of a display panel in the prior art;

[0042] Figure 3 This is a second principle schematic diagram of display abnormality of a display panel in the prior art;

[0043] Figure 4 is a schematic diagram of a first structure of a display panel provided by an embodiment of the present invention;

[0044] Figure 5 is a schematic diagram of a second structure of a display panel provided by an embodiment of the present invention;

[0045] Figure 6 yes Figure 5 A schematic diagram of a structure in the middle E region;

[0046] Figure 7 is a third structural schematic diagram of a display panel provided by an embodiment of the present invention;

[0047] Figure 8 is a schematic diagram of a film layer structure of a pixel driving circuit of a display panel provided by an embodiment of the present invention;

[0048] Fig. 9 is a schematic diagram of the film layer structure of the first active layer of the display panel provided by an embodiment of the present invention;

[0049] Fig.10 is a schematic diagram of the film layer structure of the first gate layer of the display panel provided by an embodiment of the present invention;

[0050] Fig.11 is a schematic diagram of the film layer structure of the third conductor layer of the display panel provided by an embodiment of the present invention;

[0051] Fig.12 is a schematic diagram of the film layer structure of the second active layer of the display panel provided by an embodiment of the present invention;

[0052] Fig.13 is a schematic diagram of the film layer structure of the first conductor layer of the display panel provided by an embodiment of the present invention;

[0053] Fig.14 is a schematic diagram of the film layer structure of the first metal layer of the display panel provided by an embodiment of the present invention;

[0054] Fig.15 is a schematic diagram of the film layer structure of the second conductor layer of the display panel provided by an embodiment of the present invention;

[0055] Fig.16 is a schematic structural diagram of a first via hole of a display panel provided by an embodiment of the present invention;

[0056] Fig.17 is a schematic structural diagram of a second via hole of a display panel provided by an embodiment of the present invention;

[0057] Fig.18 is a schematic structural diagram of a third via hole of a display panel provided in an embodiment of the present invention;

[0058] Fig.19 is a result diagram of the coupling capacitance ratio before and after the first shielding portion is set according to an embodiment of the present invention;

[0059] Fig. 20 is a schematic diagram of the distance between the first gate and the first shielding portion and the degree of distortion of the scanning signal received by the first gate provided by an embodiment of the present invention;

[0060] Fig.21 is a schematic structural diagram of a pixel driving circuit provided by an embodiment of the present invention;

[0061] Fig. 22 It is a schematic diagram of the structure of a display device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0062] The technical solutions in the embodiments of the present invention will be described clearly and completely below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments in the present invention, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present invention. In addition, it should be understood that the specific implementation methods described herein are only used to illustrate and explain the present invention, and are not used to limit the present invention. In the present invention, unless otherwise specified, the directional words used, such as "upper" and "lower", generally refer to the upper and lower parts of the device in actual use or working state, specifically the drawing direction in the drawings; while "inside" and "outside" refer to the outline of the device.

[0063] See also Figure 1 Currently, since the FIAA technology sets the fan-out wiring in the display area, the fan-out wiring overlaps with the gate of the thin film transistor in the display area in the thickness direction of the display panel, and the parasitic capacitance generated causes the data signal Data to be interfered, resulting in a technical problem of abnormal display of the display panel.

[0064] See also Figures 4 to 18 , an embodiment of the present invention provides a display panel 100, including a display area AA, the display panel 100 includes:

[0065] Substrate 101;

[0066] A thin film transistor layer 102, located on one side of the substrate 101, including a first thin film transistor 103 located in the display area AA and a fan-out line 104 located in the display area AA;

[0067] The first thin film transistor 103 includes a first gate 105;

[0068] The fan-out line 104 includes a first fan-out sub-segment 106, the first fan-out sub-segment 106 is located on a side of the first gate 105 away from the substrate 101, and an orthographic projection of the first fan-out sub-segment 106 on the substrate 101 and an orthographic projection of the first gate 105 on the substrate 101 have a first overlapping portion 109;

[0069] The thin film transistor layer 102 further includes a first conductor layer 107, the first conductor layer 107 is located between the first gate 105 and the first fan-out sub-segment 106, the first thin film transistor 103 further includes a first shielding portion 108 located in the first conductor layer 107, and the orthographic projection of the first shielding portion 108 on the substrate 101 at least partially overlaps with the first overlapping portion 109;

[0070] The distance between a side of the first shielding portion 108 close to the first gate 105 and a side of the first gate 105 close to the first shielding portion 108 is greater than the distance between a side of the first shielding portion 108 close to the first fan-out sub-segment 106 and a side of the first fan-out sub-segment 106 close to the first shielding portion 108.

[0071] The embodiment of the present invention improves the parasitic capacitance between the first gate 105 and the first fan-out sub-segment 106 by setting the first shielding portion 108. At the same time, a larger distance is set between the side of the first shielding portion 108 close to the first gate 105 and the first gate 105, thereby preventing the parasitic capacitance between the first shielding portion 108 and the first gate 105 from interfering with the signal received by the first gate 105, thereby improving the display quality of the display panel 100.

[0072] The technical solution of the present invention is now described in conjunction with specific embodiments.

[0073] See also Figures 4 to 6 In this embodiment, the first thin film transistor 103 includes a first active layer 110, a first gate electrode 105, and a first source-drain electrode layer 111. The first active layer 110 is located on a side of the first gate electrode 105 close to the substrate 101, and the first source-drain electrode layer 111 is located on a side of the first gate electrode 105 away from the substrate 101.

[0074] The first source-drain electrode layer 111 may include a first source electrode and a first drain electrode, and the first source electrode and the first drain electrode are respectively connected to the first active layer 110 .

[0075] The first active layer 110 includes a first channel portion 112 and a first conductor portion 113 and a second conductor portion 114 located at opposite sides of the first channel portion 112 . The first source is connected to the first conductor portion 113 , and the first drain is connected to the second conductor portion 114 .

[0076] In some embodiments, an orthographic projection of the first channel portion 112 on the substrate 101 is located within an orthographic projection of the first gate 105 on the substrate 101 .

[0077] In some embodiments, the first thin film transistor 103 may be a polysilicon thin film transistor, for example, a low-temperature polysilicon thin film transistor, and the material of the first active layer 110 includes polysilicon material.

[0078] See also Figures 4 to 6 ,and Fig.14 In some embodiments, the first fan-out sub-segment 106 and the first source-drain layer 111 are disposed on the same layer as the first metal layer 144 to simplify the manufacturing process and reduce the manufacturing cost.

[0079] See also Figure 6 In some embodiments, the orthographic projection of the first fan-out sub-segment 106 on the substrate 101 and the orthographic projection of the first gate 105 on the substrate 101 have a first overlapping portion 109, and the first overlapping portion 109 is located within the orthographic projection of the first shielding portion 108 on the substrate 101, so that the first shielding portion 108 can maximize the shielding of signal crosstalk between the first gate 105 and the first fan-out sub-segment 106, reduce the parasitic capacitance between the first gate 105 and the first fan-out sub-segment 106, and improve the display quality of the display panel 100.

[0080] In some embodiments, the thin film transistors of the thin film transistor layer 102 located in the display area AA may be composed of the first thin film transistors 103 .

[0081] See also Figure 4 and Figure 5In some embodiments, the thin film transistor layer 102 further includes a second thin film transistor 115, and the second thin film transistor 115 is electrically connected to the first thin film transistor 103. The second thin film transistor 115 includes a second active layer 116, a second gate 117, and a second source-drain electrode layer 118. The second active layer 116 is located on a side of the first active layer 110 away from the substrate 101, the second gate 117 is located on a side of the second active layer 116 away from the substrate 101, and the second source-drain electrode layer 118 is located on a side of the second gate 117 away from the substrate 101.

[0082] See also Figures 4 to 5 ,and Fig.13 , the second gate 117 can be disposed in the same layer as the first shielding portion 108, that is, the second gate 117 can be located in the first conductor layer 107; the second source-drain layer 118 can be disposed in the same layer as the first source-drain layer 111, so as to simplify the manufacturing process and reduce the manufacturing cost of the display panel 100. When the first fan-out sub-segment 106 is disposed in the same layer as the first source-drain layer 111, the first fan-out sub-segment 106, the first source-drain layer 111 and the second source-drain layer 118 are disposed in the same layer.

[0083] The second source-drain electrode layer 118 may include a second source electrode and a second drain electrode, and the second source electrode and the second drain electrode are respectively connected to the second active layer 116 .

[0084] The second active layer 116 includes a second channel portion 119 and a third conductor portion 120 and a fourth conductor portion 121 located at two opposite sides of the second channel portion 119 . The second source is connected to the third conductor portion 120 , and the second drain is connected to the fourth conductor portion 121 .

[0085] See also Figure 4 and Figure 5 In some embodiments, the second source-drain electrode layer 118 is connected to the first active layer 110, so as to realize the electrical connection between the first thin film transistor 103 and the second thin film transistor 115. Specifically, the second source electrode is connected to the second conductor portion 114 of the first active layer 110, or the second drain electrode is connected to the first conductor portion 113 of the first active layer 110, so as to realize the electrical connection between the first thin film transistor 103 and the second thin film transistor 115.

[0086] In some embodiments, the type of the second thin film transistor 115 may be different from that of the first thin film transistor 103 . The second thin film transistor 115 may be a metal oxide transistor. The second active layer 116 includes a metal oxide material, such as indium gallium zinc oxide.

[0087] See also Figure 4 and Figure 5 In some embodiments, the second thin film transistor 115 further includes a third gate 122 located on the side of the second active layer 116 close to the substrate 101. The third gate 122 and the second gate 117 form a dual-gate structure, and the second thin film transistor 115 can be a dual-gate transistor. The orthographic projection of the second active layer 116 on the substrate 101 can be located within the orthographic projection of the third gate 122 on the substrate 101. The third gate 122 is located between the second active layer 116 and the substrate 101, and plays a role in blocking light from irradiating from the side of the substrate 101 to the second active layer 116 of the second thin film transistor 115, thereby affecting the working performance of the second thin film transistor 115. The third gate 122 is located in the third conductor layer 143 of the thin film transistor layer 102.

[0088] See also Figure 4 and Figure 5 In some embodiments, the thin film transistor layer 102 further includes a first insulating layer 123 and a second insulating layer 124, wherein the first insulating layer 123 is spaced between the first gate electrode 105 and the first conductor layer 107, and the second insulating layer 124 is spaced between the first conductor layer 107 and the first fan-out sub-segment 106. When the first fan-out sub-segment 106, the first source-drain electrode layer 111, and the second source-drain electrode layer 118 are in the same layer, the second insulating layer 124 is also spaced between the first conductor layer 107 and the first source-drain electrode layer 111, and between the first conductor layer 107 and the second source-drain electrode layer 118. Specifically, the second insulating layer 124 is spaced between the first shielding portion 108 and the first fan-out sub-segment 106, between the first shielding portion 108 and the first source-drain electrode layer 111, and between the second gate electrode 117 and the second source-drain electrode layer 118. Since the distance between the side of the first shielding portion 108 close to the first gate 105 and the side of the first gate 105 close to the first shielding portion 108 is greater than the distance between the side of the first shielding portion 108 close to the first fan-out sub-segment 106 and the side of the first fan-out sub-segment 106 close to the first shielding portion 108, the thickness of the first insulating layer 123 is greater than the thickness of the second insulating layer 124.

[0089] The material of the first insulating layer 123 and the second insulating layer 124 is selected from at least one of silicon oxide and silicon nitride.

[0090] The second insulating layer 124 may be a single layer formed of a single insulating material, or may be a single layer formed of a mixture of multiple insulating materials.

[0091] When the thin film transistor of the thin film transistor layer 102 located in the display area AA can be composed of the first thin film transistor 103, the first insulating layer 123 can be a single layer formed by a single insulating material, a single layer formed by a mixture of multiple insulating materials, or a multi-layer formed by alternating multiple insulating materials.

[0092] When the thin film transistors in the thin film transistor layer 102 located in the display area AA include the first thin film transistor 103 and the second thin film transistor 115, the first insulating layer 123 includes a first insulating sublayer 125, a second insulating sublayer 126, and a third insulating sublayer 127, the first insulating sublayer 125 is located between the first gate 105 and the third gate 122, the second insulating sublayer 126 is located between the third gate 122 and the second active layer 116, and the third insulating sublayer 127 is located between the second active layer 116 and the first conductor layer 107.

[0093] In some embodiments, the thin film transistor layer 102 further includes a third insulating layer 137 located between the first active layer 110 and the first gate 105 , and the third insulating layer 137 covers the first active layer 110 .

[0094] See also Figures 4 to 5 ,and Fig.16 In some embodiments, the thin film transistor layer 102 further includes a plurality of first via holes 128 penetrating the first insulating layer 123, the second insulating layer 124, and the third insulating layer 137, and the first source-drain electrode layer 111 is connected to the first active layer 110 through the first via holes 128. The plurality of first via holes 128 are respectively located at opposite sides of the first channel portion 112, and expose the first conductor portion 113 and the second conductor portion 114, the first source electrode extends through the first via holes 128 and contacts the first conductor portion 113 to be connected to the first active layer 110, and the first drain electrode extends through the first via holes 128 and contacts the second conductor portion 114 to be connected to the first active layer 110.

[0095] See also Figures 4 to 5 ,and Fig.17In some embodiments, when the thin film transistor layer 102 further includes the second thin film transistor 115, the thin film transistor layer 102 further includes a plurality of second via holes 129 penetrating the second insulating layer 124 and the third insulating sublayer 127, and the second source-drain electrode layer 118 is connected to the second active layer 116 through the second via holes 129. The plurality of second via holes 129 are respectively located on opposite sides of the second channel portion 119 and expose the third conductor portion 120 and the fourth conductor portion 121, the second source electrode extends through the second via holes 129 and contacts the third conductor portion 120 to thereby connect to the second active layer 116, and the second drain electrode extends through the second via holes 129 and contacts the fourth conductor portion 121 to thereby connect to the second active layer 116.

[0096] See also Figures 4 to 5 ,and Fig.16 In some embodiments, when the second source-drain electrode layer 118 is connected to the first active layer 110, such as: the second source electrode is connected to the second conductor portion 114 of the first active layer 110, or the second drain electrode is connected to the first conductor portion 113 of the first active layer 110, the first via hole 128 is also located on the side of the first channel portion 112 close to the second thin film transistor 115, and the first conductor portion 113 or the second conductor portion 114 is exposed, and the second source-drain electrode layer 118 extends into the first via hole 128 and is connected to the first conductor portion 113 or the second conductor portion 114 of the second active layer 116. When the second source is connected to the second conductor portion 114, the second source extends through the first via 128 and contacts the second conductor portion 114, thereby achieving electrical connection with the first thin film transistor 103; when the second drain is connected to the second conductor portion 114, the second drain extends through the first via 128 and contacts the first conductor portion 113, thereby achieving electrical connection with the first thin film transistor 103.

[0097] In some embodiments, the display panel 100 further includes a light emitting device layer located on a side of the first source and drain electrode layer 111 away from the substrate 101. The light emitting device layer includes a light emitting device, and the light emitting device includes an anode 134 connected to the first source electrode or the first drain electrode.

[0098] In some embodiments, the light-emitting device includes an anode 134, a light-emitting layer, and a cathode along the direction from the substrate 101 to the thin film transistor layer 102. Along the direction from the anode 134 to the cathode, the light-emitting layer includes a hole transport layer (e.g., a hole injection layer, a hole transport layer), a light-emitting material layer, and an electron transport layer (e.g., an electron transport layer, an electron injection layer).

[0099] See also Figures 4 to 5 ,and Fig.15 In some embodiments, the display panel 100 also includes a second conductor layer 140 located between the first source and drain layer 111 and the light-emitting device layer, the second conductor layer 140 includes a transition portion 141, the anode 134 is connected to the transition portion 141, and the transition portion 141 is connected to the first source or the first drain, thereby realizing the connection between the anode 134 and the first source or the first drain.

[0100] In some embodiments, the materials of the first gate 105, the first conductor layer 107, the fan-out line 104, the third gate 122, the second conductor layer 140, the first source and drain layer 111, and the second source and drain layer 118 may include at least one of molybdenum (Mo), aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), titanium (Ti), tantalum (Ta), tungsten (W), and copper (Cu), for example, it may be a combination of Ti / Cu / Ti, Ti / Ag / Ti, Ti / Al / Ti, or Mo / Al / Mo.

[0101] In some embodiments, the display panel 100 also includes a planar layer 135 located between the first source and drain layer 111 and the light-emitting device layer, and the material of the planar layer 135 can be selected from at least one of tetraethyl orthosilicate (tetraethyl orthosilicate, TEOS), silicon nitride, silicon oxide, and an organic material with a low dielectric constant (for example, polyimide, etc.).

[0102] See also Figures 4 to 5 ,and Figure 17 to Figure 18The flat layer 135 may include a first flat sub-layer 135a located between the second conductor layer 140 and the first source-drain electrode layer 111, and a second flat sub-layer 135b located between the second conductor layer 140 and the anode 134. The flat layer 135 includes a third via hole 130 and a fourth via hole 131. The third via hole 130 penetrates the first flat sub-layer 135a and exposes the first source-drain electrode layer 111. The fourth via hole 131 penetrates the second flat sub-layer 135b and exposes the transition portion 141. The anode 134 extends into the fourth via hole 131 and is connected to the transition portion 141. The transition portion 141 extends into the third via hole 130 and is connected to the first source-drain electrode layer 111. Specifically, the transition portion 141 extends into the third via hole 130 and is connected to the first source electrode or the first drain electrode.

[0103] See also Figure 7 In some embodiments, the display panel 100 further includes a plurality of data lines 132 located in the display area AA, and the data lines 132 are connected to the first fan-out sub-segment 106. The data lines 132 may be disposed on the same layer as the first fan-out sub-segment 106 on the first metal layer 144, so as to facilitate the connection between the data lines 132 and the first fan-out sub-segment 106. When the first fan-out sub-segment 106, the data lines 132, the first source-drain electrode layer 111, and the second source-drain electrode layer 118 are disposed on the same layer, the data signal Data is transmitted from the first fan-out sub-segment 106 to the data lines 132, and then transmitted from the data lines 132 to the first source-drain electrode layer 111 and / or the second source-drain electrode layer 118.

[0104] See also Figure 7 In some embodiments, the fan-out line 104 further includes a second fan-out sub-segment 133, the first fan-out sub-segment 106 extends along a first direction X, the second fan-out sub-segment 133 extends along a second direction Y, and the first direction X intersects with the second direction Y. The data line 132 extends along the second direction Y, and the data lines 132 are arranged at intervals along the first direction X. Each fan-out line 104 includes a first fan-out sub-segment 106 and a second fan-out sub-segment 133, that is, each fan-out line 104 is arranged in a bent manner. The data line 132 can also be arranged in the same layer as the second fan-out sub-segment 133, and the extension direction of the data line 132 is the same as the extension direction of the second fan-out sub-segment 133. The two are arranged in the same layer, which is conducive to spatial arrangement, simplifies the process technology of the display panel 100, and reduces manufacturing costs.

[0105] In some embodiments, the first direction X and the second direction Y may be perpendicular to each other, for example, the first direction X may be a horizontal direction, and the second direction Y may be a vertical direction. Specifically, the first direction X may be a width direction of the display panel 100, and the second direction Y may be a length direction of the display panel 100.

[0106] See also Figure 7 In some embodiments, the plurality of data lines 132 are connected to the plurality of fan-out lines 104 in a one-to-one correspondence, that is, one data line 132 is connected to one fan-out line 104. The first fan-out sub-segments 106 in the plurality of fan-out lines 104 are arranged at intervals along the second direction Y, and the second fan-out sub-segments 133 in the plurality of fan-out lines 104 are arranged at intervals along the first direction X.

[0107] In some embodiments, the second fan-out sub-segment 133 is located on a side of the first fan-out sub-segment 106 away from the substrate 101. The second fan-out sub-segment 133 may be located in the second conductor layer 140, that is, the second fan-out sub-segment 133 may be arranged in the same layer as the transition portion 141, so as to simplify the process technology and reduce the process cost. The first fan-out sub-segment 106 and the second fan-out sub-segment 133 are connected through a via located in the first flat sub-layer 135a.

[0108] In some embodiments, the driver chip (Integrated Circuit, IC) on one side of the display area AA, the fan-out line 104 is electrically connected to the driver chip at one end close to the driver chip to obtain the corresponding data signal Data and transmit it to the data line 132.

[0109] In some embodiments, the display panel 100 also includes a binding area between the driver chip and the display area AA, and the display panel 100 also includes a connecting line located in the binding area, one end of the connecting line is connected to the fan-out line 104, and the other end of the connecting line is bound and connected to the driver chip.

[0110] See also Figures 1 to 3 The inventors found that because the first fan-out sub-segment extends along the first direction X, it overlaps with the gate of at least part of the thin film transistor in the display area in the thickness direction of the display panel. When the scanning signal received by the gate jumps, due to the parasitic capacitance between the gate and the first fan-out sub-segment, the data signal transmitted by the first fan-out sub-segment becomes abnormal, and the data signal received by the light-emitting device becomes abnormal. When the scanning signal received by the gate jumps at the rising edge, the light-emitting device displays darker, and when the scanning signal received by the gate jumps at the falling edge, the light-emitting device displays brighter, resulting in a "V"-shaped display abnormality.

[0111] See also Fig.19 After research, the inventors found that by providing a first shielding portion 108 between the first fan-out sub-segment 106 and the first gate 105 that overlaps with the first fan-out sub-segment 106 in the thickness direction, and when the distance between the side of the first shielding portion 108 close to the first gate 105 and the side of the first gate 105 close to the first shielding portion 108 is greater than the distance between the side of the first shielding portion 108 close to the first fan-out sub-segment 106 and the side of the first fan-out sub-segment 106 close to the first shielding portion 108, the parasitic capacitance between the first fan-out sub-segment 106 and the first gate 105 can be effectively improved, thereby improving the display abnormality of the display panel 100.

[0112] See also Figure 6 , the spacing between the side of the first shielding portion 108 close to the first gate 105 and the side of the first gate 105 close to the first shielding portion 108 is d1, and the spacing between the side of the first shielding portion 108 close to the first fan-out sub-segment 106 and the side of the first fan-out sub-segment 106 close to the first shielding portion 108 is d2. The inventors have found that when the ratio of d1 to d2 is greater than 1, and the ratio of d1 to d2 is less than or equal to 5.5, for example, it can be 1.5, 2, 2.5, 3, 3.5, 4, 4.5, 5, etc., while effectively improving the parasitic capacitance between the first fan-out sub-segment 106 and the first gate 105, it can effectively avoid the distortion of the scanning signal received by the first gate 105 caused by the excessive parasitic capacitance generated between the first shielding portion 108 and the first gate 105.

[0113] See also Figure 6 and Fig. 20 The inventors have found that when the distance between the side of the first shielding portion 108 close to the first gate 105 and the side of the first gate 105 close to the first shielding portion 108 is less than 300 nanometers, the scanning signal received by the first gate 105 is obviously distorted due to the excessive parasitic capacitance generated between the first shielding portion 108 and the first gate 105. Wherein, Tf represents the delay time of the falling edge or rising edge of the signal.

[0114] Preferably, the distance between the side of the first shielding portion 108 close to the first gate 105 and the side of the first gate 105 close to the first shielding portion 108 is greater than or equal to 300 nanometers, and the distance between the side of the first shielding portion 108 close to the first gate 105 and the side of the first gate 105 close to the first shielding portion 108 is less than 1100 nanometers, for example, it can be 400 nanometers, 500 nanometers, 600 nanometers, 700 nanometers, 800 nanometers, 900 nanometers, 1000 nanometers, etc. The distance between the side of the first shielding portion 108 close to the first fan-out sub-segment 106 and the side of the first fan-out sub-segment 106 close to the first shielding portion 108 is greater than 200 nanometers, and the distance between the side of the first shielding portion 108 close to the first fan-out sub-segment 106 and the side of the first fan-out sub-segment 106 close to the first shielding portion 108 is less than 800 nanometers, for example, it can be 300 nanometers, 400 nanometers, 500 nanometers, 600 nanometers, 700 nanometers, etc.

[0115] In some embodiments, in the thin film transistor layer 102, the first gate 105 is located in the first gate 105 layer, and the first gate 105 layer further includes a first gate signal line, and the first gate signal line is connected to the first gate 105 to transmit a scan signal to the first gate 105. The orthographic projection of the first fan-out sub-segment 106 on the substrate 101 and the orthographic projection of the first gate signal line on the substrate 101 have a second overlapping portion, that is, the first fan-out sub-segment 106 and the first gate signal line also overlap in the thickness direction of the display panel 100. The first conductor layer 107 further includes a second shielding portion, and the orthographic projection of the second shielding portion on the substrate 101 at least partially overlaps with the second overlapping portion, so as to reduce the parasitic capacitance between the first gate signal line and the first fan-out sub-segment 106, and improve the display quality of the display panel 100.

[0116] In some embodiments, the orthographic projection of the second shielding portion on the substrate 101 covers the second overlapping portion, that is, the second overlapping portion is located within the orthographic projection of the second shielding portion on the substrate 101, so that the second shielding portion can maximize the reduction of the parasitic capacitance between the first gate signal line and the first fan-out sub-segment 106, thereby improving the display quality of the display panel 100.

[0117] In some embodiments, the second shielding portion and the first shielding portion 108 form a shielding portion located between the first gate layer 142 and the first fan-out sub-segment 106. The first shielding portion 108 and the second shielding portion may be connected, that is, the first shielding portion 108 and the second shielding portion may be integrally arranged.

[0118] See also Figures 8 to 21 In some embodiments, the display panel 100 includes a pixel driving circuit located in the display area AA, and the pixel driving circuit includes a light-emitting device D and a first thin-film transistor T1, a second thin-film transistor T2, a third thin-film transistor T3, a fourth thin-film transistor T4, a fifth thin-film transistor T5, a sixth thin-film transistor T6, a seventh thin-film transistor T7 and an eighth thin-film transistor T8 located in the thin-film transistor layer 102.

[0119] The source and drain of the first type thin film transistor T1 are electrically connected between the second node N2 and the third node N3 , and the gate of the first type thin film transistor T1 is electrically connected to the first node N1 .

[0120] One of the source and the drain of the second type thin film transistor T2 is electrically connected to the second node N2, the other of the source and the drain of the second type thin film transistor T2 receives the data signal Data, and the gate of the second type thin film transistor T2 receives the second scan signal Psan1.

[0121] A source and a drain of the third type thin film transistor T3 are electrically connected between the first node N1 and the third node N3 , and a gate of the third type thin film transistor T3 receives a third scan signal Nscan-T3 .

[0122] One of the source and the drain of the fourth type thin film transistor T4 is electrically connected to the first node N1, the other of the source and the drain of the fourth type thin film transistor T4 receives the first reset signal VI1, and the gate of the fourth type thin film transistor T4 receives the first scan signal Nscan-T4.

[0123] The source and drain of the fifth type thin film transistor T5 are electrically connected between the first power supply terminal VDD and the second node N2 , and the gate of the fifth type thin film transistor T5 receives a light emitting control signal EM.

[0124] The source and drain of the sixth type thin film transistor T6 are electrically connected between the third node N3 and the light emitting device D, and the gate of the sixth type thin film transistor T6 receives a light emitting control signal EM.

[0125] One of the source and the drain of the seventh type of thin film transistor T7 is electrically connected to the light emitting device D, the other of the source and the drain of the seventh type of thin film transistor T7 receives the second reset signal VI2, and the gate of the seventh type of thin film transistor T7 receives the fourth scan signal Pscan2.

[0126] One of the source and the drain of the eighth thin film transistor T8 is electrically connected to the second node N2, one of the source and the drain of the eighth thin film transistor T8 receives the third reset signal VI3, and the gate of the eighth thin film transistor T8 receives the fifth scan signal Pscan3.

[0127] In some embodiments, the first type of thin film transistor T1, the second type of thin film transistor T2, the fifth type of thin film transistor T5, the sixth type of thin film transistor T6, the seventh type of thin film transistor T7 and the eighth type of thin film transistor T8 are all selected from polysilicon thin film transistors, that is, the active layers of the above thin film transistors include polysilicon materials. The third type of thin film transistor T3 and the fourth type of thin film transistor T4 are selected from metal oxide transistors, that is, the active layers of the above thin film transistors include metal oxide materials.

[0128] In some embodiments, the first fan-out sub-segment 106 overlaps with the gate of the seventh thin film transistor T7 and / or the eighth thin film transistor T8 in the thickness direction of the display panel 100 , and therefore, the seventh thin film transistor T7 and / or the eighth thin film transistor T8 are selected from the first thin film transistor 103 .

[0129] In some embodiments, a first fan-out sub-segment 106 overlaps with the gates of the seventh type of thin film transistor T7 and the eighth type of thin film transistor T8, and the second shielding portion located between the first shielding portion 108 of the seventh type of thin film transistor T7 and the first shielding portion 108 of the eighth type of thin film transistor T8 is connected between the first shielding portion 108 of the seventh type of thin film transistor T7 and the first shielding portion 108 of the eighth type of thin film transistor T8.

[0130] The types of the third thin film transistor T3 and the fourth thin film transistor T4 are different from those of other thin film transistors and are selected from the second thin film transistor 115 .

[0131] The first type of thin film transistor T1, the second type of thin film transistor T2, the fifth type of thin film transistor T5, and the sixth type of thin film transistor T6 can be selected from the first thin film transistor 103, or the thin film transistor layer 102 also includes a third thin film transistor, and the structure of the third thin film transistor is similar to that of the first thin film transistor 103, except that the first fan-out sub-segment 106 does not overlap with the gate of the third thin film transistor in the thickness direction, and therefore, the first shielding portion 108 is not provided in the third thin film transistor.

[0132] In some embodiments, the light emitting device D is electrically connected between the first power supply terminal VDD and the second power supply terminal VSS. The light emitting device D can be selected from organic light emitting diodes, sub-millimeter light emitting diodes, and micro light emitting diodes.

[0133] In some embodiments, the first type thin film transistor T1 is a driving transistor, which is configured to generate a driving current in a light emitting stage according to a data signal Data written in a data writing stage, so as to drive the light emitting device D to emit light.

[0134] In some embodiments, the second-type thin-film transistor T2 is a data transistor, one of the source or the drain of the second-type thin-film transistor T2 is electrically connected to the second node N2, the other of the source or the drain of the second-type thin-film transistor T2 is electrically connected to the data line 132, and the data line 132 is configured to transmit the data signal Data, and the gate of the second-type thin-film transistor T2 is electrically connected to the first scan line, and the first scan line is configured to transmit the first scan signal Nscan-T4.

[0135] In some embodiments, the third type thin film transistor T3 is a compensation transistor, and the gate of the third type thin film transistor T3 is electrically connected to a second scan line, and the second scan line is configured to transmit a second scan signal Psan1, wherein the second scan signal Psan1 is different from the first scan signal Nscan-T4.

[0136] In some embodiments, the fourth type of thin film transistor T4 is a first reset transistor, one of the source and the drain of the fourth type of thin film transistor T4 is electrically connected to the first node N1, and the other of the source and the drain of the fourth type of thin film transistor T4 is electrically connected to a first reset line, and the first reset line is configured to transmit a first reset signal VI1; the gate of the fourth type of thin film transistor T4 is electrically connected to a third scan line, and the third scan line is configured to transmit a third scan signal Nscan-T3. The third scan signal Nscan-T3 is different from the first scan signal Nscan-T4 and the second scan signal Psan1.

[0137] In some embodiments, the fifth type of thin film transistor T5 is a first light emitting control transistor, a gate of the fifth type of thin film transistor T5 is electrically connected to a light emitting control line, and the light emitting control line is configured to transmit the light emitting control signal EM; one of the source and the drain of the fifth type of thin film transistor T5 is electrically connected to the second node N2, and the other of the source and the drain of the fifth type of thin film transistor T5 is electrically connected to a first power signal line, and the first power signal line is configured to transmit a first power signal from the first power terminal VDD.

[0138] In some embodiments, the sixth type of thin film transistor T6 is a second light emitting control transistor, and a gate of the sixth type of thin film transistor T6 is electrically connected to the light emitting control line.

[0139] In some embodiments, the seventh type of thin film transistor T7 is a second reset transistor, one of the source and the drain of the seventh type of thin film transistor T7 is electrically connected to the light emitting device D, and the other of the source and the drain of the seventh type of thin film transistor T7 is electrically connected to the second reset line, and the second reset line is configured to transmit the second reset signal VI2; the gate of the seventh type of thin film transistor T7 is electrically connected to the fourth scan line, and the fourth scan line is configured to transmit the fourth scan signal Pscan2. The fourth scan signal Pscan2 is different from the third scan signal Nscan-T3 and the second scan signal Psan1. The fourth scan signal Pscan2 is the same as or different from the first scan signal Nscan-T4.

[0140] In some embodiments, the eighth type of thin film transistor T8 is a third reset transistor, one of the source and the drain of the eighth type of thin film transistor T8 is electrically connected to the second node N2, and the other of the source and the drain of the eighth type of thin film transistor T8 is electrically connected to the third reset line VL3, and the third reset line VL3 is configured to transmit a third reset signal VI3; the gate of the eighth type of thin film transistor T8 is electrically connected to the fifth scan line, and the fifth scan line is configured to transmit a fifth scan signal Pscan3, and the fifth scan signal Pscan3 is the same as the fourth scan signal Pscan2, that is, the fifth scan line and the fourth scan line can be connected to the same scan signal terminal.

[0141] In some embodiments, the second type thin film transistor T2 and the third type thin film transistor T3 are configured to transmit the data signal Data to the first node N1 during a data writing phase.

[0142] In some embodiments, the pixel driving circuit further includes a first capacitor C1, and the first capacitor C1 is connected in series to the first power supply terminal VDD and the first node N1.

[0143] In some embodiments, the pixel driving circuit further includes a second capacitor C2, and the second capacitor C2 is connected in series between the gate of the second-type thin-film transistor T2 and the first node N1.

[0144] The working principle of the pixel driving circuit is explained below by taking the first type of thin film transistor T1, the second type of thin film transistor T2, the fifth type of thin film transistor T5, the sixth type of thin film transistor T6, the seventh type of thin film transistor T7 and the eighth type of thin film transistor T8 as P-type thin film transistors, and the third type of thin film transistor T3 and the fourth type of thin film transistor T4 as N-type thin film transistors as examples.

[0145] In the reset stage, the first scan signal Nscan-T4, the third scan signal Nscan-T3, and the light-emitting control signal EM are all high levels, the second scan signal Psan1 is low level, the fourth type thin film transistor T4 is turned on, and the first reset signal VI1 is transmitted to the first node N1 to reset the potential of the first node N1.

[0146] In the data writing stage, the second scanning signal Psan1 and the light emitting control signal EM are both high levels, the first scanning signal Nscan-T4 and the third scanning signal Nscan-T3 are both low levels, the second type thin film transistor T2 and the third type thin film transistor T3 are turned on, and the data signal Data is transmitted to the first node N1.

[0147] In some embodiments, the fourth scan signal Pscan2 and / or the fifth scan signal Pscan3 may have a low level in the reset stage and / or the data writing stage to turn on the seventh thin film transistor and / or the eighth thin film transistor, thereby allowing the second reset signal VI2 and / or the third reset signal VI3 to be transmitted to the anode 134 of the light-emitting device D to reset the anode potential of the light-emitting device D.

[0148] In the node setting stage, the first scanning signal Nscan-T4, the fourth scanning signal Pscan2 and the light-emitting control signal EM are all at high levels, the light-emitting control signal EM, the second scanning signal Psan1 and the third scanning signal Nscan-T3 are all at low levels, and the first light-emitting control tube Ts1 is turned on. Since the first type of thin film transistor T1 is in the turned-on state after the data signal Data is written to the first node N1, the first voltage signal supplied by the first voltage terminal can be transmitted to the second node N2 and the third node N3.

[0149] In the light-emitting stage, the first scanning signal Nscan-T4 and the fourth scanning signal Pscan2 are both at high levels, the light-emitting control signal EM, the second scanning signal Psan1 and the third scanning signal Nscan-T3 are all at low levels, the fifth type of thin film transistor T5 and the sixth type of thin film transistor T6 are turned on, and the first type of thin film transistor T1 generates a driving current to drive the light-emitting device D to emit light.

[0150] See also Figure 8and Fig.10 In some embodiments, the first scan line, the fourth scan line, the fifth scan line, the first reset line, and the light-emitting control line are all arranged in the same layer as the first gate 105, that is, the first scan line, the fourth scan line, the fifth scan line, the first reset line, and the light-emitting control line are all located in the first gate layer 142.

[0151] See also Figure 8 and Fig.11 , Fig.13 In some embodiments, the third thin film transistor T3 and the fourth thin film transistor T4 are both dual-gate thin film transistors, and the third thin film transistor T3 and the fourth thin film transistor T4 are both selected from the second thin film transistor 115, the second scan line portion is arranged on the same layer as the second gate electrode 117, the second scan line portion is arranged on the same layer as the third gate electrode 122 (that is, the second scan line portion is located in the third conductor layer 143), the third scan line portion is arranged on the same layer as the second gate electrode 117, and the third scan line portion is arranged on the same layer as the third gate electrode 122 (that is, the third scan line portion is located in the third conductor layer 143).

[0152] See also Figure 8 and Fig.14 In some embodiments, the second reset line is disposed in the same layer as the first fan-out sub-segment 106 , the first source-drain layer 111 , and the second source-drain layer 118 in the first metal layer 144 .

[0153] See also Figure 8 and Fig.15 In some embodiments, the first power signal line, the data line 132 , and the second fan-out sub-segment 133 are all located in the second conductor layer 140 .

[0154] See also Figure 8 and Fig.13 In some embodiments, the third reset line VL3 is disposed in the same layer as the first shielding portion 108 and the second gate 117, that is, the third reset line VL3 is located in the first conductor layer 107, and the third reset line VL3 transmits the third reset signal VI3. The first shielding portion 108 is connected to the third reset signal terminal to obtain a constant voltage signal.

[0155] In some embodiments, the substrate 101 may be a hard substrate, such as a glass substrate; or, the substrate 101 may be a flexible substrate, such as a substrate formed of polyimide. When the substrate 101 is a flexible substrate, the substrate 101 includes a first flexible sub-substrate, an intermediate layer, an adhesive layer, and a second flexible sub-substrate. The first flexible sub-substrate and the second flexible sub-substrate may be formed of the same material such as polyimide, the intermediate layer may be formed of an inorganic material including at least one of SiOx and SiNx, and the adhesive layer may be formed of hydrogenated amorphous silicon (a-Si:H).

[0156] See also Figure 4 and Figure 5 In some embodiments, the display panel 100 further includes a buffer layer 136 between the substrate 101 and the thin film transistor layer 102, and the buffer layer 136 may include one or more inorganic insulating layers, the inorganic insulating layer including materials such as silicon oxide or silicon nitride. The buffer layer 136 may provide a planarization layer on the upper surface of the substrate 101, and may block or prevent impurities and moisture from penetrating from the substrate 101 into the light-emitting layer. Specifically, the buffer layer 136 includes a first sub-buffer layer formed of, for example, silicon nitride and a second sub-buffer layer formed of, for example, silicon oxide. The second sub-buffer layer and the first sub-buffer layer may be formed of silicon nitride having the same film quality (e.g., the same density and the same film stress), and an oxide film may be positioned at the interface between the second sub-buffer layer and the first sub-buffer layer. In practical applications, the thickness of the first sub-buffer layer may be 50nm to 100nm, and the thickness of the second sub-buffer layer may be 100nm to 300nm.

[0157] See also Figure 4 and Figure 5 In some embodiments, the display panel 100 further includes a pixel definition layer 138 located on a side of the planar layer 135 away from the substrate 101 , the pixel definition layer 138 includes a pixel definition portion and a pixel definition opening, and the light emitting device is located in the pixel definition opening.

[0158] See also Figure 4 and Figure 5 In some embodiments, the display panel further includes a spacer column 139 located on a side of the pixel definition portion away from the substrate 101. The spacer column 139 is used to separate the mask plate and the light-emitting device layer during the mask process of the light-emitting device layer to avoid scratches that affect the product quality of the display panel.

[0159] In some embodiments, the display panel 100 further includes an encapsulation layer, which covers the light-emitting device layer, and the encapsulation layer can be formed by alternately laminating one or more organic layers and one or more inorganic layers. Each of the inorganic layer or the organic layer can be provided with multiple layers. The organic layer is formed by a polymer, and can be, for example, a laminated layer or a monolayer formed by any one of polyethylene terephthalate, polyimide, polycarbonate, epoxy resin, polyethylene, and polyacrylate. The organic layer can be formed by polyacrylate, specifically including a substance obtained by polymerizing a monomer composition including a diacrylate-based monomer and a triacrylate-based monomer composition. Monoacrylate-based monomers can also be included in the monomer composition. In addition, the monomer composition can also include a well-known photoinitiator such as TPO, but the monomer composition is not limited thereto. The inorganic layer can be a laminated layer or a monolayer including a metal oxide or a metal nitride. For example, the inorganic layer can include any one of SiNx, Al2O3, SiO2, and TiO2. The encapsulation layer may sequentially include a first inorganic encapsulation layer, a first organic encapsulation layer, and a second inorganic encapsulation layer on the cathode in a direction away from the substrate 101. In addition, the encapsulation layer may sequentially include a first inorganic encapsulation layer, a first organic encapsulation layer, a second inorganic encapsulation layer, a second organic encapsulation layer, and a third inorganic encapsulation layer on the cathode in a direction away from the substrate 101. In addition, the encapsulation layer may sequentially include a first inorganic encapsulation layer, a first organic encapsulation layer, a second inorganic encapsulation layer, a second organic encapsulation layer, a third inorganic encapsulation layer, a third organic encapsulation layer, and a fourth inorganic encapsulation layer on the cathode in a direction away from the substrate 101.

[0160] In some embodiments, the display panel 100 may further include a touch layer, the touch layer is located on a side of the encapsulation layer away from the substrate 101, and the touch layer may implement a touch function by self-capacitive touch or mutual-capacitive touch. When the touch layer implements the touch function by self-capacitive touch, the touch layer may have only one touch metal layer. When the touch layer implements the touch function by mutual-capacitive touch, the touch layer includes a first touch metal layer, a touch insulating layer and a second touch metal layer, wherein the touch insulating layer is located on a side of the first touch metal layer away from the first insulating layer 123, and the second touch metal layer is located on a side of the touch insulating layer away from the first insulating layer 123. The first touch metal layer may be directly disposed on the encapsulation layer, or a spacer layer may be further disposed between the first touch layer and the encapsulation layer, and the spacer layer may include an inorganic spacer layer and / or an organic spacer layer. The first touch metal layer includes a first touch electrode, a second touch electrode and a first bridge wire, the second touch metal layer includes a second bridge wire, and the first touch electrode and the second touch electrode are both metal networks; or, the second touch metal layer includes a first touch electrode, a second touch electrode and a first bridge wire, and the first touch metal layer includes a second bridge wire.

[0161] In some embodiments, the display panel 100 further includes a polarizing layer located on a side of the touch layer away from the substrate 101, and a cover layer located on a side of the polarizing layer away from the substrate 101, and the cover layer may be a flexible cover layer. The display panel 100 may further include a corresponding adhesive layer located between the polarizing layer and the cover layer.

[0162] The embodiment of the present invention improves the parasitic capacitance between the first gate 105 and the first fan-out sub-segment 106 by setting the first shielding portion 108. At the same time, a larger distance is set between the side of the first shielding portion 108 close to the first gate 105 and the first gate 105, thereby preventing the parasitic capacitance between the first shielding portion 108 and the first gate 105 from interfering with the signal received by the first gate 105, thereby improving the display quality of the display panel 100.

[0163] See also Fig. 22 An embodiment of the present invention further provides a display device 10, comprising any of the above-mentioned display panels 100 and a device body 20, wherein the device body 20 and the display panel 100 are integrated into one body.

[0164] The specific structure of the display panel 100 may be referred to any of the above embodiments and drawings of the display panel 100 , and will not be described in detail herein.

[0165] In this embodiment, the device body 20 may include a middle frame, frame glue, etc., and the display device 10 may be a display terminal such as a mobile phone, a tablet, a television, etc., which is not limited here.

[0166] The embodiment of the present invention discloses a display panel and a display device, wherein the display panel includes a substrate, a thin film transistor layer, the thin film transistor layer includes a first thin film transistor, a first conductor layer and a fan-out line, the first fan-out sub-segment of the fan-out line and the first gate of the first thin film transistor have a first overlapping portion in their orthographic projection on the substrate, the orthographic projection of the first conductor layer on the substrate at least partially overlaps with the first overlapping portion, the spacing between a side of a first shielding portion close to the first gate and the first gate is greater than the spacing between a side of the first shielding portion close to the first fan-out sub-segment and the first fan-out sub-segment, and the present invention improves the parasitic capacitance between the first gate and the first fan-out sub-segment by setting the first shielding portion, and at the same time, sets the spacing between a side of the first shielding portion close to the first gate and the first gate to be larger, thereby avoiding the parasitic capacitance between the first shielding portion and the first gate interfering with the signal received by the first gate, thereby improving the display quality of the display panel.

[0167] A display panel and a display device provided by an embodiment of the present invention are introduced in detail above. Specific examples are used herein to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core idea. At the same time, for those skilled in the art, according to the idea of ​​the present invention, there will be changes in the specific implementation methods and application scopes. In summary, the content of this specification should not be understood as a limitation on the present invention.

Claims

1. A display panel, characterized in that: Comprising a display area, the display panel comprises: substrate; a thin film transistor layer, located on one side of the substrate, comprising a first thin film transistor located in the display area, a second thin film transistor and a fan-out line located in the display area, wherein the second thin film transistor is connected to the first thin film transistor; The first thin film transistor includes a first gate and a first source-drain electrode layer, and the second thin film transistor includes a second gate; The fan-out line comprises a first fan-out sub-segment, the first fan-out sub-segment is located at a side of the first gate away from the substrate and is arranged in the same layer as the first source and drain electrode layer, and an orthographic projection of the first fan-out sub-segment on the substrate has a first overlapping portion with an orthographic projection of the first gate on the substrate; The thin film transistor layer further includes a first conductor layer, the first conductor layer is located between the first gate and the first fan-out sub-segment, the first thin film transistor further includes a first shielding portion located in the first conductor layer, an orthographic projection of the first shielding portion on the substrate at least partially overlaps with the first overlapping portion, and the second gate and the first shielding portion are arranged in the same layer; The distance between a side of the first shielding portion close to the first gate and a side of the first gate close to the first shielding portion is greater than the distance between a side of the first shielding portion close to the first fan-out sub-segment and a side of the first fan-out sub-segment close to the first shielding portion.

2. The display panel according to claim 1, characterized in that: The first overlapping portion is located within an orthographic projection of the first shielding portion on the substrate.

3. The display panel according to claim 2, characterized in that: The first shielding portion is electrically connected to the constant voltage signal terminal of the display panel.

4. The display panel according to claim 1, characterized in that: The ratio of the distance between the side of the first shielding portion close to the first gate and the side of the first gate close to the first shielding portion to the distance between the side of the first shielding portion close to the first fan-out sub-segment and the side of the first fan-out sub-segment close to the first shielding portion is greater than 1; A ratio of a distance between a side of the first shielding portion close to the first gate and a side of the first gate close to the first shielding portion to a distance between a side of the first shielding portion close to the first fan-out sub-segment and a side of the first fan-out sub-segment close to the first shielding portion is less than or equal to 5.

5.

5. The display panel according to claim 4, characterized in that: A distance between a side of the first shielding portion close to the first gate and a side of the first gate close to the first shielding portion is greater than or equal to 300 nanometers, and a distance between a side of the first shielding portion close to the first gate and a side of the first gate close to the first shielding portion is less than or equal to 1100 nanometers; A distance between a side of the first shielding portion close to the first fan-out sub-segment and a side of the first fan-out sub-segment close to the first shielding portion is greater than or equal to 200 nanometers, and a distance between a side of the first shielding portion close to the first fan-out sub-segment and a side of the first fan-out sub-segment close to the first shielding portion is less than or equal to 800 nanometers.

6. The display panel according to claim 1, characterized in that: The display panel further comprises a plurality of data lines located in the display area, the data lines being connected to the first fan-out sub-segment; The fan-out line further includes a second fan-out sub-segment, the first fan-out sub-segment extends along a first direction, the second fan-out sub-segment extends along a second direction, the data line extends along the second direction, and the first direction intersects the second direction; The second fan-out sub-segment is located at a side of the first fan-out sub-segment away from the substrate.

7. The display panel according to claim 1, characterized in that: The first thin film transistor further comprises a first active layer, and the first active layer is located on a side of the first gate close to the substrate; The thin film transistor layer further includes a first insulating layer and a second insulating layer, wherein the first insulating layer is spaced between the first gate and the first conductor layer, and the second insulating layer is spaced between the first conductor layer and the first fan-out sub-segment; The thickness of the first insulating layer is greater than the thickness of the second insulating layer.

8. The display panel according to claim 7, characterized in that: The second thin film transistor also includes a second active layer, a third gate, and a second source and drain layer. The second active layer is located on a side of the first active layer away from the substrate. The second source and drain layer is arranged on the same layer as the first source and drain layer. The third gate is located on a side of the second active layer close to the substrate.

9. The display panel according to claim 8, characterized in that: The first insulating layer includes a first insulating sublayer, a second insulating sublayer, and a third insulating sublayer. The first insulating sublayer is located between the first gate and the third gate, the second insulating sublayer is located between the third gate and the second active layer, and the third insulating sublayer is located between the second active layer and the first conductor layer.

10. The display panel according to any one of claims 1 to 9, characterized in that: The thin film transistor layer includes a first thin film transistor, a second thin film transistor, a third thin film transistor, a fourth thin film transistor, a fifth thin film transistor, a sixth thin film transistor, a seventh thin film transistor and an eighth thin film transistor located in the display area; The source and drain of the first type of thin film transistor are electrically connected between the second node and the third node, and the gate of the first type of thin film transistor is electrically connected to the first node; One of the source and the drain of the second type of thin film transistor is electrically connected to the second node, the other of the source and the drain of the second type of thin film transistor receives a data signal, and the gate of the second type of thin film transistor receives a first scan signal; The source and drain of the third type of thin film transistor are electrically connected between the first node and the third node, and the gate of the third type of thin film transistor receives a second scanning signal; One of the source and the drain of the fourth type of thin film transistor is electrically connected to the first node, the other of the source and the drain of the fourth type of thin film transistor receives a first reset signal, and the gate of the fourth type of thin film transistor receives a third scan signal; The source and drain of the fifth type of thin film transistor are electrically connected between the first power supply terminal and the second node, and the gate of the fifth type of thin film transistor receives a light emitting control signal; The source and drain of the sixth type of thin film transistor are electrically connected between the third node and the light emitting device, and the gate of the sixth type of thin film transistor receives a light emitting control signal; One of the source and the drain of the seventh type of thin film transistor is electrically connected to the light emitting device, the other of the source and the drain of the seventh type of thin film transistor receives a second reset signal, and the gate of the seventh type of thin film transistor receives a fourth scan signal; One of the source and the drain of the eighth thin film transistor is electrically connected to the second node, the other of the source and the drain of the eighth thin film transistor receives a third reset signal, and the gate of the eighth thin film transistor receives a fifth scan signal; Among them, the seventh type of thin film transistor and / or the eighth type of thin film transistor is selected from the first thin film transistor, and the third type of thin film transistor and / or the fourth type of thin film transistor is selected from the second thin film transistor.

11. A display device, characterized in that: The invention comprises the display panel as claimed in any one of claims 1 to 10.

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