High electron mobility transistor and method of making the same

Abstract

A high electron mobility transistor and a method of fabricating the same are disclosed. The high electron mobility transistor includes a substrate, a buffer layer on the substrate, a gallium nitride channel layer on the buffer layer, an aluminum gallium nitride layer on the gallium nitride channel layer, a gate recess in the aluminum gallium nitride layer, a source region and a drain region on opposite sides of the gate recess, a gallium nitride source layer and a gallium nitride drain layer grown on the aluminum gallium nitride layer in the source region and the drain region, respectively, and a P-type gallium nitride gate layer in and on the gate recess.

Description

[0001] This application is a divisional application of Chinese invention patent application (application number: 201911086103.3, application date: November 8, 2019, invention title: high electron mobility transistor and method of manufacturing the same). Technical Field

[0002] This invention relates to the field of semiconductor technology, and in particular to a gallium nitride (GaN) high-electron mobility transistor (HEMT) and its fabrication method. Background Technology

[0003] Gallium nitride high electron mobility transistors are often used in high-frequency, high-power amplifier components, characterized by high breakdown voltage, high saturation electron mobility, and high-temperature operation.

[0004] In a typical HEMT, a two-dimensional electron gas (2DEG) is generated at the semiconductor heterojunction. The 2DEG represents a very thin conductive layer with highly mobile and concentrated charge carriers that can move freely in two dimensions of the conductive layer, but are restricted in a third dimension perpendicular to the conductive layer.

[0005] Currently, this technology still needs to overcome the shortcomings and deficiencies of existing technologies by providing HEMTs with high withstand voltage or high threshold voltage (Vt) and low on-resistance (Ron). Summary of the Invention

[0006] The main objective of this invention is to provide a high electron mobility transistor with high withstand voltage or high threshold voltage (Vt) and low on-resistance (Ron) to overcome the shortcomings and deficiencies of the prior art.

[0007] The present invention provides a high electron mobility transistor comprising: a substrate; a buffer layer on the substrate; a gallium nitride channel layer on the buffer layer; an aluminum gallium nitride layer on the gallium nitride channel layer; a gate recess in the aluminum gallium nitride layer; a source region and a drain region on opposite sides of the gate recess; a gallium nitride source layer and a gallium nitride drain layer respectively grown on the aluminum gallium nitride layer in the source region and the drain region; and a p-type gallium nitride gate layer located within and on the gate recess.

[0008] According to an embodiment of the present invention, the gallium nitride source layer and the gallium nitride drain layer are made of N ++ It is composed of gallium nitride doping.

[0009] According to an embodiment of the present invention, the gallium nitride source layer and the gallium nitride drain layer are composed of indium gallium nitride.

[0010] According to an embodiment of the present invention, the gate recess extends through the aluminum gallium nitride layer.

[0011] According to an embodiment of the present invention, the gate recess does not penetrate the aluminum gallium nitride layer, and the remaining thickness of the aluminum gallium nitride layer at the bottom of the gate recess is less than or equal to 2 nm.

[0012] According to an embodiment of the present invention, the high electron mobility transistor further comprises: a repeatedly grown aluminum gallium nitride film located on the aluminum gallium nitride layer, the gallium nitride source layer and the gallium nitride drain layer, and on the inner surface of the gate recess.

[0013] According to an embodiment of the present invention, the thickness of the regrown aluminum gallium nitride film is less than 2 nm.

[0014] According to an embodiment of the present invention, the high electron mobility transistor further comprises: a protective layer covering the regrown aluminum gallium nitride film and the P-type gallium nitride gate layer.

[0015] According to an embodiment of the present invention, the high electron mobility transistor further includes: a gate contact that penetrates the protective layer and directly contacts the P-type gallium nitride gate layer.

[0016] According to an embodiment of the present invention, the high electron mobility transistor further includes a source contact and a drain contact, which penetrate the protective layer and directly contact the gallium nitride source layer and the gallium nitride drain layer, respectively.

[0017] Another aspect of the present invention provides a method for forming a high electron mobility transistor, comprising: providing a substrate; forming a buffer layer on the substrate; forming a gallium nitride channel layer on the buffer layer; forming an aluminum gallium nitride layer on the gallium nitride channel layer; forming a gallium nitride source layer and a gallium nitride drain layer on the aluminum gallium nitride layer in a source region and a drain region, respectively; forming a gate recess in the aluminum gallium nitride layer between the source region and the drain region; and forming a P-type gallium nitride gate layer in and on the gate recess.

[0018] According to an embodiment of the present invention, the gallium nitride source layer and the gallium nitride drain layer are made of N ++ It is composed of gallium nitride doping.

[0019] According to an embodiment of the present invention, the gallium nitride source layer and the gallium nitride drain layer are composed of indium gallium nitride.

[0020] According to an embodiment of the present invention, the gate recess extends through the aluminum gallium nitride layer.

[0021] According to an embodiment of the present invention, the gate recess does not penetrate the aluminum gallium nitride layer, and the remaining thickness of the aluminum gallium nitride layer at the bottom of the gate recess is less than or equal to 2 nm.

[0022] According to an embodiment of the present invention, the method further includes: forming a regrown aluminum gallium nitride film on the aluminum gallium nitride layer, the gallium nitride source layer and the gallium nitride drain layer, and on the inner surface of the gate recess.

[0023] According to an embodiment of the present invention, the thickness of the regrown aluminum gallium nitride film is less than 2 nm.

[0024] According to an embodiment of the present invention, the method further includes: forming a protective layer covering the regrown aluminum gallium nitride film and the P-type gallium nitride gate layer.

[0025] According to an embodiment of the present invention, the method further includes: forming a gate contact that penetrates the protective layer and directly contacts the P-type gallium nitride gate layer.

[0026] According to an embodiment of the present invention, the method further includes: forming a source contact and a drain contact that penetrate the protective layer and directly contact the gallium nitride source layer and the gallium nitride drain layer, respectively. Attached Figure Description

[0027] Figure 1 This is a cross-sectional schematic diagram illustrating a high electron mobility transistor according to an embodiment of the present invention;

[0028] Figures 2 to 8 This is a schematic diagram illustrating a method for fabricating a high electron mobility transistor according to an embodiment of the present invention.

[0029] Explanation of main component symbols

[0030] 1 High electron mobility transistor

[0031] 100 base

[0032] 102 Buffer Layer

[0033] 104 gallium nitride channel layer

[0034] 106 aluminum gallium nitride layer

[0035] 108-fold regrown aluminum gallium nitride film

[0036] 110 gate recess

[0037] 112 P-type gallium nitride gate layer

[0038] 112G P-type gallium nitride layer

[0039] 120 gallium nitride layer

[0040] 121 Gallium Nitride Source Layer

[0041] 122 Gallium Nitride Drain Layer

[0042] 130 protective layer

[0043] 140 dielectric layers

[0044] 200 insulation structure

[0045] S-source region

[0046] D drain region

[0047] CG gate contact

[0048] CS source contact

[0049] CD drain contact

[0050] 2DEG Two-Dimensional Electronic Cloud Detailed Implementation

[0051] In the following description, details will be illustrated with reference to the accompanying drawings, which also form part of the detailed description of the specification, and which are depicted in a manner that describes specific examples in which the embodiments may be practiced. The embodiments described below are given sufficient detail to enable those skilled in the art to implement them.

[0052] Of course, other embodiments may be adopted, or any structural, logical, and electrical changes may be made without departing from the embodiments described herein. Therefore, the following detailed description should not be regarded as limiting; rather, the embodiments included therein will be defined by the appended claims.

[0053] Please see Figure 1 This is a cross-sectional schematic diagram of a high electron mobility transistor according to an embodiment of the present invention. Figure 1 As shown, the high electron mobility transistor 1 includes a substrate 100, a buffer layer 102 disposed on the substrate 100, a gallium nitride channel layer 104 located on the buffer layer 102, an aluminum gallium nitride layer 106 located on the gallium nitride channel layer 104, a gate recess 110 located in the aluminum gallium nitride layer 106, a source region S and a drain region D located on opposite sides of the gate recess 110, a gallium nitride source layer 121 and a gallium nitride drain layer 122 respectively grown on the aluminum gallium nitride layer 106 in the source region S and the drain region D, and a p-type gallium nitride gate layer 112 located in and on the gate recess 110.

[0054] According to an embodiment of the present invention, the high electron mobility transistor 1 may further include a regrown aluminum gallium nitride film 108 located on the aluminum gallium nitride layer 106, the gallium nitride source layer 121 and the gallium nitride drain layer 122, and on the inner surface of the gate recess 110.

[0055] According to an embodiment of the present invention, the high electron mobility transistor 1 may further include a protective layer 130 covering the regrown aluminum gallium nitride film 108 and the P-type gallium nitride gate layer 112. For example, the protective layer 130 may include silicon nitride or aluminum oxide, but is not limited thereto. In addition, a dielectric layer 140, such as silicon oxide, may be formed on the protective layer 130, but is not limited thereto.

[0056] According to an embodiment of the present invention, the high electron mobility transistor 1 may further include an insulating structure 200, such as a trench insulating structure, surrounding an island-shaped active region composed of a patterned gallium nitride channel layer 104 and a patterned aluminum gallium nitride layer 106.

[0057] According to an embodiment of the present invention, the gallium nitride source layer 121 and the gallium nitride drain layer 122 can be made of N ++ It is composed of gallium nitride doped layer. According to another embodiment of the present invention, the gallium nitride source layer 121 and the gallium nitride drain layer 122 may be composed of indium gallium nitride.

[0058] According to an embodiment of the present invention, the gate recess 110 penetrates the aluminum gallium nitride layer 106, exposing a portion of the gallium nitride channel layer 104. According to another embodiment of the present invention, the gate recess 110 does not penetrate the aluminum gallium nitride layer 106. In this case, the remaining thickness of the aluminum gallium nitride layer 106 at the bottom of the gate recess 110 is less than or equal to 2 nm. Within this thickness range, a two-dimensional electron cloud (2DEG) will not form directly below the aluminum gallium nitride layer 106.

[0059] According to an embodiment of the present invention, the thickness of the regrown aluminum gallium nitride film 108 is less than 2 nm.

[0060] According to an embodiment of the present invention, the high electron mobility transistor 1 further includes a gate contact CG, which penetrates the protective layer 130 and directly contacts the P-type gallium nitride gate layer 112. According to an embodiment of the present invention, the high electron mobility transistor 1 further includes a source contact CS and a drain contact CD, which penetrate the protective layer 130 and directly contact the gallium nitride source layer 121 and the gallium nitride drain layer 122, respectively.

[0061] The structural feature of this invention is that the high electron mobility transistor 1 has N ++The high electron mobility transistor 1 comprises a gallium nitride (GaN) source layer 121 and a gallium nitride (GaN) drain layer 122, both doped with gallium nitride or indium gallium nitride, and a gate recess 110. A p-type gallium nitride gate layer 112 is disposed within and on the gate recess 110. Furthermore, the high electron mobility transistor 1 has a regrown aluminum gallium nitride (AGaN) film 108 located on the AGaN layer 106, the gallium nitride source layer 121 and the gallium nitride drain layer 122, and on the inner surface of the gate recess 110. Combining these features, the high electron mobility transistor 1 of the present invention achieves a high breakdown voltage or high threshold voltage (Vt) and low on-resistance (Ron) HEMT, overcoming the shortcomings and deficiencies of the prior art.

[0062] Please see Figures 2 to 8 This is a schematic diagram illustrating a method for fabricating a high electron mobility transistor according to an embodiment of the present invention. The same symbols are used to represent the same elements, layers, regions or materials in the diagram.

[0063] like Figure 2 As shown, a substrate 100, such as a silicon substrate, is first provided. Then, a buffer layer 102, a gallium nitride channel layer 104, an aluminum gallium nitride layer 106, and a gallium nitride layer 120 are sequentially formed on the surface of the substrate 100 using an epitaxial method. According to one embodiment of the present invention, the gallium nitride layer 120 may be an N… ++ A gallium nitride (GaN) layer is doped. According to one embodiment of the present invention, the GaN layer 120 may be an indium gallium nitride (IGaN) layer. In the GaN channel layer 104, a two-dimensional electron cloud (2DEG) is formed near the aluminum gallium nitride (AGaN) layer 106.

[0064] Next, as Figure 3 As shown, optical lithography and etching processes are performed to pattern the gallium nitride layer 120, forming a gallium nitride source layer 121 and a gallium nitride drain layer 122 on the aluminum gallium nitride layer 106 within the source region S and drain region D, respectively. As previously mentioned, for example, the gallium nitride layer 120 can be an N… ++ By doping a gallium nitride layer, the invention aims to reduce the source and drain resistance. Furthermore, N-type materials are grown in an in-situ manner. ++ In the metal-organic chemical vapor deposition (MOCVD) process of gallium nitride doped layers, the dopant concentration and activation thermal budget can be effectively controlled.

[0065] like Figure 4As shown, another optical lithography and etching process is performed to form a gate recess 110 in the aluminum gallium nitride layer 106 between the source region S and the drain region D. According to an embodiment of the invention, the gate recess 110 penetrates the aluminum gallium nitride layer 106, exposing a portion of the gallium nitride channel layer 104. According to another embodiment of the invention, the gate recess 110 does not penetrate the aluminum gallium nitride layer 106. In this case, the remaining thickness of the aluminum gallium nitride layer 106 at the bottom of the gate recess 110 is less than or equal to 2 nm. Within this thickness range, a two-dimensional electron cloud (2DEG) will not form directly below the aluminum gallium nitride layer 106.

[0066] like Figure 5 As shown, a regrown aluminum gallium nitride (AGaN) film 108 is then formed on the AGaN source layer 106, the AGaN source layer 121, the AGaN drain layer 122, and the inner surface of the gate recess 110. According to an embodiment of the present invention, the thickness of the regrown AGaN film 108 is less than 2 nm. The regrown AGaN film 108 can repair surface damage caused by previous etching steps. Then, a P-type gallium nitride layer 112G is grown on the surface of the regrown AGaN film 108.

[0067] like Figure 6 As shown, another optical lithography and etching process is then performed to pattern the P-type gallium nitride layer 112G into a P-type gallium nitride gate layer 112. The P-type gallium nitride gate layer 112 is formed within and on the gate recess 110.

[0068] like Figure 7 As shown, an insulating structure 200, such as a trench insulating structure, is then formed around the island-shaped active region consisting of a patterned gallium nitride channel layer 104 and a patterned aluminum gallium nitride layer 106. A protective layer 130 is then formed, covering the regrown aluminum gallium nitride film 108 and the p-type gallium nitride gate layer 112. For example, the protective layer 130 may comprise silicon nitride or aluminum oxide, but is not limited thereto.

[0069] Subsequently, as Figure 8 As shown, a dielectric layer 140, such as silicon oxide, is formed on the protective layer 130, but is not limited thereto. Then, a gate contact CG is formed, penetrating the protective layer 130 and directly contacting the P-type gallium nitride gate layer 112. A source contact CS and a drain contact CD are formed, penetrating the protective layer 130 and directly contacting the gallium nitride source layer 121 and the gallium nitride drain layer 122, respectively.

[0070] The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made in accordance with the claims of the present invention should be included within the scope of the present invention.

Claims

1. A high electron mobility transistor, characterized in that, Include: Base; A gallium nitride channel layer is located on the substrate; An aluminum gallium nitride layer is located on the gallium nitride channel layer; The gate recess is located within the aluminum gallium nitride layer; The source region and the drain region are located on opposite sides of the gate recess; A gallium nitride source layer and a gallium nitride drain layer are grown on the aluminum gallium nitride layer in the source region and the drain region, respectively. A p-type gallium nitride gate layer is located within and on the gate recess; as well as A regrown aluminum gallium nitride (AGaN) film is located on the AGaN layer, the GaN source layer and the GaN drain layer, and on the inner surface of the gate recess, wherein the regrown AGaN film directly contacts the upper surface and sidewalls of the GaN source layer and the GaN drain layer.

2. The high electron mobility transistor of claim 1, wherein the gallium nitride source layer and the gallium nitride drain layer are made of N... ++ It is composed of gallium nitride doping.

3. The high electron mobility transistor of claim 1, wherein the gallium nitride source layer and the gallium nitride drain layer are made of indium gallium nitride.

4. The high electron mobility transistor of claim 1, wherein the gate recess extends through the aluminum gallium nitride layer.

5. The high electron mobility transistor of claim 1, wherein the gate recess does not penetrate the aluminum gallium nitride layer, and wherein the thickness of the aluminum gallium nitride layer at the bottom of the gate recess is less than or equal to 2 nm.

6. The high electron mobility transistor of claim 1, further comprising: A buffer layer is located on the substrate, wherein the gallium nitride channel layer is located on the buffer layer.

7. The high electron mobility transistor of claim 1, wherein the thickness of the regrown aluminum gallium nitride film is less than 2 nm.

8. The high electron mobility transistor of claim 7, further comprising: A protective layer covers the regrown aluminum gallium nitride film and the P-type gallium nitride gate layer.

9. The high electron mobility transistor of claim 8, wherein the protective layer comprises silicon nitride or silicon oxide.

10. The high electron mobility transistor of claim 8, further comprising: The gate contact penetrates the protective layer and directly contacts the P-type gallium nitride gate layer.

11. The high electron mobility transistor of claim 8, further comprising: The source and drain contacts penetrate the protective layer and directly contact the gallium nitride source layer and the gallium nitride drain layer, respectively.

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