Fault diagnosis and fault-tolerant operation control system for three-phase interleaved three-level converter

Abstract

This invention relates to a fault diagnosis and fault-tolerant operation control system for a three-phase interleaved parallel three-level converter, which acquires the corresponding inductor current I at the peak moment of the triangular carrier signal of the half-bridge of the six switching transistors of the converter. Li If the converter's I Li If all values ​​are greater than 0, the converter is determined to be fault-free or operating in a fault transient state. The location of the open-circuit fault is determined by the current slope between output current sampling points and the falling edge of the main control switch drive signal. If any I of the converter... Li If I is less than 0, the converter is determined to have entered a fault steady state, and I Li When the value is less than 0, the main control switch of the half-bridge is open-circuited. After fault location, the drive signals of the four switches in the corresponding phase of the faulty half-bridge are blocked, and the phase shift angle of the remaining two phase carrier signals is reconfigured to 180°, degenerating into two-phase interleaved parallel operation. This invention can quickly locate open-circuit faults in the converter and perform fault-tolerant operation to eliminate the impact of the fault.

Description

Technical Field

[0001] This invention belongs to the field of power electronic converter fault diagnosis and fault tolerance technology, and in particular relates to a fault diagnosis and fault-tolerant operation control system for a three-phase interleaved parallel three-level converter. Background Technology

[0002] In DC microgrids, energy exchange between renewable energy generation and energy storage systems is accomplished by bidirectional DC-DC converters. In this high-voltage, high-power application scenario, multiphase interleaved parallel and multilevel technologies are applied to the converter to improve power transmission performance. Three-phase interleaved parallel three-level DC-DC converters combine interleaved parallel and multilevel technologies to achieve high-power power transmission, ensuring energy flow between renewable energy generation and energy storage systems and improving the absorption capacity of renewable energy generation systems.

[0003] Because DC-DC converters in energy storage microgrids withstand large bus voltages and switch frequently between different operating states, higher demands are placed on the switching performance of power devices. This also makes power switching transistors more prone to failure under high-frequency operation. Existing surveys indicate that approximately 46% of converter failures are caused by switching devices, which include both short-circuit and open-circuit faults. In typical single-inductor DC-DC converters, short-circuit faults commonly manifest as a rise in inductor current, causing a large inrush current within a short period and leading to failures in other circuit components. Therefore, short-circuit fault diagnosis is usually integrated within the power switching device module. Overcurrent detection is used to blow the switching transistor under high current conditions, disconnecting the branch containing the power switching device and causing the short-circuit fault to develop into an open-circuit fault.

[0004] There are three main methods for diagnosing open-circuit faults in power switching devices of DC-DC converters: (1) diagnostic methods based on the converter's mathematical model; (2) diagnostic methods based on the converter's voltage and current state parameters; and (3) data processing methods based on data-driven approaches. Among these, the voltage and current state parameter diagnostic methods based on the converter have the advantages of high efficiency and low cost, making them more suitable for practical engineering applications. However, in this type of method, the characteristic quantities that can characterize the fault need to be selected individually according to the converter's topology. In a three-phase interleaved parallel three-level DC-DC converter, an open-circuit fault in a single switching device will not cause the converter to stop operating, but it will cause an increase in output voltage ripple and uneven current between phases. Therefore, open-circuit faults in the switching transistors of a three-phase interleaved parallel three-level DC-DC converter have a certain degree of concealment. If the open-circuit fault of the switching transistor cannot be detected in time, the change in operating state caused by the open-circuit fault will affect the output power quality, which is unacceptable in application scenarios where output voltage ripple requirements are high. Furthermore, given the requirement for continuous power transmission in energy storage systems, researching fault-tolerant operation methods for DC-DC converters under device failures is of great significance. Existing fault-tolerant operation methods for DC-DC converters focus on fault isolation and redundant reconfiguration. However, three-phase interleaved parallel three-level DC-DC converters, due to their interleaved parallel structure, possess the inherent advantage of rapid fault isolation and the ability to achieve degraded operation without additional hardware. No research has been found in the existing literature specifically addressing open-circuit fault detection and fault-tolerant operation methods for three-phase interleaved parallel three-level DC-DC converters. Summary of the Invention

[0005] To address the aforementioned problems, this invention proposes a fault diagnosis and fault-tolerant operation control system for a three-phase interleaved parallel three-level converter. The system locates the faulty switching transistor by sampling inductor current and output current, and provides a fault-tolerant operation scheme after fault diagnosis, ensuring the converter maintains steady-state operation capability even after an open-circuit fault. The method of this invention has advantages such as fast detection speed, accurate location, and simple diagnostic process.

[0006] On one hand, this invention proposes a fault diagnosis and fault-tolerant operation method for a three-phase interleaved parallel three-level converter, wherein the converter includes a six-switch half-bridge, comprising the following steps:

[0007] Step 1: At the peak time of the triangular carrier signal of the half-bridge of the six switching transistors of the converter, collect the corresponding inductor current I. Li i = 1 to 6, the current state of the circuit is determined based on the sign of the inductor current; if the I of the converter Li If all values ​​are greater than 0, the converter is determined to be fault-free or operating in a fault transient state; if any I of the converter is greater than 0, the converter is determined to be fault-free or operating in a fault transient state. Li If the value is less than 0, the converter is determined to have entered a fault steady state;

[0008] Step 2, in the sampled inductor current I Li When all values ​​are greater than 0, the location of the open circuit fault is determined by the current slope between the output current sampling points and the falling edge of the main control switch drive signal; at any sampled inductor current I... Li If it is less than 0, then I is determined. Li The main control switch transistor of the half-bridge corresponding to a value less than 0 has an open circuit fault;

[0009] Step 3: After completing the fault location, lock out the drive signals of the four switching transistors corresponding to the faulty half-bridge, and reconfigure the phase shift angle of the remaining two phase carrier signals to 180°, degrading to two-phase interleaved parallel operation.

[0010] Furthermore, in step 2:

[0011] in I Li When the value is greater than 0, a sampling PWM signal is constructed, and the output current i is adjusted at the rising and falling edges of the sampling PWM signal. all Samples are saved; at the rising edge of the sampled PWM signal, the output current slopes l1 and l2 between two adjacent sampling intervals are calculated. If l1 ≠ l2, it means that no open circuit fault of the main control switch is detected; if l1 = l2, it means that an open circuit fault of the main control switch has occurred, and the fault location is the switch corresponding to the high-low level transition of the switch drive signal between the two rising edge sampling times.

[0012] Furthermore, the sampled PWM signal is:

[0013] S sample =S A1 +S A4 +S B1 +S B4 +S C1 +S C4 -floor(6*D)

[0014] Among them, S A1 S A4 S B1 S B4 S C1 S C4 These are the drive signals for the main control switches of the upper and lower bridge arms of phases A, B, and C, respectively. A high level corresponds to 1, and a low level corresponds to 0. D is the output duty cycle, and the floor function is the smallest integer less than or equal to the specified expression.

[0015] Furthermore, the output current slopes l1 and l2 are expressed as:

[0016]

[0017]

[0018] Where i all_R (k) represents the sampled value of the output current at the rising edge, i all_R (k-1) represents the sampled value of the output current at the previous rising edge, i all_F (k) represents the output current sample value at the falling edge between two rising edges, Δt1 represents the duration from the previous rising edge to the falling edge, and Δt2 represents the duration from the falling edge to the current rising edge.

[0019] Furthermore, step 3 specifically involves:

[0020] If an open-circuit fault is detected in the main control switch of the upper or lower half of phase A, the drive signal S of the main control switch of the upper or lower half of phase A will be... A1 S A4 When the complementary control signal is set to 0, the carrier signals of the upper and lower half-bridge arms of phase B are phase-shifted by 120° based on the original signals, and the carrier signals of the upper and lower half-bridge arms of phase C are phase-shifted by 60° based on the original signals.

[0021] If an open-circuit fault is detected in the main control switch of the upper or lower half of phase B, the drive signal S of the main control switch of the upper or lower half of phase B will be... B1 S B4 When the complementary control signal is set to 0, the carrier signals of the upper and lower half-bridge arms of phase A remain unchanged, and the carrier signals of the upper and lower half-bridge arms of phase C are shifted by 60° based on the original signals.

[0022] If an open-circuit fault is detected in the main control switch of the upper or lower half of phase C, the drive signal S of the main control switch of the upper or lower half of phase C will be switched off. C1 S C4 When the complementary control signal is set to 0, the carrier signals of the upper and lower half-bridge arms of phase A remain unchanged, while the carrier signals of the upper and lower half-bridge arms of phase B are phase-shifted by 300° based on the original signals.

[0023] Furthermore, in step 3, to ensure that the output ripple still meets the requirements when degenerating into two-phase interleaved parallel operation, the inductors L1 to L6 of each phase and the output capacitor C... o The selection of parameters follows these principles:

[0024] L i =6L i_normal (i = 1 to 6)

[0025] C o =3C o_normal

[0026] Among them, L i_normal and C o_normalThese represent the inductor and capacitor parameters designed to meet the requirements for inductor current ripple and output voltage ripple during three-phase interleaved parallel operation, respectively.

[0027]

[0028]

[0029] Among them, V in f is the input voltage of the three-phase interleaved parallel three-level DC-DC converter. s Δi is the switching frequency. all_max For the maximum output current ripple, ΔV o_max This represents the maximum output voltage ripple.

[0030] On the other hand, this invention proposes a fault diagnosis and fault-tolerant operation control system for a three-phase interleaved parallel three-level converter, wherein the converter includes a six-switch half-bridge, comprising:

[0031] Inductor current acquisition module: used to acquire the corresponding inductor current I at the peak time of the triangular carrier signal of the half-bridge of the six switching transistors of the converter. Li , i = 1 to 6;

[0032] Circuit current state determination module: Determines the current state of the circuit based on the sign of the inductor current; if the converter's I... Li If all values ​​are greater than 0, the converter is determined to be fault-free or operating in a fault transient state; if any I of the converter is greater than 0, the converter is determined to be fault-free or operating in a fault transient state. Li If the value is less than 0, the converter is determined to have entered a fault steady state;

[0033] Fault location module: in the sampled inductor current I Li When all values ​​are greater than 0, the location of the open circuit fault is determined by the current slope between the output current sampling points and the falling edge of the main control switch drive signal; at any sampled inductor current I... Li If it is less than 0, then I is determined. Li The main control switch transistor of the half-bridge corresponding to a value less than 0 has an open circuit fault;

[0034] Fault-tolerant operation control module: After completing fault location, it blocks the drive signals of the four switching transistors of the corresponding phase of the faulty half-bridge, and reconfigures the phase shift angle of the remaining two phase carrier signals to 180°, degrading to two-phase interleaved parallel operation.

[0035] Furthermore, in the fault location module:

[0036] in I Li When the value is greater than 0, a sampling PWM signal is constructed, and the output current i is adjusted at the rising and falling edges of the sampling PWM signal. allSamples are saved; at the rising edge of the sampled PWM signal, the output current slopes l1 and l2 between two adjacent sampling intervals are calculated. If l1 ≠ l2, it means that no open circuit fault of the main control switch is detected; if l1 = l2, it means that an open circuit fault of the main control switch has occurred, and the fault location is the switch corresponding to the high-low level transition of the switch drive signal between the two rising edge sampling times.

[0037] Furthermore, in the fault-tolerant operation control module:

[0038] If an open-circuit fault is detected in the main control switch of the upper or lower half of phase A, the drive signal S of the main control switch of the upper or lower half of phase A will be... A1 S A4 When the complementary control signal is set to 0, the carrier signals of the upper and lower half-bridge arms of phase B are phase-shifted by 120° based on the original signals, and the carrier signals of the upper and lower half-bridge arms of phase C are phase-shifted by 60° based on the original signals.

[0039] If an open-circuit fault is detected in the main control switch of the upper or lower half of phase B, the drive signal S of the main control switch of the upper or lower half of phase B will be... B1 S B4 When the complementary control signal is set to 0, the carrier signals of the upper and lower half-bridge arms of phase A remain unchanged, and the carrier signals of the upper and lower half-bridge arms of phase C are shifted by 60° based on the original signals.

[0040] If an open-circuit fault is detected in the main control switch of the upper or lower half of phase C, the drive signal S of the main control switch of the upper or lower half of phase C will be switched off. C1 S C4 When the complementary control signal is set to 0, the carrier signals of the upper and lower half-bridge arms of phase A remain unchanged, while the carrier signals of the upper and lower half-bridge arms of phase B are phase-shifted by 300° based on the original signals.

[0041] Furthermore, the sampled PWM signal is:

[0042] S sample =S A1 +S A4 +S B1 +S B4 +S C1 +S C4 -floor(6*D)

[0043] Among them, S A1 S A4 S B1 S B4 S C1 S C4These are the drive signals for the main control switches of the upper and lower bridge arms of phases A, B, and C, respectively. A high level is 1, and a low level is 0. D is the output duty cycle, and the floor function is the smallest integer less than or equal to the specified expression.

[0044] The output current slopes l1 and l2 are expressed as follows:

[0045]

[0046]

[0047] Where i all_R (k) represents the sampled value of the output current at the rising edge, i all_R (k-1) represents the sampled value of the output current at the previous rising edge, i all_F (k) represents the output current sample value at the falling edge between two rising edges, Δt1 represents the duration from the previous rising edge to the falling edge, and Δt2 represents the duration from the falling edge to the current rising edge.

[0048] The beneficial technical effects of the present invention are as follows: (1) By detecting whether the average current of the inductor current corresponding to each main control switch is less than 0 when the switch is turned off, it is possible to directly determine whether the converter has entered the fault steady state; (2) By combining the fault steady state diagnosis method and the fault transient state diagnosis method, the accuracy and speed of the open circuit fault location of the main control switch are improved; (3) By blocking all the drive signals of one phase of the open circuit fault switch and reconfiguring the phase shift angle, the fault-tolerant operation scheme of the three-phase interleaved parallel three-level DC-DC converter degenerates into two-phase interleaved parallel after the fault is realized.

[0049] Figure and Table Description

[0050] Figure 1 This is a three-phase interleaved parallel three-level DC-DC converter topology in a specific embodiment of the present invention;

[0051] Figure 2 This is a flowchart of the open-circuit fault diagnosis and fault-tolerant operation method for a three-phase interleaved parallel three-level DC-DC converter according to the present invention;

[0052] Figure 3 This is the equivalent circuit of the three-phase interleaved parallel three-level DC-DC converter in a specific embodiment of the present invention;

[0053] Figure 4 This is the equivalent circuit of the upper part of the three-phase full-bridge of the three-phase interleaved parallel three-level DC-DC converter in a specific embodiment of the present invention;

[0054] Figure 5It is the common-mode equivalent circuit and differential-mode equivalent circuit of the three-phase interleaved three-level DC-DC converter in the specific embodiment of the present invention;

[0055] Figure 6 It is the key waveform during the steady-state operation without faults within the full duty cycle range in the specific embodiment of the present invention;

[0056] Figure 7 It is the key waveform during the fault transient state when the duty cycle 4 / 6 < D < 5 / 6 in the specific embodiment of the present invention;

[0057] Figure 8 It is the fault half-bridge inductor current loop during one cycle of the fault transient state in the specific embodiment of the present invention;

[0058] Figure 9 It is the fault half-bridge inductor current loop during one cycle of the fault steady state in the specific embodiment of the present invention;

[0059] Figure 10 It is the output current waveform during the operation of the fault transient state within the full duty cycle range in the specific embodiment of the present invention;

[0060] Figure 11 It is the sampled PWM signal in the specific embodiment of the present invention. Specific embodiment

[0061] The present invention will be described in detail below with reference to the attached drawings.

[0062] The following discloses a detailed reasoning and analysis method and a demonstration analysis example. However, the specific reasoning and analysis process details disclosed herein are only for the purpose of describing the demonstration analysis example.

[0063] However, it should be understood that the present invention is not limited to the disclosed specific demonstration embodiments, but covers all modifications, equivalents, and substitutions falling within the scope of this disclosure. In the description of all the drawings, the same reference numerals represent the same elements.

[0064] Aiming at the problem that after an open-circuit fault occurs in the power switch tube of the three-phase interleaved three-level DC-DC converter, it can still operate in the fault steady state and it is difficult to locate the faulty switch tube, the present invention proposes a method for open-circuit fault diagnosis and fault-tolerant operation of the three-phase interleaved three-level DC-DC converter based on the combination of inductor current sampling signals and output current slope.

[0065] The topological structure of the three-phase interleaved three-level converter in the embodiment of the present invention is as Figure 1 shown, mainly including the switching devices S wA1 、S wA2 、S wA3 、S wA4 、S wB1S wB2 S wB3 S wB4 S wC1 S wC2 S wC3 S wC4 and its anti-parallel diode D A1 D A2 D A3 D A4 D B1 D B2 D B3 D B4 D C1 D C2 D C3 D C4 High-voltage side voltage divider capacitor C b1 C b2 Low-voltage side voltage regulator capacitor C o The inductors L1 to L6 correspond to the six switching transistors in the half-bridge. The three-phase interleaved parallel three-level DC-DC converter includes two operating modes: Buck and Boost. The implementation of this invention takes the Buck mode as an example. It should be noted that the converter in this invention operates in high-voltage, high-power applications, and operates in a continuous current state by reasonably selecting the inductor parameters.

[0066] This invention samples I at the carrier peak time. Li To determine whether the circuit has entered a fault steady-state operation, a method is proposed to locate the open-circuit faulty switching transistor by using the output current slope during fault transients. This method combines the speed of fault transient diagnosis with the accuracy of fault steady-state diagnosis. First, the corresponding inductor current I is collected at the peak times of the triangular carrier signals of the six half-bridges of the converter. Li (i=1~6). If I Li If all values ​​are greater than 0, it indicates that the converter is in a fault-free or fault transient state. In this case, by comparing the output current slopes l1 and l2 calculated between two adjacent sampling intervals at the rising edge of the sampled PWM signal, it is determined whether an open-circuit fault has occurred. The fault location is then determined by the falling edge of the drive signal of each main control switch. If I exists... Li If the value is less than 0, it indicates that the converter has entered a fault steady state, and I Li The half-bridge main control switch corresponding to a value less than 0 is the open-circuit fault switch. After locating the open-circuit fault, the drive signals of all switches in the faulty phase are blocked, and the carrier phase shift angles of the remaining two phases are reconfigured, causing the converter to degenerate into two-phase interleaved parallel operation.

[0067] The method flow of this invention is as follows: Figure 2 As shown, it includes the following steps:

[0068] Step 1: At the peak of the triangular carrier signal of the six half-bridges of the three-phase interleaved parallel three-level DC-DC converter, acquire the corresponding inductor current I. Li (i = 1 to 6), determine the current state of the circuit based on the sign of the inductor current;

[0069] The circuit's operating state can be determined by sampling the corresponding inductor current I at the peak of the triangular carrier signal in the half-bridge. Li The positive and negative values ​​are determined based on the inductor current characteristics of the circuit before and after the fault, and three circuit operating states are defined: fault-free steady-state operation, transient operation with open circuit fault of main control switch, and steady-state operation with open circuit fault of main control switch.

[0070] 1) Fault-free steady-state operation:

[0071] A three-phase interleaved parallel three-level DC-DC converter contains two half-bridges and their corresponding inductors in each phase. To simplify the analysis, a controlled voltage source V is used. A1 V A4 V B1 V B4 V C1 V C4 This represents a half-bridge with switching transistors, and its equivalent circuit is as follows: Figure 3 As shown. According to the circuit operating principle, the controlled voltage is V when the corresponding main control switch is turned on. in / 2, V is 0 when the switching transistor is off. in The input voltage is V. To facilitate the analysis of the single inductor current waveform, a virtual voltage source is introduced to replace half of the three-phase full bridge. Here, the virtual voltage source V is used. GO Taking the lower half of the three-phase full-bridge as an example, let's analyze the current waveform of inductor L1. The equivalent circuit is as follows: Figure 4 As shown. Based on the principle that the current flowing into the output capacitor is equal to the current flowing out, V can be obtained. GO The expression:

[0072]

[0073] Therefore, the voltage U across inductor L1 L1 For V A1 -V GO -U o / 2, where U o For the output voltage, a three-phase interleaved parallel three-level DC-DC converter operating in steady state has U. o =DV in To simplify the total output current i all Solving for V A1 V B1 V C1 Decomposed into common-mode voltage source V cm Sum and difference mode voltage source V dmCombination form, equivalent circuit as Figure 5 As shown, the common-mode voltage V cm =(V A1 +V B1 +V C1 ) / 3, and the output current i all Related to differential mode voltage V dm It only relates to the circulating current between inductors and does not affect the output current. According to Figure 5 The common-mode voltage across a single inductor is V. cm -V GO -U o / 2, Total output current i all For the common-mode component i of a single inductor current Lcm Three times that, i all =3i Lcm .

[0074] Based on the operating characteristics of the three-phase interleaved parallel three-level converter, the converter switching transistor S... wA1 S wA4 S wB1 S wB4 S wC1 S wC4 The duty cycle D is divided into 0–1 / 6, 1 / 6–2 / 6, 2 / 6–3 / 6, 3 / 6–4 / 6, 4 / 6–5 / 6, and 5 / 6–1 for separate analysis within the range of 0–1. The key waveforms under each duty cycle range are as follows: Figure 6 As shown. According to Figure 6 The inductor current i of L1 can be calculated. L1 and output current i all The expression for one switching cycle is as follows, where I0 and I all These represent the inductor current i at the beginning of a cycle. L1 and output current i all The initial value.

[0075] a)0 <D<1 / 6

[0076]

[0077]

[0078] b) 1 / 6 <D<2 / 6

[0079]

[0080]

[0081] c)2 / 6 <D<3 / 6

[0082]

[0083]

[0084] d)3 / 6 <D<4 / 6

[0085]

[0086]

[0087] e)4 / 6 <D<5 / 6

[0088]

[0089]

[0090] f)5 / 6 <D<1

[0091]

[0092]

[0093] Based on the inductor current output current waveforms within different duty cycle ranges, the following characteristics can be summarized: During one switching cycle, the inductor current i... L1 It exhibits characteristics of single-harmonic oscillation; due to V GO The existence of i in a single switching cycle L1 The waveform is divided into 12 segments, with the peak current rise corresponding to the switching transistor S. WA1 Switching from the on state to the off state. During one switching cycle, the output current i all It exhibits characteristics of 6th harmonic frequency oscillation; within a single switching cycle, i all Although the waveform is also divided into 12 segments, it can be described in more detail as a 2-segment fluctuation within 1 / 6 of the cycle.

[0094] Based on the principle of triangular carrier wave generation of duty cycle, the peak moment of phase A carrier wave corresponds to the switching transistor S. WA1 The midpoint between the falling edge of the drive signal and the next rising edge, i.e., the inductor current i L1 The current drops from its peak value to the midpoint of the initial current I0. Therefore, it can be approximately considered that at the peak value of phase A carrier wave i... L1 The sampled value is the inductor current i L1 mean I L1 This invention targets a high-power three-phase interleaved parallel three-level DC-DC converter, which operates in a state where the inductor current is continuously on, therefore having I L1 >I0>0. Based on the principle of interleaving in a three-phase interleaved parallel three-level converter, the inductor current i0 of phases B and C at the peak of the carrier wave... L2 i L3The sampled values ​​are all the average current I. L2 I L3 And all values ​​are greater than 0 under steady-state operation.

[0095] 2) Transient operation due to open circuit fault of main control switch:

[0096] Define the corresponding inductor current i after an open-circuit fault occurs in the main control switch of a three-phase interleaved parallel three-level DC-DC converter. Li The period during which the value begins to decrease but does not fall into negative territory is the transient operating state of the converter during an open-circuit fault.

[0097] The following is a detailed analysis of the rationality of the above definition of the transient operating state of the main control switch transistor in the case of an open circuit fault:

[0098] Combination Figure 6 V during fault-free steady-state operation within different duty cycles GO The waveform can be used to obtain the virtual voltage source V. GO In a switching cycle T s The periodic average value:

[0099]

[0100] In the above formula, Let V be the periodic average value of the variable, and t0 be the start time of one period. Under normal steady-state operation, V... GO Under the full range of duty cycles, there is one and only V. in / 12 and -V in / 12 Two voltage levels, T1 and T2 represent V respectively. in / 12 and -V in / 12 is the duration within a cycle. Figure 6 It can be seen that T1 = T2, therefore Furthermore, it is obvious that the controlled voltage source V can be obtained. A1 V A4 V B1 V B4 V C1 V C4 The periodic averages are as follows:

[0101]

[0102] Therefore, the upper part of the three-phase full-bridge inductor current i L1 i L2 i L3 and the lower half of the three-phase full-bridge inductor current i L4 i L5 i L6 The current increment Δi within a switching cycle L1 ~Δi L6They are respectively:

[0103]

[0104] Δi L2 = Δi L3 = 0

[0105]

[0106] Δi L5 = Δi L6 = 0

[0107] According to the above formula, the increment of all inductor currents within one switching period is 0, which conforms to the inductor volt-second balance principle during steady-state operation. If an open-circuit fault occurs in one of the main control switch tubes in the upper half three-phase full-bridge, the original circuit balance will be broken, and the current increment of each inductor current within one period will no longer be 0. Taking the duty cycle 2 / 3 < D < 5 / 6 and the open-circuit fault of the main control switch tube S WA1 as an example, the characteristics under transient faults are analyzed, and the key waveforms are as Figure 7 shown.

[0108] According to Figure 7 , after the open-circuit fault of S WA1 , the controlled voltage source V A1 is equivalent to remaining 0 within one switching period, and the waveforms of the other controlled voltage sources remain unchanged. Therefore, its period average value is as follows:

[0109]

[0110] The virtual voltage source V GO_fault under the fault state within one switching period T s has a period average value of:

[0111]

[0112] According to the above formula, the increments of inductor currents Δi L1_fault , Δi L2_fault , Δi L3_fault , Δi L4_fault , Δi L5_fault , Δi L6_fault in one period for the upper and lower half three-phase full-bridges under fault transients can be obtained:

[0113]

[0114]

[0115]

[0116] According to the increment of inductor current ΔiLi_fault From the expression (i = 1~6), it can be seen that after the open-circuit fault of the main control switch transistor in the upper half of phase A, the corresponding inductor current begins to decrease, while the inductor currents of the other two phases in the upper half of the three-phase full bridge increase by the same increment; while the inductor current increments of all three phases in the lower half of the three-phase full bridge decrease by the same increment, but due to Δi L1_fault =5Δi L4_fault Therefore, the rate at which the inductor current in the lower half decreases is much smaller than that of the inductor current in phase A of the upper half of the bridge arm. Consequently, it can be concluded that when the inductor current in phase A of the faulty half-bridge decreases to 0, the inductor currents of the other inductors are all greater than 0.

[0117] The above characteristics are not limited to a specific range of duty cycles; they are extended to any range of output duty cycle D from 0 to 1. The characteristics of the inductor current during fault transients are summarized as follows: After a fault occurs in the main control switch of a half-bridge, the corresponding inductor current i... Li The current decreases rapidly, while the inductor currents of the other two phases in the same three-phase full bridge increase. Meanwhile, the inductor currents of all the inductors in the other half of the three-phase full bridge corresponding to the faulty half-bridge decrease, but the rate of decrease is less than that of the faulty inductor current i. Li , in i Li When the current is reduced to 0, it can be guaranteed that the current of the remaining inductors is greater than 0.

[0118] Figure 8 S is given from the perspective of equivalent circuit. WA1 The circuit operating state under fault transient conditions. WA1 An open circuit fault has occurred, which is equivalent to the absence of switch S in one switching cycle. WA1 Conduction – L1 is charged by the power supply, and the inductor current i L1 During the rising phase, the inductor current i within one switching cycle after the fault L1 All are connected through anti-parallel diode D A2 Discharge occurs, and the inductor current i L1 The energy level continues to decrease. Because inductor L1 stored energy during charging and discharging before the fault, in S... WA1 For a period of time after the fault, inductor L1 remains in a discharging state until i L1 When the value is reduced to 0, the stored energy in inductor L1 is completely released, and the fault transient phase ends.

[0119] Based on the fault transient operating characteristics of the three-phase interleaved parallel three-level DC-DC converter, the corresponding inductor current i is sampled at the carrier peak of each of the six half-bridges. Li It is still possible to guarantee all i Li Greater than 0.

[0120] 3) Steady-state operation under open-circuit fault of main control switch:

[0121] Still using S WA1Taking an open-circuit fault as an example, we analyze the circuit state during steady-state operation when the main control switch is open-circuit faulted. After the transient operation phase of the main control switch open-circuit fault, the circuit inductor current state is as follows:

[0122]

[0123] In the next cycle of operation after the fault transient (in S) WA1 The rising edge of the drive signal is the start time, in S WA1 When the drive signal is high, S WA1 With the circuit open, the energy stored in inductor L1 is fully released, and the current i L1 Keep it at 0; in S WA1 When the drive signal is low, the other switch S of the faulty half-bridge... WA2 When the drive signal is high, the voltage across inductor L1 is 0. WA2 Bearing the load U o / 2 and virtual voltage source V GO The resulting positive voltage satisfies the turn-on condition. Therefore, S WA1 When the drive signal is low, inductor L1 is connected to the load and the virtual voltage source inductor V. GO A circuit is formed, and inductor L1 is reverse-charged, i L1 The voltage decreases from 0 towards the negative peak. During this phase, the voltage across inductor L1 is -V. GO -U o / 2, and S during fault-free steady-state operation WA1 When the circuit is turned off, the voltage across the terminals is the same, so i L1 Under fault steady state, i L1 In S WA1 The waveform change trend when the drive signal is low is consistent with that in the normal state, the difference being that i is in the fault steady state. L1 It starts decreasing from 0, and under normal conditions, it starts decreasing from the peak value of the inductor current.

[0124] When S WA1 After the drive signal changes from low to high, S WA2 When closed, inductor current i L1 The direction cannot change abruptly, through S WA1 The anti-parallel diode flows to the input capacitor C b1 The voltage across inductor L1 during this stage is V. in / 2-V GO -U o / 2, and S during fault-free steady-state operation WA1 When the circuit is turned on, the voltages at both ends are the same, so i L1 Under fault steady state, i L1 In S WA1The waveform change trend when the drive signal is high is consistent with that in the normal state, the difference being that i is in the fault steady state. L1 It increases from the negative peak value, and under normal conditions, it starts from the initial value I of the inductor current. all Start increasing. The circuit state under fault steady-state conditions is as follows: Figure 9 As shown.

[0125] Based on the above analysis, the voltage across inductor L1 under fault steady-state is the same as under fault-free steady-state, therefore i L1 The waveform shape is the same as that under fault-free conditions, the difference being that i under fault steady state... L1 The voltage decreases from 0 to a negative peak, then gradually increases back to 0. Since the voltage across L1 is the same as in the fault-free state, the voltages of the other inductors in the fault state must also be the same as in the fault-free state. Therefore, i Li The waveform is also consistent with the fault-free state, the difference being the initial current I of the cycle. all The situation has changed, according to the fault transient analysis i L1 When the current of the remaining inductor drops to 0, the remaining inductor current i Li (i = 2 ~ 6) are all greater than 0, which can guarantee i under fault steady state. Li (i = 2 to 6) are all greater than 0.

[0126] Therefore, the peak moment of phase A carrier corresponds to the inductor current i. L1 The midpoint between the drop from 0 to the negative peak can be approximated as the peak moment i of phase A carrier under fault steady state. L1 The sampled value is the inductor current i L1 reverse mean I L1_N <0. And the peak time i of the remaining half-bridge carrier signals Li The sampled values ​​(i = 2 to 6) are still the average current I. Li (i=2~6), and there is I Li Greater than 0.

[0127] In summary, under the fault steady-state condition, the corresponding inductor current i is adjusted at the peak times of each half-bridge carrier signal. Li (i = 1 ~ 6) Sampling, only the half-bridge inductor current i during steady-state operation with an open-circuit fault in the main control switch. Li The sampled value is negative, and the rest of the sampled values ​​are positive.

[0128] It should be noted that from the end of the fault transient state to the complete entry into the fault steady state, there will be a period of time during which the fault inductor current waveform is distorted. This is due to the process of the output voltage decreasing and recovering after the fault, and this process still satisfies i. Li The carrier peak sampling is negative, therefore this stage is also classified as the fault steady-state stage.

[0129] Based on the analysis of the three states described above—fault-free steady-state operation, transient operation with open-circuit fault of main control transistor, and steady-state operation with open-circuit fault of main control transistor—the inductor current I is sampled at the peak time of the half-bridge carrier. Li (i = 1~6) is greater than 0 in both fault-free steady-state operation and transient operation under open-circuit fault of the main control switch. In steady-state operation under open-circuit fault of the main control switch, the faulty half-bridge corresponds to I. Li Less than 0, other sampled values ​​I Li Greater than 0.

[0130] Step 2: For the sampled inductor current I Li When all values ​​are greater than 0, the location of the open circuit fault is determined by the current slope between the output current sampling points and the falling edge of the main control switch drive signal; for any sampled inductor current I... Li If the value is less than 0, determine I. Li The main control switch of the half-bridge corresponding to a value less than 0 has an open circuit fault.

[0131] 1) For the sampled inductor current I Li All are greater than 0

[0132] in I Li If all values ​​are greater than 0, it indicates that the three-phase interleaved parallel three-level DC-DC converter is operating in a fault-free steady-state or in a fault transient state. Therefore, an open-circuit fault diagnosis method is designed based on this. Li A value greater than 0 can be used to distinguish whether an open-circuit fault has occurred in the circuit, which can prevent the circuit from developing into a fault steady state and improve the speed of fault diagnosis.

[0133] The characteristic quantity used to distinguish between fault-free steady-state operation and fault transient operation is the output current i. all , Figure 6 The output current i under fault-free steady-state operation is given. all The waveform, with S WA1 Taking an open-circuit fault as an example, the output current i under various duty cycles during the fault transient is... all_fault Other key waveforms such as Figure 10 As shown. According to Figure 10 The output current i can be calculated. all_fault The expression for I within one switching cycle is as follows, where I all_fault The output current i at the beginning of a cycle all_fault The initial value.

[0134] a)0 <D<1 / 6

[0135]

[0136] b) 1 / 6 <D<2 / 6

[0137]

[0138] c)2 / 6 <D<3 / 6

[0139]

[0140] d)3 / 6 <D<4 / 6

[0141]

[0142] e)4 / 6 <D<5 / 6

[0143]

[0144] f)5 / 6 <D<1

[0145]

[0146] contrast Figure 6 and Figure 10 From the waveform of the output current, it can be seen that in one switching cycle under fault-free conditions, the output current i all The waveform is divided into 12 segments, or more specifically, it can be described as oscillations divided into 2 segments within 1 / 6 of the cycle; during one cycle of the fault transient, the output current i all_fault The waveform is divided into 11 segments, which can be described as a monotonically decreasing wave without fluctuation during the 1 / 6 period when the fault switch drive signal changes from high level to low level, and the remaining 1 / 6 period is divided into 2 fluctuation segments.

[0147] Based on the output current i during the 1 / 6 cycle of the fault switch drive signal transitioning from high to low during the fault transient, all_fault The characteristic of no fluctuation (i.e., a constant slope) allows for the location of the open-circuit faulty switch simply by detecting the output current slope within each 1 / 6-cycle time period and simultaneously checking for changes in the drive signals of each main control switch at the beginning and end of that 1 / 6-cycle. To simplify the slope detection procedure, only the output current i at the start, peak, and end of the 1 / 6-cycle needs to be recorded. all This allows us to calculate the slopes at both ends within 1 / 6 of the period.

[0148] Therefore, specifically, in I Li When the value is greater than 0, a sampling PWM signal is constructed, and the output current i is adjusted at the rising and falling edges of the sampling PWM signal. all Perform sampling and storage;

[0149] The sampled PWM signal is as follows:

[0150] S sample =S A1 +S A4 +S B1 +SB4 +S C1 +S C4 -floor(6*D)

[0151] Among them, S A1 S A4 S B1 S B4 S C1 S C4 The main control switches S for the upper and lower bridge arms of phases A, B, and C are respectively. wA1 S wA4 S wB1 S wB4 S wC1 S wC4 The drive signal is 1 when it is high and 0 when it is low. D is the output duty cycle, and the floor function is the smallest integer less than or equal to the specified expression.

[0152] Because S is within the full duty cycle range A1 and S A4 S B1 and S B4 and S C1 and S C4 Rising edge interval T s / 2, and S A1 S B1 S C1 Rising edge interval T s / 3, disregarding the order, divide a switching cycle into 6 equal segments. The start time of each segment must correspond to the rising edge of a certain drive signal. Similarly, each T s Within / 6, there must be a falling edge of a certain drive signal, which precisely corresponds to the moment when the output current slope changes within 1 / 6 of the cycle. Considering S A1 S A4 S B1 S B4 S C1 S C4 The distribution characteristics, using S A1 +S A4 +S B1 +S B4 +S C1 +S C4 -floor(6*D) can construct a floor in T s The sampled PWM signal at the moment the rising edge appears at the start and the falling edge appears when the output current slope changes, such as... Figure 11 As shown. When sampling the PWM signal S... sample Sample the output current i when the rising edge occurs all_R(k) and save it, in the sampled PWM signal S sample Sample the output current i when the falling edge occurs all_F (k) and save.

[0153] Calculate the output current slopes l1 and l2 between two adjacent sampling intervals at the rising edge of the sampled PWM signal:

[0154]

[0155]

[0156] Where i all_R (k) represents the sampled value of the output current at the rising edge, i all_R (k-1) represents the sampled value of the output current at the previous rising edge, i all_F (k) represents the output current sample value at the falling edge between two rising edges, Δt1 represents the duration from the previous rising edge to the falling edge, and Δt2 represents the duration from the falling edge to the current rising edge.

[0157] The slope calculation program is triggered on the rising edge of each sampled PWM signal, using the inductor current sample value i at that time. all_R (k), the output current sample value i at the previous rising edge. all_R (k-1) and the output current sampling value i at the falling edge all_F (k) Calculate the slopes l1 and l2, and determine the output current i by checking whether l1 and l2 are equal. all In the T s Are there fluctuations within the 6-segment?

[0158] If l1≠l2, it means that no open circuit fault of the main control switch was detected; if l1=l2, it means that an open circuit fault of the main control switch has occurred, and the fault location is between two rising edge sampling times, when the switch drive signal has a high-low level transition and the corresponding switch has an open circuit fault.

[0159] In each sampled PWM signal S sample The rising edge of the detection S is triggered simultaneously A1 S A4 S B1 S B4 S C1 S C4 In the T s / 6 The program that performs a high-low level transition detects S. sampleIf the driving signal is low at the rising edge of the signal and the previous sample value is high, then the corresponding switching transistor driving signal undergoes a high-low level transition; if the switching transistor driving signal undergoes a high-low level transition under the premise that l1 = l2 is satisfied, then the switching transistor is a switching transistor with an open circuit fault.

[0160] 2) For any sampled inductor current I Li Cases less than 0

[0161] When a three-phase interleaved parallel three-level DC-DC converter experiences an open-circuit fault in its main control switch, the duration of the fault transient is related to the energy stored in the inductor under fault-free conditions. A larger inductance parameter results in a longer energy release time for the inductor corresponding to the faulty half-bridge, leading to a correspondingly longer fault transient time. Step 2 can locate the faulty switch before entering the fault steady state. However, in practical applications, inductor parameter selection must consider various factors, potentially resulting in a shorter inductor discharge time. Therefore, the fault transient diagnosis method may not be able to locate the faulty switch within the effective fault transient time. Thus, after entering the fault steady state, a simpler and more reliable method is used to locate the faulty switch.

[0162] From the above analysis, we can see that I Li A negative value indicates the entry into a fault steady-state state. In this state, the corresponding inductor current i is adjusted at the peak times of each half-bridge carrier signal. Li (i = 1 ~ 6) Sampling, with exactly one and only half-bridge inductor current i for a main control switch open-circuit fault. Li The sampled value is negative, and the rest of the sampled values ​​are positive, therefore I Li The half-bridge main control switch corresponding to a value less than 0 has an open circuit fault.

[0163] Step 3: After completing the fault location according to Step 2, lock out the drive signals of the four switching transistors corresponding to the faulty half-bridge, and reconfigure the phase shift angle of the remaining two phase carrier signals to 180°, degrading to two-phase interleaved parallel operation.

[0164] If an open-circuit fault is detected in the main control switch of the upper or lower half of phase A, then S... A1 S A4 When the complementary control signal is set to 0, the carrier signals of the upper and lower half-bridge arms of phase B are phase-shifted by 120° based on the original signals, and the carrier signals of the upper and lower half-bridge arms of phase C are phase-shifted by 60° based on the original signals.

[0165] If an open-circuit fault is detected in the main control switch of the upper or lower half of phase B, then S... B1 S B4 When the complementary control signal is set to 0, the carrier signals of the upper and lower half-bridge arms of phase A remain unchanged, and the carrier signals of the upper and lower half-bridge arms of phase C are shifted by 60° based on the original signals.

[0166] If an open-circuit fault is detected in the main control switch of the upper or lower half of phase C, then S... C1 S C4 When the complementary control signal is set to 0, the carrier signals of the upper and lower half-bridge arms of phase A remain unchanged, while the carrier signals of the upper and lower half-bridge arms of phase B are phase-shifted by 300° based on the original signals.

[0167] The three signal phase-shifting schemes described above can ensure that if a switch transistor in any phase experiences an open-circuit fault, the remaining two phases will degenerate into two-phase interleaved parallel operation. However, considering the difference in output ripple between two-phase interleaved parallel operation and three-phase interleaved parallel operation, the inductors (L1~L6) and output capacitor C must be considered at the beginning of the circuit design. o The issue of parameter selection. The following section discusses how to select the parameters for the inductor and output capacitor in the design.

[0168] The output current ripple of the three-phase interleaved parallel three-level DC-DC converter is:

[0169]

[0170] Among them, V in f is the input voltage of the three-phase interleaved parallel three-level DC-DC converter. s Let be the switching frequency. According to the above formula, the maximum output current ripple is:

[0171]

[0172] To meet the output current ripple requirements, the inductor L is used in the three-phase interleaved parallel three-electric steady-state operation. i_normal The design principles are as follows:

[0173]

[0174] Where, Δi all_max This represents the maximum output current ripple.

[0175] Assuming the load current is constant at I o Then the output capacitor current i c The expression is:

[0176] i c =i all -I o

[0177] When the total input current i all Greater than I o When the output capacitor is charged, the total output current i all Less than I o At this time, the output capacitor discharges. Due to the output current i allThe frequency oscillates at 6 times within one switching cycle, and the capacitor charging and discharging time is T. s The same applies within / 6, meaning both the charging and discharging processes are T. s / 12. Therefore, the peak-to-peak value of the output voltage is:

[0178]

[0179] Substituting the output current ripple expression, we can obtain the output voltage ripple as follows:

[0180]

[0181] According to the above formula, the maximum output voltage ripple is:

[0182]

[0183] To meet the output voltage ripple requirements, the inductor C of the three-phase interleaved parallel three-electric system is required to operate in steady state. o_normal The design principles are as follows:

[0184]

[0185] Where, ΔV o_max This represents the maximum output voltage ripple.

[0186] Analyzing the output current ripple of a two-phase interleaved parallel three-level DC-DC converter using the same method, we can obtain the maximum output current ripple and maximum output voltage ripple under the two-phase interleaved parallel configuration:

[0187]

[0188]

[0189] With the same inductance value, the maximum output current ripple in two-phase interleaved parallel operation is 6 times that in three-phase interleaved parallel operation; with the same capacitor value, the maximum output voltage ripple in two-phase interleaved parallel operation is 18 times that in three-phase interleaved parallel operation. Therefore, without changing the switching frequency f... s Under the premise of current ripple requirements for three-phase interleaved parallel operation in steady state, inductor L is designed. i_normal and output capacitor C o_normal Meanwhile, in order to ensure that the two-phase interleaved parallel connection can also meet the ripple requirements, the inductors (L1~L6) of each phase and the output capacitor C o The selection of parameters follows these principles:

[0190] L i =6L i_normal (i = 1 to 6)

[0191] Co =3C o_normal

[0192] The open-circuit fault diagnosis and fault-tolerant operation method for a three-phase interleaved parallel three-level DC-DC converter proposed in this invention has the main advantages of determining whether the circuit has entered a fault steady state by sampling the inductor current at a specific moment, making the fault detection process simple and reliable; it distinguishes between the fault-free state and the fault transient state of the circuit by the slope of the output current, and can locate the faulty switch during the fault transient period by combining the falling edge of the switch drive signal; the fault diagnosis method combines the current characteristics under fault transient and fault steady state, taking into account both speed and accuracy; after locating the faulty switch, the three-phase interleaved parallel three-level DC-DC converter is degraded to a two-phase interleaved parallel, realizing fault-tolerant operation.

[0193] In another embodiment of the present invention, a three-phase interleaved parallel three-level DC-DC converter open-circuit fault diagnosis and fault-tolerant operation control system is proposed, comprising:

[0194] Inductor current acquisition module: Used to acquire the corresponding inductor current I at the peak moment of the triangular carrier signal of the half-bridge of the six switching transistors of the converter. Li , i = 1 to 6;

[0195] Circuit current state determination module: Determines the current state of the circuit based on the sign of the inductor current; if the converter's I... Li If all values ​​are greater than 0, the converter is determined to be fault-free or operating in a fault transient state; if any I of the converter is greater than 0, the converter is determined to be fault-free or operating in a fault transient state. Li If the value is less than 0, the converter is determined to have entered a fault steady state;

[0196] Fault location module: in the sampled inductor current I Li When all values ​​are greater than 0, the location of the open circuit fault is determined by the current slope between the output current sampling points and the falling edge of the main control switch drive signal; at any sampled inductor current I... Li If it is less than 0, then I is determined. Li The main control switch transistor of the half-bridge corresponding to a value less than 0 has an open circuit fault;

[0197] Fault-tolerant operation control module: After completing fault location, it blocks the drive signals of the four switching transistors of the corresponding phase of the faulty half-bridge, and reconfigures the phase shift angle of the remaining two phase carrier signals to 180°, degrading to two-phase interleaved parallel operation.

[0198] The control system proposed in the embodiments of the present invention can implement any step of the above method.

[0199] It should be noted that the above embodiments are merely preferred embodiments of the present invention and should not be construed as limiting the scope of protection of the present invention. Any minor changes and modifications made to the present invention without departing from the concept of the present invention shall fall within the scope of protection of the present invention.

Claims

1. A method for fault diagnosis and fault-tolerant operation of a three-phase interleaved parallel three-level converter, characterized in that, Includes the following steps: In the three-phase interleaved parallel three-level converter, the switching transistor S WA1 S WA2 Series, S WB1 S WB2 Series, S WC1 S WC2 The three phases are connected in series to form the upper arms of the bridge; the switching transistor S WA3 S WA4 Series, S WB3 S WB4 Series, S WC3 S WC4 The three phases are connected in series to form the lower bridge arm; one end of each inductor L1, L2, and L3 is connected to the switching transistor S. WA1 S WA2 Between, S WB1 S WB2 Between, S WC1 S WC2 Between the two ends, the other end is connected to the output capacitor C. o One end of inductors L4, L5, and L6 are respectively connected to the switching transistor S. WA3 S WA4 Between, S WB3 S WB4 Between, S WC3 S WC4 Between the two ends, the other end is connected to the output capacitor C. o The other pole; Step 1: At the peak time of the triangular carrier signal of the half-bridge of the six switching transistors of the converter, collect the corresponding inductor current I. Li i = 1~6, determine the current state of the circuit based on the sign of the inductor current; If the converter I Li If all values ​​are greater than 0, the converter is determined to be fault-free or operating in a fault transient state; if any I of the converter is greater than 0, the converter is determined to be fault-free or operating in a fault transient state. Li If the value is less than 0, the converter is determined to have entered a fault steady state; Step 2, in the sampled inductor current I Li When all values ​​are greater than 0, the location of the open circuit fault is determined by the current slope between the output current sampling points and the falling edge of the main control switch drive signal; at any sampled inductor current I... Li If it is less than 0, then I is determined. Li The main control switch transistor of the half-bridge corresponding to a value less than 0 has an open circuit fault; In step 2: in I Li When the value is greater than 0, a sampling PWM signal is constructed, and the output current i is adjusted at the rising and falling edges of the sampling PWM signal. all Samples are saved; at the rising edge of the sampled PWM signal, the output current slopes l1 and l2 between two adjacent sampling intervals are calculated. If l1 ≠ l2, it means that no open circuit fault of the main control switch is detected; if l1 = l2, it means that an open circuit fault of the main control switch has occurred, and the fault location is the switch corresponding to the high-low level transition of the switch drive signal between the two rising edge sampling times. Step 3: After completing the fault location, lock out the drive signals of the four switching transistors corresponding to the faulty half-bridge, and reconfigure the phase shift angle of the remaining two phase carrier signals to 180°, degrading to two-phase interleaved parallel operation.

2. The method for fault diagnosis and fault-tolerant operation of a three-phase interleaved parallel three-level converter according to claim 1, characterized in that, The sampled PWM signal is: ； Among them, S A1 S A4 S B1 S B4 S C1 S C4 These are the drive signals for the main control switches of the upper and lower bridge arms of phases A, B, and C, respectively. A high level corresponds to 1, and a low level corresponds to 0. D is the output duty cycle, and the floor function is the smallest integer less than or equal to the specified expression.

3. The method for fault diagnosis and fault-tolerant operation of a three-phase interleaved parallel three-level converter according to claim 1, characterized in that, The output current slopes l1 and l2 are expressed as follows: ； ； Where i all_R (k) represents the sampled value of the output current at the rising edge, i all_R (k-1) represents the sampled value of the output current at the previous rising edge, i all_F (k) represents the output current sample value at the falling edge between two rising edges, Δt1 represents the duration from the previous rising edge to the falling edge, and Δt2 represents the duration from the falling edge to the current rising edge.

4. A method for fault diagnosis and fault-tolerant operation of a three-phase interleaved parallel three-level converter according to any one of claims 1-3, characterized in that, Step 3 specifically involves: If an open-circuit fault is detected in the main control switch of the upper or lower half of phase A, the drive signal S of the main control switch of the upper or lower half of phase A will be... A1 S A4 When the complementary control signal is set to 0, the carrier signals of the upper and lower half-bridge arms of phase B are phase-shifted by 120° based on the original signals, and the carrier signals of the upper and lower half-bridge arms of phase C are phase-shifted by 60° based on the original signals. If an open-circuit fault is detected in the main control switch of the upper or lower half of phase B, the drive signal S of the main control switch of the upper or lower half of phase B will be... B1 S B4 When the complementary control signal is set to 0, the carrier signals of the upper and lower half-bridge arms of phase A remain unchanged, and the carrier signals of the upper and lower half-bridge arms of phase C are shifted by 60° based on the original signals. If an open-circuit fault is detected in the main control switch of the upper or lower half of phase C, the drive signal S of the main control switch of the upper or lower half of phase C will be switched off. C1 S C4 When the complementary control signal is set to 0, the carrier signals of the upper and lower half-bridge arms of phase A remain unchanged, while the carrier signals of the upper and lower half-bridge arms of phase B are phase-shifted by 300° based on the original signals.

5. The method for fault diagnosis and fault-tolerant operation of a three-phase interleaved parallel three-level converter according to claim 1, characterized in that, In step 3, to ensure that the output ripple still meets the requirements when degenerating into two-phase interleaved parallel operation, the inductors L1~L6 of each phase and the output capacitor C are... o The selection of parameters follows these principles: ； ； Among them, L i_normal and C o_normal These represent the inductor and capacitor parameters designed to meet the requirements for inductor current ripple and output voltage ripple during three-phase interleaved parallel operation, respectively. ； ； Among them, V in f is the input voltage of the three-phase interleaved parallel three-level DC-DC converter. s Δi is the switching frequency. all_max For the maximum output current ripple, ΔV o_max This represents the maximum output voltage ripple.

6. A fault diagnosis and fault-tolerant operation control system for a three-phase interleaved parallel three-level converter, characterized in that, include: In the three-phase interleaved parallel three-level converter, the switching transistor S WA1 S WA2 Series, S WB1 S WB2 Series, S WC1 S WC2 The three phases are connected in series to form the upper arms of the bridge; the switching transistor S WA3 S WA4 Series, S WB3 S WB4 Series, S WC3 S WC4 The three phases are connected in series to form the lower bridge arm; one end of each inductor L1, L2, and L3 is connected to the switching transistor S. WA1 S WA2 Between, S WB1 S WB2 Between, S WC1 S WC2 Between the two ends, the other end is connected to the output capacitor C. o One end of inductors L4, L5, and L6 are respectively connected to the switching transistor S. WA3 S WA4 Between, S WB3 S WB4 Between, S WC3 S WC4 Between the two ends, the other end is connected to the output capacitor C. o The other pole; Inductor current acquisition module: used to acquire the corresponding inductor current I at the peak time of the triangular carrier signal of the half-bridge of the six switching transistors of the converter. Li , i = 1~6; Circuit current state determination module: Determines the current state of the circuit based on the sign of the inductor current; If the converter I Li If all values ​​are greater than 0, the converter is determined to be fault-free or operating in a fault transient state; if any I of the converter is greater than 0, the converter is determined to be fault-free or operating in a fault transient state. Li If the value is less than 0, the converter is determined to have entered a fault steady state; Fault location module: in the sampled inductor current I Li When all values ​​are greater than 0, the location of the open circuit fault is determined by the current slope between the output current sampling points and the falling edge of the main control switch drive signal; at any sampled inductor current I... Li If it is less than 0, then I is determined. Li The main control switch transistor of the half-bridge corresponding to a value less than 0 has an open circuit fault; In the fault location module: in I Li When the value is greater than 0, a sampling PWM signal is constructed, and the output current i is adjusted at the rising and falling edges of the sampling PWM signal. all Samples are saved; at the rising edge of the sampled PWM signal, the output current slopes l1 and l2 between two adjacent sampling intervals are calculated. If l1 ≠ l2, it means that no open circuit fault of the main control switch is detected; if l1 = l2, it means that an open circuit fault of the main control switch has occurred, and the fault location is the switch corresponding to the high-low level transition of the switch drive signal between the two rising edge sampling times. Fault-tolerant operation control module: After completing fault location, it blocks the drive signals of the four switching transistors of the corresponding phase of the faulty half-bridge, and reconfigures the phase shift angle of the remaining two phase carrier signals to 180°, degrading to two-phase interleaved parallel operation.

7. The fault diagnosis and fault-tolerant operation control system for a three-phase interleaved parallel three-level converter according to claim 6, characterized in that, In the fault-tolerant operation control module: If an open-circuit fault is detected in the main control switch of the upper or lower half of phase A, the drive signal S of the main control switch of the upper or lower half of phase A will be... A1 S A4 When the complementary control signal is set to 0, the carrier signals of the upper and lower half-bridge arms of phase B are phase-shifted by 120° based on the original signals, and the carrier signals of the upper and lower half-bridge arms of phase C are phase-shifted by 60° based on the original signals. If an open-circuit fault is detected in the main control switch of the upper or lower half of phase B, the drive signal S of the main control switch of the upper or lower half of phase B will be... B1 S B4 When the complementary control signal is set to 0, the carrier signals of the upper and lower half-bridge arms of phase A remain unchanged, and the carrier signals of the upper and lower half-bridge arms of phase C are shifted by 60° based on the original signals. If an open-circuit fault is detected in the main control switch of the upper or lower half of phase C, the drive signal S of the main control switch of the upper or lower half of phase C will be switched off. C1 S C4 When the complementary control signal is set to 0, the carrier signals of the upper and lower half-bridge arms of phase A remain unchanged, while the carrier signals of the upper and lower half-bridge arms of phase B are phase-shifted by 300° based on the original signals.

8. The fault diagnosis and fault-tolerant operation control system for a three-phase interleaved parallel three-level converter according to claim 6, characterized in that, The sampled PWM signal is: ； Among them, S A1 S A4 S B1 S B4 S C1 S C4 These are the drive signals for the main control switches of the upper and lower bridge arms of phases A, B, and C, respectively. A high level is 1, and a low level is 0. D is the output duty cycle, and the floor function is the smallest integer less than or equal to the specified expression. The output current slopes l1 and l2 are expressed as follows: ； ； Where i all_R (k) represents the sampled value of the output current at the rising edge, i all_R (k-1) represents the sampled value of the output current at the previous rising edge, i all_F (k) represents the output current sample value at the falling edge between two rising edges, Δt1 represents the duration from the previous rising edge to the falling edge, and Δt2 represents the duration from the falling edge to the current rising edge.

Images