Selective overflow LOFIC pixel structure

Abstract

The application discloses a selective overflow LOFIC pixel structure, which comprises a photodiode PD, a transfer transistor TG, an invalid overflow transistor SO, an effective overflow transistor SGA, a linear follow transistor OSF, a switch transistor SGB, a reset transistor RST, a LOFIC capacitor Cs, a floating diffusion capacitor FD, a source follow transistor SF and a row selection transistor SEL. Under a high light intensity condition, the photodiode PD accumulates charges to reach a full well capacity and then overflows, one of which is an invalid overflow which is discharged to VDD through the invalid overflow transistor SO, and the other is an effective overflow which is overflowed to a node of the LOFIC capacitor Cs through the effective overflow transistor SGA. The selective overflow ratio of the saturated charges is controlled by controlling the off voltage, the gate length, the gate width and the doping ability under the gate of the effective overflow transistor SGA and the invalid overflow transistor SO. The equivalent amplification of the LOFIC capacitor is realized by reducing the selective overflow ratio.

Description

Technical Field

[0001] This invention relates to the field of analog integrated circuit technology, and in particular to a selective overflow LOFIC pixel structure. Background Technology

[0002] One of the most important sources of information for humans is the human eye, and solid-state image sensors, which can record and store what the human eye sees, have become a key technology for recording image information. Image sensors are divided into charge-coupled device (CCD) image sensors and complementary metal-oxide-semiconductor (CMOS) image sensors. CMOS image sensors (CIS) are functional devices that utilize the photoelectric conversion function of the device to convert the light image on the photosensitive surface into an electrical signal proportional to the light image.

[0003] Dynamic range (DR) is one of the key performance parameters of CIS. It indicates the range of the maximum and minimum light intensity signals that CIS can detect simultaneously in the same frame of image. The higher the dynamic range, the clearer the image contrast and details. People hope to restore the true image information by improving DR.

[0004] Lateral Overflow Integration Capacitor (LOFIC) technology is an effective method to improve dynamic range. By adding capacitors within pixels, it enables the effective collection of overflow charges from photodiodes (PDs), and the total full-well capacity is no longer limited by the full-well capacity of the PD. This effectively solves the trade-off between full-well capacity and conversion gain, and is one of the research hotspots in the field of CIS.

[0005] Currently, chip sizes are gradually shrinking, while achieving high dynamic range requires large LOFIC capacitors. However, due to area limitations, it is difficult to make large LOFIC capacitors within small pixels. Therefore, how to achieve large LOFIC capacitors within small pixels is an urgent problem to be solved. Summary of the Invention

[0006] The purpose of this invention is to address the technical deficiencies in the existing technology by providing a selective overflow LOFIC pixel structure that can guarantee high light signal linearity. By selecting the overflow ratio, a large LOFIC capacitor is achieved for use in image sensor applications, solving the problem that pixels rely on large capacitors to achieve high dynamic range, resulting in a large area occupation.

[0007] The technical solution adopted to achieve the purpose of this invention is:

[0008] A selective overflow LOFIC pixel structure includes a photodiode PD, a transfer transistor TG, an invalid overflow transistor SO, an active overflow transistor SGA, a linear follower transistor OSF, a switching transistor SGB, a reset transistor RST, a LOFIC capacitor Cs, a floating diffusion capacitor FD, a source follower transistor SF, and a row selection transistor SEL.

[0009] Among them, the gate of the transmission transistor TG is given a transmission control signal TG, its source is connected to the cathode of the photodiode PD, and its drain is connected to the floating diffusion node FD; the gate of the invalid overflow transistor SO is given a turn-off voltage, its source is connected to the cathode of the photodiode PD, and its drain is connected to the source of the linear follower transistor OSF; the gate of the effective overflow transistor SGA is given an effective overflow turn-off voltage, its source is connected to the cathode of the photodiode PD, and its drain is connected to the LOFIC capacitor Cs.

[0010] The gate of the reset transistor RST is given a reset control signal RST, its source is connected to the floating diffusion capacitor FD, and its drain is connected to VDD; one end of the LOFIC capacitor Cs is grounded, and the other end is connected to the drain of the active overflow transistor SGA and the source of the switching transistor SGB.

[0011] The floating diffusion capacitor FD is connected to the gate of the source follower transistor SF and the drain of the switching transistor SGB, respectively. The gate of the switching transistor SGB is connected to the switching control signal SGB. The gate of the linear follower transistor OSF is connected to the upper plate of the LOFIC capacitor Cs, the drain is connected to VDD, and the source is connected to the drain of the invalid overflow transistor SO. The source of the source follower transistor SF is connected to VDD, and the drain is connected to the source of the row select transistor SEL. The gate of the row select transistor SEL is connected to the row select control signal SEL, and the source is connected to the column bus COLUMN.

[0012] Specifically, by controlling the turn-off voltage, gate length, and under-gate doping of the effective overflow transistor SGA and the ineffective overflow transistor SO to change the emitter barrier on the charge overflow path, and by changing the gate width to adjust the overflow channel width, the selective overflow ratio of saturated charge is controlled, and the equivalent amplification of the LOFIC capacitor is achieved by reducing the selective overflow ratio.

[0013] Here, sov is defined as the selection overflow ratio, which is the number N of electrons N emitted by the PPD to the effective overflow transistor SGA during the exposure phase. tr_SGA The number N of electrons emitted to the invalid overflow transistor SO tr_SO The ratio of is expressed as follows.

[0014]

[0015] In this process, the overflowing photogenerated charge is diverted through the pixel structure, and only the overflow charge that passes through the effective overflow transistor SGA is collected by the LOFIC capacitor Cs, thereby achieving an equivalent amplification factor.

[0016] Wherein, the equivalent amplification factor is:

[0017]

[0018] Under high light intensity conditions, the charge accumulated in the photodiode PD increases, and after reaching the full-well capacity of the photodiode PD, it overflows. There are two overflow paths for the saturated charge: one is through the ineffective overflow transistor SO to VDD, which is an ineffective overflow; the other is through the effective overflow transistor SGA to the LOFIC capacitor Cs node, which is an effective overflow.

[0019] The selective overflow LOFIC pixel structure of the present invention can achieve a large LOFIC capacitor Cs by selecting the overflow ratio, which solves the problem that the traditional LOFIC technology requires a large capacitor to improve the dynamic range, resulting in an excessive area occupation and making it unsuitable for small-sized pixels.

[0020] This invention enhances the LOCIC capacitance through selective overflow. Specifically, it adds an invalid overflow transistor to the cathode side of the photodiode (PD), creating two saturated electron overflow paths: invalid and valid overflow. By controlling the turn-off voltage, gate length, gate width, and under-gate doping of the valid and invalid overflow transistors, the selective overflow ratio of saturated charge can be adjusted. Furthermore, the change in this ratio is linearly related to the four control methods mentioned above (i.e., controlling the turn-off voltage, gate length, gate width, and under-gate doping); the lower the selective overflow ratio, the greater the increase in LOCIC capacitance.

[0021] Compared to traditional LOFIC pixels that rely on large capacitors to achieve high dynamic range, this invention can reduce the area occupied by capacitors in small-sized pixels and extend the dynamic range using LOFIC technology. Attached Figure Description

[0022] Figure 1 This is a circuit diagram of a selective overflow LOFIC pixel structure that ensures high optical fidelity.

[0023] Figure 2 yes Figure 1 Timing diagram of pixel structure operation.

[0024] Figure 3 This is a schematic diagram of the voltage follower loop during the pixel overflow process. Detailed Implementation

[0025] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

[0026] The purpose of this invention is to address the problem that, with the trend of increasingly smaller chip sizes, traditional LOFIC technology relies on large capacitors to improve dynamic range, resulting in excessive area occupation and making it unsuitable for designs with small-sized pixels.

[0027] To address the compatibility issue between small-sized pixels and large LOFIC capacitors, this invention utilizes an ineffective overflow transistor to reduce the selective overflow ratio of saturated charge, thereby achieving a linear increase in the LOFIC capacitor. Consequently, the linearity of the signal also needs to be guaranteed under bright conditions.

[0028] Figure 1 A schematic diagram of the selective overflow LOFIC pixel circuit structure proposed in this invention, which can guarantee the linearity of high-brightness signals, is shown below. Figure 1 As shown, the selective overflow LOFIC pixel circuit structure includes a photodiode PD, a transfer transistor TG, an invalid overflow transistor SO, an active overflow transistor SGA, a linear follower transistor OSF, a switching transistor SGB, a reset transistor RST, a LOFIC capacitor Cs, a floating diffusion capacitor FD, a source follower transistor SF, and a row selection transistor SEL.

[0029] In this system, the gate of the transmission transistor TG is given a transmission control signal TG, its source is connected to the cathode of the photodiode PD, and its drain is connected to the floating diffusion node FD. The gate of the invalid overflow transistor SO is given a certain turn-off voltage, its source is connected to the cathode of the photodiode PD, and its drain is connected to the source of the linear follower transistor OSF. The gate of the effective overflow transistor SGA is given a certain effective overflow turn-off voltage, its source is connected to the cathode of the photodiode PD, and its drain is connected to the LOFIC capacitor Cs. The gate of the reset transistor RST is given a reset control signal RST, its source is connected to the floating diffusion capacitor FD, and its drain is connected to VDD. One end of the LOFIC capacitor Cs is grounded, and the other end is connected to the drain of the effective overflow transistor SGA and the source of the switching transistor SGB. The floating diffusion capacitor FD is connected to the gate of the source follower transistor SF and the drain of the switching transistor SGB, with the switching control signal SGB applied to the gate of the switching transistor SGB. The gate of the linear follower transistor OSF is connected to the upper plate of the LOFIC capacitor Cs, its drain is connected to VDD, and its source is connected to the drain of the invalid overflow transistor SO. The source follower transistor SF has its source connected to VDD and its drain connected to the source of the row select transistor SEL. The row select control signal SEL is applied to the gate of the row select transistor SEL, and its source is connected to the column bus COLUMN.

[0030] Compared to the traditional LOFIC pixel structure, the proposed selective overflow LOFIC pixel structure with high light intensity guarantee adds an ineffective overflow transistor (SO) and an effective overflow transistor (SGA). Under high light intensity conditions, the charge accumulated in the photodiode (PD) increases, and overflow occurs after the photodiode reaches its full-well capacity. There are two overflow paths for this saturated charge: one is through the ineffective overflow transistor (SO) to VDD for discharge, which is called ineffective overflow; the other is through the effective overflow transistor (SGA) to the LOFIC capacitor Cs node, which is called effective overflow.

[0031] Define sov as the selected overflow ratio, which is the number N of electrons N emitted by the PPD to the effective overflow transistor SGA during the exposure phase. tr_SGA The number N of electrons emitted to the invalid overflow transistor SO tr_SO The ratio:

[0032]

[0033] Because the pixel structure shunts the overflowing photogenerated charge, and only the overflowing charge that passes through the effective overflow transistor SGA is collected by the LOFIC capacitor Cs, the selective overflow pixel structure can effectively amplify the capacitance factor, specifically the capacitance amplification factor C. AMP The relationship with the selection overflow ratio sov is:

[0034]

[0035] By controlling the turn-off voltage, gate length, and under-gate doping of the effective overflow transistor SGA and the ineffective overflow transistor SO, the emitter barrier on the charge overflow path can be changed. By changing the gate width to adjust the overflow channel width, the selective overflow ratio of saturated charge can be further controlled. By reducing the selective overflow ratio, the equivalent amplification of the LOFIC capacitor can be achieved.

[0036] For example, assuming a spillover ratio of 1 / 4, if five saturated electrons are generated, four will be expelled through the ineffective spillover transistor SO, leaving only one electron to overflow to the Cs node through the effective spillover transistor SGA. Compared to the scenario where all five electrons overflow to the Cs node, this method effectively increases the Cs node capacitance to five times its original value. This method does not reduce the conversion gain; it simply reduces the number of electrons overflowing to the Cs node, slowing down the rate at which the Cs node voltage decreases due to the accumulation of overflow charge. This allows for higher light intensity detection and enables a large LOFIC capacitance within a limited pixel area.

[0037] Since selective overflow LOFIC pixels perform proportional segmentation of charge overflow, ensuring the linearity of voltage signal changes during exposure is crucial. The pixels primarily utilize the inactive overflow transistor SO and the active overflow transistor SGA for charge overflow. During exposure, to adjust the gate potential of the overflow transistor, the gate voltage is set to V. SO_off and V SGA_off The overflow ratio sov is controlled by the gate potential of the overflow transistor. The influence of the DIBL effect in submicron devices begins to increase, while the LDD device structure can effectively alleviate the DIBL effect. In addition, the use of the linear follower transistor OSF ensures that the overflow barriers on both sides are constant, thereby effectively ensuring the signal linearity under high light conditions.

[0038] Figure 2 The operating timing of the selective overflow LOFIC pixel with high light accuracy guaranteed by the present invention is given. First, the reset transistor RST, the switching transistor SGB, and the transmission transistor TG are all turned on, and the LOFIC capacitor Cs, the floating diffusion capacitor FD, and the photodiode PD are reset. After pixel initialization is completed and exposure begins, the two overflow transistors, the effective overflow transistor SGA and the ineffective overflow transistor SO, are given a certain turn-off voltage.

[0039] After exposure, the row selection transistor SEL is given a high voltage to begin signal readout. At the same time, the effective overflow transistor SGA and the invalid overflow transistor SO are no longer subject to a certain turn-off voltage. Then, the switching transistor SGB turns on, connecting the LOFIC capacitor Cs and the floating diffusion capacitor FD node, and the overflow signal voltage OS is read out. Then, the reset transistor RST turns on to clear the overflow charge of the LOFIC capacitor Cs and the floating diffusion capacitor FD node, and turns off the reset transistor RST, and the overflow reset signal voltage OR is read out. This completes the readout of the overflow signal.

[0040] Then, the switching transistor SGB is turned off, and the reset voltage HR of the floating diffusion capacitor FD node is read out. Then, the transmission transistor TG is turned on, and all the photogenerated charge in the photodiode PD is transferred to the floating diffusion capacitor FD node. The signal voltage HS of the floating diffusion capacitor FD node is read out. The full-well capacity of FD is designed to be greater than that of the photodiode PD to ensure that the charge inside the photodiode PD can be fully contained.

[0041] When the light intensity is low, the generated signal charge is lower than the full-well capacity of the photodiode PD. At this time, the signal readout of HR and HS is more important. This is consistent with the high conversion gain and low noise signal readout of 4T pixels. In this case, the conversion gain of the pixel is q / CFD, where q is the basic charge and CFD is the total capacitance of the floating diffusion capacitor FD node.

[0042] When the light intensity is high, the generated photocharge exceeds the full-well capacitance of the photodiode PD. A portion of the overflow charge will be collected in the LOFIC capacitor Cs. In this case, the overflow signal charge is read out with a low conversion gain q / (CFD+Cs) (Cs is the total capacitance of the LOFIC capacitor Cs node). The readout noise under low conversion gain is determined by the floating diffusion capacitor FD and the thermal reset noise of the LOFIC capacitor Cs. This noise can be ignored when the optical shot noise at the signal junction is large enough.

[0043] Figure 3 A schematic diagram of the voltage follower loop during the overflow process of the pixel structure proposed in this invention is given. When the light intensity is high, the charge accumulated in the photodiode PD gradually reaches its maximum full-well capacity. The overflow of photogenerated charge generated by the light and the saturated photogenerated charge form a dynamic balance. At this time, the photodiode PD is established as the load current source of the linear follower transistor OSF. As the exposure proceeds, the ineffective overflow transistor SO and the effective overflow transistor SGA proportionally divide the saturated photogenerated current. The LOFIC capacitor Cs continuously collects the charge transferred by the effective overflow transistor SGA, and its upper plate voltage gradually decreases. The V of the effective overflow transistor SGA... ds As the voltage gradually decreases, the linear follower transistor OSF can replicate this voltage change to the drain of the invalid overflow transistor SO, causing the V of the invalid overflow transistor SO to decrease. ds The voltage drops synchronously, and the V values ​​of the two transistors... ds The voltage difference is approximately equal to the threshold voltage of the linear follower transistor OSF. Due to the synchronous decrease in source and drain voltages, the problem of unstable proportional segmentation of the saturated photocurrent caused by the source-drain voltage difference during exposure is effectively prevented, thus ensuring the linearity of the high-light signal without introducing additional power consumption.

[0044] As can be seen from the above description, this invention amplifies the LOFIC capacitor Cs by connecting an invalid overflow switch to one end of the photodiode PD, forming two overflow paths: valid overflow and invalid overflow. Under high-light conditions, the charge ratio of the valid and invalid overflows of the photodiode PD can be determined by controlling the turn-off gate voltages of the valid and invalid overflow transistors. The overflow ratio is linearly related to the difference between the turn-off gate voltages of the two switches. By controlling the selective overflow ratio to amplify the LOFIC capacitor Cs, a large LOFIC capacitor can be effectively achieved in a small pixel. At the same time, adding a linear follower transistor within the pixel ensures that the selective overflow ratio remains constant during exposure, thereby improving the linearity of the pixel's highlight signal.

[0045] The foregoing has shown and described the basic principles, main features, and advantages of the present invention. It will be apparent to those skilled in the art that the present invention is not limited to the details of the above exemplary embodiments, and that the present invention can be implemented in other specific forms without departing from the spirit or basic features of the present invention.

[0046] Therefore, the embodiments should be regarded as exemplary and non-limiting in all respects, and the scope of the invention is defined by the appended claims rather than the foregoing description. Thus, it is intended that all variations falling within the meaning and scope of the equivalents of the claims be included within the invention.

[0047] Furthermore, it should be understood that although this specification describes embodiments, not every embodiment contains only one independent technical solution. This narrative style is merely for clarity. Those skilled in the art should consider the specification as a whole, and the technical solutions in each embodiment can also be appropriately combined to form other embodiments that can be understood by those skilled in the art.

Claims

1. A selective overflow LOFIC pixel structure, characterized in that, This includes photodiodes PD, transfer transistors TG, invalid overflow transistors SO, valid overflow transistors SGA, linear follower transistors OSF, switching transistors SGB, reset transistors RST, LOFIC capacitors Cs, floating diffusion capacitors FD, source follower transistors SF, and row select transistors SEL. Among them, the gate of the transmission transistor TG is given a transmission control signal TG, its source is connected to the cathode of the photodiode PD, and its drain is connected to the floating diffusion node FD; the gate of the invalid overflow transistor SO is given a turn-off voltage, its source is connected to the cathode of the photodiode PD, and its drain is connected to the source of the linear follower transistor OSF; the gate of the effective overflow transistor SGA is given an effective overflow turn-off voltage, its source is connected to the cathode of the photodiode PD, and its drain is connected to the LOFIC capacitor Cs. The gate of the reset transistor RST is given a reset control signal RST, its source is connected to the floating diffusion capacitor FD, and its drain is connected to VDD; one end of the LOFIC capacitor Cs is grounded, and the other end is connected to the drain of the active overflow transistor SGA and the source of the switching transistor SGB. The floating diffusion capacitor FD is connected to the gate of the source follower transistor SF and the drain of the switching transistor SGB, respectively. The gate of the switching transistor SGB is connected to the switching control signal SGB. The gate of the linear follower transistor OSF is connected to the upper plate of the LOFIC capacitor Cs, the drain is connected to VDD, and the source is connected to the drain of the invalid overflow transistor SO. The source of the source follower transistor SF is connected to VDD, and the drain is connected to the source of the row select transistor SEL. The gate of the row select transistor SEL is connected to the row select control signal SEL, and the source is connected to the column bus COLUMN.

2. The selective overflow LOFIC pixel structure according to claim 1, characterized in that, By controlling the turn-off voltage, gate length, and under-gate doping of the effective overflow transistor SGA and the ineffective overflow transistor SO to change the emitter barrier on the charge overflow path, and by adjusting the overflow channel width by changing the gate width, the selective overflow ratio of saturated charge can be controlled, thereby achieving the equivalent amplification of the LOFIC capacitor by reducing the selective overflow ratio.

3. The selective overflow LOFIC pixel structure according to claim 2, characterized in that, Define sov as the selected overflow ratio, which is the number N of electrons N emitted by the PPD to the effective overflow transistor SGA during the exposure phase. tr_SGA The number N electrons emitted to the invalid overflow transistor SO tr_SO The ratio is expressed as follows: 。 4. The selective overflow LOFIC pixel structure according to claim 3, characterized in that, The overflowing photogenerated charge is diverted by the pixel structure. Only the overflowing charge that passes through the effective overflow transistor SGA is collected by the LOFIC capacitor Cs, thereby achieving an equivalent amplification factor.

5. The selective overflow LOFIC pixel structure according to claim 4, characterized in that, The equivalent amplification factor is:

6. The selective overflow LOFIC pixel structure according to claim 1, characterized in that, Under high light intensity conditions, the charge accumulated in the photodiode PD increases. After reaching the full-well capacity of the photodiode PD, it overflows. There are two overflow paths for the saturated charge: one is through the ineffective overflow transistor SO to VDD, which is an ineffective overflow; the other is through the effective overflow transistor SGA to the node of the LOFIC capacitor Cs, which is an effective overflow.

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