Method for manufacturing a semiconductor structure and semiconductor structure

Abstract

The present disclosure provides a semiconductor structure manufacturing method and a semiconductor structure, and relates to the technical field of semiconductors. The semiconductor structure manufacturing method comprises the following steps: providing a substrate; forming a plurality of initial active layers, the initial active layers extending along a first direction, the plurality of initial active layers being arranged along a second direction and a third direction, the first direction being parallel to the top surface of the substrate, and the third direction being perpendicular to the top surface of the substrate; forming a plurality of word lines, each word line extending along the third direction, and each word line covering part of the sidewall of the initial active layer arranged along the third direction; forming an active step at the first end of the initial active layer; removing part of the structure of each initial active layer to form an active layer, and the active layer retaining the active step; forming a capacitor structure; and forming a bit line. In the present disclosure, the semiconductor structure has an increasing storage density, and overcomes the problem that the storage density of a semiconductor chip is difficult to continue to increase due to size miniaturization, thereby providing a new direction for the development of semiconductor chips.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and in particular to a method for fabricating a semiconductor structure and the semiconductor structure itself. Background Technology

[0002] In the field of semiconductor chips, according to Moore's Law, the performance of a semiconductor chip doubles for every doubling of the number of semiconductor devices. To improve the performance of semiconductor chips, their feature sizes are continuously shrinking and their integration density is continuously increasing. However, due to the limitations of photolithography processes, there are limits to the size reduction of semiconductor chips. Summary of the Invention

[0003] The following is an overview of the subject matter described in detail in this disclosure. This overview is not intended to limit the scope of the claims.

[0004] This disclosure provides a method for fabricating a semiconductor structure and the semiconductor structure itself.

[0005] The first aspect of this disclosure provides a method for fabricating a semiconductor structure, the method comprising:

[0006] Provide substrate;

[0007] Multiple initial active layers are formed, each of which extends along a first direction. The multiple initial active layers are arrayed above the substrate along a second direction and a third direction. The first direction and the second direction are parallel to the top surface of the substrate, and the third direction is perpendicular to the top surface of the substrate.

[0008] Multiple word lines are formed, each word line extending along the third direction, each word line intersecting with the initial active layer arranged along the third direction, and covering a portion of the sidewall of the initial active layer arranged along the third direction;

[0009] Multiple initial active layers are etched, and the initial active layers intersecting the same word line have a length difference in the first direction, forming an active step at the first end of the initial active layer;

[0010] Remove a portion of the structure of each of the initial active layers, and the remaining portion of the structure of each of the initial active layers forms an active layer, wherein the active layer retains the active step;

[0011] A capacitor structure is formed on the side of the active layer away from the active step, and the capacitor structure is in contact with each of the active layers;

[0012] Bit lines are formed extending along the third direction, each bit line corresponding to each active step.

[0013] This involves forming multiple initial active layers, including:

[0014] A stacked structure is formed, the stacked structure comprising active material layers and insulating material layers alternately stacked along the third direction;

[0015] The stacked structure is etched to form multiple first trenches, which extend along the first direction. The multiple first trenches divide each active material layer into multiple initial active layers spaced apart in the second direction.

[0016] This forms multiple character lines, including:

[0017] A first isolation layer is formed in the first trench;

[0018] A portion of the first isolation layer and a portion of the isolation material layer are removed to form a plurality of word line slots, each of the word line slots extending along the third direction to expose a portion of the sidewall of the initial active layer arranged along the third direction, and the plurality of word line slots are arranged in multiple columns along the second direction;

[0019] The character line is formed in each of the character line slots, and the plurality of character lines are arranged in multiple columns along the second direction.

[0020] The formation of the character line in each of the character line slots includes:

[0021] A gate oxide layer is formed, which covers a portion of the sidewall of the initial active layer exposed by the word slot and the slot wall of the word slot;

[0022] A gate conductive layer is formed, which covers the gate oxide layer and fills the unfilled area of ​​the word slot;

[0023] The gate oxide layer and the gate conductive layer located in the same word line slot together form the word line.

[0024] The stacked structure defines a stepped region located between two adjacent columns of word lines, and etches multiple initial active layers, including:

[0025] Etching removes a portion of the structure of the initial active layer, a portion of the isolation material layer, and a portion of the first isolation layer located in the stepped region, forming a stepped groove;

[0026] In the third direction, the stepped groove includes a plurality of sub-grooves arranged sequentially, the width of the plurality of sub-grooves increasing in a stepped manner. In the first direction, the initial active layer, the isolation material layer and the first isolation layer that are etched and retained form a stepped structure arranged opposite to each other on both sides of the stepped groove. Each stepped structure includes multiple stepped layers arranged sequentially along the third direction. Adjacent stepped layers have a length difference in the first direction. Each stepped layer includes a portion of the structure of the initial active layer arranged along the second direction, so that the initial active layers intersecting the same word line have a length difference in the first direction.

[0027] The method for fabricating the semiconductor structure further includes:

[0028] A second trench is formed by removing a portion of the structure of each of the initial active layers and a portion of the isolation material layer and a portion of the first isolation layer, the second trench extending along the second direction, the trench walls exposing a portion of the structure of each of the initial active layers.

[0029] In the first direction, the stepped structure includes a first region close to the stepped groove and a second region away from the stepped groove, and the letter line is located in the first region;

[0030] Removing a portion of the structure from each of the initial active layers, including:

[0031] Based on the second trench, the initial active layer is etched along the first direction to remove the initial active layer located in the second region. A first opening extending along the first direction is formed at each location where the initial active layer is removed, and the initial active layer located in the first region is retained to form the active layer.

[0032] During the etching of the initial active layer along the first direction based on the second trench, the initial active layer has a high etching selectivity relative to the isolation material layer and the first isolation layer.

[0033] Wherein, a capacitor structure is formed on the side of the active layer away from the active step, including:

[0034] A lower electrode layer is formed, covering the sidewall of the first opening and the trench wall of the second trench;

[0035] A high-k dielectric layer is formed to cover the lower electrode layer;

[0036] An upper electrode layer is formed to cover the high-k dielectric layer and fill the unfilled areas of the first opening and the second trench.

[0037] The formation of the bit line extending along the third direction includes:

[0038] A second isolation layer is formed in the stepped groove;

[0039] A portion of the second isolation layer and a portion of the isolation material layer are removed to form a plurality of bit line grooves, each bit line groove extending along the third direction, each bit line groove and each active step being provided in a one-to-one correspondence, and each bit line groove exposing a portion of the top surface of the active step corresponding to it;

[0040] A bitline blocking layer is formed, which covers the groove wall of the bitline slot and the top surface of the active step exposed by the bitline slot.

[0041] A bit line conductive layer is formed, which covers the bit line blocking layer and fills the unfilled area in the bit line groove;

[0042] The bit line is formed by the bit line blocking layer and the bit line conductive layer located in the same bit line groove.

[0043] The method for fabricating the semiconductor structure further includes:

[0044] Multiple word line contact plugs are formed, and each of the multiple word line contact plugs is connected to a corresponding word line. The word line contact plugs are disposed on the top surface of the word line to which they correspond.

[0045] A second aspect of this disclosure provides a semiconductor structure, the semiconductor structure comprising:

[0046] Substrate;

[0047] Multiple active layers, each of which extends along a first direction, are arrayed above the substrate along a second direction and a third direction, the first direction and the second direction being parallel to the top surface of the substrate, adjacent active layers along the third direction having a length difference, the first ends of the multiple active layers forming multiple active steps, and the second ends of the multiple active layers being aligned.

[0048] Multiple word lines, each word line extending along the third direction, each word line intersecting with the active layers arranged along the third direction and covering a portion of the sidewalls of the active layers arranged along the third direction;

[0049] A capacitor structure is provided in the first direction on the side of the active layer away from the active step, and the capacitor structure is in contact with each of the active layers.

[0050] Multiple bit lines, each bit line extending along the third direction, and each bit line correspondingly disposed on each active step.

[0051] The capacitor structure includes multiple horizontal portions that extend along the first direction, and each horizontal portion is connected to the second end of the active layer.

[0052] The word lines are arranged in multiple columns along the second direction, and the active steps and bit lines are located between two adjacent columns of word lines.

[0053] The semiconductor structure further includes:

[0054] Multiple word line contact plugs are provided, and each of the multiple word line contact plugs is connected to a corresponding word line. The word line contact plugs are disposed on the top surface of the word line to which they correspond.

[0055] The semiconductor structure fabrication method and semiconductor structure disclosed herein allow for the control of the number of memory stacking layers in the formed semiconductor structure by adjusting the number of stacking layers of the stacking structure, thereby enabling the semiconductor structure to have continuously increasing storage density. This overcomes the problem that the storage density of semiconductor chips is difficult to continue to increase due to the miniaturization of their size, and provides a new direction for the development of semiconductor chips.

[0056] After reading and understanding the accompanying diagrams and detailed descriptions, the other aspects can be understood. Attached Figure Description

[0057] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the present disclosure and, together with the description, serve to explain the principles of these embodiments. In these drawings, similar reference numerals are used to denote similar elements. The drawings described below are some embodiments of the present disclosure, but not all embodiments. Other drawings will be readily available to those skilled in the art based on these drawings without inventive effort.

[0058] Figure 1 This is a flowchart illustrating a method for fabricating a semiconductor structure according to an exemplary embodiment.

[0059] Figure 2 This is a schematic diagram illustrating the formation of a stacked structure on a substrate according to an exemplary embodiment.

[0060] Figure 3 yes Figure 2 A cross-sectional view of section AA.

[0061] Figure 4 This is a schematic diagram illustrating the formation of a first trench according to an exemplary embodiment.

[0062] Figure 5 yes Figure 4 A cross-sectional view of section AA.

[0063] Figure 6 This is a schematic diagram illustrating the formation of a first isolation layer according to an exemplary embodiment.

[0064] Figure 7 yes Figure 6 A cross-sectional view of section AA.

[0065] Figure 8 yes Figure 6 A cross-sectional view of section BB.

[0066] Figure 9 This is a schematic diagram illustrating the formation of character line slots according to an exemplary embodiment.

[0067] Figure 10 yes Figure 9 A cross-sectional view of section AA.

[0068] Figure 11 yes Figure 9 A cross-sectional view of section BB.

[0069] Figure 12 This is a cross-sectional view of the AA section forming the gate oxide layer according to an exemplary embodiment.

[0070] Figure 13 This is a cross-sectional view of a BB section forming a gate oxide layer, according to an exemplary embodiment.

[0071] Figure 14 This is a cross-sectional view of the AA section forming the gate conductive layer according to an exemplary embodiment.

[0072] Figure 15 This is a cross-sectional view of the BB section forming the gate conductivity, according to an exemplary embodiment.

[0073] Figure 16 This is a schematic diagram illustrating the formation of word lines according to an exemplary embodiment.

[0074] Figure 17 This is a schematic diagram illustrating the formation of stepped grooves according to an exemplary embodiment.

[0075] Figure 18 yes Figure 17 A cross-sectional view of section BB.

[0076] Figure 19 This is a schematic diagram illustrating the formation of a second isolation layer according to an exemplary embodiment.

[0077] Figure 20This is a schematic diagram illustrating the formation of a second trench according to an exemplary embodiment.

[0078] Figure 21 yes Figure 20 A cross-sectional view of the COD section.

[0079] Figure 22 yes Figure 21 A cross-sectional view of the EE section.

[0080] Figure 23 This is a cross-sectional view of an EE forming a capacitor structure, according to an exemplary embodiment.

[0081] Figure 24 This is a cross-sectional view of the COD section forming the first opening, according to an exemplary embodiment.

[0082] Figure 25 yes Figure 24 A cross-sectional view of the EE section.

[0083] Figure 26 This is a cross-sectional view of the EE section forming the lower electrode layer according to an exemplary embodiment.

[0084] Figure 27 This is a cross-sectional view of an EE section forming a high-K dielectric layer, according to an exemplary embodiment.

[0085] Figure 28 This is a cross-sectional view of the EE section forming the upper electrode layer according to an exemplary embodiment.

[0086] Figure 29 This is a cross-sectional view of a COD section forming a capacitor structure, according to an exemplary embodiment.

[0087] Figure 30 This is a cross-sectional view of a COD section showing the formation of word line contact holes and bit line grooves according to an exemplary embodiment.

[0088] Figure 31 yes Figure 30 A cross-sectional view of the EE section.

[0089] Figure 32 This is a cross-sectional view of the COD section forming the word line contact plug and bit line according to an exemplary embodiment.

[0090] Figure 33 yes Figure 32 A cross-sectional view of the EE section.

[0091] Figure 34 yes Figure 33 A magnified view of a portion of region A in the middle.

[0092] Figure 35 yes Figure 33 A magnified view of a portion of region B in the middle.

[0093] Figure 36 yes Figure 33 A magnified view of a portion of region C.

[0094] Figure label:

[0095] 100, Substrate; 110, Bottom Support Layer; 200, Stacked Structure; 201, Step Region; 210, Active Material Layer; 211, Initial Active Layer; 212, Active Step; 220, Isolation Material Layer; 230, Active Layer; 240, First Isolation Layer; 270, Second Isolation Layer; 280, Third Isolation Layer; 310, First Trench; 320, Stepped Trench; 321, First Sub-Trench; 322, Second sub-trench; 32N, Nth sub-trench; 330, Second trench; 340, First opening; 500, Word line; 501, Word line slot; 510, Gate oxide layer; 520, Gate conductive layer; 600, Stepped structure; 601, First region; 602, Second region; 610, Stepped layer; 700, Capacitor structure; 710, Lower electrode layer; 720, High-K dielectric layer; 730, Upper electrode layer; 740, Horizontal portion; 800, Bit line; 801, Bit line slot; 810, Bit line blocking layer; 820, Bit line conductive layer; 900, Word line contact plug; 901, Word line contact hole; 910, First blocking layer; 920, Contact portion;

[0096] D1, First Direction; D2, Second Direction; D3, Third Direction. Detailed Implementation

[0097] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions in the disclosed embodiments will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the embodiments of this disclosure without creative effort are within the scope of protection of this disclosure. It should be noted that, unless otherwise specified, the embodiments and features in the embodiments of this disclosure can be arbitrarily combined with each other.

[0098] Currently, Dynamic Random Access Memory (DRAM) chips are typically planar in structure. The size of planar DRAM has been reduced to its limit, making it difficult to continue miniaturizing and maintaining the effectiveness of Moore's Law. As a result, DRAM is beginning to evolve from planar to three-dimensional structures.

[0099] The exemplary embodiments disclosed herein provide a method for fabricating a semiconductor structure and a semiconductor structure. The number of stacked layers of memory in the formed semiconductor structure can be controlled by adjusting the number of stacked layers of the stacked structure in the fabrication method, so that the semiconductor structure has a continuously increasing storage density. This overcomes the problem that the storage density of semiconductor chips is difficult to continue to increase due to the miniaturization of the chip size, and provides a new direction for the development of semiconductor chips.

[0100] This disclosure provides a method for fabricating a semiconductor structure in exemplary embodiments, such as... Figure 1 As shown, Figure 1 A flowchart illustrating a method for fabricating a semiconductor structure according to an exemplary embodiment of the present disclosure is shown. Figures 2-36 The diagram below illustrates the various stages of semiconductor structure fabrication. Figures 2-36 The methods for fabricating semiconductor structures are introduced.

[0101] This embodiment does not limit the semiconductor structure. The following description will take dynamic random access memory (DRAM) as an example, but this embodiment is not limited to this. Other semiconductor structures are also possible in this embodiment.

[0102] like Figure 1 As shown, an exemplary embodiment of this disclosure provides a method for fabricating a semiconductor structure, comprising the following steps:

[0103] Step S110: Provide a substrate.

[0104] Reference Figure 2 As shown, substrate 100 can be a semiconductor substrate, which may include a silicon substrate, a germanium (Ge) substrate, a silicon germanide (SiGe) substrate, an SOI (Silicon-on-Insulator) substrate, or a GOI (Germanium-on-Insulator) substrate, etc. The semiconductor substrate may be doped with ions; for example, it can be a P-type doped substrate or an N-type doped substrate. In this embodiment, substrate 100 is a silicon substrate.

[0105] Step S120: Form multiple initial active layers, each initial active layer extending along a first direction, and the multiple initial active layers arrayed above the substrate along a second direction and a third direction, the first direction and the second direction being parallel to the top surface of the substrate, and the third direction being perpendicular to the top surface of the substrate.

[0106] In this embodiment, the following implementation method can be adopted:

[0107] First, a stacked structure 200 is formed, which includes an active material layer 210 and an insulating material layer 220 that are alternately stacked along the third direction D3.

[0108] like Figure 2 , Figure 3 As shown, the active material layer 210 can be deposited using any of the following deposition processes: Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD), Atomic Layer Deposition (ALD), or sputtering. The active material layer 210 covers the top surface of the substrate 100. The material of the active material layer 210 can include semiconductor materials, such as silicon (Si), germanium (Ge), or silicon-germanium (GeSi), or silicon carbide (SiC); the semiconductor material can also be silicon-on-insulator (SOI), germanium-on-insulator (GOI); or the material of the active material layer 210 can be other materials, such as gallium arsenide or other III-V group compounds. In this embodiment, the material of the active material layer 210 includes monocrystalline silicon or polycrystalline silicon.

[0109] like Figure 2 , Figure 3 As shown, an isolation material layer 220 is then deposited using any of the above deposition processes. The isolation material layer 220 covers the top surface of the active material layer 210. The material of the isolation material layer 220 may include nitrides, for example, silicon nitride.

[0110] The steps of forming the active material layer 210 and the insulating material layer 220 are repeated sequentially to form a stacked structure 200 on the substrate 100. For example... Figure 2 , Figure 3 As shown, the active material layer 210 and the insulating material layer 220 are alternately stacked on the third direction D3. The active material layer 210 and the insulating material layer 220 can be alternately stacked in 2 to 1024 or more layers. For example, the active material layer 210 and the insulating material layer 220 can be alternately stacked in 48, 64, 128, 256, or 512 layers, etc. In this embodiment, on the third direction D3, the top and bottom structures of the stacked structure 200 are both insulating material layers 220.

[0111] like Figure 4 , Figure 5 As shown, refer to Figure 2 , Figure 3 The stacked structure 200 is etched to form multiple first trenches 310. The first trenches 310 extend along the first direction D1. The multiple first trenches 310 divide each active material layer 210 into multiple initial active layers 211 spaced apart on the second direction D2.

[0112] For example, a first mask layer (not shown in the figure) can be formed on the top surface of the stacked structure 200. The stacked structure 200 is then etched according to the first mask layer to form multiple first trenches 310. Each first trench 310 extends along a first direction D1, and the first trench 310 extends along a third direction D3 and penetrates each active material layer 210. Figure 4 , Figure 5 As shown, refer to Figure 2 , Figure 3 The portion of each active material layer 210 that is retained is divided into multiple initial active layers 211 spaced apart in the second direction D2. For example... Figure 4 , Figure 5 As shown, the initial active layers 211 are arrayed along the second direction D2 and the third direction D3. Two adjacent initial active layers 211 in the second direction D2 are separated by a first trench 310, and two adjacent initial active layers 211 in the third direction D3 are separated by a retained insulating material layer 220. In this embodiment, the first trench 310 extends in the third direction D3 and exposes the top surface of the bottommost insulating material layer 220 of the stacked structure 200. In other embodiments, the first trench 310 may penetrate the stacked structure 200 in the third direction D3.

[0113] like Figure 2 , Figure 3 As shown, in this embodiment, before forming the stacked structure 200, the following step is further included: forming a bottom support layer 110 using any of the above-described deposition processes, wherein the bottom support layer 110 is disposed between the substrate 100 and the stacked structure 200. The material of the stacked structure 200 includes an insulating material, and the stacked structure 200 is electrically isolated from the substrate 100 through the bottom support layer 110. For example, the material of the bottom support layer 110 may include silicon nitride.

[0114] Reference Figure 2 In this embodiment, the stacked structure 200 defines a step area 201, and adjacent step areas 201 are spaced apart in the first direction D1.

[0115] Step S130: Form multiple word lines, each word line extending along a third direction, each word line intersecting with the initial active layer arranged along the third direction, and covering part of the sidewall of the initial active layer arranged along the third direction.

[0116] Before forming the character line 500, such as Figure 6 , Figure 7 , Figure 8 As shown, refer to Figure 4 , Figure 5 An isolation material is deposited using any of the above deposition processes, and the isolation material fills the first trench 310 to form a first isolation layer 240. In this embodiment, the material of the first isolation layer 240 includes silicon nitride.

[0117] Then, as Figure 9 , Figure 10 , Figure 11 As shown, refer to Figure 6 , Figure 7 , Figure 8 A second mask layer (not shown) is formed on the top surface of the first isolation layer 240 and the isolation material layer 220. A portion of the first isolation layer 240 and the isolation material layer 220 are etched away according to the second mask layer, forming multiple word slots 501. These word slots 501 are arranged in multiple columns along the second direction D2. Each word slot 501 extends along the third direction D3, exposing a portion of the sidewalls of multiple initial active layers 211 arranged along the third direction D3. In this embodiment, the etching process used in the etching of the first isolation layer 240 and the isolation material layer 220 has a high etching selectivity for the initial active layers 211, avoiding damage to the initial active layers 211 during the etching process, ensuring the structural integrity of the initial active layers 211, and improving the yield of the formed semiconductor structure.

[0118] like Figure 12 , Figure 13 As shown, refer to Figure 10 , Figure 11 Then, a gate oxide layer 510 is deposited using an atomic layer deposition process. The gate oxide layer 510 covers a portion of the sidewalls of the initial active layer 211 exposed by the word slot 501 and the slot wall of the word slot 501. The material of the gate oxide layer 510 includes silicon oxide or silicon oxynitride.

[0119] like Figure 14 , Figure 15 , Figure 16 As shown, refer to Figure 12 , Figure 13 Next, a gate conductive layer 520 can be deposited using any of the following deposition processes: chemical vapor deposition, physical vapor deposition, atomic layer deposition, or sputtering. The gate conductive layer 520 covers the gate oxide layer 510 and fills the unfilled areas of the word line slot 501. The material of the gate conductive layer 520 may include at least one of titanium or its alloys, tantalum or its alloys, or tungsten or its alloys. The gate oxide layer 510 and the gate conductive layer 520, located in the same word line slot 501, together form the word line 500.

[0120] Reference Figure 14 , Figure 16 As shown, each character line slot 501 contains a corresponding character line 500, and multiple character lines 500 are arranged in multiple columns along the second direction D2. (Refer to...) Figure 15 , Figure 16As shown, in the first direction D1, a column of character lines 500 arranged along the second direction D2 is provided on each side of the stepped area 201. That is, the stepped area 201 is located between two adjacent columns of character lines 500.

[0121] Step S140: Etch multiple initial active layers, the initial active layers intersecting the same word line have a length difference in the first direction, and an active step is formed at the first end of the initial active layer.

[0122] In this embodiment, multiple initial active layers 211 are etched, and an active step 212 is formed at the first end of the initial active layer 211, including:

[0123] like Figure 17 , Figure 18 As shown, refer to Figure 15 , Figure 16 The step region 201 is etched, removing a portion of the initial active layer 211, a portion of the isolation material layer 220, and a portion of the first isolation layer 240 located in the step region 201, forming a stepped groove 320 in the step region 201. On the third direction D3, the stepped groove 320 includes a plurality of sub-grooves arranged sequentially, for example, such as... Figure 18 As shown, the stepped trench includes a first sub-trench 321, a second sub-trench 322, ..., an Nth sub-trench 32N arranged sequentially along the third direction D3. Furthermore, the trench widths of the multiple sub-trenches increase in a stepped manner along the direction away from the substrate 100.

[0124] like Figure 17 , Figure 18 As shown, the stepped groove 320 divides the retained initial active layer 211, isolation material layer 220, and first isolation layer 240 into independently set stepped structures 600. In the first direction D1, two stepped structures 600 are arranged opposite each other on both sides of the stepped groove 320, as shown... Figure 18 As shown, the stepped structure 600 extends into the stepped area 201.

[0125] like Figure 17 , Figure 18As shown, each stepped structure 600 includes multiple stepped layers 610 arranged sequentially along a third direction D3. Each stepped layer 610 includes a portion of the structure of an initial active layer 211 arranged along a second direction D2. Each stepped layer 610 also includes a portion of the structure of an isolation material layer 220 and a portion of the structure of a first isolation layer 240. In the third direction D3, adjacent stepped layers 610 have a length difference in the first direction D1. Therefore, the initial active layers 211 arranged in the third direction D3 also have a length difference; that is, the initial active layers 211 intersecting the same word line 500 have a length difference in the first direction D1. The first end of the initial active layer 211 forms an active step 212, and the first end of the initial active layer 211 is the end of the initial active layer 211 closest to the stepped groove 320.

[0126] Step S150: Remove part of the structure of each initial active layer, and the remaining part of the structure of each initial active layer forms an active layer, which retains active steps.

[0127] like Figure 18 As shown, in the first direction D1, the stepped structure 600 includes a first region 601 near the stepped groove 320 and a second region 602 away from the stepped groove 320, with the word line 500 located in the first region 601.

[0128] In this embodiment, removing a portion of the structure of each initial active layer 211 can be achieved using the following implementation method:

[0129] like Figure 19 As shown, refer to Figure 17 The second isolation layer 270 is formed by deposition through any of the above deposition processes. The second isolation layer 270 fills the stepped groove 320 and covers the top surface of the first isolation layer 240 and the top surface of the retained isolation material layer 220.

[0130] like Figure 20 , Figure 21 , Figure 22 As shown, refer to Figure 18 , Figure 19 A third mask layer (not shown in the figure) can be formed, which covers the top surface of the second isolation layer 270. The second region 602 of the stepped structure 600 is etched along the second direction D2 according to the third mask layer, removing part of the structure of each initial active layer 211, part of the structure of the isolation material layer 220, and part of the first isolation layer 240, forming a second trench 330 in the second region. The second trench 330 extends along the second direction D2.

[0131] In some examples, refer to Figure 23After the second trench 330 is formed, the portion of each initial active layer 211 that is retained forms an active layer 230, and the trench wall of the second trench 330 exposes a portion of the structure of each active layer 230.

[0132] In other examples, after removing a portion of the structure of each initial active layer 211 to form the second trench 330, the following steps were also performed:

[0133] like Figure 24 , Figure 25 As shown, refer to Figure 21 , Figure 22 Based on the second trench 330, the initial active layer 211 is etched along the first direction D1 to remove the initial active layer 211 located in the second region 602. At each location where the initial active layer 211 is removed, a first opening 340 extending along the first direction D1 is formed. The first opening 340 and the second trench 330 are connected. The initial active layer 211 located in the first region 601 is retained to form the active layer 230. In the etching process that forms the first opening 340, the etching process has a high etching selectivity for the isolation material layer 220 and the first isolation layer 240.

[0134] Step S160: A capacitor structure is formed on the side of the active layer away from the active step, and the capacitor structure is in contact with each active layer.

[0135] In some examples, such as Figure 23 As shown, refer to Figure 22 A capacitor structure 700 is formed in the second trench 330.

[0136] First, a lower electrode layer 710 can be deposited using any of the following deposition processes: chemical vapor deposition, physical vapor deposition, atomic layer deposition, or sputtering. The lower electrode layer 710 covers the trench wall of the second trench 330 and the active layer 230 exposed on the trench wall of the second trench 330. The material of the lower electrode layer 710 includes compounds formed from one or two of metal nitrides and metal silicides, such as titanium nitride (Ti2N2), titanium silicide (TiSi2), nickel silicide (Ni2Si), and titanium silicon nitride (TiSixNy).

[0137] like Figure 23 As shown, a high-k dielectric layer 720 is then deposited using any of the above-described deposition processes, covering the lower electrode layer 710. The material of the high-k dielectric layer 720 may include metal silicates or metal oxides. For example, the material of the high-k dielectric layer 720 may include at least one of tantalum oxide (Ta2O5), titanium oxide (TiO2), zirconium oxide (ZrO2), aluminum oxide (Al2O3), hafnium silicon oxide (HfSiO2), or hafnium oxide (HfO2).

[0138] like Figure 23 As shown, refer to Figure 22 Next, an upper electrode layer 730 is deposited using any of the above-described deposition processes. The upper electrode layer 730 covers the high-K dielectric layer 720 and fills the unfilled areas in the second trench 330. The material of the upper electrode layer 730 may include at least one of titanium or its alloys, tantalum or its alloys, and tungsten or its alloys.

[0139] like Figure 23 As shown, refer to Figure 22 The lower electrode layer 710, the high-K dielectric layer 720 and the upper electrode layer 730 together form a capacitor structure 700, which is disposed in the second trench 330 away from the active step 212.

[0140] This example involves fewer process steps to form the capacitor structure 700, resulting in greater process controllability and improved semiconductor structure yield.

[0141] In other examples, such as Figure 26 , Figure 27 , Figure 28 , Figure 29 As shown, refer to 24. Figure 25 The process of forming a capacitor structure 700 in the second trench 330 and the first opening 340 includes the following steps:

[0142] First, such as Figure 26 As shown, a lower electrode layer 710 is formed by deposition using any of the above deposition processes. The lower electrode layer 710 covers the sidewall of the first opening 340 and the trench wall of the second trench 330.

[0143] Then, as Figure 27 As shown, a high-K dielectric layer 720 is formed by depositing any of the above deposition processes, and the high-K dielectric layer 720 covers the lower electrode layer 710.

[0144] Next, as Figure 28 As shown, refer to Figure 27 An upper electrode layer 730 is formed by deposition using any of the above deposition processes. The upper electrode layer 730 covers the high-K dielectric layer 720 and fills the unfilled areas of the first opening 340 and the unfilled areas of the second trench 330.

[0145] like Figure 28 , Figure 29 , Figure 34 As shown, refer to 24. Figure 25The lower electrode layer 710, the high-K dielectric layer 720, and the upper electrode layer 730 together form a capacitor structure 700. The lower electrode layer 710, the high-K dielectric layer 720, and the upper electrode layer 730 located in the first opening 340 constitute the horizontal portion 740 of the capacitor structure 700. Each horizontal portion 740 is in contact with each active layer 230.

[0146] The capacitor structure 700 formed in this example includes a horizontal portion 740, which increases the proportion of the capacitor structure 700 in the semiconductor structure and improves the storage capacity of the semiconductor structure.

[0147] In this embodiment, after forming the capacitor structure 700, refer to Figure 30 As shown, a third isolation layer 280 can be deposited using any of the above deposition processes. The third isolation layer 280 covers the top surface of the capacitor structure 700 to prevent the material of the capacitor structure 700 from being exposed to the process environment and contaminated. The material of the third isolation layer 280 may include silicon oxide or silicon oxynitride.

[0148] Step S170: Form bit lines extending along a third direction, with each bit line corresponding to each active step.

[0149] First, refer to Figure 30 , Figure 31 As shown, a fourth mask layer (not shown in the figure) is formed, which exposes part of the top surface of the third isolation layer 280 located in the step region 201.

[0150] Then, refer to Figure 30 , Figure 31 As shown, according to the etching step region 201 of the fourth mask layer, a portion of the third isolation layer 280, a portion of the second isolation layer 270, and a portion of the isolation material layer 220 are removed, forming a plurality of bit line grooves 801 in the step region 201. Each bit line groove 801 extends along the third direction D3, as shown in the figure. Figure 36 Each bit line slot 801 and each active step 212 are configured in a one-to-one correspondence, and each bit line slot 801 exposes part of the top surface of its corresponding active step 212.

[0151] Next, as Figure 32 , Figure 33 As shown, any one of the following deposition processes can be selected: chemical vapor deposition, physical vapor deposition, atomic layer deposition, or sputtering, to deposit the bit line barrier layer 810, as shown in the figure. Figure 36 The bit line barrier layer 810 covers the trench wall of the bit line trench 801 and the top surface of the active step 212 exposed by the bit line trench 801. The material of the bit line barrier layer 810 may include at least one of silicon oxide or silicon oxynitride.

[0152] Next, as Figure 32 , Figure 33As shown, refer to Figure 30 , Figure 31 The bit line conductive layer 820 is deposited using any of the above deposition processes. The bit line conductive layer 820 covers the bit line blocking layer 810 and fills the unfilled areas in the bit line groove 801. The material of the bit line conductive layer 820 may include at least one of titanium or its alloy, tantalum or its alloy, and tungsten or its alloy.

[0153] like Figure 32 , Figure 33 As shown, the bit line blocking layer 810 and the bit line conductive layer 820, located in the same bit line groove 801, form the bit line 800. (Refer to...) Figure 36 The bit line barrier layer 810 is disposed between the bit line conductive layer 820 and the active step 212 to prevent the material of the bit line conductive layer 820 from diffusing into the active layer 230 and avoid contamination of other devices in the semiconductor structure.

[0154] The fabrication method of this embodiment forms a memory stacked vertically on a substrate. The semiconductor structure memory has an increaseable number of stacked layers, which can form a larger number of memories on the same area of ​​deposition, thus meeting the development needs of the semiconductor field for high-capacity memories.

[0155] The manufacturing method of this embodiment rationally plans the process steps, first forming word lines, then forming capacitor structures and bit lines. The process steps are few and simple, which can improve the yield of semiconductor structures.

[0156] According to an exemplary embodiment, this embodiment is a further description of the above embodiments. The method for fabricating the semiconductor structure in this embodiment includes all the steps in the above embodiments. In addition, the method for fabricating the semiconductor structure in this embodiment further includes the following steps:

[0157] Reference Figure 32 , Figure 33 , Figure 35 This forms multiple word line contact plugs 900, each of which is connected to a corresponding word line 500. The word line contact plugs 900 are disposed on the top surface of their respective word lines 500.

[0158] In this embodiment, the word line contact plug 900 and the bit line 800 are formed in the same process.

[0159] First, such as Figure 30 , Figure 31As shown, in the process of forming the bit line groove 801, a portion of the third isolation layer 280, a portion of the second isolation layer 270, and a portion of the isolation material layer 220 located above the word line 500 are etched away, forming a plurality of word line contact holes 901 (not shown in the figure) on the word line 500. The plurality of word line contact holes 901 correspond one-to-one with the plurality of word lines 500, and each word line contact hole 901 exposes the top surface of the corresponding word line 500.

[0160] Then, refer to Figure 32 , Figure 33 , Figure 35 In the process of forming the bit line barrier layer 810, a barrier material is simultaneously deposited to cover the hole wall of the word line contact hole 901, forming the first barrier layer 910.

[0161] Then, refer to Figure 33 , Figure 35 During the process of forming the bit line conductive layer 820, conductive material is simultaneously deposited to fill the unfilled areas of the word line contact hole 901, forming a contact portion 920. The first barrier layer 910 and the contact portion 920, located in the same word line contact hole 901, together form a word line contact plug 900. The word line contact plug 900 is used to lead out the word line 500 and connect it to other electronic devices or circuits.

[0162] According to an exemplary embodiment, this embodiment provides a semiconductor structure, such as... Figure 32 , Figure 33 , Figure 34 , Figure 35 , Figure 36 As shown, the semiconductor structure includes a substrate 100, multiple active layers 230, multiple word lines 500, a capacitor structure 700, and multiple bit lines 800. Each active layer 230 extends along a first direction D1, and the multiple active layers 230 are arrayed above the substrate 100 along a second direction D2 and a third direction D3. The first direction D1 and the second direction D2 are parallel to the top surface of the substrate 100. Adjacent active layers 230 in the third direction D3 have a length difference. Figure 18 The first ends of the multiple active layers 230 form multiple active steps 212, and the second ends of the multiple active layers 230 are aligned. In this embodiment, the first end of the active layer 230 is the end where the active step 212 is formed, and in the first direction D1, the second end of the active layer 230 is the end away from the active step 212.

[0163] like Figure 32 , Figure 33 As shown, refer to Figure 14 , Figure 15Each word line 500 extends along a third direction D3, intersecting with and covering a portion of the sidewalls of the active layers 230 arranged along the third direction D3. In the first direction D1, a capacitor structure 700 is disposed on the side of the active layer 230 away from the active step 212, and the capacitor structure 700 is in contact with each active layer 230. Each bit line extends along the third direction D3, and each bit line 800 is correspondingly disposed on each active step 212.

[0164] In some embodiments, such as Figure 32 , Figure 33 , Figure 34 As shown, the capacitor structure 700 includes multiple horizontal portions 740 extending along a first direction D1, and each horizontal portion 740 is connected to the second end of the active layer 230. This increases the proportion of the capacitor structure 700 in the semiconductor structure, fully utilizes the application space of the semiconductor structure, and increases the storage capacity of the semiconductor structure.

[0165] In some embodiments, such as Figure 32 As shown, refer to Figure 14 , Figure 18 Multiple word lines 500 are arranged in multiple columns along the second direction D2, and multiple active steps 212 and multiple bit lines 800 are located between two adjacent columns of word lines 500.

[0166] In some embodiments, such as Figure 32 As shown, Figure 33 , Figure 35 As shown, the semiconductor structure also includes multiple word line contact plugs 900, which are connected one-to-one with multiple word lines 500, and the word line contact plugs 900 are disposed on the top surface of their corresponding word lines 500.

[0167] The semiconductor structure provided in this embodiment has an increasing storage density in the direction perpendicular to the top surface of the substrate, overcoming the problem that the storage density of semiconductor chips is difficult to increase due to size reduction, and providing a new direction for the development of semiconductor chips.

[0168] The various embodiments or implementation methods described in this specification are presented in a progressive manner. Each embodiment focuses on the differences from other embodiments, and the same or similar parts between the embodiments can be referred to each other.

[0169] In the description of this specification, references to the terms "embodiment," "exemplary embodiment," "some implementation," "illustrated implementation," "example," etc., refer to specific features, structures, materials, or characteristics described in connection with an implementation or example that are included in at least one implementation or example of this disclosure.

[0170] In this specification, the illustrative expressions of the terms used do not necessarily refer to the same implementation or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more implementations or examples.

[0171] In the description of this disclosure, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this disclosure and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this disclosure.

[0172] It is understood that the terms "first," "second," etc., as used in this disclosure may be used to describe various structures, but these structures are not limited by these terms. These terms are only used to distinguish one structure from another.

[0173] In one or more accompanying drawings, the same elements are represented by similar reference numerals. For clarity, many parts in the drawings are not drawn to scale. Furthermore, certain well-known parts may not be shown. For simplicity, a structure obtained after several steps may be depicted in a single drawing. Many specific details of this disclosure, such as the structure, materials, dimensions, processing methods, and techniques of the devices, are described below to provide a clearer understanding of the disclosure. However, as those skilled in the art will understand, this disclosure may be implemented without adhering to these specific details.

[0174] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this disclosure, and are not intended to limit them. Although this disclosure has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this disclosure.

Claims

1. A method for fabricating a semiconductor structure, characterized in that, The method for fabricating the semiconductor structure includes: Provide substrate; Multiple initial active layers are formed, each of which extends along a first direction. The multiple initial active layers are arrayed above the substrate along a second direction and a third direction. The first direction and the second direction are parallel to the top surface of the substrate, and the third direction is perpendicular to the top surface of the substrate. Multiple word lines are formed, each word line extending along the third direction, each word line intersecting with the initial active layer arranged along the third direction, and covering a portion of the sidewall of the initial active layer arranged along the third direction; Multiple initial active layers are etched, and the initial active layers intersecting the same word line have a length difference in the first direction, forming an active step at the first end of the initial active layer; Remove a portion of the structure of each of the initial active layers, and the remaining portion of the structure of each of the initial active layers forms an active layer, wherein the active layer retains the active step; A capacitor structure is formed on the side of the active layer away from the active step, and the capacitor structure is in contact with each of the active layers; Bit lines are formed extending along the third direction, each bit line corresponding to each active step; wherein, Multiple initial active layers are formed, including: A stacked structure is formed, the stacked structure comprising active material layers and insulating material layers alternately stacked along the third direction; The stacked structure is etched to form multiple first trenches. The first trenches extend along the first direction, and the multiple first trenches divide each layer of the active material into multiple initial active layers that are spaced apart in the second direction. A first isolation layer is formed in the first trench; A portion of the first isolation layer and a portion of the isolation material layer are removed to form a plurality of word line grooves, and the word line is formed in each of the word line grooves; The stacked structure defines a stepped region located between two adjacent columns of word lines, and etches multiple initial active layers, including: Etching removes a portion of the structure of the initial active layer, a portion of the isolation material layer, and a portion of the first isolation layer located in the stepped region, forming a stepped groove; In the third direction, the stepped groove includes a plurality of sub-grooves arranged sequentially, the width of the plurality of sub-grooves increasing in a stepped manner. In the first direction, the initial active layer, the isolation material layer and the first isolation layer that are etched and retained form a stepped structure arranged opposite to each other on both sides of the stepped groove. Each stepped structure includes multiple stepped layers arranged sequentially along the third direction. Adjacent stepped layers have a length difference in the first direction. Each stepped layer includes a portion of the structure of the initial active layer arranged along the second direction, so that the initial active layers intersecting the same word line have a length difference in the first direction.

2. The method for fabricating a semiconductor structure according to claim 1, characterized in that, Each of the word slots extends along the third direction, exposing a portion of the sidewall of the initial active layer arranged along the third direction, and the plurality of word slots are arranged in multiple columns along the second direction.

3. The method for fabricating a semiconductor structure according to claim 1, characterized in that, Forming the character line in each of the character line slots includes: A gate oxide layer is formed, which covers a portion of the sidewall of the initial active layer exposed by the word slot and the slot wall of the word slot; A gate conductive layer is formed, which covers the gate oxide layer and fills the unfilled area of ​​the word slot; The gate oxide layer and the gate conductive layer located in the same word line slot together form the word line.

4. The method for fabricating a semiconductor structure according to claim 1, characterized in that, The method for fabricating the semiconductor structure further includes: A second trench is formed by removing a portion of the structure of each of the initial active layers and a portion of the isolation material layer and a portion of the first isolation layer, the second trench extending along the second direction, the trench walls exposing a portion of the structure of each of the initial active layers.

5. The method for fabricating a semiconductor structure according to claim 4, characterized in that, In the first direction, the stepped structure includes a first region close to the stepped groove and a second region away from the stepped groove, with the letter line located in the first region; Removing a portion of the structure from each of the initial active layers, including: Based on the second trench, the initial active layer is etched along the first direction to remove the initial active layer located in the second region. A first opening extending along the first direction is formed at each location where the initial active layer is removed, and the initial active layer located in the first region is retained to form the active layer.

6. The method for fabricating a semiconductor structure according to claim 5, characterized in that, During the etching of the initial active layer along the first direction based on the second trench, the initial active layer has a high etching selectivity relative to the isolation material layer and the first isolation layer.

7. The method for fabricating a semiconductor structure according to claim 5, characterized in that, A capacitor structure is formed on the side of the active layer away from the active step, comprising: A lower electrode layer is formed, covering the sidewall of the first opening and the trench wall of the second trench; A high-k dielectric layer is formed to cover the lower electrode layer; An upper electrode layer is formed to cover the high-k dielectric layer and fill the unfilled areas of the first opening and the second trench.

8. The method for fabricating a semiconductor structure according to claim 1, characterized in that, Forming a bit line extending along the third direction includes: A second isolation layer is formed in the stepped groove; A portion of the second isolation layer and a portion of the isolation material layer are removed to form a plurality of bit line grooves, each bit line groove extending along the third direction, each bit line groove and each active step being provided in a one-to-one correspondence, and each bit line groove exposing a portion of the top surface of the active step corresponding to it; A bitline blocking layer is formed, which covers the groove wall of the bitline slot and the top surface of the active step exposed by the bitline slot. A bit line conductive layer is formed, which covers the bit line blocking layer and fills the unfilled area in the bit line groove; The bit line is formed by the bit line blocking layer and the bit line conductive layer located in the same bit line groove.

9. The method for fabricating a semiconductor structure according to claim 1, characterized in that, The method for fabricating the semiconductor structure further includes: Multiple word line contact plugs are formed, and each of the multiple word line contact plugs is connected to a corresponding word line. The word line contact plugs are disposed on the top surface of the word line to which they correspond.

10. A semiconductor structure, characterized in that, The semiconductor structure includes: Substrate; Multiple active layers, each of which extends along a first direction, are arrayed above the substrate along a second direction and a third direction, the first direction and the second direction being parallel to the top surface of the substrate, adjacent active layers along the third direction having a length difference, the first ends of the multiple active layers forming multiple active steps, and the second ends of the multiple active layers being aligned. Multiple word lines, each word line extending along the third direction, each word line intersecting with the active layers arranged along the third direction and covering a portion of the sidewalls of the active layers arranged along the third direction; A capacitor structure is provided in the first direction on the side of the active layer away from the active step, and the capacitor structure is in contact with each of the active layers. Multiple bit lines, each bit line extending along the third direction, and each bit line correspondingly disposed on each active step; The plurality of word lines are arranged in multiple columns along the second direction, and the plurality of active steps and the plurality of bit lines are located between two adjacent columns of word lines.

11. The semiconductor structure according to claim 10, characterized in that, The capacitor structure includes a plurality of horizontal portions that extend along the first direction, and each horizontal portion is connected to the second end of the active layer.

12. The semiconductor structure according to claim 10, characterized in that, The semiconductor structure also includes: Multiple word line contact plugs are provided, and each of the multiple word line contact plugs is connected to a corresponding word line. The word line contact plugs are disposed on the top surface of the word line to which they correspond.

Images