Horizontal hall device and method of manufacturing

Abstract

A horizontal Hall device and a preparation method. The horizontal Hall device comprises a substrate layer and an upper BOX layer, an epitaxial layer is arranged on the BOX layer, a well layer is arranged on the epitaxial layer, an STI layer is arranged on the well layer, an induced electrode pair and a bias electrode pair are arranged on the STI layer, a grounding electrode is arranged on the epitaxial layer, and a current blocking layer is arranged between adjacent induced electrodes and bias electrodes. A preparation method of the horizontal Hall device comprises the following steps: preparing a substrate with a BOX layer and an epitaxial layer; performing deep trench etching on the epitaxial layer, the bottom of the deep trench directly contacts the BOX layer, the deep trench is filled to form a current blocking layer, photolithography is performed and the upper part of the epitaxial layer is doped to form a well layer, shallow trench etching is performed on the well layer region to form a shallow trench on the well layer, silicon dioxide is deposited to form an STI layer, the induced electrode pair region and the bias electrode pair region are doped to form a heavily doped contact layer, and the epitaxial layer is doped to form a heavily doped contact layer.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit design technology, and in particular to a horizontal Hall device for use in Hall sensors and its fabrication method. Background Technology

[0002] Currently, as a type of magnetic sensing, CMOS Hall sensors are widely used in automotive electronics, medical electronics, and consumer electronics due to their advantages such as process compatibility, low cost, and high integration. Hall sensors mainly consist of Hall devices and corresponding signal conditioning circuits. Specifically, for the detection of three-dimensional magnetic fields, Hall sensors include horizontal Hall devices for detecting magnetic fields perpendicular to the chip surface and vertical Hall devices for detecting magnetic fields parallel to the chip surface. The Hall devices convert magnetic field signals into electrical signals; the signal conversion efficiency and signal quality determine the overall performance of the Hall sensor. Therefore, high-performance Hall devices are crucial for Hall sensors.

[0003] For traditional Hall effect devices, improving performance mainly faces the following challenges. First, some current, after entering the device, flows out along the device edge through the sensing electrode, resulting in a "short-circuit effect." This current flowing at the device edge does not contribute to the Hall voltage signal, leading to a decrease in device sensitivity. The horizontal Hall effect device in patent application CN208297701U, compared to traditional structures, adds a P+ injection layer to the N-well. Although this suppresses the "short-circuit effect" by introducing a PN junction structure, some current still flows along a relatively short current path to the sensing electrode, causing a decrease in sensitivity. Second, the structure of traditional Hall effect devices dictates that their sensitivity is limited by the electrode size. Smaller electrode sizes can improve sensitivity, but this also brings manufacturing challenges and increases initial offset. Therefore, it is difficult to achieve both high sensitivity and low offset due to limitations in electrode size. Third, due to surface parasitic effects caused by defects and impurity particles at the interface, Hall effect devices exhibit 1 / f noise, affecting the signal-to-noise ratio. Furthermore, in CMOS integrated Hall devices, the Hall device and external circuitry are integrated on a single wafer, leading to significant crosstalk between the devices. While junction isolation technology can reduce crosstalk, it also introduces nonlinear resistance, increasing residual offset. Additionally, the larger junction isolation area increases chip cost. An integrated Hall device disclosed in patent application CN102790072A utilizes junction isolation technology, forming an isolation ring around the N-well in a P-type doped region to isolate crosstalk between the substrate and other devices. However, the introduction of the PN junction structure increases nonlinear resistance, resulting in increased residual offset. This also increases the chip area occupied by the Hall device, raising costs. Summary of the Invention

[0004] To address the shortcomings of existing technologies, this invention aims to propose a horizontal Hall effect device and its fabrication method. It utilizes Deep Trench Isolation (DTI) and STI structures to regulate the current path, avoiding short-circuit effects, reducing surface noise, and improving the sensitivity of the Hall effect device. Furthermore, it ensures that the sensitivity of the Hall effect device is not limited by electrode size; by increasing the electrode size to reduce offset, the sensitivity remains constant or even increases. A fully isolated structure completely isolates the sensor from other devices, avoiding crosstalk from other components.

[0005] To achieve the above objectives, the present invention proposes a horizontal Hall effect device, comprising:

[0006] A first conductivity type substrate layer is provided, a BOX layer is provided on the first conductivity type substrate layer, a first conductivity type epitaxial layer is provided on the BOX layer, a second conductivity type well layer is provided on the first conductivity type epitaxial layer, an STI (Shallow Trench Isolation) layer is provided on the second conductivity type well layer, a second conductivity type sensing electrode pair and a second conductivity type bias electrode pair are provided on the STI layer, the second conductivity type sensing electrode pair and the second conductivity type bias electrode pair extend into the second conductivity type well layer, and a ground electrode is connected on the first conductivity type epitaxial layer. The key feature is that a current blocking layer is provided between adjacent second conductivity type sensing electrodes and second conductivity type bias electrodes, and the current blocking layer starts from the STI layer, passes through the second conductivity type well layer and the first conductivity type epitaxial layer, and then touches the BOX layer.

[0007] To achieve the above objectives, the present invention also provides a method for fabricating a horizontal Hall effect device, comprising the following steps:

[0008] A substrate having a BOX layer and an epitaxial layer is prepared; the epitaxial layer is a first conductivity type epitaxial layer, and the substrate is a first conductivity type substrate.

[0009] Deep trench etching is performed on the epitaxial layer of the first conductivity type to form a deep trench located on the BOX layer, with the bottom of the deep trench in direct contact with the BOX layer. A current blocking layer is formed by depositing silicon dioxide to fill the deep trench.

[0010] A doped window exposed by photoresist is formed by photolithography, and a current blocking layer is covered by photoresist. A second conductivity type well layer is formed on top of the first conductivity type epitaxial layer by doping.

[0011] Shallow trench etching is performed on the second conductivity type well layer region, excluding the current blocking layer, the sensing electrode pair region, and the bias electrode pair region, to form shallow trenches on the second conductivity type well layer. An STI layer is then formed by depositing silicon dioxide.

[0012] The sensing electrode pair region and the bias electrode pair region are doped to form a heavily doped second conductivity type contact layer, and the first conductivity type epitaxial layer is doped to form a heavily doped first conductivity type contact layer.

[0013] Compared with the prior art, the present invention has the following advantages:

[0014] (1) This invention employs a current blocking layer, particularly a DTI structure, which improves the device's sensitivity and suppresses the "short-circuit effect." Because current tends to flow along short current paths (i.e., low-resistance directions), in traditional Hall devices, some current flows out along the device edge through the sensing electrode after entering the device, resulting in a "short-circuit effect." This portion of current experiencing the "short-circuit effect" does not generate an effective Hall voltage when subjected to a magnetic field during the Hall device's operation, thus reducing the device's sensitivity to magnetic fields. The Hall device of this invention, through the introduction of a current blocking layer (DTI structure), alters the internal resistance distribution, transforming the original low-resistance current path into a high-resistance path. Current no longer flows along short current paths, suppressing the "short-circuit effect." Furthermore, this portion of current generates a Hall voltage perpendicular to the current flow direction after being subjected to a magnetic field, improving the device's sensitivity and resolving the "short-circuit effect" that restricts the improvement of Hall device sensitivity.

[0015] (2) This invention eliminates the constraint of electrode size on the sensitivity of Hall devices, enabling the increase of electrode size to reduce offset without affecting device sensitivity. For traditional Hall devices, sensitivity is directly proportional to the geometric factor, while the geometric factor is inversely proportional to the electrode size. Therefore, a smaller electrode size can achieve greater sensitivity. However, due to factors such as process precision and process fluctuations, it is more difficult to ensure symmetrical distribution between electrodes as the electrode size decreases. Asymmetry between electrodes will increase the initial offset of the device, thereby affecting the resolution of the Hall sensor. Therefore, traditional structures are limited by adjusting the electrode size, making it difficult to achieve both high sensitivity and low offset. For the horizontal Hall device proposed in this invention, a DTI structure is used to regulate the current path, so that the sensitivity of the Hall device is no longer constrained by the geometric factor in traditional theory, but is adjusted by the length of the DTI structure. This avoids the influence of electrode size on device sensitivity, thus enabling the increase of electrode size to reduce offset while ensuring that device sensitivity is not affected.

[0016] (3) Improved device sensitivity. For horizontal Hall devices, a shallower active region N-well can lead to higher sensitivity. In the horizontal Hall device proposed in this invention, the introduction of a surface-controllable depth STI structure effectively reduces the depth of the active region N-well, thereby improving device sensitivity. Furthermore, the device sensitivity is also significantly improved due to the resolution of the "short-circuit effect."

[0017] (4) Fully Isolated Structure. Unlike the PN junction isolation structure used in traditional Hall devices, the horizontal Hall device proposed in this invention achieves a fully isolated structure through the combination of a DTI structure and a BOX layer. On the one hand, in traditional structures, the junction field effect introduced by the PN junction at the edge of the Hall device leads to a decrease in the symmetry of the Hall device, which in turn leads to an increase in offset. However, the horizontal Hall device proposed in this invention uses a trench isolation structure, which eliminates the junction field effect at the edge of the device, thereby reducing the initial offset of the Hall device. On the other hand, the horizontal Hall device proposed in this invention is completely isolated from other areas, isolating substrate noise and crosstalk from other devices. This allows the Hall device to operate normally after integration with external circuits without being affected by signal crosstalk from other devices, thus improving the operating stability of the Hall device. Attached Figure Description

[0018] The accompanying drawings are provided to further illustrate the invention and are used together with the embodiments of the invention to explain the invention, but do not constitute a limitation thereof:

[0019] Figure 1 This is a three-dimensional structural diagram of a horizontal Hall effect device according to the present invention;

[0020] Figure 2 for Figure 1 A cross-sectional view of a horizontal Hall device A1-A1' according to the present invention;

[0021] Figure 3 for Figure 1 A cross-sectional view of a horizontal Hall device B1-B1' according to the present invention;

[0022] Figure 4 for Figure 1 A schematic diagram of the current density distribution obtained from a top view of the horizontal Hall device with the structure of the present invention and the conventional structure.

[0023] Figure 5 The Hall voltage output curves of the horizontal Hall devices of the present invention and the conventional structure are shown below.

[0024] Figure 6 The Hall voltage output curve of a horizontal Hall device according to the present invention is shown.

[0025] Figure 7 This is a flowchart illustrating the fabrication process of a horizontal Hall effect device according to the present invention.

[0026] In the figure, there is a first conductivity type substrate 1, a BOX layer 2, a first conductivity type epitaxial layer 3, a DTI isolation structure 4, a current blocking layer 5, a second conductivity type well layer 6, an STI layer 7, a heavily doped second conductivity type contact layer 8, a heavily doped first conductivity type contact layer 9, sensing electrode pairs 91 and 92, bias electrode pairs 93 and 94, and a ground electrode 100. Detailed Implementation

[0027] Embodiments of the present invention will now be described in more detail with reference to the accompanying drawings. While some embodiments of the invention are shown in the drawings, it should be understood that the invention can be implemented in various forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided to provide a more thorough and complete understanding of the invention. It should be understood that the accompanying drawings and embodiments are for illustrative purposes only and are not intended to limit the scope of protection of the invention.

[0028] It should be understood that the various steps described in the method embodiments of the present invention may be performed in different orders and / or in parallel. Furthermore, the method embodiments may include additional steps and / or omit the steps shown. The scope of the present invention is not limited in this respect.

[0029] The term "comprising" and its variations as used herein are open-ended inclusions, meaning "including but not limited to". The term "based on" means "at least partially based on". The term "one embodiment" means "at least one embodiment"; the term "another embodiment" means "at least one additional embodiment"; the term "some embodiments" means "at least some embodiments". Definitions of other terms will be given in the description below.

[0030] It should be noted that the terms "a" and "a plurality of" used in this invention are illustrative rather than restrictive. Those skilled in the art should understand that, unless explicitly stated otherwise in the context, they should be understood as "one or more". "A plurality of" should be understood as two or more.

[0031] Example 1

[0032] A horizontal Hall effect device includes: a first conductivity type substrate layer 1, a BOX layer 2 disposed on the first conductivity type substrate layer 1, a first conductivity type epitaxial layer 3 disposed on the BOX layer 2, a second conductivity type well layer 6 disposed on the first conductivity type epitaxial layer 3, an STI layer 7 disposed on the second conductivity type well layer 6, a pair of second conductivity type sensing electrodes 91 and 92 and a pair of second conductivity type bias electrodes 93 and 94 disposed on the STI layer 7, the second conductivity type sensing electrodes 91 and 92 and the second conductivity type bias electrodes 93 and 94 extending into the second conductivity type well layer 6, and a ground electrode 100 connected to the first conductivity type epitaxial layer 3. The device is characterized in that a current blocking layer 5 is disposed between adjacent second conductivity type sensing electrodes and second conductivity type bias electrodes, and the current blocking layer 5 starts from the STI layer 7, passes through the second conductivity type well layer 6 and the first conductivity type epitaxial layer 3, and then touches the BOX layer 2. In this embodiment...

[0033] The current blocking layer 5 extends outward to the edge of the first conductivity type epitaxial layer 3, the second conductivity type well layer 6, and the STI layer 7.

[0034] An isolation structure 4 is provided on the BOX layer 2, and the isolation structure 4 is located outside the first conductivity type epitaxial layer 3, the second conductivity type well layer 6, the STI layer 7 and the current blocking layer 5 and surrounds the first conductivity type epitaxial layer 3, the second conductivity type well layer 6, the STI layer 7 and the current blocking layer 5.

[0035] The isolation structure 4 is a DTI deep trench isolation structure; the current blocking layer 5 is a DTI deep trench isolation region.

[0036] In this embodiment, the first conductivity type is p-type and the second conductivity type is n-type, or the first conductivity type is n-type and the second conductivity type is p-type.

[0037] Example 2

[0038] A method for fabricating a horizontal Hall effect device, comprising:

[0039] A substrate having a BOX layer and an epitaxial layer is prepared; the epitaxial layer is a first conductivity type epitaxial layer, and the substrate is a first conductivity type substrate.

[0040] Deep trench etching is performed on the epitaxial layer of the first conductivity type to form a deep trench located on the BOX layer. The bottom of the deep trench is in direct contact with the BOX layer. A current blocking layer 5 is formed by depositing silicon dioxide to fill the deep trench.

[0041] A doped window exposed by photoresist is formed by photolithography, and the flow barrier layer 5 is covered by photoresist. A second conductivity type well layer 6 is formed on top of the first conductivity type epitaxial layer by doping.

[0042] Shallow trench etching is performed on the second conductivity type well layer 6 region outside the current blocking layer 5, the sensing electrode pair region, and the bias electrode pair region to form shallow trenches on the second conductivity type well layer. An STI layer 7 is then formed by depositing silicon dioxide.

[0043] The sensing electrode pair region and the bias electrode pair region are doped to form a heavily doped second conductivity type contact layer 8, and the first conductivity type epitaxial layer is doped to form a heavily doped first conductivity type contact layer 9.

[0044] In this embodiment, when performing deep trench etching on the first conductivity type epitaxial layer, the first conductivity type epitaxial layer is etched to form a square deep trench on the BOX layer. The square deep trench is filled by depositing silicon dioxide to form an isolation structure 4. The isolation structure 4 can surround the flow barrier layer 5, the heavily doped second conductivity type contact layer 8, the STI layer 7 and the second conductivity type well layer 6 below it and the first conductivity type epitaxial layer. Furthermore, the first conductivity type epitaxial layer located in the corner region of the isolation structure 4 is exposed on the surface of the isolation structure 4.

[0045] Embodiment 1 of the present invention will now be described in more detail with reference to the accompanying drawings.

[0046] Reference Figure 1 A BOX layer 2 is provided on a first conductivity type substrate layer 1, and a first conductivity type epitaxial layer 3 is provided on the BOX layer 2, as shown in the figure. Figure 2 and Figure 3Deep trench etching is performed on the first conductivity type epitaxial layer to form a square deep trench and four strip deep trenches on the BOX layer 2. Silicon dioxide is deposited in the square deep trench and the four strip deep trenches to form an isolation structure 4 and a current blocking layer 5, respectively. The current blocking layer 5 can be a DTI structure, i.e., deep trench isolation, to achieve complete current blocking and complete device isolation by increasing the resistance between them to hinder or even block the electron flow path. An octagonal window is provided in the first conductivity type epitaxial layer 3, and the four alternate sides of the octagonal window coincide with the four sides of the isolation structure 4. The four current blocking layers 5 are located on the other four alternate sides of the octagonal window. The area inside the octagonal window outside the current blocking layer 5 is doped to form a second conductivity type well layer 6. The second conductivity type well layer 6 is etched to remove the surface layer of the area other than the area to be formed as the sensing electrode pair and the bias electrode pair. A second conductivity type well layer 6 is formed, and silicon dioxide is deposited on it to form an STI layer 7. The second conductivity type well layer, which is to be formed into a pair of sensing electrodes and a pair of bias electrodes, is then doped to form a heavily doped second conductivity type contact layer 8. The first conductivity type epitaxial layer located at the corner of the isolation structure 4 is doped to form a heavily doped first conductivity type contact layer 9. Finally, a dielectric layer is covered, and holes are drilled and metal is deposited on it to form a pair of sensing electrodes 91, 92 and a pair of bias electrodes 93, 94 connected to each of the second conductivity type contact layers 8, and a ground electrode 100 connected to each of the heavily doped first conductivity type contact layers 9.

[0047] Reference Figure 1 The isolation structure 4 is square, and a current-blocking layer 5 is disposed within the cavity, located on the diagonal of the square and exhibiting 90° symmetry. Both the current-blocking layer 5 and the second conductive contact layer 8 have rectangular cross-sections. The current-blocking layer 5 has a length not exceeding 30 μm and a width not exceeding 1.5 μm; the second conductive contact layer 8 has a length not less than one-tenth of the side length of its respective STI layer and a width not exceeding 1.5 μm. The distance between the second conductive contact layer 8 and the side of its adjacent octagonal N-well layer is >0.5 μm. (Refer to...) Figure 2 or Figure 3 The maximum depth of STI layer 7 is less than 5 μm.

[0048] The second type of conductive sensing electrode pairs 91 and 92 are symmetrically distributed, and the second type of conductive bias electrode pairs 93 and 94 are symmetrically distributed. In the working state, the second type of conductive bias electrode pairs 93 and 94 are used to input and output bias electrical signals, and the second type of conductive sensing electrode pairs 91 and 92 are used to output induced electrical signals.

[0049] Figure 4 for Figure 1A top-view schematic diagram of the current density distribution of a horizontal Hall device with the structure of the present invention and a conventional structure is shown below. Figure 4 As shown in (b), in a traditional horizontal Hall effect device, current tends to flow along the low-resistance direction. A portion of the current flows directly along the shortest path on the device surface to adjacent electrodes, causing a decrease in sensitivity, i.e., a "short-circuit effect." Figure 4 As shown in (a), the horizontal Hall device proposed in this invention has a current blocking layer 5 with controllable length inside the cavity, which changes the distribution of resistance inside the device, making the original low-resistance current path a high-resistance path. Part of the current no longer flows along the path where a "short-circuit effect" occurs, and this part of the current generates a Hall voltage perpendicular to the current flow direction after being subjected to a magnetic field. Figure 5 As shown, the structure of this invention increases the Hall voltage by up to 92% compared to the traditional structure, thereby improving the sensitivity of the device and solving the "short-circuit effect" that restricts the improvement of the sensitivity of the Hall device.

[0050] Figure 5 for Figure 1 The Hall voltage output curves of a horizontal Hall device with the structure of this invention and a conventional structure are shown in the figure, with different electrode sizes L. c Compared to the traditional structure, the Hall voltage of the present invention is increased by up to 92%. When the electrode size is changed, the Hall voltage of the present invention remains almost unchanged, while the traditional structure shows a significant change. This indicates that the present invention, by controlling the current path, frees the Hall device's sensitivity from the constraints of geometric factors in traditional theory, avoiding the influence of electrode size on device sensitivity. The electrode size can be increased to reduce misalignment without affecting device sensitivity.

[0051] Figure 6 The figure shows the Hall voltage output curve of a horizontal Hall device according to the present invention. As the length L of the current blocking layer 5 increases... D As the length of the current blocking layer 5 increases, the Hall voltage of the horizontal Hall device of the present invention also increases, indicating that the sensitivity of the Hall device of the present invention is adjusted by the length of the current blocking layer 5.

[0052] Figure 7 The following is a flowchart illustrating the fabrication process of a horizontal Hall effect device according to the present invention. Figure 7 The present invention provides a detailed description of a method for fabricating a horizontal Hall effect device.

[0053] like Figure 7 (a) A P-type substrate with a BOX layer and a P-type epitaxial layer is obtained by wafer bonding technology.

[0054] like Figure 7(b) Deep trench etching is performed on the P-type epitaxial layer by dry etching to form a deep trench with a specific shape on the BOX layer, with the bottom of the deep trench in direct contact with the BOX layer.

[0055] like Figure 7 (c) A DTI structure is formed by depositing silica in a deep trench using chemical vapor deposition.

[0056] like Figure 7 (d) A shallow N-well layer is formed in the P-type epitaxial layer 3 by high-energy N-type ion implantation;

[0057] like Figure 7 (e) Shallow trench etching of the shallow N-well layer by dry etching

[0058] like Figure 7 (f) A silica layer is formed by depositing silica in a shallow trench to fill the trench using chemical vapor deposition.

[0059] like Figure 7 (g) An N+ contact layer is formed on a shallow N-well layer by high-energy N-type ion implantation.

[0060] like Figure 7 (h) A P+ contact layer is formed on a P-type epitaxial layer by high-energy P-type ion implantation.

[0061] like Figure 7 (i) A dielectric layer is deposited on a P-type epitaxial layer.

[0062] like Figure 7 (j) Drill holes in the dielectric layer above the N+ contact layer and the P+ contact layer.

[0063] like Figure 7 (k) deposits a metal layer on the dielectric layer.

[0064] like Figure 7 (i) Photolithography and etching of the metal layer to form metal electrodes on the N+ contact layer and P+ contact layer.

[0065] Finally, it should be noted that although the present invention has been described in detail with reference to the embodiments, those skilled in the art can still modify the technical solutions described in the foregoing embodiments or make equivalent substitutions for some of the technical features. However, any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A horizontal Hall effect device, characterized in that, include: A first conductivity type substrate layer (1) is provided, a BOX layer (2) is provided on the first conductivity type substrate layer (1), a first conductivity type epitaxial layer (3) is provided on the BOX layer (2), a second conductivity type well layer (6) is provided on the first conductivity type epitaxial layer (3), an STI layer (7) is provided on the second conductivity type well layer (6), a second conductivity type sensing electrode pair (91, 92) and a second conductivity type bias electrode pair (93, 94) are provided on the STI layer (7), the second conductivity type sensing electrode pair (91, 92) and the second conductivity type bias electrode pair (93, 94) extend to the second conductivity type well layer (6), and a ground electrode (100) is connected on the first conductivity type epitaxial layer (3). The feature is that a current blocking layer (5) is provided between adjacent second conductivity type sensing electrodes and second conductivity type bias electrodes, and the current blocking layer (5) starts from the STI layer (7) and passes through the second conductivity type well layer (6) and the first conductivity type epitaxial layer (3) before touching the BOX layer (2).

2. The horizontal Hall effect device according to claim 1, characterized in that, The current blocking layer (5) extends outward to the edge of the first conductivity type epitaxial layer (3), the second conductivity type well layer (6), and the STI layer (7).

3. The horizontal Hall effect device according to claim 1 or 2, characterized in that, An isolation structure (4) is provided on the BOX layer (2), and the isolation structure (4) is located outside the first conductivity type epitaxial layer (3), the second conductivity type well layer (6), the STI layer (7) and the current blocking layer (5) and surrounds the first conductivity type epitaxial layer (3), the second conductivity type well layer (6), the STI layer (7) and the current blocking layer (5).

4. The horizontal Hall effect device according to claim 3, characterized in that, The isolation structure (4) is a DTI deep trench isolation structure.

5. The horizontal Hall effect device according to claim 1 or 2, characterized in that, The current blocking layer (5) is a DTI deep trench isolation region.

6. The horizontal Hall effect device according to claim 1, characterized in that, The first conductivity type is p-type, and the second conductivity type is n-type.

7. The horizontal Hall effect device according to claim 1, characterized in that, The first conductivity type is n-type, and the second conductivity type is p-type.

8. The horizontal Hall effect device according to claim 1, characterized in that, The line connecting the sensing electrodes in the second conductivity type sensing electrode pair is perpendicular to the line connecting the bias electrodes in the second conductivity type bias electrode pair.

9. A method for fabricating a horizontal Hall effect device, comprising: A substrate with a BOX layer and an epitaxial layer was prepared. The epitaxial layer is a first conductivity type epitaxial layer, and the substrate is a first conductivity type substrate. Deep trench etching is performed on the first conductivity type epitaxial layer to form a deep trench on the BOX layer. The bottom of the deep trench is in direct contact with the BOX layer. A current blocking layer is formed by depositing silicon dioxide to fill the deep trench (5). A doped window exposed by photoresist is formed by photolithography and a flow barrier layer is covered by photoresist (5). A second conductivity type well layer is formed on the top of the first conductivity type epitaxial layer by doping (6). Shallow trench etching is performed on the second conductivity type well layer (6) region outside the current blocking layer (5), the sensing electrode pair region and the bias electrode pair region to form a shallow trench on the second conductivity type well layer, and an STI layer (7) is formed by depositing silicon dioxide. The sensing electrode pair region and the bias electrode pair region are doped to form a heavily doped second conductivity type contact layer (8), and the first conductivity type epitaxial layer (3) is doped to form a heavily doped first conductivity type contact layer (9).

10. The method for fabricating a horizontal Hall device according to claim 9, characterized in that, When the first conductivity type epitaxial layer is etched into a deep trench, the first conductivity type epitaxial layer is etched to form a square deep trench on the BOX layer. The square deep trench is filled by depositing silicon dioxide to form an isolation structure (4). The isolation structure (4) can surround the current blocking layer (5), the heavily doped second conductivity type contact layer (8), the STI layer (7) and the second conductivity type well layer (6) below it, the first conductivity type epitaxial layer (3) and the heavily doped first conductivity type contact layer (9). The first conductivity type epitaxial layer located in the corner area of ​​the isolation structure (4) is exposed on the surface of the isolation structure (4).

Images