Pixel circuit, driving method and display device

Abstract

This disclosure provides a pixel circuit, a driving method, and a display device. The pixel circuit includes a light-emitting element, a first reset circuit, a control circuit, and a driving circuit. Under the control of a first reset control signal, the first reset circuit writes a first initial voltage into a first node. Under the control of a first control signal provided by a first control terminal, the control circuit controls the connection between the control terminal of the driving circuit and the first node; under the control of a second control signal provided by a second control terminal, it controls the connection between the first node and a first terminal of the driving circuit. The first terminal of the driving circuit is electrically connected to the light-emitting element, and the driving circuit drives the light-emitting element to emit light. This disclosure can improve hysteresis phenomena.

Description

Technical Field

[0001] This disclosure relates to the field of display technology, and more particularly to a pixel circuit, driving method, and display device. Background Technology

[0002] In recent years, with the advancement of smart display technology, organic light-emitting diode (OLED) displays have become one of the hottest topics in the field of display research. With the thinning of display panels, the narrowing of bezels, and the development of low-frequency display technology, the optimization design of display panels has become increasingly challenging.

[0003] In related technologies, pixel circuits exhibit severe hysteresis during operation, which affects display quality. Summary of the Invention

[0004] In one aspect, embodiments of this disclosure provide a pixel circuit, including a light-emitting element, a first reset circuit, a control circuit, and a driving circuit, wherein...

[0005] The first reset circuit is electrically connected to the first reset control terminal, the first initial voltage terminal, and the first node, respectively, and is used to write the first initial voltage provided by the first initial voltage terminal into the first node under the control of the first reset control signal provided by the first reset control terminal.

[0006] The control circuit is electrically connected to the first control terminal, the second control terminal, the first node, the control terminal of the drive circuit, and the first terminal of the drive circuit, respectively. It is used to control the connection between the control terminal of the drive circuit and the first node under the control of the first control signal provided by the first control terminal, and to control the connection between the first node and the first terminal of the drive circuit under the control of the second control signal provided by the second control terminal.

[0007] The first terminal of the driving circuit is electrically connected to the light-emitting element, and the driving circuit is used to drive the light-emitting element to emit light.

[0008] Optionally, the pixel circuit described in at least one embodiment of this disclosure further includes a second reset circuit;

[0009] The second reset circuit is electrically connected to the second reset control terminal, the second initial voltage terminal and the first node respectively, and is used to write the second initial voltage provided by the second initial voltage terminal into the first node under the control of the second reset control signal provided by the second reset control terminal.

[0010] Optionally, the pixel circuit described in at least one embodiment of this disclosure further includes an energy storage circuit, a data writing circuit, a first light emission control circuit, and a second light emission control circuit;

[0011] The first terminal of the energy storage circuit is electrically connected to the control terminal of the drive circuit, and the second terminal of the energy storage circuit is electrically connected to the first voltage terminal. The energy storage circuit is used to store electrical energy.

[0012] The first light-emitting control circuit is electrically connected to the light-emitting control terminal, the first voltage terminal, and the second terminal of the driving circuit, respectively, and is used to control the connection between the first voltage terminal and the second terminal of the driving circuit under the control of the light-emitting control signal provided by the light-emitting control terminal.

[0013] The second light-emitting control circuit is electrically connected to the light-emitting control terminal, the first terminal of the driving circuit, and the first electrode of the light-emitting element, respectively, and is used to control the first terminal of the driving circuit and the first electrode of the light-emitting element to be connected under the control of the light-emitting control signal;

[0014] The data writing circuit is electrically connected to the write control terminal, the data line and the second terminal of the driving circuit, respectively, and is used to write the data voltage provided by the data line to the second terminal of the driving circuit under the control of the write control signal provided by the write control terminal.

[0015] The second electrode of the light-emitting element is electrically connected to the second voltage terminal.

[0016] Optionally, the pixel circuit described in at least one embodiment of this disclosure further includes a third reset circuit;

[0017] The third reset circuit is electrically connected to the third reset control terminal, the first electrode of the light-emitting element, and the third initial voltage terminal, respectively, and is used to write the third initial voltage provided by the third initial voltage terminal into the first electrode of the light-emitting element under the control of the third reset control signal provided by the third reset control terminal.

[0018] Optionally, the first reset circuit includes a first transistor;

[0019] The control electrode of the first transistor is electrically connected to the first reset control terminal, the first electrode of the first transistor is electrically connected to the first initial voltage terminal, and the second electrode of the first transistor is electrically connected to the first node.

[0020] Optionally, the control circuit includes a second transistor and a third transistor;

[0021] The control electrode of the second transistor is electrically connected to the first control terminal, the first electrode of the second transistor is electrically connected to the first node, and the second electrode of the second transistor is electrically connected to the control terminal of the driving circuit.

[0022] The control electrode of the third transistor is electrically connected to the second control terminal, the first electrode of the third transistor is electrically connected to the first node, and the second electrode of the third transistor is electrically connected to the first terminal of the driving circuit.

[0023] Optionally, the second reset circuit includes a fourth transistor;

[0024] The control electrode of the fourth transistor is electrically connected to the second reset control terminal, the first electrode of the fourth transistor is electrically connected to the second initial voltage terminal, and the second electrode of the fourth transistor is electrically connected to the first node.

[0025] Optionally, the energy storage circuit includes a storage capacitor; the first light-emitting control circuit includes a fifth transistor; the second light-emitting control circuit includes a sixth transistor; the driving circuit includes a driving transistor; and the data writing circuit includes a seventh transistor.

[0026] The control electrode of the fifth transistor is electrically connected to the light-emitting control terminal, the first electrode of the fifth transistor is electrically connected to the first voltage terminal, and the second electrode of the fifth transistor is electrically connected to the second terminal of the driving circuit.

[0027] The control electrode of the sixth transistor is electrically connected to the light-emitting control terminal, the first electrode of the sixth transistor is electrically connected to the first terminal of the driving circuit, and the second electrode of the sixth transistor is electrically connected to the first electrode of the light-emitting element.

[0028] The control electrode of the seventh transistor is electrically connected to the write control terminal, the first electrode of the seventh transistor is electrically connected to the data line, and the second electrode of the seventh transistor is electrically connected to the second terminal of the drive circuit.

[0029] The first end of the storage capacitor is electrically connected to the control terminal of the driving circuit, and the second end of the storage capacitor is electrically connected to the first voltage terminal.

[0030] The control terminal of the driving transistor is the control terminal of the driving circuit, the first terminal of the driving transistor is the first terminal of the driving circuit, and the second terminal of the driving transistor is the second terminal of the driving circuit.

[0031] Optionally, the third reset circuit includes an eighth transistor;

[0032] The control electrode of the eighth transistor is electrically connected to the third reset control terminal, the first electrode of the eighth transistor is electrically connected to the third initial voltage terminal, and the second electrode of the eighth transistor is electrically connected to the first electrode of the light-emitting element.

[0033] In a second aspect, embodiments of this disclosure provide a driving method applied to the aforementioned pixel circuit, wherein the display cycle includes a first reset phase and a second reset phase set sequentially, and the driving method includes:

[0034] In the first reset phase, the first reset circuit, under the control of the first reset control signal, writes the first initial voltage provided by the first initial voltage terminal into the first node; the control circuit, under the control of the first control signal, controls the connection between the control terminal of the drive circuit and the first node; the control circuit, under the control of the second control signal, controls the connection between the first node and the first terminal of the drive circuit.

[0035] In the second reset phase, under the control of the first control signal, the control circuit connects the control terminal of the drive circuit with the first node, and under the control of the second control signal, the control circuit connects the first node with the first terminal of the drive circuit.

[0036] Optionally, the pixel circuit further includes a second reset circuit; the driving method further includes:

[0037] During the second reset phase, the second reset circuit, under the control of the second reset control signal, writes the second initialization voltage provided by the second initial voltage terminal into the first node.

[0038] Optionally, the pixel circuit further includes an energy storage circuit, a data writing circuit, a first light-emitting control circuit, and a second light-emitting control circuit; the display cycle further includes a charging phase and a first light-emitting phase set after the second reset phase; the driving method further includes:

[0039] During the charging phase, the data writing circuit, under the control of the writing control signal, writes the data voltage provided by the data line to the second terminal of the driving circuit. Under the control of the first control signal, the control circuit controls the connection between the control terminal of the driving circuit and the first node. Under the control of the second control signal, the control circuit controls the connection between the first node and the first terminal of the driving circuit.

[0040] At the start of the charging phase, the drive circuit, under the control of the potential of its control terminal, controls the connection between the first terminal and the second terminal of the drive circuit to charge the energy storage circuit through the data voltage, and changes the potential of the control terminal of the drive circuit until the drive circuit controls the disconnection between the first terminal and the second terminal of the drive circuit.

[0041] In the first light-emitting stage, the first light-emitting control circuit, under the control of the light-emitting control signal, controls the connection between the first voltage terminal and the second terminal of the driving circuit; the second light-emitting control circuit, under the control of the light-emitting control signal, controls the connection between the first terminal of the driving circuit and the first electrode of the light-emitting element; the driving circuit drives the light-emitting element to emit light.

[0042] Optionally, the pixel circuit further includes a third reset circuit; the display cycle further includes a third reset phase disposed between the second reset phase and the charging phase, and the driving method further includes:

[0043] During the third reset phase, the third reset circuit, under the control of the third reset control signal, writes the third initial voltage provided by the third initial voltage terminal into the first electrode of the light-emitting element.

[0044] Optionally, in low-frequency display, the display time period includes refresh frames and hold frames, wherein the refresh frames are the display cycle; the hold frames include a fourth reset stage, a fifth reset stage, a sixth reset stage, a seventh reset stage, and a second light-emitting stage set sequentially.

[0045] The driving method further includes:

[0046] During the holding frame, under the control of the first control signal provided by the first control terminal, the control circuit controls the control terminal of the drive circuit to disconnect from the first node;

[0047] In the fourth reset phase, the first reset circuit, under the control of the first reset control signal, writes the first initial voltage provided by the first initial voltage terminal into the first node; the control circuit, under the control of the second control signal, controls the connection between the first node and the first terminal of the drive circuit to write the first initial voltage into the first terminal of the drive circuit.

[0048] In the fifth reset phase, the second reset circuit, under the control of the second reset control signal, writes the second initial voltage provided by the second initial voltage terminal into the first node. The control circuit, under the control of the second control signal, controls the connection between the first node and the first terminal of the drive circuit to write the second initial voltage into the first terminal of the drive circuit.

[0049] In the sixth reset phase, under the control of the third reset control signal, the third reset circuit writes the third initial voltage provided by the third initial voltage terminal into the first electrode of the light-emitting element;

[0050] In the seventh reset phase, the data writing circuit, under the control of the write control signal, writes the voltage signal provided by the data line to the second terminal of the drive circuit;

[0051] In the second light-emitting stage, the first light-emitting control circuit, under the control of the light-emitting control signal, controls the connection between the first voltage terminal and the second terminal of the driving circuit; the second light-emitting control circuit, under the control of the light-emitting control signal, controls the connection between the first terminal of the driving circuit and the first electrode of the light-emitting element; the driving circuit drives the light-emitting element to emit light.

[0052] In a third aspect, embodiments of this disclosure also provide a display device including the pixel circuit described above. Attached Figure Description

[0053] Figure 1 This is a structural diagram of the pixel circuit described in the embodiments of this disclosure;

[0054] Figure 2 This is a structural diagram of the pixel circuit according to at least one embodiment of the present disclosure;

[0055] Figure 3 This is a structural diagram of the pixel circuit according to at least one embodiment of the present disclosure;

[0056] Figure 4 This is a structural diagram of the pixel circuit according to at least one embodiment of the present disclosure;

[0057] Figure 5 This is a circuit diagram of a pixel circuit shown in at least one embodiment of the present disclosure;

[0058] Figure 6 This is a public announcement. Figure 5 The timing diagram of at least one embodiment of the pixel circuit shown;

[0059] Figure 7A yes Figure 5 A schematic diagram of the operating state of at least one embodiment of the pixel circuit shown in the first reset stage;

[0060] Figure 7B yes Figure 5 The diagram shows the operating state of at least one embodiment of the pixel circuit in the second reset phase.

[0061] Figure 7C yes Figure 5 A schematic diagram of the operating state of at least one embodiment of the pixel circuit during the charging phase;

[0062] Figure 7D yes Figure 5 A schematic diagram of the operating state of at least one embodiment of the pixel circuit shown in the first light-emitting stage;

[0063] Figure 8 This is a public announcement Figure 5 The timing diagram shows the operation of at least one embodiment of the pixel circuit. Detailed Implementation

[0064] The technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. Based on the embodiments of this disclosure, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this disclosure.

[0065] In all embodiments of this disclosure, the transistors used can be bipolar junction transistors (BJTs), thin-film transistors (TFTs), field-effect transistors (FETs), or other devices with similar characteristics. In the embodiments of this disclosure, to distinguish the two terminals of the transistor other than the control terminal, one terminal is referred to as the first terminal and the other as the second terminal.

[0066] In actual operation, when the transistor is a bipolar junction transistor (BJT), the control electrode can be the base, the first electrode can be the collector, and the second electrode can be the emitter; or, the control electrode can be the base, the first electrode can be the emitter, and the second electrode can be the collector.

[0067] In actual operation, when the transistor is a thin-film transistor or a field-effect transistor, the control electrode can be the gate, the first electrode can be the drain, and the second electrode can be the source; or, the control electrode can be the gate, the first electrode can be the source, and the second electrode can be the drain.

[0068] like Figure 1 As shown, the pixel circuit described in this embodiment includes a light-emitting element 10, a first reset circuit 11, a control circuit 12, and a driving circuit 13, wherein...

[0069] The first reset circuit 11 is electrically connected to the first reset control terminal PR1, the first initial voltage terminal I1 and the first node N1 respectively, and is used to write the first initial voltage Vi1 provided by the first initial voltage terminal I1 into the first node N1 under the control of the first reset control signal provided by the first reset control terminal PR1.

[0070] The control circuit 12 is electrically connected to the first control terminal NG1, the second control terminal NG2, the first node N1, the control terminal of the drive circuit 13, and the first terminal of the drive circuit 13, respectively. It is used to control the connection between the control terminal of the drive circuit 13 and the first node N1 under the control of the first control signal provided by the first control terminal NG1, and to control the connection between the first node N1 and the first terminal of the drive circuit 13 under the control of the second control signal provided by the second control terminal NG2.

[0071] The first end of the driving circuit 13 is electrically connected to the light-emitting element 10, and the driving circuit 13 is used to drive the light-emitting element 10 to emit light.

[0072] In at least one embodiment of this disclosure, the voltage value of the first initial voltage Vi1 may be greater than or equal to 5V and less than or equal to 8V, but is not limited thereto.

[0073] When the pixel circuit described in at least one embodiment of this disclosure is working, the display cycle includes a first reset phase and a second reset phase that are set sequentially.

[0074] In the first reset phase, the first reset circuit 11, under the control of the first reset control signal, writes the first initial voltage Vi1 provided by the first initial voltage terminal I1 into the first node N1; the control circuit 12, under the control of the first control signal, controls the control terminal of the drive circuit 13 to connect with the first node N1, and the control circuit 12, under the control of the second control signal, controls the first node N1 to connect with the first terminal of the drive circuit 13.

[0075] During the second reset phase, under the control of the first control signal, the control circuit 12 controls the connection between the control terminal of the drive circuit 13 and the first node N1. Under the control of the second control signal, the control circuit 12 controls the connection between the first node N1 and the first terminal of the drive circuit 13.

[0076] The pixel circuit described in this embodiment of the present disclosure, by setting a first reset circuit 11 and a control circuit 12, in the first reset stage, the first reset circuit 11 writes a first initial voltage Vi1 into the first node N1, and the control circuit 12 controls the control terminal of the driving circuit 13 to connect with the first node N1, and controls the first node N1 to connect with the first terminal of the driving circuit 13, so that the potential of the control terminal of the driving circuit 13 and the potential of the first terminal of the driving circuit 13 are the first initial voltage Vi1, so as to provide a bias voltage to the driving transistors included in the driving circuit 13, so that the driving transistors included in the driving circuit 13 are in a biased state, improving the hysteresis phenomenon and enhancing the display effect.

[0077] The pixel circuit described in this embodiment can improve the flicker phenomenon when displaying at low frequencies.

[0078] Since the display time period includes refresh frames and hold frames during low-frequency display, the drive transistors included in the drive circuit 13 are biased and reset during a portion of the hold frame. During the hold frame, the potential of the source and drain of the drive transistors in the drive circuit 13 are consistent with the refresh frame, which can improve the flickering phenomenon.

[0079] In at least one embodiment of this disclosure, when performing high-frequency display, the display period can be one frame time, and when performing low-frequency display, the display period can be the refresh frame.

[0080] like Figure 2 As shown, in Figure 1 Based on at least one embodiment of the pixel circuit shown, the pixel circuit of at least one embodiment of this disclosure further includes a second reset circuit 21;

[0081] The second reset circuit 21 is electrically connected to the second reset control terminal PG1, the second initial voltage terminal I2 and the first node N1 respectively, and is used to write the second initialization voltage Vi2 provided by the second initial voltage terminal I2 into the first node N1 under the control of the second reset control signal provided by the second reset control terminal PG1.

[0082] In at least one embodiment of this disclosure, the voltage value of the second initial voltage Vi2 may be greater than or equal to -5V and less than or equal to -2V, but is not limited thereto.

[0083] This disclosure is as follows Figure 2 At least one embodiment of the pixel circuit shown, when in operation,

[0084] During the second reset phase, under the control of the second reset control signal, the second reset circuit 21 writes the second initialization voltage Vi2 provided by the second initial voltage terminal I2 into the first node N1, so that when the charging phase after the second reset phase begins, the driving transistor can be turned on to perform threshold voltage compensation.

[0085] like Figure 3 As shown in this disclosure Figure 2 Based on at least one embodiment of the pixel circuit shown, the pixel circuit of at least one embodiment of this disclosure further includes an energy storage circuit 31, a data writing circuit 32, a first light emission control circuit 33, and a second light emission control circuit 34.

[0086] The first end of the energy storage circuit 31 is electrically connected to the control end of the drive circuit 13, and the second end of the energy storage circuit 31 is electrically connected to the first voltage end V1. The energy storage circuit 31 is used to store electrical energy.

[0087] The first light-emitting control circuit 33 is electrically connected to the light-emitting control terminal E1, the first voltage terminal V1 and the second terminal of the driving circuit 13 respectively, and is used to control the connection between the first voltage terminal V1 and the second terminal of the driving circuit 13 under the control of the light-emitting control signal provided by the light-emitting control terminal E1.

[0088] The second light-emitting control circuit 34 is electrically connected to the light-emitting control terminal E1, the first terminal of the driving circuit 13 and the first electrode of the light-emitting element 10, respectively, and is used to control the first terminal of the driving circuit 13 and the first electrode of the light-emitting element 10 to be connected under the control of the light-emitting control signal.

[0089] The data writing circuit 32 is electrically connected to the write control terminal PG2, the data line D1 and the second terminal of the driving circuit 13, respectively, and is used to write the data voltage Vdta provided by the data line D1 to the second terminal of the driving circuit 13 under the control of the write control signal provided by the write control terminal PG2.

[0090] The second electrode of the light-emitting element 10 is electrically connected to the second voltage terminal V2.

[0091] In at least one embodiment of this disclosure, the first voltage terminal V1 can be a high voltage terminal and the second voltage terminal V2 can be a low voltage terminal, but this is not a limitation.

[0092] This disclosure is as follows Figure 3 When at least one embodiment of the pixel circuit shown is in operation, the display cycle further includes a charging phase and a first light-emitting phase disposed after the second reset phase;

[0093] During the charging phase, under the control of the write control signal, the data writing circuit 32 writes the data voltage Vdata provided by the data line D1 to the second terminal of the drive circuit 13. Under the control of the first control signal, the control circuit 12 controls the connection between the control terminal of the drive circuit 13 and the first node N1. Under the control of the second control signal, the control circuit 12 controls the connection between the first node N1 and the first terminal of the drive circuit 13.

[0094] At the start of the charging phase, the drive circuit 13, under the control of the potential of its control terminal, controls the connection between the first terminal and the second terminal of the drive circuit 13 to charge the energy storage circuit 31 through the data voltage Vdata, and changes the potential of the control terminal of the drive circuit 13 until the drive circuit 13 controls the connection between the first terminal and the second terminal of the drive circuit 13 to perform threshold voltage compensation.

[0095] During the first light-emitting stage, the first light-emitting control circuit 33, under the control of the light-emitting control signal, controls the first voltage terminal V1 to be connected to the second terminal of the driving circuit 13; the second light-emitting control circuit 34, under the control of the light-emitting control signal, controls the first terminal of the driving circuit 13 to be connected to the first electrode of the light-emitting element 10; the driving circuit 13 drives the light-emitting element 10 to emit light.

[0096] like Figure 4 As shown, in Figure 3 Based on at least one embodiment of the pixel circuit shown, the pixel circuit of at least one embodiment of this disclosure further includes a third reset circuit 41;

[0097] The third reset circuit 41 is electrically connected to the third reset control terminal PR2, the first electrode of the light-emitting element 10, and the third initial voltage terminal I3, respectively. Under the control of the third reset control signal provided by the third reset control terminal PR2, it is used to write the third initial voltage Vi3 provided by the third initial voltage terminal I3 into the first electrode of the light-emitting element 10.

[0098] This disclosure is as follows Figure 4 When at least one embodiment of the pixel circuit shown is in operation, the display cycle further includes a third reset phase disposed between the second reset phase and the charging phase;

[0099] In the third reset phase, under the control of the third reset control signal, the third reset circuit 41 writes the third initial voltage Vi3 provided by the third initial voltage terminal I3 into the first electrode of the light-emitting element 10 to control the light-emitting element 10 to not emit light and to clear the charge remaining in the first electrode of the light-emitting element 10.

[0100] In at least one embodiment of this disclosure, the voltage value of the third initial voltage Vi3 may be greater than or equal to -5V and less than or equal to -2V, but is not limited thereto.

[0101] This disclosure is as follows Figure 4 When at least one embodiment of the pixel circuit shown is in operation, during low-frequency display, the display time period includes a refresh frame and a hold frame; the refresh frame can be the display cycle, and the hold frame can include a fourth reset stage, a fifth reset stage, a sixth reset stage, a seventh reset stage, and a second light-emitting stage set sequentially;

[0102] During the holding frame, under the control of the first control signal provided by the first control terminal NG1, the control circuit 12 controls the control terminal of the drive circuit 13 to disconnect from the first node N1;

[0103] In the fourth reset stage, under the control of the first reset control signal, the first reset circuit 11 writes the first initial voltage Vi1 provided by the first initial voltage terminal I1 into the first node N1; under the control of the second control signal, the control circuit 12 controls the connection between the first node N1 and the first terminal of the drive circuit 13 to write the first initial voltage Vi1 into the first terminal of the drive circuit 13 to reset the potential of the first terminal of the drive circuit 13.

[0104] In the fifth reset phase, under the control of the second reset control signal, the second reset circuit 21 writes the second initial voltage Vi2 provided by the second initial voltage terminal I2 into the first node N1. Under the control of the second control signal, the control circuit 12 controls the first node N1 to connect with the first terminal of the drive circuit 13 so as to write the second initial voltage Vi2 into the first terminal of the drive circuit 13.

[0105] In the sixth reset stage, under the control of the third reset control signal, the third reset circuit 41 writes the third initial voltage Vi3 provided by the third initial voltage terminal I3 into the first electrode of the light-emitting element 10 to control the light-emitting element 10 to not emit light and to clear the residual charge on the first electrode of the light-emitting element 10.

[0106] In the seventh reset phase, the data writing circuit 32, under the control of the writing control signal, writes the voltage signal provided by the data line D1 to the second terminal of the drive circuit 13.

[0107] In the second light-emitting stage, the first light-emitting control circuit 33, under the control of the light-emitting control signal, controls the first voltage terminal V1 to be connected with the second terminal of the driving circuit 13; the second light-emitting control circuit 34, under the control of the light-emitting control signal, controls the first terminal of the driving circuit 13 to be connected with the first electrode of the light-emitting element 10; the driving circuit 13 drives the light-emitting element 10 to emit light.

[0108] In specific implementation, during the seventh reset phase, the voltage signal provided by the data line D1 can be a data voltage Vdata. This data voltage Vdata is the data voltage provided by the data line D1 during the charging phase, and its voltage range can be, for example, greater than or equal to 1V and less than or equal to 6.5V; or...

[0109] In the seventh reset stage, the voltage signal provided by the data line D1 can be a reset voltage signal, and the voltage value range of the reset voltage signal can be greater than or equal to 4.6V and less than or equal to 7V.

[0110] However, this is not the only limit.

[0111] When the pixel circuit described in at least one embodiment of this disclosure is in operation, during the seventh reset phase, the data writing circuit 32, under the control of the writing control signal, writes the voltage signal provided by the data line D1 to the second terminal of the driving circuit 13 to provide a bias voltage to the driving transistor included in the driving circuit 13, so that the driving transistor included in the driving circuit 13 is in a biased state to improve the hysteresis phenomenon.

[0112] When the pixel circuit described in at least one embodiment of this disclosure performs low-frequency display, for example, when the refresh frequency is 1Hz, the display time period may include one refresh frame and 59 hold frames set after the refresh frame. In the seventh reset stage included in each of the hold frames, the potential of the second terminal of the driving circuit 13 can be reset by the voltage signal provided by the data line D1 to improve the hysteresis phenomenon.

[0113] This disclosure is as follows Figure 4 In at least one embodiment of the pixel circuit shown, during the fourth reset phase, the driving circuit 13 can control the connection between the first terminal and the second terminal of the driving circuit 13 under the control of the potential of its control terminal, but is not limited thereto.

[0114] This disclosure is as follows Figure 4 In at least one embodiment of the pixel circuit shown, during operation, at low frequency display, in a holding frame, in the fourth reset phase, the first initial voltage Vi1 is written to the first terminal of the driving circuit 13 to reset the potential of the first terminal of the driving circuit 13; in the fifth reset phase, the second initial voltage Vi2 is written to the first terminal of the driving circuit 13; in the seventh reset phase, the voltage signal provided by the data line D1 is written to the second terminal of the driving circuit 13 so that in the holding frame, the potential of the first terminal and the potential of the second terminal of the driving circuit 13 are consistent with those in the refresh frame, thereby improving the flickering phenomenon.

[0115] Optionally, the first reset circuit includes a first transistor;

[0116] The control electrode of the first transistor is electrically connected to the first reset control terminal, the first electrode of the first transistor is electrically connected to the first initial voltage terminal, and the second electrode of the first transistor is electrically connected to the first node.

[0117] Optionally, the control circuit includes a second transistor and a third transistor;

[0118] The control electrode of the second transistor is electrically connected to the first control terminal, the first electrode of the second transistor is electrically connected to the first node, and the second electrode of the second transistor is electrically connected to the control terminal of the driving circuit.

[0119] The control electrode of the third transistor is electrically connected to the second control terminal, the first electrode of the third transistor is electrically connected to the first node, and the second electrode of the third transistor is electrically connected to the first terminal of the driving circuit.

[0120] Optionally, the second reset circuit includes a fourth transistor;

[0121] The control electrode of the fourth transistor is electrically connected to the second reset control terminal, the first electrode of the fourth transistor is electrically connected to the second initial voltage terminal, and the second electrode of the fourth transistor is electrically connected to the first node.

[0122] Optionally, the energy storage circuit includes a storage capacitor; the first light-emitting control circuit includes a fifth transistor; the second light-emitting control circuit includes a sixth transistor; the driving circuit includes a driving transistor; and the data writing circuit includes a seventh transistor.

[0123] The control electrode of the fifth transistor is electrically connected to the light-emitting control terminal, the first electrode of the fifth transistor is electrically connected to the first voltage terminal, and the second electrode of the fifth transistor is electrically connected to the second terminal of the driving circuit.

[0124] The control electrode of the sixth transistor is electrically connected to the light-emitting control terminal, the first electrode of the sixth transistor is electrically connected to the first terminal of the driving circuit, and the second electrode of the sixth transistor is electrically connected to the first electrode of the light-emitting element.

[0125] The control electrode of the seventh transistor is electrically connected to the write control terminal, the first electrode of the seventh transistor is electrically connected to the data line, and the second electrode of the seventh transistor is electrically connected to the second terminal of the drive circuit.

[0126] The first end of the storage capacitor is electrically connected to the control terminal of the driving circuit, and the second end of the storage capacitor is electrically connected to the first voltage terminal.

[0127] The control terminal of the driving transistor is the control terminal of the driving circuit, the first terminal of the driving transistor is the first terminal of the driving circuit, and the second terminal of the driving transistor is the second terminal of the driving circuit.

[0128] Optionally, the third reset circuit includes an eighth transistor;

[0129] The control electrode of the eighth transistor is electrically connected to the third reset control terminal, the first electrode of the eighth transistor is electrically connected to the third initial voltage terminal, and the second electrode of the eighth transistor is electrically connected to the first electrode of the light-emitting element.

[0130] like Figure 5 As shown, in Figure 4 Based on at least one embodiment of the pixel circuit shown, the first reset circuit 11 includes a first transistor T1; the driving circuit 13 includes a driving transistor T0; and the light-emitting element is an organic light-emitting diode O1.

[0131] The gate of the first transistor T1 is electrically connected to the first reset control terminal PR1, the source of the first transistor T1 is electrically connected to the first initial voltage terminal I1, and the drain of the first transistor T1 is electrically connected to the first node N1.

[0132] The control circuit 12 includes a second transistor T2 and a third transistor T3;

[0133] The gate of the second transistor T2 is electrically connected to the first control terminal NG1, the source of the second transistor T2 is electrically connected to the first node N1, and the drain of the second transistor T2 is electrically connected to the gate of the driving transistor T0.

[0134] The gate of the third transistor T3 is electrically connected to the second control terminal NG2, the source of the third transistor T3 is electrically connected to the first node N1, and the drain of the third transistor T3 is electrically connected to the source of the driving transistor T0.

[0135] The second reset circuit 21 includes a fourth transistor T4;

[0136] The gate of the fourth transistor T4 is electrically connected to the second reset control terminal PG1, the source of the fourth transistor T4 is electrically connected to the second initial voltage terminal I2, and the drain of the fourth transistor T4 is electrically connected to the first node N1.

[0137] The energy storage circuit 31 includes a storage capacitor C0, the first light-emitting control circuit 33 includes a fifth transistor T5, the second light-emitting control circuit 34 includes a sixth transistor T6, and the data writing circuit 32 includes a seventh transistor T7.

[0138] The gate of the fifth transistor T5 is electrically connected to the light-emitting control terminal E1, the source of the fifth transistor T5 is electrically connected to the high voltage terminal VDD, and the drain of the fifth transistor T5 is electrically connected to the drain of the driving transistor T0.

[0139] The gate of the sixth transistor T6 is electrically connected to the light-emitting control terminal E1, the source of the sixth transistor T6 is electrically connected to the source of the driving transistor T0, and the drain of the sixth transistor T6 is electrically connected to the anode of the organic light-emitting diode O1.

[0140] The gate of the seventh transistor T7 is electrically connected to the write control terminal PG2, the source of the seventh transistor T7 is electrically connected to the data line D1, and the drain of the seventh transistor T7 is electrically connected to the drain of the driving transistor T0.

[0141] The first terminal of the storage capacitor C0 is electrically connected to the gate of the driving transistor T0, and the second terminal of the storage capacitor C0 is electrically connected to the high voltage terminal VDD.

[0142] The third reset circuit 41 includes an eighth transistor T8;

[0143] The gate of the eighth transistor T8 is electrically connected to the third reset control terminal PR2, the source of the eighth transistor T8 is electrically connected to the third initial voltage terminal I3, and the drain of the eighth transistor T8 is electrically connected to the anode of the organic light-emitting diode O1.

[0144] The cathode of the organic light-emitting diode O1 is electrically connected to the low-voltage terminal VSS.

[0145] exist Figure 5 In at least one embodiment of the pixel circuit shown, T2 and T3 are n-type transistors, and T1, T4, T5, T6, T7, T8 and T0 are p-type transistors, but are not limited thereto.

[0146] exist Figure 5 In at least one embodiment of the pixel circuit shown, T2 and T3 are IGZO (indium gallium zinc oxide) TFTs (thin film transistors), and T1, T4, T5, T6, T7, T8 and T0 are LTPS (low temperature polycrystalline silicon) TFTs, but are not limited thereto.

[0147] This disclosure is as follows Figure 5 At least one embodiment of the pixel circuit shown can improve hysteresis when in operation, thereby enabling good display performance in terms of FFR (first frame response) and VRR (variable refresh rate).

[0148] like Figure 6 As shown, this disclosure is as follows Figure 5 When at least one embodiment of the pixel circuit shown is in operation, the display cycle may include a first reset phase S1, a second reset phase S2, a third reset phase S3, a charging phase S4, and a first light-emitting phase S5, which are set sequentially.

[0149] During the first reset phase S1, PR1 provides a low voltage signal, PG1 provides a high voltage signal, NG1 provides a high voltage signal, NG2 provides a high voltage signal, PR2 provides a high voltage signal, PG2 provides a high voltage signal, and E1 provides a high voltage signal. Figure 7A As shown, T1, T2 and T3 are all turned on. I1 provides a first initial voltage Vi1 to write the first initial voltage Vi1 into the gate and drain of T0 to apply a bias voltage to T0 and control T0 to be in a bias state to improve the hysteresis phenomenon; the first initial voltage Vi1 is a positive voltage.

[0150] During the first reset phase S1, T4, T5, T6, T7, T8 and T0 are all turned off;

[0151] In the second reset phase S2, PR1 provides a high voltage signal, PG1 provides a low voltage signal, NG1 provides a high voltage signal, NG2 provides a high voltage signal, PR2 provides a high voltage signal, PG2 provides a high voltage signal, and E1 provides a high voltage signal. Figure 7B As shown, T4, T2, and T3 are all turned on. I2 provides a second initial voltage Vi2 to write the second initial voltage Vi2 into the gate of T3 so that T0 can be turned on when the charging phase S4 begins. The second initial voltage Vi2 is also written into the drain of T3 to pull down the potential of the drain of T0 so that the charging progress is faster through the data voltage Vdata during the charging phase (the second initial voltage Vi2 is negative and the data voltage Vdata is negative).

[0152] During the second reset phase S2, T1, T5, T6, T7, T8 and T0 are all turned off;

[0153] In the third reset phase S3, PR1 provides a high voltage signal, PG1 provides a high voltage signal, NG1 provides a high voltage signal, NG2 provides a high voltage signal, PR2 provides a low voltage signal, PG2 provides a high voltage signal, T8 is turned on, and I3 provides a third initial voltage Vi3 to write the third initial voltage Vi3 into the anode of O1 to control O1 from emitting light and to clear the charge remaining in the anode of O1.

[0154] During the third reset phase S3, T1, T2, T3, T4, T5, T6, T7 and T0 are all turned off;

[0155] During the charging phase S4, PR1 provides a high voltage signal, PG1 provides a high voltage signal, NG1 provides a high voltage signal, NG2 provides a high voltage signal, PR2 provides a high voltage signal, PG2 provides a low voltage signal, and E1 provides a high voltage signal. Figure 7C As shown, T7 is turned on, T2 and T3 are turned on, and D1 provides the data voltage Vdata;

[0156] At the start of the charging phase S4, T0 is turned on, and C0 is charged by the data voltage Vdata to increase the potential of the gate of T0 until T0 is turned off. At this time, the potential of the gate of T0 is Vdata + Vth, where Vth is the threshold voltage of T0.

[0157] During the charging phase S4, T1, T4, T5, T6 and T8 are all turned off;

[0158] In the first light-emitting stage S5, PR1 provides a high-voltage signal, PG1 provides a high-voltage signal, NG1 provides a low-voltage signal, NG2 provides a low-voltage signal, PR2 provides a high-voltage signal, PG2 provides a high-voltage signal, and E1 provides a low-voltage signal. Figure 7D As shown, T5, T6, and T0 are all on, and T0 drives O1 to emit light;

[0159] During the first light-emitting stage S5, T1, T2, T3, T4, T7 and T8 are all turned off.

[0160] This disclosure is as follows Figure 5 At least one embodiment of the pixel circuit shown, during operation, in low-frequency display, includes a display time period comprising a refresh frame and a hold frame; the refresh frame can be the display cycle, such as... Figure 8 As shown, the holding frame may include a fourth reset stage S6, a fifth reset stage S7, a sixth reset stage S8, a seventh reset stage S9, and a second light emission stage S10, which are set sequentially.

[0161] During the hold frame, NG1 provides a low voltage signal, T2 is disconnected, to control the disconnection between the gate of T0 and the first node N1, so as not to change the potential of the gate of T0;

[0162] In the fourth reset phase S6, PR1 provides a low voltage signal, PG1 provides a high voltage signal, NG2 provides a high voltage signal, PR2 provides a high voltage signal, PG2 provides a high voltage signal, E1 provides a high voltage signal, T1 and T3 are both turned on, and I1 provides a first initial voltage Vi1 to write the first initial voltage Vi1 to the drain of T0; the first initial voltage Vi1 is a positive voltage.

[0163] During the fourth reset phase S6, T4, T5, T6, T7, and T8 are all turned off;

[0164] In the fifth reset phase S7, PR1 provides a high voltage signal, PG1 provides a low voltage signal, NG2 provides a high voltage signal, PR2 provides a high voltage signal, PG2 provides a high voltage signal, E1 provides a high voltage signal, T4 and T3 are both turned on, I2 provides a second initial voltage Vi2, and the second initial voltage Vi2 is written to the drain of T3;

[0165] In the fifth reset phase S7, T1, T5, T6, T7, T8 and T0 are all turned off;

[0166] In the sixth reset phase S8, PR1 provides a high voltage signal, PG1 provides a high voltage signal, NG2 provides a high voltage signal, PR2 provides a low voltage signal, PG2 provides a high voltage signal, E1 provides a high voltage signal, T8 is turned on, and I3 provides a third initial voltage Vi3 to write the third initial voltage Vi3 into the anode of O1 to control O1 from emitting light and to clear the charge remaining in the anode of O1.

[0167] During the sixth reset phase S8, T1, T2, T3, T4, T5, T6, T7, and T0 are all turned off;

[0168] In the seventh reset phase S9, PR1 provides a high voltage signal, PG1 provides a high voltage signal, NG2 provides a high voltage signal, PR2 provides a high voltage signal, PG2 provides a low voltage signal, E1 provides a high voltage signal, T7 is turned on, T3 is turned on, and D1 provides a voltage signal to write the voltage signal to the source of T0.

[0169] In the seventh reset phase S9, T1, T4, T5, T6 and T8 are all turned off;

[0170] In the second light-emitting stage S10, PR1 provides a high voltage signal, PG1 provides a high voltage signal, NG1 provides a low voltage signal, NG2 provides a low voltage signal, PR2 provides a high voltage signal, PG2 provides a high voltage signal, E1 provides a low voltage signal, T5, T6 and T0 are all turned on, and T0 drives O1 to emit light;

[0171] During the second light-emitting stage S10, T1, T2, T3, T4, T7 and T8 are all turned off.

[0172] This disclosure is as follows Figure 5 In at least one embodiment of the pixel circuit shown, T0 can be turned on during the fourth reset phase S6, but this is not a limitation.

[0173] This disclosure is as follows Figure 5 In at least one embodiment of the pixel circuit shown, during operation, in the seventh reset phase, the voltage signal provided by the data line D1 can be a data voltage Vdata, the voltage value range of which can be, for example, greater than or equal to 1V and less than or equal to 6.5V; or,

[0174] In the seventh reset stage, the voltage signal provided by the data line D1 can be a reset voltage signal, and the voltage value range of the reset voltage signal can be greater than or equal to 4.6V and less than or equal to 7V.

[0175] However, this is not the only limit.

[0176] This disclosure is as follows Figure 5In at least one embodiment of the pixel circuit shown, during operation, in the seventh reset phase, T7 is turned on, and the voltage signal provided by the data line D1 is written to the second terminal of the drive circuit 13 to provide a bias voltage to T0, so that T0 is in a biased state to improve the hysteresis phenomenon.

[0177] The driving method described in this embodiment is applied to the pixel circuit described above. The display cycle includes a first reset stage and a second reset stage set sequentially. The driving method includes:

[0178] In the first reset phase, the first reset circuit, under the control of the first reset control signal, writes the first initial voltage provided by the first initial voltage terminal into the first node; the control circuit, under the control of the first control signal, controls the connection between the control terminal of the drive circuit and the first node; the control circuit, under the control of the second control signal, controls the connection between the first node and the first terminal of the drive circuit.

[0179] In the second reset phase, under the control of the first control signal, the control circuit connects the control terminal of the drive circuit with the first node, and under the control of the second control signal, the control circuit connects the first node with the first terminal of the drive circuit.

[0180] In the driving method described in the embodiments of this disclosure, during the first reset stage, the first reset circuit writes a first initial voltage to the first node, and the control circuit controls the connection between the control terminal of the driving circuit and the first node, and controls the connection between the first node and the first terminal of the driving circuit, so that the potential of the control terminal of the driving circuit and the potential of the first terminal of the driving circuit are the first initial voltage, so as to provide a bias voltage to the driving transistor included in the driving circuit, so that the driving transistor included in the driving circuit is in a biased state, improving the hysteresis phenomenon and enhancing the display effect.

[0181] In at least one embodiment of this disclosure, the pixel circuit further includes a second reset circuit; the driving method further includes:

[0182] During the second reset phase, the second reset circuit, under the control of the second reset control signal, writes the second initialization voltage provided by the second initial voltage terminal into the first node so that the drive transistors included in the drive circuit can be turned on when the charging phase begins.

[0183] In at least one embodiment of this disclosure, the pixel circuit further includes an energy storage circuit, a data writing circuit, a first light-emitting control circuit, and a second light-emitting control circuit; the display cycle further includes a charging phase and a first light-emitting phase disposed after the second reset phase; the driving method further includes:

[0184] During the charging phase, the data writing circuit, under the control of the writing control signal, writes the data voltage provided by the data line to the second terminal of the driving circuit. Under the control of the first control signal, the control circuit controls the connection between the control terminal of the driving circuit and the first node. Under the control of the second control signal, the control circuit controls the connection between the first node and the first terminal of the driving circuit.

[0185] At the start of the charging phase, the driving circuit, under the control of the potential of its control terminal, controls the connection between the first terminal and the second terminal of the driving circuit to charge the energy storage circuit through the data voltage, and changes the potential of the control terminal of the driving circuit until the driving circuit controls the disconnection between the first terminal and the second terminal of the driving circuit so as to enable threshold voltage compensation.

[0186] In the first light-emitting stage, the first light-emitting control circuit, under the control of the light-emitting control signal, controls the connection between the first voltage terminal and the second terminal of the driving circuit; the second light-emitting control circuit, under the control of the light-emitting control signal, controls the connection between the first terminal of the driving circuit and the first electrode of the light-emitting element; the driving circuit drives the light-emitting element to emit light.

[0187] In at least one embodiment of this disclosure, the pixel circuit further includes a third reset circuit; the display cycle further includes a third reset phase disposed between the second reset phase and the charging phase; and the driving method further includes:

[0188] In the third reset phase, under the control of the third reset control signal, the third reset circuit writes the third initial voltage provided by the third initial voltage terminal into the first electrode of the light-emitting element to control the light-emitting element to not emit light and to clear the charge remaining in the first electrode of the light-emitting element.

[0189] In at least one embodiment of this disclosure, during low-frequency display, the display time period includes a refresh frame and a hold frame, wherein the refresh frame is the display cycle; and the hold frame includes a fourth reset stage, a fifth reset stage, a sixth reset stage, a seventh reset stage, and a second light-emitting stage that are set sequentially.

[0190] The driving method further includes:

[0191] During the holding frame, under the control of the first control signal provided by the first control terminal, the control circuit controls the control terminal of the drive circuit to disconnect from the first node;

[0192] In the fourth reset phase, the first reset circuit, under the control of the first reset control signal, writes the first initial voltage provided by the first initial voltage terminal into the first node; the control circuit, under the control of the second control signal, controls the connection between the first node and the first terminal of the drive circuit to write the first initial voltage into the first terminal of the drive circuit.

[0193] In the fifth reset phase, the second reset circuit, under the control of the second reset control signal, writes the second initial voltage provided by the second initial voltage terminal into the first node. The control circuit, under the control of the second control signal, controls the connection between the first node and the first terminal of the drive circuit to write the second initial voltage into the first terminal of the drive circuit.

[0194] In the sixth reset phase, under the control of the third reset control signal, the third reset circuit writes the third initial voltage provided by the third initial voltage terminal into the first electrode of the light-emitting element;

[0195] In the seventh reset phase, the data writing circuit, under the control of the write control signal, writes the voltage signal provided by the data line to the second terminal of the drive circuit;

[0196] In the second light-emitting stage, the first light-emitting control circuit, under the control of the light-emitting control signal, controls the connection between the first voltage terminal and the second terminal of the driving circuit; the second light-emitting control circuit, under the control of the light-emitting control signal, controls the connection between the first terminal of the driving circuit and the first electrode of the light-emitting element; the driving circuit drives the light-emitting element to emit light.

[0197] The display device described in this disclosure includes the pixel circuit described above.

[0198] The display device provided in this disclosure can be any product or component with display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigator.

[0199] The above description represents the preferred embodiments of this disclosure. It should be noted that those skilled in the art can make various improvements and modifications without departing from the principles described herein, and these improvements and modifications should also be considered within the scope of protection of this disclosure.

Claims

1. A pixel circuit, comprising a light-emitting element, a first reset circuit, a control circuit, and a driving circuit, wherein, The pixel circuit also includes a second reset circuit, a third reset circuit, and a data writing circuit; The first reset circuit is electrically connected to the first reset control terminal, the first initial voltage terminal, and the first node, respectively, and is used to write the first initial voltage provided by the first initial voltage terminal into the first node under the control of the first reset control signal provided by the first reset control terminal. The control circuit is electrically connected to the first control terminal, the second control terminal, the first node, the control terminal of the drive circuit, and the first terminal of the drive circuit, respectively. It is used to control the connection between the control terminal of the drive circuit and the first node under the control of the first control signal provided by the first control terminal, and to control the connection between the first node and the first terminal of the drive circuit under the control of the second control signal provided by the second control terminal. The first terminal of the driving circuit is electrically connected to the light-emitting element, and the driving circuit is used to drive the light-emitting element to emit light. When displaying at low frequency, the display time period includes refresh frames and hold frames. The refresh frames are the display cycle. The hold frames include a fourth reset stage, a fifth reset stage, a sixth reset stage, and a seventh reset stage, which are set sequentially. The control circuit is used to disconnect the control terminal of the drive circuit from the first node under the control of the first control signal provided by the first control terminal in the holding frame. The first reset circuit is used in the fourth reset phase to write the first initial voltage provided by the first initial voltage terminal into the first node under the control of the first reset control signal. The control circuit is used in the fourth reset phase to control the connection between the first node and the first terminal of the drive circuit under the control of the second control signal, so as to write the first initial voltage into the first terminal of the drive circuit. The second reset circuit is used to write the second initialization voltage provided by the second initial voltage terminal into the first node under the control of the second reset control signal in the fifth reset stage. The control circuit is used to control the connection between the first node and the first terminal of the drive circuit under the control of the second control signal in the fifth reset stage, so as to write the second initialization voltage into the first terminal of the drive circuit. The third reset circuit is used in the sixth reset stage, under the control of the third reset control signal, to write the third initial voltage provided by the third initial voltage terminal into the first electrode of the light-emitting element; The data writing circuit is used, during the seventh reset phase, under the control of the write control signal, to write the voltage signal provided by the data line to the second terminal of the drive circuit.

2. The pixel circuit as described in claim 1, wherein, The second reset circuit is electrically connected to the second reset control terminal, the second initial voltage terminal and the first node respectively, and is used to write the second initial voltage provided by the second initial voltage terminal into the first node under the control of the second reset control signal provided by the second reset control terminal.

3. The pixel circuit as described in claim 1, wherein, It also includes an energy storage circuit, a first light-emitting control circuit, and a second light-emitting control circuit; The first terminal of the energy storage circuit is electrically connected to the control terminal of the drive circuit, and the second terminal of the energy storage circuit is electrically connected to the first voltage terminal. The energy storage circuit is used to store electrical energy. The first light-emitting control circuit is electrically connected to the light-emitting control terminal, the first voltage terminal, and the second terminal of the driving circuit, respectively, and is used to control the connection between the first voltage terminal and the second terminal of the driving circuit under the control of the light-emitting control signal provided by the light-emitting control terminal. The second light-emitting control circuit is electrically connected to the light-emitting control terminal, the first terminal of the driving circuit, and the first electrode of the light-emitting element, respectively, and is used to control the first terminal of the driving circuit and the first electrode of the light-emitting element to be connected under the control of the light-emitting control signal; The data writing circuit is electrically connected to the write control terminal, the data line and the second terminal of the driving circuit, respectively, and is used to write the data voltage provided by the data line to the second terminal of the driving circuit under the control of the write control signal provided by the write control terminal. The second electrode of the light-emitting element is electrically connected to the second voltage terminal.

4. The pixel circuit as described in claim 3, wherein, The third reset circuit is electrically connected to the third reset control terminal, the first electrode of the light-emitting element, and the third initial voltage terminal, respectively, and is used to write the third initial voltage provided by the third initial voltage terminal into the first electrode of the light-emitting element under the control of the third reset control signal provided by the third reset control terminal.

5. The pixel circuit as described in claim 1, wherein, The first reset circuit includes a first transistor; The control electrode of the first transistor is electrically connected to the first reset control terminal, the first electrode of the first transistor is electrically connected to the first initial voltage terminal, and the second electrode of the first transistor is electrically connected to the first node.

6. The pixel circuit as described in claim 1, wherein, The control circuit includes a second transistor and a third transistor; The control electrode of the second transistor is electrically connected to the first control terminal, the first electrode of the second transistor is electrically connected to the first node, and the second electrode of the second transistor is electrically connected to the control terminal of the driving circuit. The control electrode of the third transistor is electrically connected to the second control terminal, the first electrode of the third transistor is electrically connected to the first node, and the second electrode of the third transistor is electrically connected to the first terminal of the driving circuit.

7. The pixel circuit as described in claim 2, wherein, The second reset circuit includes a fourth transistor; The control electrode of the fourth transistor is electrically connected to the second reset control terminal, the first electrode of the fourth transistor is electrically connected to the second initial voltage terminal, and the second electrode of the fourth transistor is electrically connected to the first node.

8. The pixel circuit as described in claim 3, wherein, The energy storage circuit includes a storage capacitor; the first light-emitting control circuit includes a fifth transistor; the second light-emitting control circuit includes a sixth transistor; the driving circuit includes a driving transistor; and the data writing circuit includes a seventh transistor. The control electrode of the fifth transistor is electrically connected to the light-emitting control terminal, the first electrode of the fifth transistor is electrically connected to the first voltage terminal, and the second electrode of the fifth transistor is electrically connected to the second terminal of the driving circuit. The control electrode of the sixth transistor is electrically connected to the light-emitting control terminal, the first electrode of the sixth transistor is electrically connected to the first terminal of the driving circuit, and the second electrode of the sixth transistor is electrically connected to the first electrode of the light-emitting element. The control electrode of the seventh transistor is electrically connected to the write control terminal, the first electrode of the seventh transistor is electrically connected to the data line, and the second electrode of the seventh transistor is electrically connected to the second terminal of the drive circuit. The first end of the storage capacitor is electrically connected to the control terminal of the driving circuit, and the second end of the storage capacitor is electrically connected to the first voltage terminal. The control terminal of the driving transistor is the control terminal of the driving circuit, the first terminal of the driving transistor is the first terminal of the driving circuit, and the second terminal of the driving transistor is the second terminal of the driving circuit.

9. The pixel circuit as described in claim 4, wherein, The third reset circuit includes an eighth transistor; The control electrode of the eighth transistor is electrically connected to the third reset control terminal, the first electrode of the eighth transistor is electrically connected to the third initial voltage terminal, and the second electrode of the eighth transistor is electrically connected to the first electrode of the light-emitting element.

10. A driving method applied to a pixel circuit according to any one of claims 1 to 9, wherein the display cycle includes a first reset phase and a second reset phase set sequentially, the driving method comprising: In the first reset phase, the first reset circuit, under the control of the first reset control signal, writes the first initial voltage provided by the first initial voltage terminal into the first node; Under the control of the first control signal, the control circuit connects the control terminal of the drive circuit with the first node; under the control of the second control signal, the control circuit connects the first node with the first terminal of the drive circuit. In the second reset phase, under the control of the first control signal, the control circuit connects the control terminal of the drive circuit with the first node, and under the control of the second control signal, the control circuit connects the first node with the first terminal of the drive circuit. When displaying at low frequency, the display time period includes refresh frames and hold frames, wherein the refresh frames are the display cycle; the hold frames include a fourth reset stage, a fifth reset stage, a sixth reset stage, and a seventh reset stage set sequentially. The pixel circuit also includes a second reset circuit, a third reset circuit, and a data writing circuit; The driving method further includes: During the holding frame, under the control of the first control signal provided by the first control terminal, the control circuit controls the control terminal of the drive circuit to disconnect from the first node; In the fourth reset phase, the first reset circuit, under the control of the first reset control signal, writes the first initial voltage provided by the first initial voltage terminal into the first node; the control circuit, under the control of the second control signal, controls the connection between the first node and the first terminal of the drive circuit to write the first initial voltage into the first terminal of the drive circuit. In the fifth reset phase, the second reset circuit, under the control of the second reset control signal, writes the second initial voltage provided by the second initial voltage terminal into the first node. The control circuit, under the control of the second control signal, controls the connection between the first node and the first terminal of the drive circuit to write the second initial voltage into the first terminal of the drive circuit. In the sixth reset phase, under the control of the third reset control signal, the third reset circuit writes the third initial voltage provided by the third initial voltage terminal into the first electrode of the light-emitting element; In the seventh reset phase, the data writing circuit, under the control of the write control signal, writes the voltage signal provided by the data line to the second terminal of the drive circuit.

11. The driving method as described in claim 10, wherein, The driving method further includes: During the second reset phase, the second reset circuit, under the control of the second reset control signal, writes the second initialization voltage provided by the second initial voltage terminal into the first node.

12. The driving method as described in claim 11, wherein, The pixel circuit further includes an energy storage circuit, a first light-emitting control circuit, and a second light-emitting control circuit; the display cycle further includes a charging phase and a first light-emitting phase disposed after the second reset phase; the driving method further includes: During the charging phase, the data writing circuit, under the control of the writing control signal, writes the data voltage provided by the data line to the second terminal of the driving circuit. Under the control of the first control signal, the control circuit controls the connection between the control terminal of the driving circuit and the first node. Under the control of the second control signal, the control circuit controls the connection between the first node and the first terminal of the driving circuit. At the start of the charging phase, the drive circuit, under the control of the potential of its control terminal, controls the connection between the first terminal and the second terminal of the drive circuit to charge the energy storage circuit through the data voltage, and changes the potential of the control terminal of the drive circuit until the drive circuit controls the disconnection between the first terminal and the second terminal of the drive circuit. In the first light-emitting stage, the first light-emitting control circuit, under the control of the light-emitting control signal, controls the connection between the first voltage terminal and the second terminal of the driving circuit; the second light-emitting control circuit, under the control of the light-emitting control signal, controls the connection between the first terminal of the driving circuit and the first electrode of the light-emitting element; the driving circuit drives the light-emitting element to emit light.

13. The driving method as described in claim 12, wherein, The display cycle further includes a third reset phase disposed between the second reset phase and the charging phase, and the driving method further includes: During the third reset phase, the third reset circuit, under the control of the third reset control signal, writes the third initial voltage provided by the third initial voltage terminal into the first electrode of the light-emitting element.

14. The driving method as described in claim 13, wherein, The holding frame includes a second emission phase set after the seventh reset phase; The driving method further includes: In the second light-emitting stage, the first light-emitting control circuit, under the control of the light-emitting control signal, controls the connection between the first voltage terminal and the second terminal of the driving circuit; the second light-emitting control circuit, under the control of the light-emitting control signal, controls the connection between the first terminal of the driving circuit and the first electrode of the light-emitting element; the driving circuit drives the light-emitting element to emit light.

15. A display device comprising a pixel circuit as claimed in any one of claims 1 to 9.

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