Method for processing silicon islands in pressure-sensitive chip, pressure-sensitive chip and manufacturing method thereof, and pressure sensor
Patent Information
- Application Number
- CN202311440230.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2023-10-31
- Publication Date
- 2026-10-20
- Estimated Expiration
- 2043-10-31
AI Technical Summary
[0056](1)针对现有加工方法难以有效控制硅岛高度和重量等不足，以及由此导致的硅岛高度较高、重量较大，芯片在高频环境下存在波动干扰等缺陷，本发明中创造性的提出了一种压力敏感芯片中硅岛的加工方法，根据硅岛的设定高度，先在硅片背面制备合适厚度的氧化硅层，然后在氧化硅层上制备光刻胶，并通过曝光显影，去除部分光刻胶，由此在硅片背面的氧化硅层上形成回形区域，进而其他区域在光刻胶的保护下，依次对硅片背面回形区域内的氧化硅和硅进行刻蚀，通过去除回形区域内的氧化硅和硅，在硅片内形成回形凹槽，进一步的，去除硅片背面剩余光刻胶后，继续在硅片背面制备光刻胶，曝光显影，去除回形凹槽内的光刻胶，由此在回形凹槽的区域内形成口形区域，最后对口形区域内的氧化硅和硅进行刻蚀，同时去除口形区域内的氧化硅和硅，在此过程中，利用硅的刻蚀速率大于氧化硅的刻蚀速率的特点以及氧化硅层的设定厚度，调控硅岛的高度，当氧化硅层被去除干净后，即可形成设定高度的硅岛，与此同时，当氧化硅层被去除干净后，口形区域内只有硅材料，因而在刻蚀后期只对单一的硅材料进行刻蚀，此时由于硅岛底部和顶部的刻蚀速率相同，由此能够使硅岛的形状和高度保持不变，进而在保持硅岛形状和高度不变的前提下能够使硅片整体往下刻蚀(向内刻蚀)，直至刻蚀到膜片设定的厚度，去除硅片背面的光刻胶，完成对硅岛的加工，得到E形膜片。本发明加工方法，可根据硅岛高度的设定值，先在硅片背面沉积合适厚度的氧化硅层，进而在光刻胶的保护作用下，对口形区域内的氧化硅层和硅进行刻蚀，获得高度和质量可控的硅岛，从而有利于获得硅岛高度低且重量小、抗力冲击能力强的E形膜片，对于制备加速度敏感性低、测量稳定性好的压力敏感芯片具有重要意义。
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Abstract
Description
Technical Field
[0001] This invention belongs to the field of pressure-sensitive chip manufacturing, and relates to a method for processing silicon islands in a pressure-sensitive chip, a pressure-sensitive chip and its manufacturing method, and a pressure sensor. Background Technology
[0002] In the fabrication of pressure-sensitive chips, there are two main processing techniques for silicon islands on E-shaped diaphragms:
[0003] The first processing method involves coating the back of the silicon wafer with adhesive in one step, followed by photolithography to create a ring-shaped surface to be etched. Then, deep silicon dry etching is used to reach the required depth, forming a ring-shaped deep cavity, thus completing the fabrication of the silicon island. Figure 1 and Figure 2 As shown, in the prepared E-shaped diaphragm, the silicon island surface and the chip support surface are on the same plane. It is evident that the prepared silicon island still has shortcomings such as high height and heavy weight, which can easily lead to defects such as fluctuation interference in the chip under high-frequency environments. Furthermore, when using the aforementioned E-shaped diaphragm to fabricate pressure-sensitive chips, it needs to be anoly bonded to the support surface for pressure sensing, or directly adhered to the support surface. Therefore, to ensure that the silicon diaphragm deforms under pressure, the silicon island must have a free space, typically ranging from 2µm to 10µm. This requires a shallow groove of 2µm to 10µm on the support surface, meaning the support surface needs to be processed. However, the support materials are mainly metals, glass, and other materials. If it is a metal material, machining is required; if it is a glass material, laser processing is required. Obviously, this processing scheme requires additional processing equipment, easily increasing processing costs, resulting in a significant increase in chip manufacturing costs.
[0004] The second processing method involves first applying a resist to the entire back of the silicon wafer, followed by a first photolithography process to etch a square surface to be etched. Then, shallow grooves of 10µm to 20µm are etched using a dry etching method. After removing the resist, a second resist application is performed, followed by a second photolithography process. After development, a ring-shaped surface to be etched is exposed. Finally, under the protection of the photoresist, the ring-shaped surface is deeply etched to complete the silicon island fabrication. Figure 3 and Figure 4 As shown, although this processing method can form a shallow trench on the back of the silicon wafer, the depth of this trench cannot exceed 20µm. This is because if the trench depth exceeds 20µm, existing photoresist coating processes will struggle to form a complete or smooth photoresist layer on the back of the silicon wafer, making subsequent processes impossible. Therefore, the second processing method still suffers from the drawback of difficulty in reducing the height and weight of the silicon island. Consequently, it can also easily lead to defects such as fluctuation interference in high-frequency environments, affecting the normal output of the chip.
[0005] It is evident that existing processing methods for E-shaped diaphragm silicon islands still struggle to effectively control the island's height and weight, making it difficult to obtain silicon islands with controllable height and weight. This results in chips being more susceptible to fluctuations and interference in high-frequency environments, and their resistance to mechanical shock is inferior to that of C-shaped diaphragms. These drawbacks are particularly pronounced in the fabrication of small-range and small-volume chips. Therefore, effectively controlling the height and weight of silicon islands is crucial for obtaining E-shaped diaphragms that are low in height, lightweight, and highly resistant to shock, as well as for fabricating pressure-sensitive chips with low acceleration sensitivity and good measurement stability. Summary of the Invention
[0006] The technical problem to be solved by the present invention is to address the shortcomings of the prior art by providing a method for processing silicon islands in a pressure-sensitive chip with controllable silicon island height and weight, as well as a pressure-sensitive chip with low acceleration sensitivity, good measurement stability, and easy packaging, and a matching manufacturing method with simple processes, fewer steps, and easy quality control, and a pressure sensor composed of the pressure-sensitive chip.
[0007] To solve the above-mentioned technical problems, the present invention adopts the following technical solution.
[0008] A method for fabricating silicon islands in a pressure-sensitive chip includes the following steps:
[0009] (1) Clean the SOI silicon wafer used to fabricate pressure-sensitive chips;
[0010] (2) Prepare a SiO2 layer on the back side of the SOI silicon wafer;
[0011] (3) Photoresist is prepared on the SiO2 layer on the back side of the SOI silicon wafer, and exposed and developed to form a loop-shaped area on the back side of the SOI silicon wafer.
[0012] (4) Etch the SiO2 layer in the loop area on the back side of the SOI silicon wafer to form a loop groove on the back side of the SOI silicon wafer;
[0013] (5) Remove the photoresist from the back of the SOI silicon wafer;
[0014] (6) Prepare photoresist on the back side of SOI silicon wafer, expose and develop, remove photoresist in the back groove area of SOI silicon wafer, and form a mouth-shaped area in the area of the back groove.
[0015] (7) Etch the Si in the mouth-shaped area on the back of the SOI silicon wafer to form a silicon island on the back of the SOI silicon wafer;
[0016] (8) Remove the photoresist on the back of the SOI silicon wafer to complete the processing of the silicon island.
[0017] In a further improvement to the above processing method, in step (1), the thickness of the top silicon layer in the SOI silicon wafer is 0.3um to 2um.
[0018] The above processing method is further improved by step (2) using thermal oxidation, PECVD or LPCVD to prepare a SiO2 layer on the back side of the SOI silicon wafer; the process parameters of the thermal oxidation process are: process gas is O2 and temperature is 900℃.
[0019] The above processing method is further improved in step (4) by using ICP etching process to etch the SiO2 layer in the loop area on the back side of the SOI silicon wafer; the process parameters of the ICP etching process are: the process gas is CH3F.
[0020] In a further improvement to the above processing method, in step (7), the Si in the aperture region on the back side of the SOI silicon wafer is etched using the DRIE etching process; the etching rate of Si during the etching process is 500nm / min to 700nm / min; the etching process also includes etching the SiO2 layer on the back side, and the etching rate ratio of the Si to the SiO2 layer is 70 to 100:1; the height of the silicon island is 70μm.
[0021] As a general technical concept, the present invention provides a method for manufacturing a pressure-sensitive chip, comprising the following steps:
[0022] S1. Clean the SOI silicon wafer;
[0023] S2. Prepare photoresist on the front side of the SOI silicon wafer, expose and develop it, and retain the photoresist on the front side of the silicon wafer where the resistor strips and interconnects are located.
[0024] S3. Etch the area on the front side of the SOI silicon wafer that is not covered with photoresist.
[0025] S4. Remove the photoresist from the resistor strips and interconnects;
[0026] S5. Prepare SiO2 layers on both sides of the SOI silicon wafer;
[0027] S6. Prepare photoresist on the front side of the SOI silicon wafer, expose and develop it, and make windows in the areas on the resistor strip where interconnects and ohmic contacts need to be made.
[0028] S7. Remove the silicon oxide layer from the areas where interconnects and ohmic contacts need to be fabricated;
[0029] S8. Remove the photoresist from the surface of the unopened area;
[0030] S9. Prepare photoresist on the front side of the SOI silicon wafer, expose and develop it, and make windows in the area on the resistor strip where interconnects and ohmic contacts need to be made, so that the area of the windowed area is larger than the windowed area in step S6.
[0031] S10. Fabricate an electrode metal layer on the front side of the SOI silicon wafer;
[0032] S11. Remove the photoresist from the surface of the unopened area, and perform heat treatment on the remaining electrode metal layer to complete the fabrication of the ohmic contact electrode.
[0033] S12. Photoresist is prepared on the SiO2 layer on the back side of the SOI silicon wafer, and exposed and developed to form a loop-shaped area on the back side of the SOI silicon wafer.
[0034] S13. Etch the SiO2 layer in the loop-shaped area on the back of the SOI silicon wafer to form a loop-shaped groove on the back of the SOI silicon wafer.
[0035] S14. Remove the photoresist from the back of the SOI silicon wafer;
[0036] S15. Prepare photoresist on the back side of the SOI silicon wafer, expose and develop it to form a mouth-shaped area in the area of the groove on the back side of the SOI silicon wafer.
[0037] S16. Etch the Si in the orifice region on the back of the SOI silicon wafer to form a silicon island on the back of the SOI silicon wafer;
[0038] S17. Remove the photoresist on the back of the SOI silicon wafer to complete the fabrication of the pressure-sensitive chip.
[0039] In a further improvement to the above-described fabrication method, in step S1, the thickness of the top silicon layer in the SOI silicon wafer is 0.3µm to 2µm.
[0040] In a further improvement to the above-mentioned manufacturing method, in step S3, the dry etching process or wet etching process is used to etch the area on the front side of the SOI silicon wafer that is not covered with photoresist until the silicon oxide layer is exposed.
[0041] In a further improvement to the above-mentioned manufacturing method, in step S4, acetone is used to clean the photoresist on the resistor strip and interconnects to remove the photoresist from the resistor strip and interconnects.
[0042] In a further improvement to the above-described fabrication method, in step S5, an LPCVD process is used to prepare a SiO2 layer on the front side of the SOI silicon wafer, so that the surface and sides of the resistor strip and interconnects are covered with a silicon oxide layer; the process parameters of the LPCVD process are: process gas is O2, and temperature is 900℃; a thermal oxidation process, PECVD, or LPCVD process is used to prepare a SiO2 layer on the back side of the SOI silicon wafer; the process parameters of the thermal oxidation process are: process gas is O2, and temperature is 900℃.
[0043] In a further improvement to the above-mentioned manufacturing method, in step S7, a dry etching process is used to etch the area on the front side of the SOI silicon wafer that is not covered with photoresist to remove the silicon oxide layer until the resistor strip and interconnect lines are exposed.
[0044] In a further improvement to the above-mentioned fabrication method, in step S8, acetone is used to clean the photoresist on the surface of the unwindowed area on the front side of the SOI silicon wafer, thereby removing the photoresist from the unwindowed area.
[0045] In a further improvement to the above-described manufacturing method, in step S10, the electrode metal layer includes at least one of titanium and gold.
[0046] In a further improvement to the above-described fabrication method, in step S11, the photoresist on the surface of the unopened area is removed by peeling, while retaining the electrode metal layer in the area where interconnects and ohmic contacts need to be fabricated.
[0047] In a further improvement to the above-mentioned fabrication method, in step S13, the SiO2 layer in the loop-shaped area on the back side of the SOI silicon wafer is etched using an ICP etching process; the process parameters of the ICP etching process are: the process gas is CH3F.
[0048] In a further improvement to the above-described fabrication method, in step S16, the Si in the aperture-shaped region on the back side of the SOI silicon wafer is etched using the DRIE etching process; the etching rate of Si during the etching process is 500 nm / min to 700 nm / min; the etching process also includes etching the SiO2 layer on the back side, and the etching rate ratio of the Si to the SiO2 layer is 70 to 100:1; the height of the silicon island is 70 μm.
[0049] In a further improvement to the above-mentioned fabrication method, in step S17, acetone is used to clean the photoresist on the back of the SOI silicon wafer, thereby removing the photoresist from the back of the SOI silicon wafer.
[0050] As a general technical concept, the present invention also provides a pressure-sensitive chip comprising a silicon island fabricated by the above-described processing method.
[0051] As a general technical concept, the present invention also provides a pressure-sensitive chip, which is prepared by the above-described manufacturing method.
[0052] As a general technical concept, the present invention also provides a pressure sensor, which includes the pressure-sensitive chip described above.
[0053] In a further improvement to the aforementioned pressure sensor, a support body is provided on the back of the pressure-sensitive chip; a stress reference cavity is formed between the pressure-sensitive chip and the support body.
[0054] In a further improvement of the aforementioned pressure sensor, the support body is a bonded glass sheet or a bonded silicon sheet.
[0055] Compared with the prior art, the advantages of the present invention are as follows:
[0056] (1) To address the shortcomings of existing processing methods in effectively controlling the height and weight of silicon islands, and the resulting high height and weight of silicon islands, leading to fluctuations and interference in the chip under high-frequency environments, this invention creatively proposes a processing method for silicon islands in pressure-sensitive chips. Based on the set height of the silicon island, a silicon oxide layer of appropriate thickness is first prepared on the back side of the silicon wafer. Then, photoresist is prepared on the silicon oxide layer, and through exposure and development, part of the photoresist is removed, thereby forming a loop-shaped region on the silicon oxide layer on the back side of the silicon wafer. Subsequently, under the protection of the photoresist, the silicon oxide and silicon in the loop-shaped region on the back side of the silicon wafer are etched sequentially. By removing the silicon oxide and silicon in the loop-shaped region, a loop-shaped groove is formed within the silicon wafer. Further, after removing the remaining photoresist on the back side of the silicon wafer, photoresist is prepared again on the back side of the silicon wafer, and through exposure and development, the photoresist in the loop-shaped groove is removed. This creates an indentation within the recessed area. The silicon oxide and silicon within this indentation are then etched away. During this process, the etching rate of silicon is greater than that of silicon oxide, and the set thickness of the silicon oxide layer is used to control the height of the silicon island. Once the silicon oxide layer is completely removed, a silicon island of the set height is formed. Simultaneously, after the silicon oxide layer is completely removed, only silicon material remains within the indentation. Therefore, in the later stages of etching, only the single silicon material is etched. Since the etching rates at the bottom and top of the silicon island are the same, the shape and height of the silicon island remain unchanged. This allows the silicon wafer to be etched downwards (inwards) while maintaining the shape and height of the silicon island, until the set thickness of the film is reached. The photoresist on the back of the silicon wafer is then removed, completing the processing of the silicon island and obtaining an E-shaped film. The processing method of this invention can first deposit a silicon oxide layer of appropriate thickness on the back of the silicon wafer according to the set value of the silicon island height, and then etch the silicon oxide layer and silicon in the aperture area under the protection of photoresist to obtain a silicon island with controllable height and quality. This is beneficial for obtaining an E-shaped film with low silicon island height, light weight and strong impact resistance, which is of great significance for the preparation of pressure-sensitive chips with low acceleration sensitivity and good measurement stability.
[0057] (2) To address the shortcomings of existing manufacturing methods, such as difficulty in effectively controlling the height and weight of silicon islands, and the resulting defects in E-shaped films, such as high silicon island height, heavy weight, poor resistance to mechanical impact, and fluctuation interference in high-frequency environments, this invention creatively proposes a method for manufacturing pressure-sensitive chips. First, photoresist is applied to the surface of the silicon wafer except for the resistor strips and interconnects. Under the protection of the photoresist, silicon material in other areas is removed until the silicon oxide layer is exposed. Then, the photoresist on the resistor strips and interconnects is removed. Based on the set height of the silicon island, silicon oxide layers of appropriate thickness are prepared on both sides of the silicon wafer. Ohmic contact electrodes are then prepared on the front side of the silicon wafer. After the front electrode preparation is completed, photoresist is prepared on the silicon oxide layer on the back side of the silicon wafer. Through exposure and development, some photoresist is removed, thereby forming a loop-shaped area on the silicon oxide layer on the back side of the silicon wafer. Further, under the protection of the photoresist, the silicon oxide and silicon in the loop-shaped area on the back side of the silicon wafer are etched sequentially. By removing the silicon oxide and silicon in the loop-shaped area, the silicon... A recessed groove is formed within the wafer. Further, the remaining photoresist on the back of the silicon wafer is removed, and more photoresist is prepared on the back of the wafer. Through exposure and development, the photoresist within the recessed groove is removed, thus forming a chamfered area within the recessed region. Finally, the silicon oxide and silicon within the chamfered area are etched, while simultaneously removing the silicon oxide and silicon within the chamfered area. During this process, the height of the silicon island is controlled by utilizing the characteristic that the etching rate of silicon is greater than that of silicon oxide, and the set thickness of the silicon oxide layer. Once the silicon oxide layer is completely removed, a silicon island of the set height is formed. Simultaneously, after the silicon oxide layer is completely removed, only silicon material remains within the chamfered area. Therefore, in the later stages of etching, only the single silicon material is etched. Since the etching rates at the bottom and top of the silicon island are the same, the shape and height of the silicon island remain unchanged. Thus, while maintaining the shape and height of the silicon island, the entire silicon wafer can be etched downwards (inwards) until the set thickness of the film is reached. The photoresist on the back of the silicon wafer is then removed, completing the fabrication of the pressure-sensitive chip. The manufacturing method of this invention involves depositing a silicon oxide layer of appropriate thickness on the back of a silicon wafer according to a set value for the height of the silicon island. Then, under the protection of photoresist, the silicon oxide layer and silicon in the aperture area are etched to obtain a silicon island with controllable height and quality. This is beneficial for obtaining an E-shaped diaphragm with low silicon island height, light weight, and strong impact resistance, as well as reducing acceleration sensitivity and improving the stability of pressure measurement. The pressure-sensitive chip obtained in this way has the advantages of low acceleration sensitivity, good measurement stability, and easy packaging, which is of great significance for obtaining pressure sensors with strong anti-interference capabilities. Attached Figure Description
[0058] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings.
[0059] Figure 1 This is a schematic diagram of an existing pressure-sensitive chip without shallow grooves.
[0060] Figure 2 A schematic diagram of the structure of a pressure sensor constructed from an existing pressure-sensitive chip that does not have a shallow groove.
[0061] Figure 3 This is a schematic diagram of an existing pressure-sensitive chip with shallow grooves.
[0062] Figure 4 A schematic diagram of the structure of a pressure sensor constructed from an existing pressure-sensitive chip with shallow grooves.
[0063] Figure 5 This is a schematic diagram of the fabrication process of the silicon island in the pressure-sensitive chip in Embodiment 1 of the present invention.
[0064] Figure 6 This is a schematic diagram of the manufacturing process of the pressure-sensitive chip in Embodiment 2 of the present invention.
[0065] Figure 7 This is a schematic diagram of the front structure of the silicon wafer in Embodiment 2 of the present invention.
[0066] Figure 8 This is a schematic diagram of the structure of the back side of the silicon wafer in Embodiment 2 of the present invention.
[0067] Figure 9 This is a schematic diagram of the pressure sensor in Embodiment 2 of the present invention. Detailed Implementation
[0068] The present invention will be further described below with reference to the accompanying drawings and specific preferred embodiments, but this does not limit the scope of protection of the present invention.
[0069] The materials and instruments used in the following examples are all commercially available.
[0070] Example 1
[0071] A method for fabricating silicon islands in a pressure-sensitive chip, the process flow diagram of which is shown below. Figure 5 As shown, it includes the following steps:
[0072] (1) Clean the SOI silicon wafer used to fabricate the pressure-sensitive chip. The thickness of the top silicon layer in the SOI silicon wafer is 1µm.
[0073] (2) A SiO2 layer is prepared on the back side of the silicon wafer. Specifically, a SiO2 layer is deposited on the back side of the silicon wafer using a thermal oxidation process. The process parameters for the thermal oxidation process are: the process gas is O2, and the temperature is 900℃. The thickness of the SiO2 layer is calculated based on the etching rate ratio of SiO2 to Si and the required height of the final silicon island. Specifically, in this embodiment, the thickness of the SiO2 layer is 700nm. Other preparation processes, such as PECVD or LPCVD, can also be used to prepare the SiO2 layer.
[0074] (3) Coat the silicon oxide layer on the back of the silicon wafer with photoresist, expose and develop it to remove part of the photoresist, and form a loop-shaped area on the back of the silicon wafer. There is no photoresist in the loop-shaped area, while other areas (including the area where the silicon island is located) have photoresist.
[0075] (4) Under the protection of photoresist, the SiO2 layer in the loop-shaped area on the back of the silicon wafer is etched and over-etched using ICP etching (i.e., inductively coupled plasma etching). The process gas used in the etching process is CH3F. The silicon oxide layer and silicon material on the back of the silicon wafer are removed, forming a loop-shaped groove with a depth of 70 μm in the silicon wafer. The silicon island is located in the middle of the loop-shaped groove. In this step, the Si etching depth is calculated and determined by the etching rate of Si, the etching rate of SiO2, the thickness of SiO2, and the target height of the silicon island.
[0076] (5) Use acetone to clean and remove the photoresist on the back of the silicon wafer.
[0077] (6) Coat the back of the silicon wafer with photoresist, expose and develop it to remove all photoresist (including photoresist on the surface of the silicon island) in the area of the groove on the back of the silicon wafer, and form an apex-shaped area within the area of the groove, that is, the area of the apex-shaped area is smaller than that of the groove area.
[0078] (7) The Si in the aperture area on the back of the silicon wafer is etched using the DRIE etching process (deep reactive ion etching process). In the early stage of etching, the top surface of the silicon island is a silicon oxide layer and the surrounding area is silicon. During this etching process, silicon oxide and silicon are etched at the same time. However, since the etching rate of Si is faster than that of SiO2, the silicon material can be removed more quickly. That is, by utilizing the difference in etching rates between silicon and silicon oxide, a silicon island of a certain height can be formed. At the same time, combined with a silicon oxide layer of a set thickness, a silicon island with controllable height can be obtained. Furthermore, in the later stage of etching, since the silicon oxide layer is relatively thin, after a period of etching, the silicon oxide layer is completely removed. At this time, only silicon material remains in the aperture area. That is, the top surface and surrounding area of the silicon island are silicon. At the same time, since the etching rate is the same, during this etching process, not only can the height and shape of the silicon island remain unchanged, but the entire silicon wafer can be etched downwards until the thickness set by the E-shaped film is reached, thereby forming a silicon island on the back of the silicon wafer. Specifically, during the etching of Si in the shaped region on the back side of the silicon wafer using the DRIE etching process, the etching rate of Si is 700 nm / min. This process parameter also etches SiO2. The etching rate ratio of Si to SiO2 is 100:1. Therefore, when the thickness of the SiO2 layer is 700 nm, after 100 min of etching, the SiO2 is completely etched away, and 70 μm of Si is also etched away, thus forming a silicon island with a height of 70 μm.
[0079] (8) Use acetone to remove the photoresist on the back of the silicon wafer to complete the processing of the silicon island.
[0080] The processing method of this invention can first deposit a silicon oxide layer of appropriate thickness on the back of the silicon wafer according to the set value of the silicon island height, and then etch the silicon oxide layer and silicon in the aperture area under the protection of photoresist to obtain a silicon island with controllable height and quality. This is beneficial for obtaining an E-shaped film with low silicon island height, light weight and strong impact resistance, which is of great significance for the preparation of pressure-sensitive chips with low acceleration sensitivity and good measurement stability.
[0081] Example 2
[0082] A method for fabricating a pressure-sensitive chip, the process flow diagram of which is shown below. Figure 6 As shown, it includes the following steps:
[0083] S1. Clean the SOI silicon wafer, the thickness of the top silicon layer in the SOI silicon wafer is 1um.
[0084] S2. Coat the top silicon surface of the SOI silicon wafer with photoresist, expose and develop it, and cover the resistor strips and interconnects with photoresist.
[0085] S3. Use a dry etching process to etch the top silicon layer that is not covered with photoresist, remove the top silicon layer until the SiO2 layer is exposed. At this time, only the varistor strip and interconnects covered with photoresist remain on the SiO2 surface.
[0086] S4. Use acetone to clean the photoresist on the resistor strip and interconnects. Once the photoresist is cleaned, only the varistor strip and interconnects remain on the SiO2 surface.
[0087] S5. An SiO2 layer is deposited on the front side of the cleaned and desizing silicon wafer using LPCVD. A SiO2 layer is then deposited on the back side of the silicon wafer using thermal oxidation. At this point, the resistor strips and interconnects are surrounded by a SiO2 layer, and the back side of the silicon wafer is also covered. In this step, the process parameters for thermal oxidation are: process gas is O2, temperature is 900℃, and the thickness of the SiO2 layer on the back side is calculated based on the etching rate ratio of SiO2 to Si and the required final height of the silicon island. Specifically, in this embodiment, the thickness of the SiO2 layer is 700 nm. Other fabrication processes, such as PECVD or LPCVD, can also be used to prepare the SiO2 layer.
[0088] S6. Coat the front side of the silicon wafer with photoresist, expose and develop it, and open windows in the areas on the resistor strip where interconnects and ohmic contacts need to be made, and remove the photoresist in those areas.
[0089] S7. Use a dry etching process to etch the SiO2 layer in the windowed area where there is no photoresist coverage, removing the SiO2 in the uncoated areas. After etching, use acetone to clean away the photoresist. This step prepares for subsequent processes to fabricate metal interconnects and ohmic contact holes.
[0090] S8. Coat the front side of the silicon wafer with photoresist, expose and develop it, and make a window in the area on the resistor strip where interconnects and ohmic contacts need to be made. Remove the photoresist in this area. The windowed area is larger than the area etched in step S6.
[0091] S9. Deposit a metal layer (such as a Ti layer or Au layer) on the entire surface of the silicon wafer to fabricate the electrodes. Remove the photoresist by peeling, leaving the metal layer. Alloy the metal layer through heat treatment to complete the fabrication of the ohmic contact electrode. At this point, a schematic diagram of the front side of the silicon wafer is shown below. Figure 7 As shown.
[0092] S10. Apply photoresist to the back side of the silicon wafer, perform exposure and development, remove part of the photoresist, and form a "loop"-shaped region on the back side of the silicon wafer, where no photoresist is present in the "loop"-shaped region, and photoresist remains in all other regions (including the region where the silicon island is located). Then, under the protection of the photoresist, the SiO₂ layer within the loop-shaped region on the back side of the silicon wafer is etched and overetched using an ICP etching process (i.e., inductively coupled plasma etching process), wherein the process gas used during the etching process is CH₃F, the silicon oxide layer and silicon material on the back side of the silicon wafer are removed, a loop-shaped groove with a depth of 70 μm is formed in the silicon wafer, and the position of the silicon island is in the middle of the loop-shaped groove. In this step, the Si etching depth is calculated and determined based on the etching rate of the equipment for Si, the etching rate for SiO₂, the thickness of SiO₂, and the target height of the silicon island.
[0093] S11. The photoresist on the back side of the silicon wafer is cleaned off using acetone.
[0094] S12. Apply photoresist to the back side of the silicon wafer, perform exposure and development, remove all photoresist within the loop-shaped groove region on the back side of the silicon wafer (including the photoresist on the surface of the silicon island), and form a "square"-shaped region within the scope of the loop-shaped groove region, that is, the area of the "square"-shaped region is smaller than that of the "loop"-shaped region.
[0095] S13. Use a DRIE etching process (deep reactive ion etching process) to etch the Si in the "square"-shaped region. In the early stage of etching, the top surface of the silicon island is a silicon oxide layer, and the surrounding sides are silicon. During this etching process, both silicon oxide and silicon are etched at the same time. However, since the etching rate of the process for Si is faster than the etching rate for SiO₂, the silicon material can be removed more quickly. That is, by utilizing the etching rate difference between silicon and silicon oxide, a silicon island with a certain height can be formed, and in combination with the silicon oxide layer of a set thickness, a silicon island with a controllable height can be obtained. Further, in the later stage of etching, since the silicon oxide layer is relatively thin, the silicon oxide layer is completely removed after a period of etching. At this time, only silicon material remains in the square-shaped region, that is, both the top surface and the surrounding sides of the silicon island are silicon. Meanwhile, since the etching rates are the same, during this etching process, not only can the height and shape of the silicon island be kept unchanged, but also the entire silicon wafer can be etched downward until the set thickness of the E-shaped diaphragm is reached, thereby forming the silicon island on the back side of the silicon wafer. Specifically, during the process of etching the Si in the square-shaped region on the back side of the silicon wafer using the DRIE etching process, the etching rate of Si is 700 nm / min. This process parameter will also etch SiO₂ at the same time, and the etching rate ratio of Si to SiO₂ is 100:1. Therefore, when the thickness of the SiO₂ layer is 700 nm, after 100 minutes of etching, the SiO₂ is completely etched away, and at the same time, 70 μm of Si is etched off, thereby forming a silicon island with a height of 70 μm.
[0096] S14. After etching, acetone is used to clean and remove the photoresist on the back of the silicon wafer. At this point, the structural diagram of the back of the silicon wafer is shown in the figure. Figure 8 As shown, the fabrication of the pressure-sensitive chip is complete.
[0097] like Figure 9 As shown, the back side of the pressure-sensitive chip fabricated in this embodiment is bonded to glass (support), forming a stress reference cavity between the pressure-sensitive chip and the glass, thereby constructing a pressure sensor. (Comparison) Figure 4 and Figure 9 As can be seen, the height of the silicon island in this pressure sensor is significantly smaller than that of conventional pressure sensors.
[0098] The manufacturing method of this invention involves depositing a silicon oxide (SiO2) layer of appropriate thickness on the back of a silicon wafer according to a set value for the silicon island height. Then, under the protection of photoresist, the silicon oxide layer and silicon in the aperture-shaped area are etched to obtain a silicon island with controllable height and quality. This is beneficial for obtaining an E-shaped diaphragm with low silicon island height, light weight, and strong impact resistance, as well as reducing acceleration sensitivity and improving the stability of pressure measurement. The pressure-sensitive chip obtained in this way has advantages such as low acceleration sensitivity, good measurement stability, and easy packaging, which is of great significance for obtaining pressure sensors with strong anti-interference capabilities.
[0099] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention in any way. Although the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make many possible variations and modifications to the technical solutions of the present invention using the methods and techniques disclosed above, or modify them into equivalent embodiments with equivalent changes, without departing from the spirit and technical essence of the present invention. Therefore, any simple modifications, equivalent substitutions, equivalent changes, and modifications made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solutions of the present invention shall still fall within the protection scope of the technical solutions of the present invention.
Claims
1. A method for fabricating silicon islands in a pressure-sensitive chip, characterized in that, Includes the following steps: (1) Clean the SOI silicon wafer used to fabricate the pressure-sensitive chip; (2) Prepare a silicon oxide layer on the back side of the SOI silicon wafer; (3) Photoresist is prepared on the silicon oxide layer on the back side of the SOI silicon wafer, exposed and developed to form a loop-shaped area on the back side of the SOI silicon wafer; (4) The silicon oxide layer in the back-shaped area of the SOI silicon wafer is etched by ICP etching process to form a back-shaped groove on the back of the SOI silicon wafer. (5) Remove the photoresist from the back of the SOI silicon wafer; (6) Prepare photoresist on the back side of the SOI silicon wafer, expose and develop it to remove the photoresist in the groove area on the back side of the SOI silicon wafer, and form an indented area within the groove area. (7) The Si in the aperture area on the back side of the SOI silicon wafer is etched using the DRIE etching process to form a silicon island on the back side of the SOI silicon wafer; The etching rate of Si during the etching process is 500 nm / min to 700 nm / min; the etching process also includes etching the silicon oxide layer on the back side, and the etching rate ratio of Si to silicon oxide layer is 70 to 100:
1. (8) Remove the photoresist on the back of the SOI silicon wafer to complete the processing of the silicon island.
2. The processing method according to claim 1, characterized in that, In step (1), the thickness of the top silicon layer in the SOI silicon wafer is 0.3um to 2um; In step (2), a silicon oxide layer is prepared on the back side of the SOI silicon wafer using thermal oxidation, PECVD, or LPCVD processes; the process parameters for the thermal oxidation process are: process gas is O2, and temperature is 900℃. In step (4), the process parameters of the ICP etching process are: the process gas is CH3F; In step (7), the height of the silicon island is 70 μm.
3. A method for manufacturing a pressure-sensitive chip, characterized in that, Includes the following steps: S1. Clean the SOI silicon wafer; S2. Prepare photoresist on the front side of the SOI silicon wafer, expose and develop it, and retain the photoresist on the front side of the silicon wafer where the resistor strips and interconnects are located. S3. Etch the area on the front side of the SOI silicon wafer that is not covered with photoresist. S4. Remove the photoresist from the resistor strips and interconnects; S5. Prepare silicon oxide layers on both sides of the SOI silicon wafer; S6. Prepare photoresist on the front side of the SOI silicon wafer, expose and develop it, and make windows in the areas on the resistor strip where interconnects and ohmic contacts need to be made. S7. Remove the silicon oxide layer from the areas where interconnects and ohmic contacts need to be fabricated; S8. Remove the photoresist from the surface of the unopened area; S9. Prepare photoresist on the front side of the SOI silicon wafer, expose and develop it, and make windows in the area on the resistor strip where interconnects and ohmic contacts need to be made, so that the area of the windowed area is larger than the windowed area in step S6. S10. Fabricate an electrode metal layer on the front side of the SOI silicon wafer; S11. Remove the photoresist from the surface of the unopened area, and perform heat treatment on the remaining electrode metal layer to complete the fabrication of the ohmic contact electrode. S12. Photoresist is prepared on the silicon oxide layer on the back side of the SOI silicon wafer, exposed and developed to form a loop-shaped area on the back side of the SOI silicon wafer. S13. The silicon oxide layer in the back-shaped area of the SOI silicon wafer is etched using the ICP etching process to form a back-shaped groove on the back of the SOI silicon wafer. S14. Remove the photoresist from the back of the SOI silicon wafer; S15. Prepare photoresist on the back side of the SOI silicon wafer, expose and develop it to form a mouth-shaped area in the area of the groove on the back side of the SOI silicon wafer. S16. The Si in the aperture area on the back side of the SOI silicon wafer is etched using the DRIE etching process to form a silicon island on the back side of the SOI silicon wafer. The etching rate of Si during the etching process is 500 nm / min to 700 nm / min; the etching process also includes etching the silicon oxide layer on the back side, and the etching rate ratio of Si to silicon oxide layer is 70 to 100:
1. S17. Remove the photoresist on the back of the SOI silicon wafer to complete the fabrication of the pressure-sensitive chip.
4. The manufacturing method according to claim 3, characterized in that, In step S1, the thickness of the top silicon layer in the SOI silicon wafer is 0.3µm to 2µm; In step S3, a dry etching process or a wet etching process is used to etch the area on the front side of the SOI silicon wafer that is not covered with photoresist until the silicon oxide layer is exposed. In step S4, acetone is used to clean the photoresist on the resistor strip and interconnects to remove the photoresist from the resistor strip and interconnects. In step S5, a silicon oxide layer is prepared on the front side of the SOI silicon wafer using LPCVD technology, so that the surface and sides of the resistor strips and interconnects are covered with a silicon oxide layer; the process parameters of the LPCVD process are: process gas is O2, and temperature is 900℃; a silicon oxide layer is prepared on the back side of the SOI silicon wafer using thermal oxidation, PECVD, or LPCVD technology; the process parameters of the thermal oxidation process are: process gas is O2, and temperature is 900℃; In step S7, a dry etching process is used to etch the area on the front side of the SOI silicon wafer that is not covered with photoresist to remove the silicon oxide layer until the resistor strip and interconnect are exposed. In step S8, acetone is used to clean the photoresist on the unopened area of the front side of the SOI silicon wafer, thus removing the photoresist from the unopened area. In step S10, the electrode metal layer includes at least one of titanium and gold; In step S11, the photoresist on the surface of the unopened area is removed by peeling, while the electrode metal layer in the area where interconnects and ohmic contacts need to be fabricated is retained. In step S13, the process parameters for the ICP etching process are: the process gas is CH3F; In step S16, the height of the silicon island is 70 μm; In step S17, acetone is used to clean the photoresist on the back of the SOI silicon wafer, thus completing the removal of the photoresist on the back of the SOI silicon wafer.
5. A pressure-sensitive chip, characterized in that, Including silicon islands fabricated by the processing method described in claim 1 or 2.
6. A pressure-sensitive chip, characterized in that, The pressure-sensitive chip is prepared by the manufacturing method described in claim 3 or 4.
7. A pressure sensor, characterized in that, The pressure sensor includes the pressure-sensitive chip as described in claim 5 or 6.
8. The pressure sensor according to claim 7, characterized in that, The pressure-sensitive chip also has a support on its back side; a stress reference cavity is formed between the pressure-sensitive chip and the support.
9. The pressure sensor according to claim 8, characterized in that, The support is a bonded glass sheet or a bonded silicon wafer.