Burr detection unit, method, processing unit and computing system

Abstract

The embodiment of the present application provides a spur detection unit, a method, a processing unit and a computing system, the spur detection unit comprises: a signal sampler, which is used for sampling a target voltage to be detected, and generating a voltage indication signal for indicating a spur in the target voltage according to a sampling result, wherein the voltage indication signal is a rectangular wave signal; a level converter, which is used for performing level conversion on the voltage indication signal in an analog circuit to obtain a spur signal in a digital circuit; a pulse width counter, which is used for performing pulse width counting on the spur signal to obtain a pulse width count value; and an alarm decision maker, which is used for issuing a prompt signal for prompting that there is an abnormal number of spur signals in the target voltage when the pulse width count value is located in a predetermined count range. The present scheme can improve the accuracy of a spur detection result.

Description

Technical Field

[0001] This application relates to the field of chip technology, and in particular to a burr detection unit, method, processing unit, and computing system. Background Technology

[0002] In modern cryptography applications, encryption algorithms can be used to protect sensitive user information. The encrypted sensitive information and the encryption key are the information that needs protection. Chips can encrypt and decrypt sensitive information using cryptographic algorithms. By performing a fault attack on the chip, the key to the cryptographic algorithm can be obtained, and then the encrypted sensitive information can be decrypted using the key. A fault attack refers to operating the chip under abnormal operating conditions, such as abnormal voltage, temperature, clock frequency, or electromagnetic environment. These abnormal operating environments can induce erroneous behavior in the chip, leading to the leakage of keys or sensitive information. Voltage glitches are one type of fault attack. Voltage glitches refer to the spikes or troughs formed on the voltage change curve by rapid voltage changes. By rapidly changing the voltage input to the chip, voltage glitches can be injected into the chip's power pins, causing unexpected errors in the chip's operation. By analyzing these unexpected errors, the encryption / decryption algorithm key can be deduced. Therefore, voltage glitches need to be detected in chips to prevent voltage glitch injection attacks.

[0003] Currently, voltage glitches are detected in chips using analog circuits.

[0004] However, when detecting voltage glitches using analog circuits, the range of voltage glitches that the analog circuits can detect is not configurable. It is impossible to configure the voltage glitch detection range according to the actual application scenario, which may lead to problems such as false voltage glitches or voltage glitches not being detected, resulting in low accuracy of voltage glitch detection on the chip. Summary of the Invention

[0005] In view of this, embodiments of this application provide a burr detection unit, method, processing unit, and computing system to at least solve or alleviate the above-mentioned problems.

[0006] According to a first aspect of the embodiments of this application, a glitch detection unit is provided, comprising: a signal sampler, configured to sample a target voltage to be detected and generate a voltage indication signal for indicating glitch in the target voltage based on the sampling result, wherein the voltage indication signal is a rectangular wave signal; a level converter, configured to perform level conversion on the voltage indication signal in an analog circuit to obtain a glitch signal in a digital circuit; a pulse width counter, configured to count the pulse width of the glitch signal to obtain a pulse width count value; and an alarm decision unit, configured to issue a prompt signal indicating that the target voltage has an abnormal number of glitch signals when the pulse width count value is within a predetermined counting range.

[0007] According to a second aspect of the embodiments of this application, a protection unit is provided, comprising: a burr detection unit according to the first aspect above; and a controller for controlling the operation of the burr detection unit.

[0008] According to a third aspect of the embodiments of this application, a processing unit is provided, including: a protection unit according to the second aspect above; and a scheduling unit for scheduling the protection unit to perform a burr detection task.

[0009] According to a fourth aspect of the embodiments of this application, a computing system is provided, including the processing unit described in the third aspect above.

[0010] According to a fifth aspect of the embodiments of this application, a glitch detection method is provided, comprising: sampling a target voltage to be detected, and generating a voltage indication signal for indicating glitch in the target voltage based on the sampling result, wherein the voltage indication signal is a rectangular wave signal; performing level conversion on the voltage indication signal in an analog circuit to obtain a glitch signal in a digital circuit; performing pulse width counting on the glitch signal to obtain a pulse width count value; and issuing a prompt signal to indicate that the target voltage has an abnormal number of glitch signals when the pulse width count value is within a predetermined counting range.

[0011] According to the glitch detection scheme provided in this application embodiment, the signal sampler inputs an analog circuit, while the pulse width counter and alarm decision unit are digital circuits. The signal sampler samples the target voltage and generates a voltage indication signal based on the sampling result. A level converter then converts the voltage indication signal in the analog circuit into a glitch signal in the digital circuit. The pulse width counter then counts the pulse width of the glitch signal to obtain a pulse width count value. The alarm decision unit issues a warning signal when the pulse width count value is within a predetermined counting range. In the digital circuit, by adjusting the predetermined counting range, the glitch detection range can be configured according to the actual application scenario, thereby enabling the detection of glitches of different depths and widths in different application scenarios, reducing false alarms during glitch detection, and improving the accuracy of glitch detection on the chip. Attached Figure Description

[0012] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings.

[0013] Figure 1 This is a schematic diagram of a computing system according to an embodiment of this application;

[0014] Figure 2 This is a schematic diagram of a processing unit according to an embodiment of this application;

[0015] Figure 3 This is a schematic diagram of a processing unit according to another embodiment of this application;

[0016] Figure 4 This is a schematic diagram of a burr detection unit according to an embodiment of this application;

[0017] Figure 5 This is a schematic diagram of a burr detection unit according to another embodiment of this application;

[0018] Figure 6 This is a schematic diagram of a glitch signal according to an embodiment of this application;

[0019] Figure 7 This is a schematic diagram of a glitch signal according to another embodiment of this application;

[0020] Figure 8 This is a schematic diagram of a burr detection unit according to yet another embodiment of this application;

[0021] Figure 9 This is a flowchart of a burr detection method according to an embodiment of this application. Detailed Implementation

[0022] The present application is described below based on embodiments, but it is not limited to these embodiments. In the detailed description of the present application below, certain specific details are described in detail. Those skilled in the art can fully understand the present application without these details. To avoid obscuring the essence of the present application, well-known methods, processes, and flows are not described in detail. Furthermore, the accompanying drawings are not necessarily drawn to scale.

[0023] First, some nouns or terms that appear in the description of the embodiments of this application shall be interpreted as follows.

[0024] Fault attack: The basic principle of a fault attack is to place the cryptographic chip in a strong magnetic field, or change the chip's power supply voltage, operating frequency, temperature, etc., so that the registers and memory in the cryptographic chip produce random errors during the encryption and decryption process. Some output bits change from 0 to 1 or 1 to 0. Then, by comparing the correct ciphertext output and the incorrect ciphertext output, the secret data inside the chip can be obtained through theoretical analysis.

[0025] Glitch injection attack: Glitch injection attack is a common fault attack method. By injecting glitch into the power supply or wafer circuit of the encryption / decryption algorithm, the encryption / decryption algorithm is made to malfunction, and then the key is deduced from the error information output by the encryption / decryption algorithm.

[0026] Upward spikes: The voltage injected into the circuit is in the same direction as the original voltage in the circuit, which increases the voltage in the circuit and causes a peak in the voltage curve of the circuit, which is manifested as an upward spike in the voltage curve.

[0027] Downward spurs: The voltage injected into the circuit is opposite in direction to the original voltage in the circuit, which reduces the voltage in the circuit and causes a trough in the voltage curve of the circuit, which is manifested as a downward spur in the voltage curve.

[0028] Computing System

[0029] Figure 1 A schematic block diagram of a computing system 10 is shown. The computing system 10 can be built based on various types of processing units. The computing system 10 can be, for example, an Internet of Things (IoT) processing unit, a system-on-a-chip (SoC), a desktop processing system, or a data center processing system.

[0030] like Figure 1As shown, the computing system 10 may include one or more processing units 12 and a memory 15. The memory 15 in the computing system 10 may serve as main memory (or simply main memory or RAM) for storing instruction information and / or data information represented by data signals. For example, the memory 15 may store data provided by the processing unit 12 (e.g., budget results), and may also be used to realize data exchange between the processing unit 12 and the external storage device 16 (or auxiliary memory or external memory).

[0031] In some cases, the processing unit 12 needs to access the memory 15 via the bus 11 to retrieve or modify data in the memory 15. Since the access speed of the memory 15 is relatively slow, to alleviate the speed difference between the processing unit 12 and the memory 15, the computing system 10 also includes a cache memory 18 communicatively connected to the bus 11. The cache memory 18 is used to cache some program data or message data in the memory 15 that may be repeatedly accessed. The cache memory 18 can be implemented using a storage device such as Static Random Access Memory (SRAM). The cache memory 18 can be a multi-level structure, such as a three-level cache structure with a level 1 cache (L1Cache), a level 2 cache (L2Cache), and a level 3 cache (L3Cache). The cache memory 18 can also be a cache structure with more than three levels or other types of cache structures. In some embodiments, a portion of the cache memory 18 (e.g., the level 1 cache, or both the level 1 cache and the level 2 cache) can be integrated inside the processing unit 12 or integrated with the processing unit 12 in the same computing system.

[0032] Based on this, the processing unit 12 may include an instruction execution unit 136 and a memory management unit 122, among other components. When executing instructions that require memory modification, the instruction execution unit 136 initiates a write access request, specifying the data to be written into memory and its corresponding physical address. The memory management unit 122 translates the virtual addresses specified by these instructions into the physical addresses mapped to those virtual addresses. The physical address specified in the write access request may be the same as the physical address specified in the corresponding instruction.

[0033] Information exchange between memory 15 and cache memory 18 can be organized according to data blocks. In some embodiments, cache memory 18 and memory 15 can be divided into data blocks with the same spatial size. A data block can serve as the smallest unit of data exchange between cache memory 18 and memory 15 (including one or more data of a preset length). For the sake of brevity and clarity, each data block in cache memory 18 will be referred to as a cache block (or cache line), and different cache blocks will have different cache block addresses. Each data block in memory 15 will be referred to as a memory block, and different memory blocks will have different memory block addresses. Cache block addresses and / or memory block addresses may include physical address tags used to locate data blocks.

[0034] Due to space and resource limitations, cache memory 18 cannot cache all the contents of memory 15; that is, the storage capacity of cache memory 18 is usually smaller than that of memory 15, and the addresses of individual cache blocks provided by cache memory 18 cannot correspond to all the memory block addresses provided by memory 15. When processing unit 12 needs to access memory, it first accesses cache memory 18 via bus 11 to determine whether the content to be accessed is already stored in cache memory 18. If the content to be accessed is already stored in cache memory 18, cache memory 18 is hit, and processing unit 12 directly retrieves the content to be accessed from cache memory 18. If the content to be accessed is not stored in cache memory 18, cache memory 18 and processing unit 12 need to access memory 15 via bus 11 to find the corresponding information in memory 15. Because the access speed of cache memory 18 is very fast, the efficiency of processing unit 12 can be significantly improved when cache memory 18 is hit, thereby improving the performance and efficiency of the entire computing system 10.

[0035] In addition, the computing system 10 may also include a storage device 16, a display device, an audio device, a mouse / keyboard, and other input / output devices. The storage device 16 may be a hard disk, optical disk, or flash memory, etc., coupled to the bus 11 via a corresponding interface, for storing and retrieving information. The display device may be coupled to the bus 11 via a corresponding graphics card, and is used to display information according to the display signals provided by the bus 11.

[0036] The computing system 10 may also include a communication device 17, enabling the computing system 10 to communicate with networks or other devices in various ways. The communication device 17 may include one or more communication modules, including wireless communication modules adapted to specific wireless communication protocols. For example, the communication device 17 may include a WLAN module for implementing WiFi communication conforming to the IEEE 802.11 standard. The communication device 17 may include a WWAN module for implementing wireless wide-area communication conforming to cellular or other wireless wide-area protocols. The communication device 17 may also include communication modules employing other protocols, such as a Bluetooth module, or other custom-type communication modules. The communication device 17 may also be a port for serial data transmission.

[0037] It should be noted that the structure of the computing system 10 may vary depending on the motherboard, operating system, and instruction set architecture. For example, many current computing systems have an input / output control center connected between the bus 11 and various input / output devices, and this input / output control center may be integrated into the processing unit 12 or independent of the processing unit 12.

[0038] Processing unit

[0039] Figure 2 A schematic block diagram of a processing unit 12 is shown, such as Figure 2 As shown, the processing unit 12 includes a scheduling unit cluster 13 and a protection unit cluster 14. The scheduling unit cluster 13 includes one or more scheduling units 130. The protection unit cluster 14 includes one or more protection units 140. In this embodiment, the protection unit 140 is a dedicated processing unit designed primarily for detecting voltage spikes. The processing unit 12 can be a processor (CPU), image processing unit (GPU), application-specific integrated circuit (ASIC), or field-programmable gate array (FPGA) that runs encryption and decryption algorithms. For example, the processing unit 12 can be a processor used for face recognition, fingerprint payment, etc., that requires running encryption and decryption algorithms.

[0040] Figure 3 A schematic block diagram of another processing unit 12 is shown. Taking the processing unit 12 as an example, which includes a scheduling unit 130 and a protection unit 140, the internal structure of the scheduling unit 130 and the protection unit 140 is described to illustrate how the scheduling unit 130 schedules the protection unit 140 to work.

[0041] like Figure 3As shown, the scheduling unit 130 includes multiple processor cores 131 and a cache 132 shared by the multiple processor cores 131. Each processor core 131 includes an instruction fetch unit 133, an instruction decode unit 134, an instruction issue unit 135, an instruction execution unit 136, and a memory control unit 137.

[0042] The instruction fetch unit 133 is used to move the instruction to be executed from the memory 110 to the instruction register (which may be a storage control unit 137) via the storage control unit 137. Figure 2 The instruction is stored in one of the registers in the register file 138 shown, and the next fetch address is received or calculated according to the fetch algorithm, which may include, for example, incrementing or decrementing the address based on the instruction length.

[0043] After the instruction is fetched, the scheduling unit 130 enters the instruction decoding stage. The instruction decoding unit 134 decodes the fetched instruction according to a predetermined instruction format to obtain the operand fetch information required by the fetched instruction, thereby preparing for the operation of the instruction execution unit 136. Operand fetch information may include pointers to immediate values, registers, or other software / hardware that can provide source operands.

[0044] The instruction issuing unit 135 is located between the instruction decoding unit 134 and the instruction execution unit 136. It is used for instruction scheduling and control to efficiently allocate various instructions to different instruction execution units 136, making parallel operation of multiple instructions possible. After the instruction issuing unit 135 issues an instruction to the instruction execution unit 136, the instruction execution unit 136 begins to execute the instruction.

[0045] Processor core 131 includes encryption / decryption algorithm circuits. The encryption / decryption algorithm circuits in different processor cores 131 operate based on the same or different operating voltages. When a glitch is injected into the operating voltage of the encryption / decryption algorithm circuit, it will cause unexpected errors in the calculation results. By analyzing these unexpected errors, the key can be deduced. The protection unit 140 is subject to scheduling by the scheduling unit 130. The protection unit 140 includes a controller 141 and a glitch detection unit 142. After receiving the scheduling instruction from the scheduling unit 130, the controller 141 can send control instructions to the glitch detection unit 142 to control the glitch detection unit 142 to perform voltage glitch detection on one or more corresponding processor cores 131 to determine whether the encryption / decryption algorithm circuit in the processor core 131 has been subjected to a glitch injection attack. The glitch detection unit 142 is connected to the power supply voltage line of the processor core 131. When a glitch is injected into the power supply voltage of the processor core 131, the voltage on the power supply voltage line of the processor core 131 changes accordingly. The glitch detection unit 142 detects the voltage glitch by sampling the voltage on the power supply voltage line of the processor core 131 and based on the sampling results. The power supply voltage line of the processor core 131 is used to provide power voltage for circuits that need protection, such as providing power voltage for one or more encryption / decryption algorithm circuits within the processor core 131. This embodiment mainly focuses on the process of glitch detection by the protection unit 140, and the glitch detection process will be described in detail below.

[0046] Burr detection unit

[0047] Figure 4 This is a schematic diagram of the internal structure of a burr detection unit according to an embodiment of this application. Figure 4 As shown, the glitch detection unit 142 includes a signal sampler 143, a level converter 144, a pulse width counter 145, and an alarm decision unit 146. The signal sampler 143 samples the target voltage to be detected and generates a voltage indication signal (a rectangular wave signal) to indicate glitches in the target voltage based on the sampling result. The level converter 144 performs level conversion on the voltage indication signal in the analog circuit to obtain the glitches signal in the digital circuit. The pulse width counter 145 counts the pulse width of the glitches to obtain a pulse width count value. The alarm decision unit 146 determines whether the pulse width count value is within a preset count range. If the pulse width count value is within the preset count range, it issues an alarm signal indicating an abnormal number of glitches in the target voltage.

[0048] The target of the glitch injection attack is the encryption and decryption algorithm in the chip. Therefore, the target voltage to be detected can be the power supply voltage of the encryption and decryption algorithm. The signal sampler 143 is connected to the power supply voltage line of the encryption and decryption algorithm circuit in the processor core 131. The signal sampler 143 samples the power supply voltage line of the encryption and decryption algorithm circuit. If a voltage glitch is injected into the power supply voltage of the encryption and decryption algorithm circuit, the sampling result of the signal sampler 143 will change accordingly.

[0049] The glitch detection unit 142 includes analog and digital circuits, which are connected via a level converter 144. The analog circuit includes a signal sampler 143, and the digital circuit includes a pulse width counter 145 and an alarm decision unit 146. The voltage indication signal generated by the signal sampler 143 is an analog voltage signal. The level converter 144 performs level conversion on the voltage indication signal to obtain a glitch signal, which is a digital voltage signal. Because the voltage specifications of the analog and digital circuits are different, the level converter 144 converts the voltage indication signal into a glitch signal so that the voltage specifications of the glitch signal meet the requirements of the pulse width counter 145, thereby enabling the digital circuit to detect the glitch.

[0050] The signal sampler 143 is implemented using analog circuitry, so the voltage indication signal generated by the signal sampler 143 is an analog voltage signal. The pulse width counter 145 is implemented using digital circuitry, so the glitches input to the pulse width counter 145 should be digital signals. To enable communication between the signal sampler 143 and the pulse width counter 145, a level converter 144 is provided between them. The level converter 144 can convert the analog voltage indication signal into a digital glitches signal.

[0051] After sampling the target voltage, signal sampler 143 calculates the difference between the sampled result and the reference value of the target voltage. This difference is shaped using a Schmitt trigger to obtain a voltage indication signal as a rectangular wave. This signal indicates whether the target voltage is over- or under-voltage, and the duration of over- or under-voltage. Level converter 144 converts the voltage indication signal into a glitch signal and sends it to pulse width counter 145, where the glitch signal remains a rectangular wave. Upon receiving the glitch signal, pulse width counter 145 counts the pulse widths of the glitch signals to obtain a pulse width count value. This count value can be the number of clock signals or the duration of the clock signal. The pulse width count value is then sent to alarm decision unit 146. A predetermined counting range for glitch widths during a glitch injection attack is pre-set. After receiving the pulse width count value, alarm decision unit 146 determines whether the count value is within the predetermined range. If the count value is within the predetermined range, it indicates that the target voltage has an abnormal number of glitch signals, meaning the target voltage has been subjected to a glitch injection attack.

[0052] The voltage indication signal is a rectangular wave signal. A glitch signal is obtained by level conversion of the voltage indication signal. Level conversion does not change the waveform type of the signal; therefore, the glitch signal is also a rectangular wave signal. When the target voltage is attacked by a glitch injection, corresponding pulses will appear in the glitch signal. The pulse width counter 145 counts the pulse width of the glitch signal to obtain the pulse width count value corresponding to each pulse in the glitch signal. The pulse width counter 145 operates according to a corresponding clock frequency. The pulse width count value can be the number of clock signals or a specific time length.

[0053] After receiving the pulse width count value, the alarm decision unit 146 determines whether the pulse width count value is within a preset count range. If the pulse width count value is within the preset count range, it determines that the target voltage has been subjected to a glitch injection attack and issues a warning signal. Since the target voltage fluctuates during normal chip operation, pulses with smaller or larger pulse width count values ​​corresponding to the target voltage are not caused by glitch injection attacks. By setting a preset count range, pulses with pulse width count values ​​within the preset range are identified as glitch injection attacks, ensuring accurate glitch identification while preventing alarms for glitch attacks not caused by glitch injection attacks, thus ensuring the stability of chip operation.

[0054] In this embodiment, the signal sampler 143 is input to the analog circuit, while the pulse width counter 145 and alarm decision unit 146 are digital circuits. The signal sampler 143 samples the target voltage and generates a voltage indication signal based on the sampling result. The level converter 144 converts the voltage indication signal in the analog circuit into a glitch signal in the digital circuit. The pulse width counter 145 then counts the pulse width of the glitch signal to obtain a pulse width count value. The alarm decision unit 146 issues a warning signal when the pulse width count value is within a predetermined counting range. In the digital circuit, by adjusting the predetermined counting range, the glitch detection range can be configured according to the actual application scenario, thereby enabling the detection of glitches of different depths and widths in different application scenarios, reducing false alarms during glitch detection, and improving the accuracy of glitch detection on the chip.

[0055] In one possible implementation, the glitches sent by the level converter 144 to the pulse width counter 145 include an overshoot glitch signal and an undershoot glitch signal. The overshoot glitch signal indicates an overshoot glitch in the target voltage, and the undershoot glitch signal indicates an undershoot glitch in the target voltage. The pulse width counter 145 can count the pulse widths of the overshoot glitch signal and the undershoot glitch signal separately, obtaining a first pulse width count value by counting the pulse widths of the overshoot glitch signal and a second pulse width count value by counting the pulse widths of the undershoot glitch signal.

[0056] The alarm decision unit 146 determines whether an overshoot or undershoot is a glitch based on a first pulse width count value and a second pulse width count value. If the first pulse width count value is within a preset first predetermined count range, it determines that the target voltage is attacked by an overshoot glitch and issues a first alert signal indicating an abnormal number of overshoot glitch signals at the target voltage; otherwise, it determines that the target voltage is not attacked by an overshoot glitch and does not issue the first alert signal. If the second pulse width count value is within a preset second predetermined count range, it determines that the target voltage is attacked by an undershoot glitch and issues a second alert signal indicating an abnormal number of undershoot glitch signals at the target voltage; otherwise, it determines that the target voltage is not attacked by an undershoot glitch and does not issue the second alert signal.

[0057] In this embodiment, the overshoot glitch signal can indicate an overshoot glitch in the target voltage, and the undershoot glitch signal can indicate an undershoot glitch in the target voltage. The pulse width counter 145 can count the pulse width of the overshoot glitch signal and the undershoot glitch signal respectively to obtain a first pulse width count value and a second pulse width count value. The alarm decision unit 146 can determine whether the target voltage is attacked by an overshoot glitch based on the first pulse width counter, and can determine whether the target voltage is attacked by an undershoot glitch based on the second pulse width count value. After determining that it has been attacked by a corresponding glitch, it issues a corresponding prompt signal. Thus, the glitch detection unit 142 can detect both overshoot glitch and undershoot glitch, improving the comprehensiveness of detecting glitch injection attacks in the chip.

[0058] Figure 5 This is a schematic diagram of the internal structure of a burr detection unit according to another embodiment of this application. Figure 5 As shown, the pulse width counter 145 includes a first counter 1451 and a second counter 1452, and the alarm decision unit 146 includes a first decision unit 1461 and a second decision unit 1462.

[0059] The first counter 1451 can acquire the upward glitch signal and count the pulse width of the upward glitch signal to obtain the corresponding first pulse width count value. The second counter 1452 can acquire the downward glitch signal and count the pulse width of the downward glitch signal to obtain the corresponding second pulse width count value. After acquiring the first pulse width count value, the first counter 1451 will send the first pulse width count value to the first decision unit 1461. After acquiring the second pulse width count value, the second counter 1452 will send the second pulse width count value to the second decision unit 1462.

[0060] The first decision unit 1461 can determine whether the first pulse width count value is within a preset first predetermined counting range. If the first pulse width count value is within the first predetermined counting range, it is determined that the target voltage has been subjected to an upward glitch injection attack, and a first warning signal is issued. If the first pulse width count value is outside the first predetermined counting range, it is determined that the target voltage has not been subjected to an upward glitch injection attack, and no first warning signal is issued. The second decision unit 1462 can determine whether the second pulse width count value is within a preset second predetermined counting range. If the second pulse width count value is within the second predetermined counting range, it is determined that the target voltage has been subjected to a downward glitch injection attack, and a second warning signal is issued. If the second pulse width count value is outside the second predetermined counting range, it is determined that the target voltage has not been subjected to a downward glitch injection attack, and no second warning signal is issued.

[0061] The first and second predetermined counting ranges are preset glitch detection ranges. Depending on the actual application scenario, the first and second predetermined counting ranges can be the same or different. When the first pulse width count value and the second pulse width count value are the number of clock signals, the first and second predetermined counting ranges are the range of the number of clock signals. For example, if both the first and second predetermined counting ranges are [10, 100], that is, when the first pulse width count value is greater than or equal to 10 and less than or equal to 100, it is determined that the target voltage has been attacked by an upward glitch injection, and a first warning signal is issued. When the second pulse width count value is greater than or equal to 10 and less than or equal to 100, it is determined that the target voltage has been attacked by a downward glitch injection, and a second warning signal is issued. When the first and second pulse width count values ​​are the time length, the first and second predetermined counting ranges are the time range.

[0062] By configuring a first predetermined counting range and a second predetermined counting range, glitch detection of different specifications can be performed. For example, when the chip's operating clock frequency is 1.6GHz, the first predetermined counting range and the second predetermined counting range can be any subset of [625ps, 2.684s], where 625ps is 625 picoseconds and 2.684s is 2.684 seconds.

[0063] In this embodiment, the first counter 1451 and the first decision unit 1461 are used to count the pulse width and make decisions on the upward burr signal, and the second counter 1452 and the second decision unit are used to count the pulse width and make decisions on the downward burr signal, so that the upward burr detection and the downward burr detection are performed separately, avoiding mutual interference between the upward burr detection and the downward burr detection, and ensuring the accuracy of burr detection.

[0064] In one possible implementation, after issuing a first prompt signal, the first decision unit 1461 can receive a first reset signal and clear the historical first prompt signal according to the first reset signal to restart the detection of the next upward punch glitch. After issuing a second prompt signal, the second decision unit 1462 can receive a second reset signal and clear the historical second prompt signal according to the second reset signal to restart the detection of the next downward punch glitch.

[0065] The first reset signal and the second reset signal can be sent by the controller 141.

[0066] In this embodiment, the first decision unit 1461 and the second decision unit 1462 can be reloaded. The first reset signal can clear the historical first prompt signal so that the first decision unit 1461 can restart the next upward glitch detection. The second reset signal can clear the historical second prompt signal so that the second decision unit 1462 can restart the next downward glitch detection. This allows for continuous glitch detection and ensures the effectiveness of chip protection.

[0067] In one possible implementation, depending on the operating principle of the signal sampler 143, glitches in the target voltage can be indicated by either a high level or a low level in the rectangular wave signal. The pulse width counting methods for indicating glitches by a high level and by a low level are explained below.

[0068] When a high level in a rectangular wave signal indicates a glitch, the first counter 1451 can determine the duration or number of clock signals between sequentially adjacent rising and falling edges in the overshoot glitch signal as the first pulse width count value, and the second counter 1452 can determine the duration or number of clock signals between sequentially adjacent rising and falling edges in the undershoot glitch signal as the second pulse width count value.

[0069] Figure 6 This is a schematic diagram of a glitch signal according to an embodiment of this application. Figure 6 As shown, a high level in the rectangular wave signal indicates a glitch in the target voltage. When the rectangular wave signal is an overshoot glitch signal, a high level in the rectangular wave signal indicates an overshoot glitch. The first counter 1451 starts counting when it detects the rising edge 601 of the overshoot glitch signal and stops counting when it detects the falling edge 602 of the overshoot glitch signal, obtaining the duration or number of clock signals between sequentially adjacent rising edges 601 and falling edges 602 as the first pulse width count value. When the rectangular wave signal is a undershoot glitch signal, a high level in the rectangular wave signal indicates a undershoot glitch. The second counter 1452 starts counting when it detects the rising edge 601 of the undershoot glitch signal and stops counting when it detects the falling edge 602 of the undershoot glitch signal, obtaining the duration or number of clock signals between sequentially adjacent rising edges 601 and falling edges 602 as the second pulse width count value.

[0070] When a low level in the rectangular wave signal indicates a glitch, the first counter 1451 can determine the duration or number of clock signals between sequentially adjacent falling and rising edges in the overshoot glitch signal as the first pulse width count value, and the second counter 1452 can determine the duration or number of clock signals between sequentially adjacent falling and rising edges in the undershoot glitch signal as the second pulse width count value.

[0071] Figure 7 This is a schematic diagram of a glitch signal according to another embodiment of this application. Figure 7 As shown, a low level in the rectangular wave signal indicates a glitch in the target voltage. When the rectangular wave signal is an overshoot glitch signal, a low level in the rectangular wave signal indicates an overshoot glitch. The first counter 1451 starts counting when it detects the falling edge 701 of the overshoot glitch signal and stops counting when it detects the rising edge 702 of the overshoot glitch signal, obtaining the duration or number of clock signals between sequentially adjacent falling edges 701 and rising edges 702 as the first pulse width count value. When the rectangular wave signal is a undershoot glitch signal, a low level in the rectangular wave signal indicates a undershoot glitch. The second counter 1452 starts counting when it detects the falling edge 701 of the undershoot glitch signal and stops counting when it detects the rising edge 702 of the undershoot glitch signal, obtaining the duration or number of clock signals between sequentially adjacent falling edges 701 and rising edges 702 as the second pulse width count value.

[0072] In this embodiment, glitches in the target voltage can be represented by high or low levels in the rectangular wave signal. This allows the signal sampler 143 to generate voltage indication signals in different ways to suit various application scenarios, ensuring the glitch detection unit 142 has strong applicability. Furthermore, the first counter 1451 and the second counter 1452 count pulse widths based on the rising and falling edges of the glitch signal, ensuring the accuracy of the obtained pulse width count values ​​and thus guaranteeing the accuracy of glitch detection in the target voltage.

[0073] In one possible implementation, such as Figure 5 As shown, the glitch detection unit 142 also includes a first synchronizer 147 and a second synchronizer 148. The level converter 144 can send an overshoot glitch signal to the first synchronizer 147 and an undershoot glitch signal to the second synchronizer 148. The first synchronizer 147 can perform clock domain synchronization processing on the overshoot glitch signal, synchronizing it with the operating clocks of the first counter 1451 and the first decision unit 1461. The second synchronizer 148 can perform clock domain synchronization processing on the undershoot glitch signal, synchronizing it with the operating clocks of the second counter 1452 and the second decision unit 1462.

[0074] The glitch detection unit 142 includes analog and digital circuits. The analog circuit includes a signal sampler 143, and the digital circuit includes a first synchronizer 147, a second synchronizer 148, a first counter 1451, a second counter 1452, a first decision unit 1461, and a second decision unit 1462. The first synchronizer 147, second synchronizer 148, first counter 1451, second counter 1452, first decision unit 1461, and second decision unit 1462 in the digital circuit operate according to the same clock signal. The analog and digital circuits use different operating clocks. The first synchronizer 147 performs clock domain synchronization processing on overshoot glitch signals, and the second synchronizer 148 performs clock domain synchronization processing on undershoot glitch signals, ensuring that the overshoot and undershoot glitch signals after clock domain synchronization processing are synchronized with the operating clock of the digital circuit.

[0075] The first synchronizer 147 and the second synchronizer 148 can both be constructed by linking three levels of registers. Each level of register has a working clock signal input from the digital circuit. The three levels of registers perform clock signal synchronization processing on the input overshoot or undershoot signals based on the input working clock signal, so that the overshoot or undershoot signal output from the third level register is synchronized with the working clock of the digital circuit.

[0076] In this embodiment, the first synchronizer 147 can perform clock domain synchronization processing on the overshoot glitch signal, and the second synchronizer 148 can perform clock domain synchronization processing on the undershoot glitch signal, thereby achieving cross-clock domain synchronization of the overshoot glitch signal and the undershoot glitch signal. This ensures that the overshoot glitch signal and the undershoot glitch signal after clock domain synchronization processing are synchronized with the clock signal of the digital circuit, guaranteeing the accuracy of pulse width counting of the overshoot glitch signal and the undershoot glitch signal in the digital circuit, and thus ensuring the accuracy of detecting the overshoot glitch and the undershoot glitch.

[0077] In one possible implementation, the signal sampler 143 can sample the target voltage and determine an overvoltage indication signal and an undervoltage indication signal based on the difference between the sampling result and the bandgap reference voltage. The overvoltage indication signal is used to indicate an overshoot glitch in the target voltage, and the undervoltage indication signal is used to indicate a undershoot glitch in the target voltage. Both the overvoltage and undervoltage indication signals are rectangular wave signals. The level converter 144 can perform level conversion on the overvoltage and undervoltage indication signals respectively. The overshoot glitch signal is obtained by level conversion of the overvoltage indication signal, and the undershoot glitch signal is obtained by level conversion of the undervoltage indication signal.

[0078] In this embodiment, the signal sampler 143 samples the target voltage and determines an overvoltage indication signal for indicating an overshoot glitch and an undervoltage indication signal for indicating a undershoot glitch based on the difference between the sampling result and the bandgap reference voltage. Since the bandgap reference voltage is not easily disturbed and has strong stability, the overvoltage indication signal and undervoltage indication signal are determined based on the difference between the sampling result and the bandgap reference voltage. This ensures that the determined overvoltage indication signal can accurately indicate an overshoot glitch in the target voltage, and the determined undervoltage indication signal can accurately indicate a undershoot glitch in the target voltage. Therefore, when performing glitch detection based on the overvoltage indication signal and the undervoltage indication signal, the overshoot glitch and undershoot glitch in the target voltage can be accurately detected, ensuring the accuracy of glitch detection.

[0079] Figure 8 This is a schematic diagram of a burr detection unit 142 according to another embodiment of this application. Figure 8 As shown, the signal sampler 143 includes a first comparator 1431 and a second comparator 1432. By sampling the target voltage Vcore, a first voltage V1 and a second voltage V2 can be obtained. When there are no glitches in the target voltage Vcore, the first voltage V1 is greater than the bandgap reference voltage Vref, and the bandgap reference voltage Vref is greater than the second voltage V2.

[0080] The first comparator 1431 calculates the first voltage difference between the first voltage V1 and the bandgap reference voltage Vref, and shapes the first voltage difference using a Schmitt trigger to obtain an overvoltage indication signal as a rectangular wave signal. This overvoltage indication signal is then sent to the level converter 144, which converts it into an overshoot glitch signal DO_VCORE_H. The second comparator 1432 calculates the second voltage difference between the bandgap reference voltage Vref and the second voltage V2, and shapes the second voltage difference using a Schmitt trigger to obtain an undervoltage indication signal as a rectangular wave signal. This undervoltage indication signal is then sent to the level converter 144, which converts it into an undershoot glitch signal DO_VCORE_L.

[0081] The signal sampler 143 also includes a voltage divider circuit composed of multiple resistors connected in series. One end of the voltage divider circuit is connected to the target voltage Vcore, and the other end is grounded, so that the voltage applied to the voltage divider circuit is equal to the target voltage. A first voltage V1 and a second voltage V2 are sampled on the voltage divider circuit. There are at least two resistors between the sampling point of the first voltage V1 and the reference ground, and at least one resistor between the sampling point of the second voltage V2 and the reference ground. That is, there is at least one resistor between the sampling points of the first voltage V1 and the sampling points of the second voltage V2, ensuring that the first voltage V1 is greater than the bandgap reference voltage Vref, and the bandgap reference voltage Vref is greater than the second voltage V2.

[0082] By shaping the first voltage difference and the second voltage difference using a Schmitt trigger, overvoltage indication signals and undervoltage indication signals in the form of rectangular waves can be obtained. Moreover, the overshoot in the target voltage corresponds to the high level in the overvoltage indication signal, and the undershoot in the target voltage corresponds to the high level in the undervoltage indication signal.

[0083] In this embodiment, the first comparator 1431 calculates the first voltage difference between the first voltage V1 and the bandgap reference voltage Vref, and shapes the first voltage difference using a Schmitt trigger to obtain an overvoltage indication signal as a rectangular wave signal. The second comparator 1432 calculates the second voltage difference between the bandgap reference voltage Vref and the second voltage V2, and shapes the second voltage difference using a Schmitt trigger to obtain an undervoltage indication signal as a rectangular wave signal. Overshoot and undershoot in the target voltage are represented as high levels in the overvoltage and undervoltage indication signals. Therefore, after converting the overvoltage and undervoltage indication signals into overshoot and undershoot signals, pulse width counting can be performed on the overshoot and undershoot signals, and the target voltage can be determined based on the pulse width count value to determine whether it has been attacked by overshoot and undershoot, thus ensuring the accuracy of glitch detection while displaying the glitch detection.

[0084] The following is combined with Figure 8 The burr detection unit 142 shown provides a detailed explanation of the burr detection process.

[0085] The first comparator 1431 acquires the first voltage V1 and calculates the first voltage difference between the first voltage V1 and the bandgap reference voltage Vref. It then shapes the first voltage difference using a Schmitt trigger to obtain an overvoltage indication signal as a rectangular wave, which is sent to the level converter 144. An overshoot in the target voltage Vcore corresponds to a high level in the overvoltage indication signal.

[0086] The second comparator 1432 acquires the second voltage V2 and calculates the second voltage difference between the bandgap reference voltage Vref and the second voltage V2. It then shapes the second voltage difference using a Schmitt trigger to obtain an undervoltage indication signal as a rectangular wave, which is sent to the level converter 144. The undershoot in the target voltage Vcore corresponds to the high level in the undervoltage indication signal.

[0087] Level converter 144 performs level conversion on the overvoltage indication signal to obtain an overshoot glitch signal DO_VCORE_H that meets the voltage specifications of the digital circuit, and sends the overshoot glitch signal DO_VCORE_H to the first synchronizer 147. Level converter 144 performs level conversion on the undervoltage indication signal to obtain a undershoot glitch signal DO_VCORE_L that meets the voltage specifications of the digital circuit, and sends the undershoot glitch signal DO_VCORE_L to the second synchronizer 148. Both the overshoot glitch signal DO_VCORE_H and the undershoot glitch signal DO_VCORE_L are rectangular wave signals.

[0088] The first synchronizer 147 performs clock domain synchronization processing on the overshoot glitch signal DO_VCORE_H to obtain an overshoot glitch signal vcore_h synchronized with the working clock signal of the first counter 1451, and sends the overshoot glitch signal vcore_h to the first counter 1451.

[0089] The second synchronizer 148 performs clock domain synchronization processing on the undershoot glitch signal DO_VCORE_L to obtain an undershoot glitch signal vcore_l synchronized with the working clock signal of the second counter 1452, and sends the undershoot glitch signal vcore_l to the second counter 1452.

[0090] When the glitch detection enable signal glt_vcore_enable is valid, the first counter 1451 counts the pulse width of the high level in the overshoot glitch signal vcore_h to obtain a first pulse width count value vcoreglt_higcnter, and sends the first pulse width count value vcoreglt_higcnter to the first decision unit 1461. Simultaneously, the first counter 1451 generates a first decision enable signal vcore_h_neg on the falling edge of the overshoot glitch signal vcore_h, instructing the first decision unit 1461 to perform a decision action.

[0091] When the glitch detection enable signal glt_vcore_enable is valid, the second counter 1452 counts the pulse width of the high level in the undershoot glitch signal vcore_l to obtain a second pulse width count value vcoreglt_lowcnter, and sends the second pulse width count value vcoreglt_lowcnter to the second decision unit 1462. Simultaneously, the second counter 1452 generates a second decision enable signal vcore_l_neg on the falling edge of the undershoot glitch signal vcore_l, instructing the second decision unit 1462 to perform a decision action.

[0092] When the first decision unit 1461 receives the first pulse width count value vcoreglt_higcnter and the first decision enable signal vcore_h_neg is valid, it determines whether the first pulse width count value vcoreglt_higcnter is between the predetermined count range lower limit threshold glitch_lowthrod and the predetermined count range upper limit threshold glitch_higthrod. If so, it issues a first alert signal vcoreglitch_h_alarm. After issuing the first alert signal vcoreglitch_h_alarm, the first decision unit 1461 can receive a first reset signal vcoreglitch_h_rearm. After receiving the first reset signal vcoreglitch_h_rearm, it clears the historical first alert signal vcoreglitch_h_alarm to re-detect the next overshoot glitches in the target voltage Vcore.

[0093] When the second decision unit 1462 receives the second pulse width count value vcoreglt_lowcnter and the second decision enable signal vcore_l_neg is valid, it determines whether the second pulse width count value vcoreglt_lowcnter is between the predetermined count range lower threshold glitch_lowthrod and the predetermined count range upper threshold glitch_higthrod. If so, it issues a second alert signal vcoreglitch_l_alarm. After issuing the second alert signal vcoreglitch_l_alarm, the second decision unit 1462 can receive a second reset signal vcoreglitch_l_rearm. After receiving the second reset signal vcoreglitch_l_rearm, it clears the historical second alert signal vcoreglitch_l_alarm to re-detect the next undershoot glitches in the target voltage Vcore.

[0094] In one example, the bit widths of the glitch detection enable signal glt_vcore_enable, the first alert signal vcoreglitch_h_alarm, the second alert signal vcoreglitch_l_alarm, the first reset signal vcoreglitch_h_rearm, the second reset signal vcoreglitch_l_rearm, the overshoot glitch signal DO_VCORE_H, the overshoot glitch signal vcore_h, the undershoot glitch signal DO_VCORE_L, and the undershoot glitch signal vcore_l are all 1, and the bit widths of the predetermined count range upper limit threshold glitch_higthrod and the predetermined count range lower limit threshold glitch_lowthrod are both 32.

[0095] Burr detection method

[0096] Figure 9 This is a flowchart of a burr detection method according to an embodiment of this application. This burr detection method can be executed by the burr detection unit 142 in the above embodiment. Figure 9 As shown, the burr detection method includes the following steps:

[0097] Step 901: Sample the target voltage to be detected, and generate a voltage indication signal to indicate glitches in the target voltage based on the sampling results. The voltage indication signal is a rectangular wave signal.

[0098] Step 902: Perform level conversion on the voltage indication signal in the analog circuit to obtain the glitch signal in the digital circuit;

[0099] Step 903: Count the pulse width of the glitch signal to obtain the pulse width count value;

[0100] Step 904: When the pulse width count value is within the predetermined count range, issue a prompt signal to indicate that the number of glitches in the target voltage is abnormal.

[0101] In this embodiment, the target voltage is sampled, and a voltage indication signal is generated based on the sampling result. The voltage indication signal in the analog circuit is converted into a glitch signal in the digital circuit. The glitch signal can then be pulse-width counted to obtain a pulse-width count value. When the pulse-width count value is within a predetermined counting range, a prompt signal is issued. In the digital circuit, by adjusting the predetermined counting range, the glitch detection range can be configured according to the actual application scenario. This allows for the detection of glitches of different depths and widths in different application scenarios, reducing false alarms during glitch detection and improving the accuracy of glitch detection on the chip.

[0102] In one possible implementation, the glitch signal includes an overshoot glitch signal and a undershoot glitch signal. The overshoot glitch signal indicates an overshoot glitch in the target voltage, and the undershoot glitch signal indicates a undershoot glitch in the target voltage. When counting the pulse width of the glitch signals, the pulse width of the overshoot glitch signal can be counted to obtain a first pulse width count value, and the pulse width of the undershoot glitch signal can be counted to obtain a second pulse width count value. When the first pulse width count value is within a first predetermined counting range, a first alert signal indicating that the target voltage has been attacked by an overshoot glitch injection is issued, and when the second pulse width count value is within a second predetermined counting range, a second alert signal indicating that the target voltage has been attacked by a undershoot glitch injection is issued.

[0103] In one possible implementation, a first prompt signal is issued when the first pulse width count value is within a first predetermined count range, and a second prompt signal is issued when the second pulse width count value is within a second predetermined count range.

[0104] In one possible implementation, after issuing a first alert signal, a first reset signal is received, and the historical first alert signal is cleared according to the first reset signal to re-detect the next upward spike in the target voltage. After issuing a second alert signal, a second reset signal is received, and the historical second alert signal is cleared according to the second reset signal to re-detect the next downward spike in the target voltage.

[0105] In one possible implementation, when a high-level indication glitch occurs in the rectangular wave signal, the duration or number of clock signals between sequentially adjacent rising and falling edges in the overshoot glitch signal is determined as a first pulse width count value, and the duration or number of clock signals between sequentially adjacent rising and falling edges in the undershoot glitch signal is determined as a second pulse width count value. When a low-level indication glitch occurs in the rectangular wave signal, the duration or number of clock signals between sequentially adjacent falling and rising edges in the overshoot glitch signal is determined as the first pulse width count value, and the duration or number of clock signals between sequentially adjacent falling and rising edges in the undershoot glitch signal is determined as the second pulse width count value.

[0106] In one possible implementation, the overshoot glitch signal is clock-domain synchronized to synchronize it with the operating clocks of the first counter and the first decision unit. The undershoot glitch signal is also clock-domain synchronized to synchronize it with the operating clocks of the second counter and the second decision unit.

[0107] In one possible implementation, when generating the voltage indication signal, the target voltage can be sampled, and an overvoltage indication signal and an undervoltage indication signal can be determined based on the difference between the sampling result and the bandgap reference voltage. The overvoltage indication signal indicates an upward spike in the target voltage, and the undervoltage indication signal indicates a downward spike in the target voltage. Both the overvoltage and undervoltage indication signals are rectangular wave signals. When performing level conversion on the voltage indication signals, the overvoltage indication signal can be level-converted to obtain an upward spike signal, and the undervoltage indication signal can be level-converted to obtain a downward spike signal.

[0108] In one possible implementation, when generating the voltage indication signal, a first voltage difference between a first voltage obtained by sampling the target voltage and a bandgap reference voltage can be calculated. This first voltage difference is then shaped using a Schmitt trigger to obtain an overvoltage indication signal. Conversely, a second voltage difference between the bandgap reference voltage and a second voltage obtained by sampling the target voltage can be calculated. This second voltage difference is then shaped using a Schmitt trigger to obtain an undervoltage indication signal. Where the target voltage is free of glitches, the first voltage is greater than the bandgap reference voltage, and the bandgap reference voltage is greater than the second voltage.

[0109] It should be noted that the details of the burr detection method have been described in detail in conjunction with the structural diagram in the burr detection unit section of the above embodiments. For the specific process, please refer to the description in the aforementioned burr detection unit embodiments, and will not be repeated here.

[0110] The commercial value of the embodiments in this application

[0111] In this embodiment, the target voltage is sampled using an analog circuit to obtain a voltage indication signal for indicating glitches in the target voltage. Then, a level converter converts the voltage indication signal into a glitch signal in a digital circuit. A pulse width counter counts the pulse width of the glitch signal. An alarm decision unit issues a warning signal when the pulse width count value is within a predetermined range. Since the predetermined counting range is configurable, it can be used for glitches with different pulse widths, resulting in a wide detection range and strong applicability. The detection accuracy is flexible, capable of detecting both overshoot and undershoot glitches, and the glitch width can be flexibly configured. A reloading function is included; after clearing historical warning signals, glitches can be re-detected, improving the comprehensiveness of glitch detection.

[0112] It should be understood that the various embodiments in this specification are described in a progressive manner, and the same or similar parts between the various embodiments can be referred to mutually. Each embodiment focuses on describing the differences from other embodiments. In particular, for the method embodiments, since they are basically similar to the methods described in the apparatus and system embodiments, the description is relatively simple, and relevant parts can be referred to the descriptions of other embodiments.

[0113] It should be understood that the foregoing describes specific embodiments of this specification. Other embodiments are within the scope of the claims. In some cases, the actions or steps recited in the claims may be performed in a different order than that shown in the embodiments and may still achieve the desired result. Furthermore, the processes depicted in the drawings do not necessarily require the specific or sequential order shown to achieve the desired result. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.

[0114] It should be understood that the use of a singular form to describe an element or to show only one element in the accompanying drawings does not imply that the number of such element is limited to one. Furthermore, modules or elements described or shown as separate herein may be combined into a single module or element, and modules or elements described or shown as single herein may be broken down into multiple modules or elements.

[0115] It should also be understood that the terminology and expressions used herein are for descriptive purposes only, and one or more embodiments described herein should not be limited to these terms and expressions. The use of these terms and expressions does not exclude any illustrative and descriptive equivalent features (or parts thereof), and it should be recognized that various modifications that may exist should also be included within the scope of the claims. Other modifications, variations, and substitutions may also exist. Accordingly, the claims should be considered to cover all such equivalents.

Claims

1. A burr detection unit, comprising: A signal sampler is used to sample the target voltage to be detected and generate a voltage indication signal to indicate glitches in the target voltage based on the sampling results, wherein the voltage indication signal is a rectangular wave signal; A level converter is used to convert the voltage indication signal in the analog circuit to obtain the glitch signal in the digital circuit. A pulse width counter is used to count the pulse width of the glitch signal and obtain a pulse width count value. An alarm decision unit is used to issue a warning signal indicating that the number of glitches in the target voltage is abnormal when the pulse width count value is within a predetermined count range. The glitch signal includes an upward glitch signal and a downward glitch signal. The upward glitch signal is used to indicate an upward glitch in the target voltage, and the downward glitch signal is used to indicate a downward glitch in the target voltage. The pulse width counter is used to count the pulse width of the upward spur signal to obtain a first pulse width count value, and to count the pulse width of the downward spur signal to obtain a second pulse width count value. The alarm decision device is used to issue a first prompt signal indicating that the target voltage has an abnormal number of upward glitch signals when the first pulse width count value is within a first predetermined count range, and / or to issue a second prompt signal indicating that the target voltage has an abnormal number of downward glitch signals when the second pulse width count value is within a second predetermined count range. The signal sampler is used to sample the target voltage and determine an overvoltage indication signal and an undervoltage indication signal based on the difference between the sampling result and the bandgap reference voltage, wherein the overvoltage indication signal and the undervoltage indication signal are both rectangular wave signals. The level converter is used to perform level conversion on the overvoltage indication signal to obtain the overshoot glitch signal, and to perform level conversion on the undervoltage indication signal to obtain the undershoot glitch signal.

2. The burr detection unit according to claim 1, wherein, The pulse width counter includes a first counter and a second counter, and the alarm decision unit includes a first decision unit and a second decision unit; The first counter is used to count the pulse width of the upward burr signal to obtain the first pulse width count value; The second counter is used to count the pulse width of the undercut glitch signal to obtain the second pulse width count value; The first decision device is configured to issue the first prompt signal when the first pulse width count value is within the first predetermined count range; The second decision device is used to issue the second prompt signal when the second pulse width count value is within the second predetermined count range.

3. The burr detection unit according to claim 2, wherein, The first decision device is configured to receive a first reset signal after issuing a first prompt signal, and clear the historical first prompt signal according to the first reset signal, so as to re-detect the next upward spike in the target voltage; The second decision device is configured to receive a second reset signal after issuing a second prompt signal, and clear the historical second prompt signal according to the second reset signal, so as to re-detect the next undershoot glitch in the target voltage.

4. The burr detection unit according to claim 2, wherein, When a high level in a rectangular wave signal indicates a glitch, the first counter is used to determine the duration or number of clock signals between sequentially adjacent rising and falling edges in the up-thrust glitch signal as the first pulse width count value, and the second counter is used to determine the duration or number of clock signals between sequentially adjacent rising and falling edges in the down-thrust glitch signal as the second pulse width count value. When a low level in the rectangular wave signal indicates a glitch, the first counter is used to determine the duration or number of clock signals between sequentially adjacent falling edges and rising edges in the upward glitch signal as the first pulse width count value, and the second counter is used to determine the duration or number of clock signals between sequentially adjacent falling edges and rising edges in the downward glitch signal as the second pulse width count value.

5. The burr detection unit according to claim 2, wherein, The burr detection unit further includes: a first synchronizer and a second synchronizer; The level converter is used to send the overshoot glitch signal to the first synchronizer and the undershoot glitch signal to the second synchronizer. The first synchronizer is used to perform clock domain synchronization processing on the overshoot glitch signal, so that the overshoot glitch signal is synchronized with the working clock of the first counter and the first decision unit. The second synchronizer is used to perform clock domain synchronization processing on the undershoot glitch signal, so that the undershoot glitch signal is synchronized with the working clock of the second counter and the second decision unit.

6. The burr detection unit according to claim 1, wherein, The signal sampler includes: A first comparator is used to calculate a first voltage difference between a first voltage obtained by sampling the target voltage and the bandgap reference voltage, and to shape the first voltage difference using a Schmitt trigger to obtain the overvoltage indication signal, and then send the overvoltage indication signal to the level converter. The second comparator is used to calculate the second voltage difference between the bandgap reference voltage and the second voltage obtained by sampling the target voltage, and to shape the second voltage difference through a Schmitt trigger to obtain the undervoltage indication signal, and to send the undervoltage indication signal to the level converter; Wherein, when there are no glitches in the target voltage, the first voltage is greater than the bandgap reference voltage, and the bandgap reference voltage is greater than the second voltage.

7. A protective unit, comprising: The burr detection unit according to any one of claims 1-6; A controller is used to control the operation of the burr detection unit.

8. A processing unit, comprising: The protective unit according to claim 7; The scheduling unit is used to schedule the protection unit to perform burr detection tasks.

9. A computing system comprising the processing unit according to claim 8.

10. A method for detecting burrs, comprising: The target voltage to be detected is sampled, and a voltage indication signal is generated based on the sampling result to indicate glitches in the target voltage, wherein the voltage indication signal is a rectangular wave signal; The voltage indication signal in the analog circuit is level-converted to obtain the glitch signal in the digital circuit. The pulse width count is performed on the glitch signal to obtain the pulse width count value; When the pulse width count value is within a predetermined count range, a prompt signal is issued to indicate that the target voltage has an abnormal number of glitches. The glitch signal includes an upward glitch signal and a downward glitch signal. The upward glitch signal is used to indicate an upward glitch in the target voltage, and the downward glitch signal is used to indicate a downward glitch in the target voltage. The step of counting the pulse width of the glitch signal to obtain a pulse width count value includes: counting the pulse width of the upward glitch signal to obtain a first pulse width count value, and counting the pulse width of the downward glitch signal to obtain a second pulse width count value. The step of issuing a prompt signal to indicate that the number of glitches in the target voltage is abnormal when the pulse width count value is within a predetermined count range includes: issuing a first prompt signal to indicate that the number of upward glitches in the target voltage is abnormal when the first pulse width count value is within a first predetermined count range, and / or issuing a second prompt signal to indicate that the number of downward glitches in the target voltage is abnormal when the second pulse width count value is within a second predetermined count range; The step of sampling the target voltage to be detected and generating a voltage indication signal to indicate glitches in the target voltage based on the sampling result includes: sampling the target voltage and determining an overvoltage indication signal and an undervoltage indication signal based on the difference between the sampling result and the bandgap reference voltage, wherein the overvoltage indication signal and the undervoltage indication signal are both rectangular wave signals; The step of level-converting the voltage indication signal in the analog circuit to obtain the glitch signal in the digital circuit includes: level-converting the overvoltage indication signal to obtain the overshoot glitch signal, and level-converting the undervoltage indication signal to obtain the undershoot glitch signal.

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