Frequency detection device of clock signal and detection method thereof

Abstract

The present application provides a clock signal frequency detection device and a detection method thereof. The clock signal frequency detection device includes a pulse signal generator, a sampling signal generator, a delay device, and a sampling circuit. The pulse signal generator detects multiple transition edges of a clock signal and generates a pulse signal according to the transition edges of the clock signal. The sampling signal generator generates a sampling signal according to a pulse on the pulse signal based on a command signal. The delay device delays the command signal to generate a delayed command signal. The sampling circuit samples the delayed command signal according to the sampling signal to generate a detection result.

Description

Technical Field

[0001] This invention relates to a clock signal frequency detection device and method, and more particularly to a clock signal frequency detection device and method that does not require a reference clock signal. Background Technology

[0002] In memory circuits, users can perform read operations at different frequencies. During high-frequency read operations, the memory circuit must increase the operating current of the sense amplifier and charge pump circuit to cope with the high-speed read operation. However, maintaining a high operating current for the sense amplifier and charge pump circuit during low-frequency read operations would result in wasted current. Summary of the Invention

[0003] This invention relates to a clock signal frequency detection device and method, which can effectively detect the frequency of a clock signal without the need for an additional reference clock signal.

[0004] According to an embodiment of the present invention, a clock signal frequency detection device includes a pulse signal generator, a sampling signal generator, a delay unit, and a sampling circuit. The pulse signal generator detects multiple transition edges of the clock signal and generates a pulse signal based on these transition edges. The sampling signal generator generates a sampling signal based on a command signal and multiple pulses in the pulse signal. The delay unit delays the command signal to generate a delayed command signal. The sampling circuit samples the delayed command signal based on the sampling signal to generate a detection result.

[0005] According to an embodiment of the present invention, a clock signal frequency detection method includes: detecting a plurality of transition edges of a clock signal and generating a pulse signal based on the transition edges of the clock signal; generating a sampling signal based on a plurality of pulses on the pulse signal according to a command signal; delaying the command signal to generate a delayed command signal; and sampling the delayed command signal based on the sampling signal to generate a detection result.

[0006] Based on the above, this invention delays the command signal using a delay unit and generates a sampling signal using a sampling signal generator based on the pulse signal generated by the transition edge of the clock signal. By sampling the delayed command signal using this sampling signal, it is possible to effectively determine whether the clock signal frequency is too slow. The frequency detection device of this invention does not require an additional reference clock signal, reducing power consumption caused by the transition edge of the reference clock signal and reducing the required circuit area. Furthermore, based on the frequency detection result of the clock signal, subsequent circuits (e.g., memory circuits) can adjust, for example, the operating frequency of the charge pump circuit and the operating bias voltage of the address decoder, effectively reducing the overall power consumption of the circuit. Attached Figure Description

[0007] Figure 1 This is a schematic diagram of a clock signal frequency detection device according to an embodiment of the present invention;

[0008] Figure 2 This is a circuit diagram of a clock signal frequency detection device according to another embodiment of the present invention;

[0009] Figure 3A as well as Figure 3B The waveform diagram shows the frequency detection operation of the frequency detection device according to an embodiment of the present invention.

[0010] Figure 4 This is a schematic diagram illustrating an embodiment of the delay unit of the frequency detection device according to an embodiment of the present invention;

[0011] Figure 5 This is a circuit diagram of a clock signal frequency detection device according to another embodiment of the present invention;

[0012] Figure 6 This is a flowchart of the frequency detection operation of a clock signal according to an embodiment of the present invention.

[0013] Explanation of icon numbers

[0014] 100, 200, 500: Frequency detection device;

[0015] 110, 210, 510: Pulse signal generator;

[0016] 120, 220, 520: Sampling signal generator;

[0017] 130, 230, 400, 530: Delay units;

[0018] 140, 240, 540: Sampling circuit;

[0019] CKIN: pulse signal;

[0020] CLK: Clock signal;

[0021] DS: Delayed command signal;

[0022] READS: Command signal;

[0023] SLOWCLK: Detection results;

[0024] SS: Sampling signal;

[0025] AD1: AND gate;

[0026] EN: Enable signal;

[0027] DFF1~DFFN+1: Reversing circuit;

[0028] D: Data terminal;

[0029] Q: Output terminal;

[0030] CK: Clock input;

[0031] QB: Inverting output terminal;

[0032] dRB, DET, Q1: Signals;

[0033] CSB: Chip Select Signal;

[0034] IV1~IV3: Inverters;

[0035] dT: Delay time;

[0036] TS1, TS2: Set time intervals;

[0037] NO1, NO2: NOR gates;

[0038] CSBb: Output signal;

[0039] 410: Comparator circuit;

[0040] 420: Reference voltage generator;

[0041] 412: Differential pair;

[0042] 411: Active load;

[0043] 413: Current source;

[0044] VR: Reference voltage;

[0045] M1: Transistor;

[0046] R1~R4: Resistors;

[0047] C1: Capacitor;

[0048] VP1, VP2, VSS, RVPP: Power supply voltages;

[0049] S610~S640: Steps. Detailed Implementation

[0050] Please refer to Figure 1The frequency detection device 100 includes a pulse signal generator 110, a sampling signal generator 120, a delay unit 130, and a sampling circuit 140. The pulse signal generator 110 receives a clock signal CLK. The pulse signal generator 110 detects multiple transition edges of the clock signal CLK and generates a pulse signal CKIN based on the transition edges of the clock signal CLK. The clock signal CLK can be an external input from the user and serves as the operating clock for accessing core circuits (e.g., memory circuits) downstream of the frequency detection device 100.

[0051] In this embodiment, the pulse signal generator 110 can detect multiple rising edges or multiple falling edges of the clock signal CLK. It then generates multiple pulses in the pulse signal CKIN corresponding to the rising (or falling) edges of the clock signal CLK. Specifically, the pulse signal generator 110 can be a one-shot circuit that performs logic operations on the clock signal CLK and its inverted signal to generate the pulse signal CKIN.

[0052] In detail, when the pulse signal generator 110 performs an AND logic operation on the clock signal CLK and its inverted signal, the pulse signal generator 110 can generate multiple pulses on the pulse signal CKIN corresponding to multiple rising edges of the clock signal CLK. Additionally, when the pulse signal generator 110 performs a NOR logic operation on the clock signal CLK and its inverted signal, the pulse signal generator 110 can generate multiple pulses on the pulse signal CKIN corresponding to multiple falling edges of the clock signal CLK.

[0053] On the other hand, sampling signal generator 120 is coupled to pulse signal generator 110. Sampling signal generator 120 can receive command signal READS and pulse signal CKIN generated by pulse signal generator 110. During a set time interval in the frequency detection operation, command signal READS can be set to a first logic value, and sampling signal generator 120 can generate sampling signal SS based on multiple pulses on pulse signal CKIN according to command signal READS.

[0054] Specifically, after the command signal READS is set to the first logic value, the sampling signal generator 120 can generate an enabled sampling signal SS corresponding to the Mth pulse of the pulse signal CKIN. Here, M can be any positive integer greater than 1, and can be set by the designer according to actual needs.

[0055] Delay unit 130 is coupled to sampling signal generator 120. Delay unit 130 receives command signal READS and generates delayed command signal DS by delaying command signal READS. Sampling circuit 140 is coupled to delay unit 130 and sampling signal generator 120. Sampling circuit 140 receives delayed command signal DS and sampling signal SS. Sampling circuit 140 samples delayed command signal DS using sampling signal SS to generate detection result SLOWCLK. Delay unit 130 can delay command signal READS according to a preset delay time, and can postpone the transition time of delayed command signal DS.

[0056] In this embodiment, if the clock signal CLK is too slow, the frequency of the pulse signal CKIN generated based on the transition edge of the clock signal CLK will also be too slow. Therefore, the sampling time point of the sampling signal SS generated based on a specific pulse of the pulse signal CKIN can fall after the transition time point of the delayed command signal DS. In this way, the sampling circuit 140 can generate a detection result SLOWCLK equal to the first logic value, indicating that the frequency of the user-input clock signal CLK is too slow.

[0057] In the above description, the first logic value can be a logic value 1, and the second logic value can be a logic value 0. Alternatively, in other embodiments, the first logic value can be a logic value 0, and the second logic value can be a logic value 1.

[0058] Conversely, if the clock signal CLK is not too slow, the sampling time of the sampling signal SS generated based on a specific pulse of the pulse signal CKIN can fall before the transition time of the delayed command signal DS. In this way, the sampling circuit 140 can generate a detection result SLOWCLK that is not equal to the first logic value (for example, equal to the second logic value), indicating that the frequency of the user-input clock signal CLK is not too slow.

[0059] In other words, the first detection frequency of the clock signal CLK when the detection result SLOWCLK equals the first logic value can be higher than the second detection frequency of the clock signal CLK when the detection result SLOWCLK equals the second logic value, where the first logic value is the inverse of the second logic value.

[0060] Please refer to the following: Figure 2The frequency detection device 200 includes a pulse signal generator 210, a sampling signal generator 220, a delay unit 230, and a sampling circuit 240. The pulse signal generator 210 receives the clock signal CLK via an AND gate AD1. The AND gate AD1 also receives an enable signal EN. When the enable signal EN is logic 0, it blocks the pulse signal generator 210 from receiving the clock signal CLK, and the pulse signal generator 210 does not perform any operation. When the enable signal EN is logic 1, the pulse signal generator 210 can receive the clock signal CLK and generates a pulse signal CKIN based on the transition edge of the clock signal CLK.

[0061] The sampling signal generator 220 includes multiple flip-flops DFF1 to DFF3. Each flip-flop DFF1 to DFF3 has a data terminal D, a clock terminal CK, an output terminal Q, and an inverting output terminal QB. Specifically, the data terminal D of the first-stage flip-flop DFF1 receives the command signal READS; the clock terminals CK of flip-flops DFF1 to DFF3 all receive the pulse signal CKIN; the output terminal Q of flip-flop DFF1 is coupled to the data terminal D of the secondary flip-flop DFF2; the output terminal Q of flip-flop DFF2 is coupled to the data terminal D of the secondary flip-flop DFF3; the inverting output terminal QB of flip-flop DFF1 generates the signal dRB; and the output terminal Q of flip-flop DFF2 generates the sampling signal SS. The signal dRB can be the inverse of the command signal READS with a time delay. Flip-flop DFF1 can perform a synchronization action on the pulses of the pulse signal CKIN corresponding to the command signal READS.

[0062] In this embodiment, after the command signal READS changes to the first logic value, the flip-flop DFF2 can enable the sampling signal SS (change to the first logic value) by the second pulse on the corresponding pulse signal CKIN.

[0063] The delay unit 230 receives the signal dRB and the enable signal EN. When the enable signal EN is a logic value of 0, the delay unit 230 is not activated; conversely, when the enable signal EN is a logic value of 1, the delay unit 230 can be activated. The delay unit 230 can delay the signal dRB and generate a delay command signal DS.

[0064] The sampling circuit 240 is constructed using a flip-flop DFF4. The data terminal D of the flip-flop DFF4 receives the delay command signal DS, and the clock terminal CK of the flip-flop DFF4 receives the sampling signal SS. In this way, the flip-flop DFF4 can sample the delay command signal DS through the sampling signal SS to generate the detection result SLOWCLK.

[0065] Incidentally, in this embodiment, the flip-flop DFF4 can generate the detection result SLOWCLK through the inverting output terminal QB and the inverter IV2. In other embodiments, the flip-flop DFF4 can also directly generate the detection result SLOWCLK through the inverting output terminal QB.

[0066] It can be seen that the frequency detection device 200 of the present invention can quickly generate a detection result SLOWCLK by having the sampling circuit 240 sample the delayed command signal DS for the sampling signal SS, which corresponds to the frequency change of the clock signal CLK provided by the user, thus achieving a rapid response effect.

[0067] In addition, the frequency detection device 200 further includes a NOR gate NO1 and an inverter IV1. Inverter IV1 receives the signal DET, while NOR gate NO1 receives its output signal and the chip select signal CSB. When either the chip select signal CSB or the output signal of inverter IV1 is a logic value of 1, NOR gate NO1 generates an output signal CSBb to reset the sampling signal generator 220 and the sampling circuit 240. When the output signal of inverter IV1 is a logic value of 0, the output signal CSBb can be an inverted chip select signal.

[0068] The frequency detection device 200 also includes a NOR gate NO2. The NOR gate NO2 receives the output signal of the output terminal Q of the flip-flop DFF3 and the chip selection signal CSB, and generates an enable signal EN.

[0069] Please refer to the following as well. Figure 2 , Figure 3A as well as Figure 3B , Figure 3A The waveform diagram shows the frequency detection operation where the clock signal CLK does not exhibit excessive slowness. When the command signal READS is set to a first logic value (e.g., logic 1) within the set time interval TS1, the pulse signal generator 210 generates a pulse signal CKIN with multiple pulses based on the rising edge of the clock signal CLK. The first pulse of the pulse signal CKIN causes the output Q of the flip-flop DFF1 to generate a signal Q1 with a logic value of 1. The flip-flop DFF2 then generates a sampling signal SS at its output Q based on the second pulse of the pulse signal CKIN. Meanwhile, the delay unit 230 generates a delayed command signal DS based on the signal dRB provided by the inverted output QB of the flip-flop DFF1, wherein the delay command signal DS is delayed by a time dT from the rising edge of the signal Q1.

[0070] Furthermore, the sampling circuit 240 samples the delayed command signal DS based on the sampling signal SS. Figure 3AIn the middle, the sampling circuit 240 samples the delayed command signal DS based on the sampling signal SS, which can generate a detection result SLOWCLK equal to the logic value 0, and indicates that the frequency of the clock signal CLK is not too slow.

[0071] Incidentally, during the reset time RSTT1, the chip select signal CSB can be pulled high, resetting the sampling signal generator 220 and the sampling circuit 240. After the chip select signal CSB is pulled low again, the frequency detection device 200 can perform the next frequency detection operation.

[0072] Please note that the delay time dT can be set according to the allowable value of the frequency of the clock signal CLK to be judged. Specifically, if the allowable value of the frequency of the clock signal CLK being too slow is high, the delay unit 230 can provide a relatively large delay time dT; conversely, if the allowable value of the frequency of the clock signal CLK being too slow is low, the delay unit 230 can provide a relatively small delay time dT.

[0073] Figure 3B The waveform diagram illustrates the frequency detection operation for a clock signal CLK that is too slow. When the command signal READS is set to a first logic value (e.g., logic 1) within a set time interval TS2, the pulse signal generator 210 generates a pulse signal CKIN with multiple pulses based on the rising edge of the clock signal CLK. The first pulse of the pulse signal CKIN causes the output Q of the flip-flop DFF1 to generate a signal Q1 with a logic value of 1. The flip-flop DFF2 then generates a sampling signal SS at its output Q based on the second pulse of the pulse signal CKIN. Meanwhile, the delay unit 230 generates a delayed command signal DS based on the signal dRB provided by the inverted output QB of the flip-flop DFF1, wherein the delay command signal DS is delayed by a time dT from the rising edge of the signal Q1.

[0074] Furthermore, the sampling circuit 240 samples the delayed command signal DS based on the sampling signal SS. Figure 3B The sampling circuit 240 samples the delayed command signal DS based on the sampling signal SS, which can generate a detection result SLOWCLK equal to the logic value 1, indicating that the frequency of the clock signal CLK is too slow.

[0075] Similarly, during the reset time RSTT2, the chip select signal CSB can be pulled high, resetting the sampling signal generator 220 and the sampling circuit 240. After the chip select signal CSB is pulled low again, the frequency detection device 200 can perform the next frequency detection operation.

[0076] Please refer to the following: Figure 4The delay unit 400 includes a comparator circuit 410 and a reference voltage generator 420. The comparator circuit 410 includes a differential pair 412, an active load 411, and a current source 413. The first terminal of the differential pair 412 receives signal A1, and the second terminal receives a reference voltage VR. The input stage of the delay unit 400 may include inverters IV41 and IV42 connected in series, and resistors R1 and R2. Signal A1 can be generated by a delayed signal dRB, where signal A1 can be an inverse delayed signal of a command signal. A transistor M1 and a capacitor C1 are coupled to the first terminal of the differential pair 412. Transistor M1 is connected in series between the first terminal of the differential pair 412 and the power supply voltage VP1, and capacitor C1 is connected in series between the first terminal of the differential pair 412 and the power supply voltage VSS. The power supply voltage VP1 can be an operating power supply, and the power supply VSS can be a reference ground power supply.

[0077] The control terminal of transistor M1 receives the output signal CSBb, which is an inverted chip select signal, and when the output signal CSBb is equal to the logic value 0, the delay unit 400 can be deactivated.

[0078] Additionally, the reference voltage generator 420 includes resistors R3 and R4. Resistors R3 and R4 are connected in series between the power supply voltage VP2 and the power supply voltage VSS, forming a voltage divider circuit. The reference voltage generator 420 generates a reference voltage VR by dividing the power supply voltage VP2, wherein the power supply voltage VP2 may or may not be equal to the power supply voltage VP1, and the reference voltage VR may be equal to half of the power supply voltage VP2.

[0079] In this embodiment, the delay unit 400 generates a delay effect by comparing the inverse delayed signal of the command signal with the reference voltage VR, instead of using multiple inverters to provide the delay effect. Therefore, the delay unit 400 does not consume power due to the frequent switching operations of multiple inverters, achieving energy saving and carbon reduction.

[0080] Incidentally, the current source 413 of the comparator circuit 410 is biased to the power supply voltage RVPP, providing a stable bias current.

[0081] Please refer to the following: Figure 5The frequency detection device 500 includes a pulse signal generator 510, a sampling signal generator 520, a delay unit 530, and a sampling circuit 540. The frequency detection device 500 in this embodiment is largely the same as the aforementioned frequency detection device 200, and related operational details will not be elaborated here. Unlike the frequency detection device 200, in the frequency detection device 500, the sampling signal generator 520 may include multiple flip-flops (e.g., N, where N is a positive integer) DFF1 to DFFN. The designer can select any one of the flip-flops DFF2 to DFFN-1 to generate the sampling signal SS according to actual application requirements, without specific limitations.

[0082] Furthermore, in this embodiment, the sampling circuit 540 can be constructed using a flip-flop DFFN+1.

[0083] Incidentally, in this embodiment, the frequency detection device 500 can be applied to a memory circuit and performs frequency detection of the user-input clock signal CLK during a read operation. Therefore, the command signal READS used by the frequency detection device 500 can be a data read command executed on the memory circuit. Of course, the frequency detection device 500 can also be used with other types of command signals to perform frequency detection operations, and there are no fixed limitations.

[0084] In this embodiment, when the clock signal frequency is detected to be too slow, subsequent circuits (e.g., memory circuits) can adjust the operating clock of, for example, the charge pump circuit, and the operating bias voltage of the address decoder. This effectively reduces the overall power consumption of the circuit and improves the overall circuit efficiency.

[0085] Please refer to the following: Figure 6 In step S610, multiple transition edges of the clock signal are detected, and a pulse signal is generated based on the transition edges of the clock signal. In step S620, a sampling signal is generated based on multiple pulses in the pulse signal, according to the command signal. Furthermore, in step S630, the command signal is delayed to generate a delayed command signal. In step S640, the delayed command signal is sampled based on the sampling signal to generate a detection result.

[0086] The implementation details of the above steps have been described in detail in the aforementioned embodiments and implementation methods, and will not be repeated here.

[0087] In summary, the clock signal frequency detection device of the present invention generates a pulse signal based on the transition edge of the clock signal, and generates a sampling signal based on the pulse signal. The sampling signal is used to sample the delayed command signal, thereby determining whether the clock signal frequency is too slow. The frequency detection device of the present invention does not require a reference clock signal, effectively reducing power consumption and circuit area. Furthermore, by using a sampling circuit to sample the delayed command signal based on the sampling signal, the present invention can quickly obtain the frequency state of the clock signal, improving the response rate.

[0088] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A frequency detection device for a clock signal, comprising: A pulse signal generator detects multiple transition edges of the clock signal and generates a pulse signal having multiple pulses corresponding to the multiple transition edges based on the multiple transition edges of the clock signal. A sampling signal generator generates a sampling signal by sequentially delaying the command signal according to the plurality of pulses on the pulse signal within a set time interval, based on a command signal. Delay unit, which delays the command signal to generate a delayed command signal; as well as A sampling circuit samples the delayed command signal based on the sampling signal to generate a detection result. The sampling circuit then uses the logic value of the detection result to determine whether the frequency of the clock signal is too slow. The sampling signal generator includes multiple flip-flops, each of which receives the pulse signal at multiple clock terminals. The output of each flip-flop is coupled to the data terminal of the next-stage flip-flop. The data terminal of the first-stage flip-flop receives the command signal. The output of the last-stage flip-flop is passed through a NOR gate to generate an enable signal. The pulse signal generator and the delay unit are activated according to the enable signal.

2. The frequency detection device according to claim 1, wherein the pulse signal generator is a single-click circuit that generates the plurality of pulses on the pulse signal according to the plurality of rising edges of the clock signal.

3. The frequency detection device according to claim 1, wherein the sampling signal is generated at the output of one of the flip-flops from the second stage to the last stage.

4. The frequency detection device according to claim 1, wherein the output terminal of the first stage flip-flop transmits the inverse delay signal of the command signal.

5. The frequency detection device according to claim 4, wherein the delay unit comprises: A comparator circuit generates the delayed command signal by comparing the inverse delayed signal of the command signal with a reference voltage; as well as A reference voltage generator is used to generate the reference voltage.

6. The frequency detection device according to claim 5, wherein the delay unit further comprises: A transistor, coupled between a first power supply voltage and an endpoint of the inverse delayed signal of the comparator circuit receiving the command signal, is controlled by an inverse chip select signal; as well as A capacitor is coupled between the endpoint of the inverse delayed signal of the comparator circuit receiving the command signal and the second power supply voltage.

7. The frequency detection device according to claim 5, wherein the comparison circuit comprises: The differential pair receives the inverse delayed signal of the command signal and the reference voltage, respectively. An active load is coupled between the differential pair and the first power supply voltage; as well as A current source is coupled between the differential pair and the second power supply voltage.

8. The frequency detection device according to claim 5, wherein the reference voltage generator comprises: A voltage divider circuit receives a third power supply voltage and divides the third power supply voltage to generate the reference voltage.

9. The frequency detection device according to claim 1, wherein the sampling circuit comprises: A flip-flop has a data terminal to receive the delayed command signal, a clock terminal to receive the sampling signal, and an output terminal to generate the detection result.

10. The frequency detection device according to claim 1, wherein the sampling signal generator and the sampling circuit perform a reset operation according to a chip selection signal.

11. The frequency detection device according to claim 10, wherein when the sample signal generator and the sampling circuit perform a reset operation, the pulse signal generator and the delay unit stop operating.

12. A method for detecting the frequency of a clock signal, comprising: A pulse signal generator is provided to detect multiple transition edges of the clock signal and generate a pulse signal having multiple pulses corresponding to the multiple transition edges based on the multiple transition edges of the clock signal. A sampling signal generator is provided to generate a sampling signal based on a command signal, by sequentially delaying the command signal according to the plurality of pulses on the pulse signal within a set time interval. A delayer is provided to delay the command signal to generate a delayed command signal; A sampling circuit is provided to sample the delayed command signal based on the sampling signal to generate a detection result, and the frequency of the clock signal is determined based on the logic value of the detection result. The sampling signal generator provides multiple flip-flops, which receive the pulse signal at multiple clock terminals of the multiple flip-flops, and the output terminals of each flip-flop are coupled to the data terminals of each flip-flop in the next stage. The data terminals of the flip-flops in the first stage receive the command signal, and the output terminals of the flip-flops in the last stage are passed through a NOR gate to generate an enable signal. as well as The pulse signal generator and the delay unit are activated according to the enable signal.

13. The frequency detection method according to claim 12, wherein the step of generating the pulse signal based on the plurality of transition edges of the clock signal comprises: The plurality of pulses on the pulse signal are generated based on the plurality of rising edges of the clock signal.

14. The frequency detection method according to claim 12, further comprising: During the detection process, the command signal is set to a first logic value within a set time interval; When the generated detection result is equal to the first logic value, the detection result indicates that the frequency of the clock signal is the first detection frequency; as well as When the generated detection result is equal to the second logic value, the detection result indicates that the frequency of the clock signal is the second detection frequency. The first detection frequency is higher than the second detection frequency, and the first logic value is the inverse of the second logic value.

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