Array substrate and liquid crystal display panel

Abstract

The application provides an array substrate and a liquid crystal display panel. The array substrate comprises a substrate, a common electrode line, an insulating layer, a common electrode, a first passivation layer and a pixel electrode layer which are sequentially stacked. The pixel electrode layer comprises a pixel electrode and a bridging electrode insulated from the pixel electrode. The common electrode is provided with a first through hole, the first passivation layer is provided with a second through hole, and the insulating layer is provided with a third through hole which exposes the common electrode line. The orthogonal projection of the hole wall of the first through hole on the substrate is a first orthogonal projection, the orthogonal projection of the hole wall of the second through hole on the substrate is a second orthogonal projection, and the first orthogonal projection partially overlaps with the second orthogonal projection. The first through hole, the second through hole and the third through hole are connected, and the bridging electrode extends into the first through hole, the second through hole and the third through hole to be connected with the common electrode and the common electrode line. The application can improve the success rate of deep hole formation by setting the partially overlapped first through hole and the second through hole.

Description

Technical Field

[0001] This application relates to the field of display technology, and more particularly to an array substrate and a liquid crystal display panel. Background Technology

[0002] Fringe field switching (FFS) liquid crystal display panels and in-plane switching (IPS) liquid crystal display panels both control the rotation of liquid crystal molecules within a plane to achieve image display. One known type of FFS liquid crystal display panel uses, for example... Figure 1 The diagram shows a 5-mask architecture. This 5-mask architecture includes a substrate S, a common electrode M1, a gate insulating layer GI, a first passivation layer PV1, a common electrode CITO, a second passivation layer PV2, and a pixel electrode layer PITO, all sequentially stacked on the substrate S. The first metal layer M1 is the layer where the gate signal is located. The gate insulating layer GI isolates the first metal layer M1 from the second metal layer M2. The second metal layer M2 is the layer where the data signal is located. The first passivation layer PV1 isolates the first metal layer M1 from the common electrode layer CITO. The second passivation layer PV2 isolates the common electrode layer CITO from the pixel electrode layer PITO. However, in this 5-mask architecture, the pixel electrode layer PITO is needed to bridge the first metal layer M1 and the common electrode layer CITO to stabilize the pixel voltage.

[0003] In the 5-mask architecture, the pixel electrode layer PITO is located at the very top of the pixel, and its fabrication is the final step in the pixel fabrication process. Meanwhile, the common electrode layer CITO is located in the middle, below the second passivation layer PV2. The main advantages of this process are: First, the closer proximity of the common electrode layer C-ITO and the pixel electrode layer PITO reduces the torque of the electric field between the two electrode layers, thus facilitating liquid crystal rotation and reducing the voltage value (Vop) required for the pixel to reach maximum brightness, thereby reducing power consumption; Second, a non-halftone mask process can be used, reducing the distance between the gate and drain, and between the pixel electrode and drain, thus narrowing the black matrix width and increasing the pixel aperture ratio. However, the 5-mask architecture results in a pixel thickness of 13000 Å. The deep hole connecting the first metal layer M1 and the pixel electrode layer PITO needs to penetrate the second passivation layer PV2, the first passivation layer PV1, and the gate insulating layer GI in a single photomask fabrication process, making the fabrication of the deep hole challenging. If the deep hole cannot be successfully formed, the first metal layer M1 cannot be connected to the pixel electrode layer PITO, resulting in poor connection. Summary of the Invention

[0004] In view of this, this application provides an array substrate and a liquid crystal display panel that can improve the success rate of deep hole formation.

[0005] This application provides an array substrate, comprising: a substrate, a common electrode line disposed on the substrate, a gate insulating layer disposed on the common electrode line, a first passivation layer disposed on the gate insulating layer, a common electrode disposed on the first passivation layer, a second passivation layer disposed on the common electrode, and a pixel electrode layer disposed on the second passivation layer.

[0006] The pixel electrode layer includes a pixel electrode and a bridging electrode insulated from the pixel electrode. A first through-hole is formed in the common electrode, a second through-hole is formed in the first passivation layer, and a third through-hole is formed in the insulating layer. The third through-hole exposes the common electrode line. The orthographic projection of the hole wall of the first through-hole on the substrate is a first orthographic projection, and the orthographic projection of the hole wall of the second through-hole on the substrate is a second orthographic projection. The first and second orthographic projections partially overlap. The first through-hole, the second through-hole, and the third through-hole are connected. The bridging electrode extends into the first through-hole, the second through-hole, and the third through-hole and connects with the common electrode and the common electrode line.

[0007] Optionally, the length direction of the second orthographic projection is defined as the first direction, and the direction perpendicular to the first direction is defined as the second direction. In the first direction and / or the second direction, at least one end of the second orthographic projection is located outside the first orthographic projection.

[0008] Optionally, the length direction of the second orthographic projection is defined as the first direction, and the direction perpendicular to the first direction is defined as the second direction. In the first direction and / or the second direction, at least one end of the first orthographic projection is located outside the second orthographic projection.

[0009] Optionally, the length direction of the second orthographic projection is defined as the first direction, and the direction perpendicular to the first direction is defined as the second direction. In the first direction and / or the second direction, at least one end of the second orthographic projection is located outside the first orthographic projection; and

[0010] In the first direction and / or the second direction, at least one end of the first orthographic projection is located outside the second orthographic projection.

[0011] Optionally, in the second direction, both ends of the second orthographic projection are located outside the first orthographic projection; and

[0012] In the first direction, both ends of the first orthographic projection are located outside the second orthographic projection.

[0013] Optionally, in the second direction, one end of the second orthographic projection is located outside the first orthographic projection, and the other end is located inside the first orthographic projection; and

[0014] In the first direction, both ends of the first orthographic projection are located outside the second orthographic projection.

[0015] Optionally, the array substrate further includes a metal pad, which is disposed between the common electrode line and the common electrode. In the first direction and / or the second direction, the orthographic projection of the pad on the substrate extends from outside the first orthographic projection to between the first orthographic projection and the second orthographic projection.

[0016] Optionally, the first direction is the extension direction of the common electrode line.

[0017] Optionally, the first through hole and the second through hole are both rectangular or rounded rectangles, the length direction of the first through hole is one of the first direction and the second direction, and the length direction of the second through hole is the other of the first direction and the second direction.

[0018] Optionally, in the first direction and / or the second direction, the first passivation layer covers the common electrode.

[0019] Optionally, in the first direction and / or the second direction, the first through-hole exposes the common electrode.

[0020] This application also provides a liquid crystal display panel, which includes the array substrate described above.

[0021] According to the array substrate and liquid crystal display panel of this application, a first via is formed by patterning a common electrode before patterning the first passivation layer, and the first via partially overlaps with a second via. Since there is no common electrode obstructing the overlap between the second and first vias, the underlying insulating layer can be etched while the first passivation layer is being etched, thereby improving the success rate of deep hole formation. Furthermore, in the non-overlapping areas of the second and first vias, the common electrode is exposed, allowing the bridging portion to connect to the common electrode line. Attached Figure Description

[0022] To more clearly illustrate the technical solutions in this application, the drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0023] Figure 1This is a schematic diagram of a known 5mask architecture.

[0024] Figure 2 This is a top view of an array substrate according to an embodiment of this application.

[0025] Figure 3(a) shows Figure 2 A schematic diagram of the first via of the common electrode layer in the array substrate, Figure 3(b) is shown. Figure 2 In the array substrate, a schematic diagram of the second via of the first passivation layer is shown. Figure 3(c) is a top view of the first via and the second via of Figures 3(a) and 3(b). Figure 3(d) is a cross-sectional view of Figure 3(c) along line AA. Figure 3(e) is a cross-sectional view of Figure 3(c) along line BB.

[0026] Figure 4(a) is a top view of the first through hole and the second through hole of the array substrate according to another embodiment of the present application, Figure 4(b) is a cross-sectional view of Figure 4(a) along line AA, and Figure 4(c) is a cross-sectional view of Figure 4(a) along line BB.

[0027] Figure 5(a) is a top view of the first through hole and the second through hole of the array substrate according to another embodiment of the present application, Figure 5(b) is a cross-sectional view of Figure 5(a) along line AA, and Figure 5(c) is a cross-sectional view of Figure 5(a) along line BB. Detailed Implementation

[0028] The technical solutions of this application will now be clearly and completely described with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.

[0029] In this application, unless otherwise expressly specified and limited, "above" or "below" a second feature can include the first and second features being directly connected, or it can include the first and second features not being directly connected but contacting each other through another feature between them. Furthermore, "above," "over," and "on top" of a second feature includes the first feature being directly above or diagonally above the second feature, or simply indicates that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" a second feature includes the first feature being directly below or diagonally below the second feature, or simply indicates that the first feature is at a lower horizontal level than the second feature. Moreover, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, features defined with "first" and "second" may explicitly or implicitly include one or more features.

[0030] While researching the difficulties in manufacturing deep holes using the 5mask architecture, the inventors discovered that: Figure 1 In the 5-mask architecture, the bridging via H, used to bridge the common electrode line CL and the common electrode CITO, is formed by patterning the second passivation layer PV2, the first passivation layer PV1, and the gate insulating layer GI in a single photomask process. Because the common electrode CITO is located below the second passivation layer PV2 at the bridging via H, and the material of the common electrode CITO is a transparent conductive material, while the second passivation layer PV2, the first passivation layer PV1, and the gate insulating layer GI are inorganic materials, the etching methods for transparent conductive materials and inorganic materials differ. The common electrode CITO below the second passivation layer PV2 prevents the simultaneous etching of the first passivation layer PV1 and the gate insulating layer GI, leading to deep via formation failure. If the bridging electrode above is misaligned during deposition, bridging may also fail.

[0031] This application provides an array substrate and a liquid crystal display panel using such an array substrate. The array substrate includes a substrate, a common electrode line disposed on the substrate, a gate insulating layer disposed on the common electrode line, a first passivation layer disposed on the gate insulating layer, a common electrode disposed on the first passivation layer, a second passivation layer disposed on the common electrode, and a pixel electrode layer disposed on the second passivation layer. The pixel electrode layer includes a pixel electrode and a bridging electrode insulated from the pixel electrode. A first via is formed in the common electrode, a second via is formed in the first passivation layer, and a third via is formed in the insulating layer. The third via exposes the common electrode line. The orthographic projection of the wall of the first via on the substrate is a first orthographic projection, and the orthographic projection of the wall of the second via on the substrate is a second orthographic projection. The first and second orthographic projections partially overlap. The first, second, and third vias are connected. The bridging electrode extends into the first, second, and third vias and connects to the common electrode and the common electrode line.

[0032] This application patterns a common electrode to form a first via before patterning the first passivation layer, with the first via partially overlapping with a second via. Since there is no common electrode obstructing the overlap between the second and first vias, the underlying insulating layer can be etched simultaneously with the first passivation layer, thereby improving the success rate of deep via formation. Furthermore, in the non-overlapping areas of the second and first vias, the common electrode is exposed, allowing the bridging portion to connect to the common electrode line.

[0033] The specific embodiments of this application will be described below with reference to the accompanying drawings.

[0034] Please refer to Figure 2 , Figure 3(d) and 3(e)An array substrate 100 according to one embodiment of this application includes a substrate 10 and multiple parallel scan lines GL (only one is shown in the figure), multiple parallel data lines DL (only one is shown in the figure), multiple thin film transistors (only one is shown in the figure) T and multiple pixel electrodes PX disposed on the substrate 10.

[0035] The substrate 10 is used to support various components disposed thereon. The substrate 10 can be a rigid substrate 10 such as glass or plastic, or an organic flexible substrate 10.

[0036] Multiple scan lines GL and multiple data lines DL intersect to define multiple pixel regions. Optionally, the scan lines GL and data lines DL can intersect perpendicularly. Multiple thin-film transistors T serve as switching elements. Each pixel region is provided with one thin-film transistor T and one pixel electrode PX. The thin-film transistor T includes a gate GE, a source SE, and a drain DE. The gate GE is connected to the scan line GL, the source SE is connected to the data line DL, and the drain DE is connected to the pixel electrode PX.

[0037] The array substrate 100 also includes a common electrode line CL, an insulating layer IL, a common electrode CE, a first passivation layer PV1, and a pixel electrode layer PL.

[0038] The common electrode line CL is used to provide a common signal to the common electrode CE. The common electrode line CL is disposed on the same layer as the gate GE of the thin-film transistor T on the array substrate 100. The materials of the common electrode line CL and the gate can be selected from copper (Cu), tantalum (Ta), tungsten (W), molybdenum (Mo), aluminum (Al), titanium (Ti), or alloys thereof. The materials of the common electrode line CL and the gate GE can be a single layer of metal or a multilayer of metal. Examples of multilayer metals include a stack of copper (Cu) and molybdenum (Mo), a stack of copper (Cu) and molybdenum-titanium (MoTi) alloy, a stack of copper (Cu) and titanium (Ti), a stack of aluminum (Al) and molybdenum (Mo), a stack of molybdenum (Mo) and tantalum (Ta), a stack of molybdenum (Mo) and tungsten (W), and a stack of molybdenum (Mo)-aluminum (Al)-molybdenum (Mo), etc.

[0039] An insulating layer IL covers the common electrode line CL. Optionally, the thin-film transistor T in this embodiment is a bottom-gate thin-film transistor. The insulating layer IL includes a gate insulating layer GI covering the gate GE and the common electrode line CL, and a second passivation layer PV2 disposed on the gate insulating layer GI. In other embodiments of this application, depending on the type of thin-film transistor T, the insulating layer IL may also include other film layers. For example, when the thin-film transistor T is a top-gate thin-film transistor T, the insulating layer IL may include an interlayer insulating layer. The insulating layer IL can be a single layer or a stack of silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, titanium oxide, etc.

[0040] The common electrode CE is disposed on the insulating layer IL, specifically on the second passivation layer PV2. The common electrode CE provides a common voltage and forms an electric field with the pixel electrode PX to drive the liquid crystal deflection. The material of the common electrode CE can be indium tin oxide (ITO).

[0041] The first passivation layer PV1 covers the common electrode CE. The first passivation layer PV1 can be a single layer or a stack of silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, titanium oxide, etc.

[0042] The pixel electrode layer PL is disposed on the first passivation layer PV1. The pixel electrode layer PL includes a pixel electrode PX and a bridging electrode BE that is insulated from the pixel electrode PX.

[0043] Please refer to Figures 3(a) to 3(e) A first via TH1 is formed in the common electrode CE, a second via TH2 is formed in the first passivation layer PV1, and a third via TH3 is formed in the insulating layer IL. That is, the third via TH3 penetrates both the first passivation layer PV1 and the gate insulating layer GI. The third via TH3 exposes the common electrode line CL. The orthographic projection of the wall of the first via TH1 onto the substrate 10 is the first orthographic projection O1, and the orthographic projection of the wall of the second via TH2 onto the substrate 10 is the second orthographic projection O2. The first orthographic projection O1 and the second orthographic projection O2 partially overlap. Two directions parallel to the surface of the substrate 10 are defined as the first direction D1 and the second direction D2, and the first direction D1 and the second direction D2 intersect. Here, "the surface of the substrate 10" refers to the surface perpendicular to the thickness direction. In the first direction D1 and / or the second direction D2, at least one end of the second orthographic projection O2 is located outside the first orthographic projection O1, then the first orthographic projection O1 and the second orthographic projection O2 partially overlap. In other words, in a top view, as shown in Figure 3(c), the first through hole TH1 and the second through hole TH2 partially overlap. As shown in Figures 3(d) and 3(e), the first through hole TH1, the second through hole TH2, and the third through hole TH3 are connected, and the bridging electrode BE extends into the first through hole TH1, the second through hole TH2, and the third through hole TH3 to connect with the common electrode CE and the common electrode line CL.

[0044] In the part where the second via TH2 overlaps with the first via TH1, since there is no common electrode CE blocking it, the first passivation layer PV1 can be etched while the underlying insulating layer IL is being etched, thereby improving the success rate of deep hole formation. In the part where the second via TH2 does not overlap with the first via TH1, the common electrode CE is exposed, so that the bridging electrode BE can be connected to the common electrode CE and thus connected to the common electrode line CL.

[0045] On the other hand, in Figure 3(d), during the etching of the first passivation layer PV1, due to the obstruction of the common electrode CE below the passivation layer, etching defects are easily generated during the etching of the insulating layer IL (i.e., the second passivation layer PV2 and the gate insulating layer GI), forming holes on the sidewalls of the insulating layer IL. Subsequently, when the bridging electrode BE is formed on the sidewalls, wire breakage is likely to occur. In Figure 3(e), since there is no obstruction of the common electrode CE, the first passivation layer PV1 is etched together with the insulating layer IL, and no holes are formed on the sidewalls of the insulating layer IL, thereby preventing the subsequent wire breakage of the bridging electrode BE.

[0046] Furthermore, the length direction of the second orthographic projection O2 is defined as the first direction D1, and the direction perpendicular to the first direction D1 is defined as the second direction D2. It should be noted that the orthographic projections of the first via TH1 and the second via TH2 on the substrate 10 may be regular shapes such as rectangles, rounded rectangles, squares, circles, and ellipses, or other irregular shapes. As shown in Figure 3(b), the length direction of the second orthographic projection O2 is defined as the direction of the line connecting the two farthest points on the second orthographic projection O2, or any direction parallel to the line connecting the two farthest points on the second orthographic projection O2. That is, neither the first direction D1 nor the second direction D2 is limited to a specific starting or ending point; they only represent their direction. Optionally, the extension direction of the common electrode line CL is defined as the first direction D1, and the direction perpendicular to the first direction D1 is defined as the second direction D2. However, this application does not limit the specific directions of the first direction D1 and the second direction D2. The first direction D1 can also be any direction intersecting the extension direction of the common electrode CL.

[0047] In the first direction D1 and / or the second direction D2, at least one end of the second orthographic projection O2 is located outside the first orthographic projection O1. That is, in the first direction D1 and / or the second direction D2, the orthographic projection of the hole wall of at least one end of the second via TH2 onto the substrate 10 is located outside the orthographic projection of the hole wall of the first via TH1 onto the substrate 10. Thus, in the first direction D1 and / or the second direction D2, the first passivation layer PV1 can cover the common electrode CE. It can be understood that this is based on the premise that the first orthographic projection O1 and the second orthographic projection O2 partially overlap, excluding the case where the first orthographic projection O1 and the second orthographic projection O2 completely overlap.

[0048] When the orthographic projection of the hole wall at at least one end of the second via TH2 onto the substrate 10 is outside the orthographic projection of the hole wall of the first via TH1 onto the substrate 10, the first passivation layer PV1 covers the common electrode CE. When the first passivation layer PV1 is etched, it is not blocked by the common electrode CE below, and the underlying insulating layer IL can be etched away together.

[0049] Optionally, in this embodiment, in the first direction D1, both ends of the second orthographic projection O2 are located outside the first orthographic projection O1.

[0050] In the first direction D1 and / or the second direction D2, at least one end of the first orthographic projection O1 is located outside the second orthographic projection O2. That is, in the first direction D1 and / or the second direction D2, the orthographic projection of the hole wall of at least one end of the first via TH1 onto the substrate 10 is located outside the orthographic projection of the hole wall of the second via TH2 onto the substrate 10. Thus, the first via TH1 exposes the common electrode CE for bridging electrode BE connection.

[0051] Specifically, the first through-hole TH1 and the second through-hole TH2 are either rectangular or rounded rectangles. The length direction of the first through-hole TH1 is one of the first direction D1 and the second direction D2, and the length direction of the second through-hole TH2 is the other of the first direction D1 and the second direction D2. As shown in Figure 3(c), the first through-hole TH1 is a rounded rectangle with a length direction of 12 μm in the first direction D1 and a width direction of 5.5 μm in the second direction D2. Furthermore, the first direction D1 is the extension direction of the common electrode line CL. The second through-hole TH2 is also a rounded rectangle with a length direction of 12 μm in the second direction D2 and a width direction of 5.5 μm in the first direction D1. The first through-hole TH1 and the second through-hole TH2 intersect in a cross shape when viewed from above. Both the first through-hole TH1 and the second through-hole TH2 are elongated holes, and their extension directions are perpendicular to each other, which is beneficial for the alignment of the two holes and increases the overlap area. In addition, the dimensions of the first through-hole TH1 and the second through-hole TH2 can be designed according to process constraints to ensure the aperture ratio.

[0052] In the second direction D2, both ends of the second orthographic projection O2 are located outside the first orthographic projection O1, and in the first direction D1, both ends of the first orthographic projection O1 are located outside the second orthographic projection O2. That is, from a top view, both ends of the first through-hole TH1 in the first direction D1 are located outside the ends of the second through-hole TH2 in the first direction D1, for bridging purposes; and both ends of the second through-hole TH2 in the second direction D2 are located outside the ends of the first through-hole TH1 in the second direction D2, facilitating deep hole etching.

[0053] It is understood that this application does not limit the shape of the first through hole TH1 and the second through hole TH2. The first through hole TH1 and the second through hole TH2 can also be square holes or circular holes.

[0054] Please refer to Figures 4(a) to 4(c)In another embodiment of this application, in the second direction D2, one end of the second orthographic projection O2 is located outside the first orthographic projection O1, and the other end is located inside the first orthographic projection O1. Furthermore, in the first direction D1, both ends of the first orthographic projection O1 are located outside the second orthographic projection O2. That is, from a top-view perspective, in the second direction D2, one end of the first through-hole TH1 is located outside the second through-hole TH2, and the other end is located inside the second through-hole TH2. Thus, the common electrode CE is exposed from the first through-hole TH1, and the bridging electrode BE can be connected to the common electrode line CL through the exposed common electrode CE. Moreover, a step S is formed between the first passivation layer PV1 and the common electrode CE. Compared to the side without the step S, the alignment film flows more easily from the location where the step S is formed, thereby preventing alignment film accumulation.

[0055] It is understood that in this embodiment, the bridging function can be achieved solely through the setting on the second direction D2, thereby improving the success rate of deep hole formation and solving the technical problem. In other embodiments, the setting of the first through hole TH1 and the second through hole TH2 on the first direction D1 is not limited. Of course, in this embodiment, the through hole setting on the first direction D1 can increase the connection reliability of the bridging electrode BE, the common electrode CE, and the common electrode line CL.

[0056] Please refer to Figures 5(a) to 5(c) In another embodiment of this application, the array substrate 100 further includes a raised portion M, which is disposed between the common electrode line CL and the common electrode CE. Specifically, in the first direction D1 and / or the second direction D2, the orthogonal projection of the raised portion M on the substrate 10 extends from the outside of the first orthogonal projection O1 to between the first orthogonal projection O1 and the second orthogonal projection O2. When viewed from above, since the raised portion M extends from below the first passivation layer PV1 to between the first via TH1 and the second via TH2, it raises the common electrode CE between the first via TH1 and the second via TH2, thereby forming a step S on the common electrode CE. Compared to the side without the step S, the alignment film flows more easily from the location where the step S is formed, thereby preventing alignment film accumulation. Optionally, considering the aperture ratio and wiring design, the raised portion M extends along the first direction D1.

[0057] Furthermore, in this embodiment, the insulating layer IL includes a gate insulating layer GI and a second passivation layer PV2, and the raised portion M is located between the gate insulating layer GI and the second passivation layer PV2, and can be formed using the same layer of metal as the source SE and drain DE. It is understood that this application does not limit this aspect.

[0058] The material of the raised portion M can be selected from copper (Cu), tantalum (Ta), tungsten (W), molybdenum (Mo), aluminum (Al), titanium (Ti), or alloys thereof. The material of the raised portion M can be a single layer of metal or a multilayer of metal. Examples of multilayer metals include a stack of copper (Cu) and molybdenum (Mo), a stack of copper (Cu) and molybdenum-titanium (MoTi) alloy, a stack of copper (Cu) and titanium (Ti), a stack of aluminum (Al) and molybdenum (Mo), a stack of molybdenum (Mo) and tantalum (Ta), a stack of molybdenum (Mo) and tungsten (W), and a stack of molybdenum (Mo)-aluminum (Al)-molybdenum (Mo), etc.

[0059] This application also provides a liquid crystal display panel 1, which includes an array substrate 100, a color filter substrate 200, and a liquid crystal layer 300. The array substrate 100 and the color filter substrate 200 are disposed opposite to each other. The liquid crystal layer 300 is disposed between the array substrate 100 and the color filter substrate 200.

[0060] The foregoing has provided a detailed description of the embodiments of this application. Specific examples have been used to illustrate the principles and implementation methods of this application. The descriptions of the embodiments above are only for the purpose of helping to understand this application. Furthermore, those skilled in the art will recognize that, based on the ideas of this application, there will be changes in the specific implementation methods and application scope. Therefore, the content of this specification should not be construed as a limitation of this application.

Claims

1. An array substrate, characterized in that, include: Substrate; A common electrode line is disposed on the substrate; A gate insulating layer is disposed on the common electrode line; A second passivation layer is disposed on the gate insulating layer; A common electrode is disposed on the second passivation layer; A first passivation layer is disposed on the common electrode; as well as A pixel electrode layer is disposed on the first passivation layer. The pixel electrode layer includes a pixel electrode and a bridging electrode insulated from the pixel electrode. A first via is formed in the common electrode, a second via is formed in the first passivation layer, and a third via is formed in the gate insulating layer and the second passivation layer. The third via exposes the common electrode line. The orthographic projection of the wall of the first via on the substrate is a first orthographic projection, and the orthographic projection of the wall of the second via on the substrate is a second orthographic projection. The first and second orthographic projections partially overlap. The first via, the second via, and the third via are connected. The bridging electrode extends into the first via, the second via, and the third via and connects to the common electrode and the common electrode line. The length direction of the second orthographic projection is defined as the first direction, and the direction perpendicular to the first direction is defined as the second direction. In the first direction and / or the second direction, at least one end of the second orthographic projection is located outside the first orthographic projection, and in the first direction and / or the second direction, at least one end of the first orthographic projection is located outside the second orthographic projection. The array substrate further includes a metal pad, which is disposed between the common electrode line and the common electrode. In the first direction and / or the second direction, the orthogonal projection of the pad on the substrate extends from the outside of the second orthogonal projection to the second orthogonal projection, but does not extend into the first orthogonal projection.

2. The array substrate as described in claim 1, characterized in that, In the second direction, both ends of the second orthographic projection are located outside the first orthographic projection; and In the first direction, both ends of the first orthographic projection are located outside the second orthographic projection.

3. The array substrate as described in claim 1, characterized in that, In the second direction, one end of the second orthographic projection is located outside the first orthographic projection, and the other end is located inside the first orthographic projection; and In the first direction, both ends of the first orthographic projection are located outside the second orthographic projection.

4. The array substrate as described in any one of claims 1-3, characterized in that, The first direction is the extension direction of the common electrode line.

5. The array substrate as described in claim 4, characterized in that, The first through hole and the second through hole are both rectangular or rounded rectangles. The length direction of the first through hole is one of the first direction and the second direction, and the length direction of the second through hole is the other of the first direction and the second direction.

6. The array substrate as described in any one of claims 1-3, characterized in that, In the first direction and / or the second direction, the first passivation layer covers the common electrode.

7. The array substrate as described in any one of claims 1-3, characterized in that, In the first direction and / or the second direction, the first through-hole exposes the common electrode.

8. A liquid crystal display panel, characterized in that, Includes the array substrate as described in any one of claims 1 to 6.

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