Three-dimensional chip and method for manufacturing the same

Abstract

The application provides a three-dimensional chip and a preparation method thereof, and the method comprises the following steps: forming a first pattern on a first wafer by using a first mask plate; the first mask plate comprises a first alignment mark; aligning a second alignment mark on a second mask plate with the first alignment mark, and forming a second pattern on a second wafer by using the second mask plate; the second mask plate is different in size from the first mask plate; moving the second mask plate by a predetermined distance along a predetermined direction, and forming the second pattern on the second wafer by using the second mask plate again; wherein the size of the predetermined distance satisfies that the second alignment mark is aligned with the first alignment mark again. Through the above method, the alignment of the mask plates with different sizes can be realized by using simple alignment marks without affecting the layout and wiring, so that the three-dimensional chip can be prepared by using the mask plates with different sizes.

Description

Technical Field

[0001] This invention relates to the field of three-dimensional chip manufacturing technology, and in particular to a three-dimensional chip based on photomasks of different sizes and its fabrication method. Background Technology

[0002] In the integrated circuit manufacturing process, the pattern on the layout is first made into a mask, with each chip as a unit. Then, a photolithography machine projects the pattern from the mask onto a wafer, and moves the mask to fill the entire wafer with the pattern. The size of the mask is generally related to the size of the chip layout. For example, for Dynamic Random Access Memory (DRAM) chips, the area is generally not very large, and when manufacturing masks, an array of chips is considered on each mask, meaning that each mask will have several identical chip patterns. For System-on-Chips (SOC) chips, the area is generally larger, and each mask may only have one chip.

[0003] In 3D integrated circuit manufacturing, DRAM chips are typically used as the bottom layer and SOC chips as the top layer. Alignment marks required for the 3D integrated circuit manufacturing process are pre-set in the masks for both types of chips. If the masks for both types of chips are the same size and the alignment marks are positioned accordingly, they can be aligned and bonded to form a 3D chip. A schematic diagram of this stacking is shown below. Figure 1 As shown. However, in order to match larger capacity DRAM chips, SOC chips are often larger than DRAM chips. In this case, one SOC chip may cover one or more DRAM chips, which means that the alignment marks on the SOC chip cannot correspond one-to-one with the alignment marks on the DRAM chip's mask, making it difficult to achieve three-dimensional bonding.

[0004] For example, for Figure 1 A DRAM mask with pre-set alignment marks and a 4×6 layout is to be aligned with a 6×8 SOC mask. Figure 2 The alignment method shown requires six different SOC masks with different alignment marks to ensure a one-to-one correspondence with the alignment marks in the DRAM mask, which is clearly impractical. If only one SOC mask is used, then the six different alignment mark methods must be combined and formed in the mask as shown. Figure 3 The alignment marks shown are excessive, but too many alignment marks will occupy a large number of the winding channels of the SOC chip, seriously affecting the layout and routing of the SOC chip.

[0005] In view of this, it is necessary to design an improved method for fabricating three-dimensional chips to align masks of different sizes in order to solve the above problems. Summary of the Invention

[0006] To address the shortcomings of the prior art, the present invention aims to provide a three-dimensional chip and its fabrication method, which achieves alignment of masks of different sizes with simple alignment marks without affecting the layout and wiring, and then uses masks of different sizes to fabricate a three-dimensional chip.

[0007] To achieve the above objectives, the present invention provides a method for fabricating a three-dimensional chip, comprising:

[0008] A first pattern is formed on a first wafer using a first mask; the first mask includes a first alignment mark;

[0009] Align the second alignment mark on the second mask with the first alignment mark, and use the second mask to form a second pattern on the second wafer; the second mask has a different size than the first mask;

[0010] The second mask is moved a predetermined distance along a predetermined direction, and the second pattern is formed again on the second wafer using the second mask; wherein the predetermined distance is such that the second alignment mark is aligned with the first alignment mark again.

[0011] As a further improvement of the present invention, moving the second mask plate a predetermined distance along a predetermined direction includes:

[0012] The second mask is moved a first predetermined distance along a first direction so that the second alignment mark is aligned with the first alignment mark again. The first predetermined distance is n1(a+m), where n1 is a positive integer, a is the width of the second pattern, and m is the width of the longitudinal cut. And / or

[0013] The second mask is moved a second predetermined distance along the second direction so that the second alignment mark is aligned with the first alignment mark again. The second predetermined distance is n2(b+l), where n2 is a positive integer, b is the length of the second pattern, and l is the width of the transverse cutting channel.

[0014] As a further improvement of the present invention, moving the second mask plate a predetermined distance along a predetermined direction includes:

[0015] The second mask is moved a third predetermined distance along a predetermined direction. The third predetermined distance is the sum of the width of the second pattern and the width of the longitudinal cutting channel, or the third predetermined distance is the sum of the length of the second pattern and the width of the transverse cutting channel.

[0016] As a further improvement of the present invention, the preparation method further includes:

[0017] The first wafer and the second wafer are three-dimensionally bonded, and the first wafer and the second wafer are cut along the longitudinal dicing and the transverse dicing.

[0018] As a further improvement of the present invention, the size of the first mask is smaller than the size of the second mask.

[0019] As a further improvement of the present invention, the step of forming a first pattern on a first wafer using the first mask includes:

[0020] The first mask is moved a fourth distance along the first direction; the fourth distance is the sum of the width of the first pattern and the width of the longitudinal cut; and / or

[0021] The first mask is moved a fifth distance along the second direction; the fifth distance is the sum of the length of the first pattern and the width of the transverse cut.

[0022] As a further improvement of the present invention, the first mask includes a plurality of first chip unit patterns arranged in an array along the first direction and / or the second direction, the longitudinal cutting channel is formed between adjacent first chip unit patterns arranged along the first direction, and the transverse cutting channel is formed between adjacent first chip unit patterns arranged along the second direction; the first alignment mark includes a first transverse alignment mark disposed in the transverse cutting channel and a first longitudinal alignment mark disposed in the longitudinal cutting channel.

[0023] To achieve the above objectives, the present invention also provides a three-dimensional chip, comprising a first wafer and a second wafer stacked together;

[0024] The first wafer includes a first pattern; the first pattern includes a first alignment mark;

[0025] The second wafer includes a second pattern; the second pattern includes a second alignment mark, and the second pattern has a different size from the first pattern;

[0026] The second pattern is formed by a mask when the second alignment mark is aligned with the first alignment mark, or by the mask being formed by moving a predetermined distance along a predetermined direction when the second alignment mark is aligned with the first alignment mark.

[0027] As a further improvement of the present invention, the first pattern includes a first chip unit, and the second pattern includes a second chip unit; the first sub-pattern in the first chip unit and the second sub-pattern in the second chip unit are physically connected; the first sub-pattern includes an initial pattern that matches the second sub-pattern and an extended pattern formed by extending the extension of the initial pattern outward by a predetermined size.

[0028] As a further improvement of the present invention, the predetermined size is 0.1 to 3 μm.

[0029] The beneficial effects of this invention are:

[0030] 1. The method for fabricating a three-dimensional chip provided by this invention involves transferring a first pattern from a first mask onto a first wafer, and then aligning only when the second alignment mark on the second mask aligns with the first alignment mark. In other positions, the alignment process is omitted, and blind movement is performed directly at a predetermined distance under misalignment conditions. Alignment is then performed again when the second alignment mark on the second mask aligns with the first alignment mark, thus correcting errors caused by blind movement. Based on the method provided by this invention, alignment is not required for every movement of the second mask, simplifying the alignment process. Furthermore, the first and second alignment marks only need to be aligned after moving a predetermined distance along a predetermined direction. Therefore, it is unnecessary to fabricate multiple first masks with different alignment marks, nor is it necessary to set a large number of alignment marks to achieve alignment after each movement, effectively reducing the impact of alignment marks on layout and wiring.

[0031] 2. The three-dimensional chip provided by the present invention improves the layout structure during the layout design stage, and extends the extension of the initial graphic in the first graphic, which is used to physically connect with the second graphic, by a predetermined size to form an extended graphic, so that the part that is not aligned with the initial graphic due to misalignment during blind shifting can still fall into the range of the extended graphic, ensuring that a good physical connection can still be maintained after blind shifting. Attached Figure Description

[0032] Figure 1 A stacking diagram illustrating the alignment of two identical photomasks.

[0033] Figure 2 This is a schematic diagram of the alignment marks in different SOC masks when aligning SOC masks and DRAM masks one by one.

[0034] Figure 3 for Figure 2 A schematic diagram of the structure after taking the alignment marks and combining them in different SOC masks.

[0035] Figure 4This is a schematic diagram of the stacking of the first and second photomasks after alignment in one embodiment of the present invention.

[0036] Figure 5 This is a schematic diagram of the structure of a first pattern arranged in an array on a first wafer, as shown in one embodiment of the present invention.

[0037] Figure 6 for Figure 4 The relative position of the projection of the second mask and the first pattern in the center alignment state.

[0038] Figure 7 This is a schematic diagram of the arrangement of the second pattern formed on the second wafer in one embodiment of the present invention.

[0039] Figure 8 This is a schematic diagram of the structure when the second sub-graphic is aligned with the first sub-graphic in one embodiment of the present invention.

[0040] Figure 9 This is a schematic diagram illustrating the alignment of the second sub-figure with the first sub-figure under different conditions.

[0041] Figure Labels

[0042] 10-First mask; 11-First alignment mark; 111-First lateral alignment mark; 112-First longitudinal alignment mark; 12-First chip cell pattern; 121-First sub-pattern; 1211-Initial pattern; 1212-Extended pattern; 13-lateral cut; 14-longitudinal cut; 20-Second mask; 21-Second pattern; 211-Second alignment mark; 2111-Second lateral alignment mark; 2112-Second longitudinal alignment mark; 212-Second sub-pattern. Detailed Implementation

[0043] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be described in detail below with reference to the accompanying drawings and specific embodiments.

[0044] It should also be noted that, in order to avoid obscuring the present invention with unnecessary details, only the structures and / or processing steps closely related to the present invention are shown in the accompanying drawings, while other details that are not closely related to the present invention are omitted.

[0045] Additionally, it should be noted that the terms “comprising,” “including,” or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article, or apparatus.

[0046] like Figure 4-8As shown, the present invention provides a method for fabricating a three-dimensional chip, comprising:

[0047] A first pattern is formed on a first wafer using a first mask 10; the first mask 10 includes a first alignment mark 11.

[0048] Align the second alignment mark 211 on the second mask 20 with the first alignment mark 11, and use the second mask 20 to form the second pattern 21 on the second wafer; the second mask 20 is different in size from the first mask 10.

[0049] The second mask 20 is moved a predetermined distance along a predetermined direction, and the second pattern 21 is formed on the second wafer again using the second mask 20; wherein the predetermined distance is such that the second alignment mark 20 is aligned with the first alignment mark 11 again.

[0050] Based on the above method, the present invention can achieve alignment between masks of different sizes by moving the second mask 20 a predetermined distance in a predetermined direction, so that the second alignment mark 211 in the second mask 20 after the predetermined distance is moved is aligned with the first alignment mark 11, under the condition that the first alignment mark 11 and the second alignment mark 211 are different in size and cannot be aligned one by one, by moving the second mask 20 a predetermined distance in a predetermined direction.

[0051] In some embodiments of the present invention, the step of forming a first pattern on a first wafer using a first mask 10 includes:

[0052] The first mask 10 is moved along the first direction, and the distance moved each time is the sum of the width of the first pattern and the width of the longitudinal cutting channel 14; and / or

[0053] The first mask 10 is moved along the second direction, and the distance moved each time is the sum of the length of the first pattern and the width of the transverse cutting channel 13.

[0054] The first direction and the second direction are two mutually perpendicular directions parallel to the plane of the first wafer. The above steps can be completed using a photolithography system. By performing photolithography after each movement of the first mask 10, several first patterns arranged in an array along the first and second directions can be formed on the first wafer.

[0055] Similarly, in some embodiments of the present invention, when forming the second pattern 21 on the second wafer using the second mask 20, a photolithography system can also be used to form a plurality of second patterns 21 on the second wafer by performing photolithography after each movement of the second mask 20.

[0056] In some embodiments of the present invention, moving the second mask 20 a predetermined distance along a predetermined direction includes:

[0057] The second mask 20 is moved a first predetermined distance along the first direction so that the second alignment mark 211 is aligned with the first alignment mark 11 again. The first predetermined distance is n1(a+m), where n1 is a positive integer, a is the width of the second pattern 21, and m is the width of the longitudinal cutting channel 14; and / or

[0058] The second mask 20 is moved a second predetermined distance along the second direction so that the second alignment mark 211 is aligned with the first alignment mark 11 again. The second predetermined distance is n2(b+l), where n2 is a positive integer, b is the length of the second pattern 21, and l is the width of the transverse cutting channel 13.

[0059] Wherein, n1 and n2 can be calculated based on the dimensions of the first and second figures 21. For example, if the width and length of the second figure 21 are a and b respectively, and the width and length of the first figure are c and d respectively, then n1 = [a,c] / a, n2 = [b,d] / b. Wherein, [a,c] represents the least common multiple of a and c, and [b,d] represents the least common multiple of b and d.

[0060] After moving the material a predetermined distance as described above, the second alignment mark 211 in the second mask 20 can be aligned with the first alignment mark 11.

[0061] In some embodiments of the present invention, when moving along the first direction, the distance of each movement is the sum of the width of the second pattern 21 and the width of the longitudinal cutting channel 14. When the number of movements is less than n1, the second alignment mark 211 in the second mask 20 cannot be aligned with the first alignment mark 11. In this case, alignment can be omitted and the second pattern 21 can be formed directly by photolithography. When the number of movements is n1, the second alignment mark 211 in the second mask 20 can be aligned with the first alignment mark 11. Then, alignment is performed and the second pattern 21 is formed by photolithography.

[0062] Similarly, when moving along the second direction, the distance moved each time is the sum of the length of the second pattern 21 and the width of the transverse cutting channel 13. When the number of moves is less than n², the second alignment mark 211 in the second mask 20 cannot be aligned with the first alignment mark 11. In this case, alignment can be omitted and the second pattern 21 can be formed directly by photolithography. When the number of moves is n², the second alignment mark 211 in the second mask 20 can be aligned with the first alignment mark 11. Then, alignment is performed before photolithography is used to form the second pattern 21.

[0063] By employing the above method, alignment is not required for every movement of the second mask 20. Alignment is only needed in the initial state, and then again when the second alignment mark 211 aligns with the first alignment mark 11 after moving a predetermined distance in a predetermined direction. This corrects errors caused by blind movement, effectively simplifying the alignment process. Furthermore, since the first alignment mark 11 and the second alignment mark 211 only need to be aligned after moving a predetermined distance in a predetermined direction, it is unnecessary to fabricate multiple first masks 10 with different alignment marks, nor is it necessary to set a large number of alignment marks to achieve alignment after each movement. This effectively reduces the impact of alignment marks on layout and wiring. Based on the above alignment method, it is possible to align masks of different sizes, reducing the limitations on mask size during chip manufacturing to ensure compatibility with chips of different sizes.

[0064] More specifically, such as Figure 4 As shown, in one embodiment of the present invention, the first mask 10 is a DRAM mask. The first pattern of the DRAM mask includes a plurality of DRAM chip cell patterns arranged in an array along a first direction and a second direction. Adjacent DRAM chip cell patterns form mutually perpendicular horizontal cutting channels 13 and vertical cutting channels 14. The first alignment mark 11 includes a rectangular first horizontal alignment mark 111 disposed in the horizontal cutting channel 13 and a rectangular first vertical alignment mark 112 disposed in the vertical cutting channel 14. The second mask 20 is a SOC mask. The second pattern 21 of the SOC mask includes a SOC chip cell pattern and a second alignment mark 211. The shape and size of the second alignment mark 211 are completely consistent with the first alignment mark 11. It includes a second horizontal alignment mark 2111 consistent with the first horizontal alignment mark 111 and a second vertical alignment mark 2112 consistent with the first vertical alignment mark 112. Alignment can be achieved by moving the second alignment mark 211 to coincide with the first alignment mark 11.

[0065] In other embodiments of the present invention, the first chip unit pattern 12 in the first mask 10 and the second chip unit pattern in the second mask 20 can be selected from any stackable / bonded semiconductor chip product pattern, and are not limited to DRAM chips and SOC chips. The first chip unit pattern 12 and the second chip unit pattern are photolithographically etched on the first wafer and the second wafer, respectively, to form a three-dimensional chip in a stacking / bonding manner. The number of first chip unit patterns 12 in the first mask 10 and the number of second chip unit patterns in the second mask 20 can be adjusted according to actual needs. The specific shape, number, and position of the first alignment mark 11 and the second alignment mark 211 can also be adjusted according to actual needs, as long as alignment can be achieved without affecting the layout and wiring. The present invention is not limited thereto.

[0066] In this invention, the first mask 10 and the second mask 20, which are of different sizes, can be that the size of the first mask 10 is larger than the size of the second mask 20, so that the first mask 10 completely covers the second mask 20; or the size of the first mask 10 is smaller than the size of the second mask 20, so that the second mask 20 completely covers the first mask 10; or the sizes of the first mask 10 and the second mask 20 are different, and neither mask can completely cover the other, all of which can be aligned according to the method provided by this invention. Preferably, the size of the first mask 10 is smaller than the size of the second mask 20. With this configuration, under the same alignment area, the number of second patterns 21 that need to be photolithographically etched on the second wafer is less than the number of first patterns. By first forming a larger number of first patterns and then aligning the second patterns with the first patterns according to the method provided by this invention, fewer exposures are required, resulting in higher efficiency.

[0067] More specifically, in one embodiment of the present invention, when transferring the first pattern of the first mask 10 onto the first wafer using a photolithography system, the first mask 10 is moved along a first direction and a second direction perpendicular to each other on the wafer plane: when moving along the first direction, the distance moved each time is the sum of the width of the first pattern and the width of the longitudinal dicing 14; when moving along the second direction, the distance moved each time is the sum of the length of the first pattern and the width of the transverse dicing 13. After moving and photolithography in this manner, a pattern is formed on the wafer as shown in the image. Figure 5 The image shows several first figures arranged in an array. For ease of description, in... Figure 5 In the diagram, x and y represent the first direction and the second direction, respectively. In other embodiments of the present invention, the number, spacing, and arrangement of the first patterns on the first wafer can be adjusted as needed, and the present invention is not limited thereto.

[0068] Please refer to the following: Figure 4-7 In one embodiment of the present invention, both the first mask 10 and the second mask 20 are rectangular. When the lower left corner of the second graphic 21 (SOC11) projected by the second mask 20 coincides with the lower left corner of the first graphic, the second alignment mark 211 in the second mask 20 can be aligned with the first alignment mark 11 in the first graphic. At this time, the relative position of the projection of the second mask 20 and the first graphic is as follows: Figure 6 As shown. After photolithography is performed at this relative position, the second pattern 21 (SOC11) is formed.

[0069] Based on the dimensions of the first graphic (4×6) and the second graphic (6×8), we can calculate n1=2 and n2=3. That is, when blindly moving the second alignment mark 211 after it is aligned with the first alignment mark 11, if blindly moving along the x-direction, the distance moved each time is the sum of the width of the second graphic 21 and the width of the longitudinal cutting channel 14. Two moves are enough to align the second alignment mark 211 with the first alignment mark 11. If blindly moving along the y-direction, the distance moved each time is the sum of the length of the second graphic 21 and the width of the transverse cutting channel 13. Three moves are enough to align the second alignment mark 211 with the first alignment mark 11.

[0070] Based on the above pattern, the second mask 20 is changed from... Figure 4 The position corresponding to SOC11 in the image is blindly shifted along the x-direction. Each blind shift involves a distance equal to the sum of the width of the second pattern 21 and the width of the longitudinal cutting channel 14. During one blind shift, the second pattern 21 projected onto the second mask 20 is located at... Figure 4 At the position corresponding to SOC21, the second alignment mark 211 on the second mask 20 cannot be aligned with the first alignment mark 11 in any of the first patterns it covers (the second alignment mark 21 is in...). Figure 4 The stacking diagram is not shown, but can be determined according to... Figure 7 The position of the second alignment mark 211 in each of the second patterns 21 shown is determined, thus omitting the alignment and directly forming the second pattern 21 (SOC 21). Then, in a similar manner, a second blind shift is performed along the x-direction with a predetermined distance equal to the sum of the width of the second pattern 21 and the width of the longitudinal cut 14, so that the second pattern 21 projected by the second mask 20 is located in the position of the second pattern 21. Figure 4 At the position corresponding to SOC31, the second alignment mark 211 can be aligned with the first alignment mark 11. After alignment correction, photolithography is performed to form the second pattern 21 (SOC31) on the second wafer, thus correcting the errors generated during the previous blind moving process. Subsequently, blind moving continues in the above manner. If alignment fails after the first blind moving, alignment is omitted and photolithography is performed directly. If alignment is achieved after the second blind moving, alignment correction is performed before photolithography.

[0071] After the blind shift in the x-direction is completed, the second mask 20 can be blindly shifted in the y-direction. The distance of each blind shift is the sum of the length of the second pattern 21 and the width of the transverse cutting channel 13. The specific method is similar to the blind shift method in the x-direction. After the first and second blind shifts, since the second alignment mark 211 cannot be aligned with the first alignment mark 11, the alignment is omitted and photolithography is performed directly. After the third blind shift, the second alignment mark 211 can be aligned with the first alignment mark 11. Then, alignment correction is performed before photolithography. The specific process will not be described in detail here.

[0072] Repeat the movement in the x and y directions as described above until... Figure 7 The second figure 21 in the middle can completely cover Figure 5 The first graphic in the image represents the alignment completed. Figure 7 In the diagram, SOC11, SOC12, SOC13, etc., represent the second figure 21 in different positions.

[0073] In other embodiments of the present invention, when the second alignment mark 211 on the second mask 20 is aligned with the first alignment mark 11, the relative position of the second pattern 21 projected by the second mask and the first pattern is not limited to... Figure 6 The state shown can be adjusted according to the positions of the first alignment mark 11 and the second alignment mark 211. For example, when the first alignment mark 11 and the second alignment mark 211 are respectively set at the lower right corners of the first mask 10 and the second mask 20, alignment can only be achieved when the lower right corner of the second graphic 21 projected by the second mask 20 coincides with the lower right corner of the first graphic.

[0074] After forming the first pattern and the second pattern on the first wafer and the second wafer respectively according to the above method provided by the present invention, the first wafer and the second wafer are further three-dimensionally bonded, and the first wafer and the second wafer are cut along the longitudinal cutting channel 14 and the transverse cutting channel 13 to obtain a three-dimensional chip.

[0075] The three-dimensional chip includes a first wafer and a second wafer stacked together; the first wafer includes a first pattern; the first pattern includes a first alignment mark 11; the second wafer includes a second pattern 21; the second pattern 21 includes a second alignment mark 211, and the second pattern has a different size from the first pattern.

[0076] The second pattern 21 is formed by a mask when the second alignment mark 211 is aligned with the first alignment mark 11, or by moving the mask a predetermined distance along a predetermined direction after the second alignment mark 211 is aligned with the first alignment mark 11. The method of moving the mask a predetermined distance along the predetermined direction is consistent with the method described in the fabrication method of the three-dimensional chip, and will not be repeated here.

[0077] In some embodiments of the present invention, the first pattern includes a first chip unit, and the second pattern includes a second chip unit; the first sub-pattern in the first chip unit and the second sub-pattern in the second chip unit are physically connected.

[0078] More preferably, in some embodiments of the present invention, to avoid misalignment that may occur during blind shifting after omitting alignment, which could affect the physical connection between the first chip unit and the second chip unit in the three-dimensional chip, the first sub-pattern 121 in the first chip unit used for physical connection with the second chip unit is improved during the layout design stage. In conventional layout design, the initial pattern 1211 is used for physical connection with the second sub-pattern 212 in the second chip unit. The improved first sub-pattern 121 of the present invention is based on the initial pattern 1211, by extending the outer edge of the initial pattern 1211 outward by a predetermined size to form an extended pattern 1212 surrounding the initial pattern 1211. This ensures that the portion of the initial pattern 1211 that is misaligned during blind shifting can still fall within the range of the extended pattern 1212, guaranteeing a good physical connection after blind shifting.

[0079] Specifically, please refer to Figure 8-9 In one embodiment of the present invention, a first sub-pattern 121 corresponds to two second sub-patterns 212. The first sub-pattern 121 has a size of 1.7μm × 4.6μm, including an initial pattern 1211 with a size of 1.5μm × 4.4μm and an extended pattern 1212 surrounding the initial pattern 1211. The extended pattern 1212 is formed by extending outward by 0.1μm from the extension of the initial pattern 1211. Under the condition of perfect alignment without errors or misalignment, the projection (dashed line portion) of the second sub-pattern 212 should be in accordance with... Figure 9 As shown in (a), the second sub-pattern 212 falls into the corresponding position in the initial pattern 1211. However, if alignment is omitted during the alignment process and blind shifting is performed directly, errors and misalignments may occur during continuous blind shifting. Consequently, the projection of the second sub-pattern 212 after blind shifting may not completely fall into the initial pattern 1211, affecting the physical connection between the chip units corresponding to the first mask 10 and the second mask 20. In this embodiment, by expanding the initial pattern 1211 during the layout design stage to form a first sub-pattern 121 that also includes the expanded pattern 1212, the projection of the second sub-pattern 212 can still fall into the corresponding position in the initial pattern 1211 even after misalignment. Figure 9 The arrangement shown in (b) falls within the range of the first sub-pattern 121, ensuring good physical connectivity after blind shifting. Furthermore, in this embodiment, the extended size is designed to be 0.1 μm, which is small enough to achieve good physical connectivity without significantly affecting the area of ​​the final chip.

[0080] In other embodiments of the present invention, the outward extension dimension of the initial pattern 1211 can be adjusted based on the different dimensions of the first sub-pattern 121. Generally, the larger the size of the initial pattern 1211, the larger the outward extension dimension from the initial pattern 1211, and the outward extension dimension generally does not exceed 20% of the size of the initial pattern 1211; furthermore, in order to minimize the impact on the chip area while maintaining good physical connectivity, the outward extension dimension is preferably 0.1 to 3 μm.

[0081] Through the above methods, the present invention optimizes the alignment process. When the second alignment mark 211 of the second mask 20 cannot be aligned with the first alignment mark 11, the alignment is omitted and photolithography is performed directly after blind shifting. This eliminates the need to set a large number of alignment marks to ensure alignment in each movement, and also eliminates the need to fabricate multiple first masks 10 with different alignment marks. While greatly simplifying the alignment process, the present invention can also utilize the alignment states encountered periodically during blind shifting to correct errors caused by blind shifting. On the other hand, the present invention further adjusts the graphic design method in the layout design stage. Based on the initial graphic 1211 obtained by conventional layout design, the outer periphery of the initial graphic 1211 is extended outward by a predetermined size to form an extended graphic 1212 surrounding the initial graphic 1211. This effectively avoids the impact of misalignment phenomena that may occur when blind shifting directly without omitting alignment on the connection state without affecting the final chip size. This ensures that the part of the initial graphic 1211 that is not aligned due to misalignment during blind shifting can still fall within the range of the extended graphic 1212, guaranteeing good physical connection after blind shifting.

[0082] In summary, this invention provides a three-dimensional chip and a method for fabricating the same. The method includes forming a first pattern on a first wafer using a first mask; the first mask includes a first alignment mark; aligning a second alignment mark on a second mask with the first alignment mark, and forming a second pattern on the second wafer using the second mask; the second mask has a different size from the first mask; moving the second mask a predetermined distance along a predetermined direction, and forming the second pattern again on the second wafer using the second mask; wherein the predetermined distance satisfies the requirement that the second alignment mark aligns with the first alignment mark again. Through this method, the present invention can achieve alignment of masks of different sizes using simple alignment marks without affecting the layout and wiring, reducing the limitations on mask size during three-dimensional chip manufacturing and facilitating compatibility with chips of different sizes.

[0083] The above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit it. Although the present invention has been described in detail with reference to preferred embodiments, those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions of the present invention without departing from the spirit and scope of the technical solutions of the present invention.

Claims

1. A method for fabricating a three-dimensional chip, characterized in that, include: A first pattern is formed on a first wafer using a first photomask; The first mask includes a first alignment mark; Align the second alignment mark on the second mask with the first alignment mark, and use the second mask to form a second pattern on the second wafer; the second mask has a different size than the first mask; The second mask is moved a predetermined distance along a predetermined direction, and a second pattern is formed on the second wafer again using the second mask; wherein, the predetermined distance is such that the second alignment mark is aligned with the first alignment mark again; moving the second mask a predetermined distance along the predetermined direction includes: The second mask is moved n1 times along the first direction, and the cumulative movement is a first predetermined distance, so that the second alignment mark is aligned with the first alignment mark again. The distance moved each time is a+m, the first predetermined distance is n1(a+m), n1 is a positive integer greater than 1, a is the width of the second pattern, and m is the width of the longitudinal cutting channel. When the number of movements along the first direction is less than n1, the alignment operation is omitted, and the second pattern is formed directly by photolithography. When the number of movements along the first direction is equal to n1, the second alignment mark can be aligned with the first alignment mark. Alignment is performed first, and then the second pattern is formed by photolithography. The second mask is moved n2 times along the second direction, and the cumulative movement is a second predetermined distance, so that the second alignment mark is aligned with the first alignment mark again. The distance moved each time is b+l, the second predetermined distance is n2(b+l), n2 is a positive integer greater than 1, b is the length of the second pattern, and l is the width of the transverse cutting channel. When the number of movements along the second direction is less than n2, the alignment operation is omitted, and the second pattern is formed directly by photolithography. When the number of movements along the second direction is equal to n2, the second alignment mark can be aligned with the first alignment mark. Alignment is performed first, and then the second pattern is formed by photolithography.

2. The preparation method according to claim 1, characterized in that, The preparation method further includes: The first wafer and the second wafer are three-dimensionally bonded, and the first wafer and the second wafer are cut along the longitudinal dicing and the transverse dicing.

3. The preparation method according to claim 1, characterized in that, The size of the first mask is smaller than the size of the second mask.

4. The preparation method according to claim 1, characterized in that: The step of forming a first pattern on a first wafer using the first mask includes: The first mask is moved a fourth distance along the first direction; the fourth distance is the sum of the width of the first pattern and the width of the longitudinal cut; and / or The first mask is moved a fifth distance along the second direction; the fifth distance is the sum of the length of the first pattern and the width of the transverse cut.

5. The preparation method according to claim 1, characterized in that: The first mask includes a plurality of first chip unit patterns arranged in an array along the first direction and / or the second direction. The longitudinal cutting channel is formed between adjacent first chip unit patterns arranged along the first direction, and the transverse cutting channel is formed between adjacent first chip unit patterns arranged along the second direction. The first alignment mark includes a first transverse alignment mark disposed in the transverse cutting channel and a first longitudinal alignment mark disposed in the longitudinal cutting channel.

6. The preparation method according to claim 1, characterized in that: The first pattern includes a first chip unit, and the second pattern includes a second chip unit; a first sub-pattern in the first chip unit and a second sub-pattern in the second chip unit are physically connected; the first sub-pattern includes an initial pattern that matches the second sub-pattern and an extended pattern formed by extending the outer edge of the initial pattern by a predetermined size.

7. The preparation method according to claim 6, characterized in that: The predetermined size is 0.1~3μm.

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