FPGA-based CAN to SERDES converter

Abstract

This invention discloses a CAN to SERDES converter implemented based on FPGA, belonging to the field of radar beam control technology. The invention includes a SERDES control module, a data management module, and a CAN control module. The SERDES control module receives high-speed serial data of the SERDES protocol, performs serial-to-parallel conversion, encoding, or decoding, and interacts with the data management module; it also outputs the converted high-speed serial data of the SERDES protocol. The data management module controls the data buffering and scheduling between the SERDES control module and the CAN control module; the CAN control module converts data into CAN protocol serial data and outputs it; and it receives CAN protocol serial data, converts it into parallel data, and sends it to the data management module. This invention can simultaneously convert and output data from both the SERDES bus and CAN bus, filling the technological gap in CAN to high-speed serial interface conversion.

Description

Technical Field

[0001] This invention belongs to the field of radar beam control technology, specifically relating to a CAN to SERDES converter based on FPGA implementation. Background Technology

[0002] Currently, there are only conversion devices for low-speed buses such as CAN bus to UART bus and CAN bus to SPI bus, but no conversion devices for CAN to SERDES or other high-speed serial buses.

[0003] For example, Chinese patent application No. 201110130591.0 discloses a protocol converter between a multi-channel UART bus and a CAN bus, enabling data transmission between the CAN bus and the UART bus. Another example is Chinese patent application No. 201510647609.2, which discloses an SPI bus to CAN bus protocol conversion circuit and method, achieving transparent protocol conversion between SPI data and CAN bus data, as well as a logic control method for initializing and managing the SPI and CAN modules. While these inventions achieve protocol conversion between CAN and low-speed interfaces such as UART and SPI, they cannot be applied to scenarios requiring conversion between CAN and high-speed interfaces.

[0004] Because the SERDES bus has a high transmission rate, reaching Gbit / s, it is used in high-speed data transmission scenarios. In contrast, the CAN bus has a low transmission rate, and due to interface differences, devices using the CAN bus interface cannot connect to high-speed bus systems. Current technology can only convert the CAN bus to equally low-speed interfaces such as UART, SPI, and I2C; existing conversion devices are incapable of connecting to high-speed bus systems. Therefore, there is an urgent need to fill the technological gap in converting CAN to high-speed serial interfaces such as SERDES. Summary of the Invention

[0005] The purpose of this invention is to provide a CAN to SERDES converter based on FPGA, which can realize the conversion between CAN and high-speed interfaces. The internal CAN control module and SERDES control module are both implemented through logic. The number of CAN interfaces or SERDES interfaces can be increased by instantiating multiple CAN control modules and SERDES control modules inside the FPGA as needed, making it suitable for different application scenarios.

[0006] Specifically, the present invention provides a CAN to SERDES converter based on FPGA to realize protocol conversion between CAN bus and SERDES bus, characterized in that it includes a SERDES control module, a data management module and a CAN control module;

[0007] The SERDES control module includes a SERDES bus interface, a PMA controller, a PCS controller, and a user bus interface. The SERDES bus interface has receive ports RXP and RXN, and transmit ports TXP and TXN. The receive ports RXP and RXN receive high-speed serial data of the SERDES protocol to be converted into CAN protocol serial data, and the transmit ports TXP and TXN output the converted high-speed serial data of the SERDES protocol. The PMA controller is connected to the SERDES bus interface and performs serial-to-parallel conversion on the data to be converted. The PCS controller is connected to the PMA controller and encodes or decodes the data to be converted. The user bus interface connects the PCS controller and the data management module, and interacts with the data management module for data exchange.

[0008] The data management module is connected between the SERDES control module and the CAN control module. It controls the data signal transmission between the SERDES control module and the CAN control module according to external control commands, and performs buffering and scheduling of the sent or received parallel data.

[0009] The CAN control module includes a user bus interface, a transmit FIFO, a receive FIFO, a bit stream timing controller, and a CAN bus interface. The user bus interface interacts with the data management module. The CAN bus interface has a serial transmit port TX and a serial receive port RX. The transmit FIFO buffers the parallel data to be transmitted on the user bus interface. The bit stream timing controller converts the parallel data read from the transmit FIFO into CAN protocol serial data and outputs it to the serial transmit port TX of the CAN bus interface. The serial transmit port TX transmits CAN protocol serial data after converting it to SERDES protocol high-speed serial data. The serial receive port RX receives CAN protocol serial data to be converted into SERDES protocol high-speed serial data and transmits it to the bit stream timing controller. The bit stream timing controller converts the CAN protocol serial data into parallel data according to the CAN protocol and outputs it to the receive FIFO. The receive FIFO buffers the parallel data output by the bit stream timing controller and is connected to the user bus interface.

[0010] Furthermore, the data management module includes a data scheduling module on the SERDES control module side, a data scheduling module on the CAN control module side, and a transmission control module;

[0011] The data scheduling module on the SERDES control module side schedules the transmission and reception of data on the user bus interface of the SERDES control module; the data scheduling module on the CAN control module side schedules the transmission and reception of data on the user bus interface of the CAN control module; the transmission control module receives external control commands, determines the data transmission direction according to the external control commands, and performs data transmission between the data scheduling module on the SERDES control module side and the data scheduling module on the CAN control module side.

[0012] Furthermore, when the transmission control module determines the data transmission direction to be from SERDES to CAN according to the external control command, the data scheduling module on the SERDES control module side receives the data sent by the SERDES control module on the user bus interface and transmits the data to the data scheduling module on the CAN control module side. The data scheduling module on the CAN control module side sends the data to the CAN control module, and finally the CAN control module completes the conversion of SERDES interface data to CAN interface data and outputs it.

[0013] When the transmission control module determines the data transmission direction to switch from CAN to SERDES based on external control commands, the data scheduling module on the CAN control module side receives the data sent by the CAN control module on the user bus interface and transmits the data to the data scheduling module on the SERDES control module side. The data scheduling module on the SERDES control module side then sends the data to the SERDES control module, which finally completes the conversion from CAN interface data to SERDES interface data and outputs it.

[0014] Furthermore, when CAN protocol serial data is input to the receiving port RX of the CAN bus interface in the CAN control module, the bit stream timing controller of the CAN control module converts the CAN protocol serial data into parallel data, writes it into the receiving FIFO, and sends a data read request to the data management module.

[0015] After receiving the data read request, the data management module reads the data in the receive FIFO through the user bus interface of the CAN control module, sends it to the user bus interface of the SERDES control module, and sends a data read request to the SERDES control module.

[0016] After receiving a data read request, the SERDES control module reads the parallel data from the user bus interface of the SERDES control module. After encoding processing by the PCS controller and parallel-to-serial conversion processing by the PMA controller, it is converted into high-speed serial data of the SERDES protocol and output through the TXP and TXN ports of the SERDES bus interface.

[0017] Furthermore, when SERDES protocol serial data is input to the receiving ports RXP and RXN of the SERDES bus interface in the SERDES control module, the PMA controller of the SERDES control module performs serial-to-parallel conversion on the SERDES protocol serial data, the PCS controller encodes the parallel data to be sent or decodes the received parallel data, writes it to the user bus interface of the SERDES control module, and sends a data read request to the data management module.

[0018] After receiving the data read request, the data management module reads the parallel data through the user bus interface of the SERDES control module, sends it to the user bus interface of the CAN control module, and sends a data read request to the CAN control module.

[0019] After receiving the data read request, the CAN control module reads the parallel data from the user bus interface of the CAN control module and writes it into the transmit FIFO. When the bit stream timing controller determines that the empty signal of the transmit FIFO is invalid, it enables the reading of the parallel data in the transmit FIFO, converts the parallel data into serial data of the CAN protocol, and outputs it through the TX port of the CAN bus interface.

[0020] Furthermore, the CAN control module, SERDES control module, and data management module are implemented within the FPGA using RTL, IP cores, or schematic diagrams.

[0021] Furthermore, at least two CAN control modules and at least two SERDES control modules are instantiated inside the FPGA.

[0022] Furthermore, the TXP, TXN, RXP, and RXN of the SERDES bus interface in each SERDES control module are all independent and connected to different external SERDES devices; the user bus interface of each SERDES control module is connected to the independent signal interface of the scheduling module on the SERDES control module side of the data management module.

[0023] Each CAN control module's CAN bus interface has independent TX and RX, and is connected to different external CAN devices; each CAN control module's user bus interface is connected to the independent signal interface of the scheduling module on the CAN control module side within the data management module.

[0024] The transmission control module within the data management module receives external control commands to control the scheduling module on the SERDES control module side to receive data from each SERDES control module and to send data to be sent to each SERDES control module; the transmission control module within the data management module receives external control commands to control the scheduling module on the CAN control module side to receive data from each CAN control module and to send data to be sent to each CAN control module.

[0025] The beneficial effects of the FPGA-based CAN to SERDES converter of the present invention are as follows:

[0026] The FPGA-based CAN to SERDES converter of this invention can simultaneously convert data received from the SERDES bus to CAN bus output and data received from the CAN bus to SERDES bus output, filling the technological gap in CAN to high-speed serial interface conversion. This allows devices that traditionally use CAN bus interfaces to be connected to systems with high-speed bus interfaces. Specifically, it has the following advantages:

[0027] 1. The core chip of the converter is implemented using FPGA, which has high real-time data processing performance, reaching the nanosecond level.

[0028] 2. Integrate the CAN controller's functions into the FPGA and implement these functions through logic, reducing hardware components and lowering the converter's cost.

[0029] 3. The number of CAN controllers can be increased or decreased as needed, providing scalability.

[0030] 4. The converter can convert between CAN interface and high-speed interface protocols, such as SERDES. Attached Figure Description

[0031] Figure 1 This is a principle block diagram of an embodiment of the present invention.

[0032] Figure 2 This is a schematic diagram of another embodiment of the present invention. Detailed Implementation

[0033] The present invention will now be described in further detail with reference to the embodiments and the accompanying drawings.

[0034] One embodiment of the present invention is a CAN to SERDES converter implemented based on FPGA, used to realize protocol conversion between CAN bus and SERDES bus. Figure 1 As shown, the CAN to SERDES converter based on FPGA of the present invention includes a SERDES control module, a data management module and a CAN control module.

[0035] The SERDES control module includes a SERDES bus interface, a PMA controller, a PCS controller, and a user bus interface.

[0036] The SERDES bus interface has receive ports RXP and RXN, and transmit ports TXP and TXN. Receive ports RXP and RXN receive high-speed SERDES protocol serial data to be converted into CAN protocol serial data, while transmit ports TXP and TXN output the converted high-speed SERDES protocol serial data.

[0037] The PMA controller is connected to the SERDES bus interface to perform serial-to-parallel conversion on the data to be converted.

[0038] The PCS controller is connected to the PMA controller to encode or decode the data to be converted.

[0039] The user bus interface connects the PCS controller and the data management module, and interacts with the data management module for data exchange.

[0040] The data management module is connected between the SERDES control module and the CAN control module. It controls the data signal transmission between the SERDES control module and the CAN control module according to the received external control commands, and buffers and schedules the sent or received data.

[0041] The CAN control module includes a user bus interface, a transmit FIFO (First In First Out) memory, a receive FIFO, a bit stream timing controller, and a CAN bus interface.

[0042] The user bus interface interacts with the data management module.

[0043] The bitstream timing controller performs serial-to-parallel and parallel-to-serial conversion on the data according to the CAN protocol.

[0044] The transmit FIFO is connected to the CAN bus interface and serves as a buffer for parallel data to be transmitted, received from the user bus interface.

[0045] The receiving FIFO is connected to the CAN bus interface and serves as a buffer for parallel data converted from serial data of the CAN protocol received from the bit stream timing controller.

[0046] The CAN bus interface has a serial transmit port TX and a serial receive port RX. The serial transmit port TX transmits converted CAN protocol serial data, and the serial receive port RX receives CAN protocol serial data to be converted into high-speed SERDES protocol serial data.

[0047] The transmit FIFO buffers the parallel data to be transmitted on the user bus interface; the bit stream timing controller converts the parallel data read from the transmit FIFO into CAN protocol serial data and outputs it to the serial transmit port TX of the CAN bus interface; the serial transmit port TX transmits the CAN protocol serial data after converting the SERDES protocol high-speed serial data.

[0048] The serial receiving port RX receives CAN protocol serial data to be converted into high-speed serial data of the SERDES protocol and transmits it to the bit stream timing controller; the bit stream timing controller converts the CAN protocol serial data into parallel data according to the CAN protocol and outputs it to the receiving FIFO; the receiving FIFO buffers the parallel data output by the bit stream timing controller and connects it to the user bus interface.

[0049] The CAN control module, SERDES control module, and data management module are all implemented within the FPGA using RTL, IP cores (Intellectual Property Cores), schematics, and other methods.

[0050] like Figure 1 As shown, the CAN control module includes a CAN bus interface, a receive FIFO, a transmit FIFO, a bit stream timing controller, and a user bus interface. After power-on, the CAN control module completes the configuration of its internal initialization parameters, including bus speed, operating mode, and CAN port number.

[0051] The SERDES control module includes a SERDES bus interface, a PMA controller, a PCS controller, and a user bus interface. Upon power-up, the SERDES control module configures its internal initialization parameters, including bus speed, clock frequency, and transmission protocol.

[0052] The data management module includes a data scheduling module on the SERDES control module side, a data scheduling module on the CAN control module side, and a transmission control module. The data scheduling module on the SERDES control module side schedules the transmission and reception of data on the user bus interface of the SERDES control module; the data scheduling module on the CAN control module side schedules the transmission and reception of data on the user bus interface of the CAN control module; the transmission control module receives external control commands, determines the data transmission direction based on the external control commands, and performs data transmission between the data scheduling modules on the SERDES control module side and the CAN control module side.

[0053] When the transmission control module determines the data transmission direction to be switched from SERDES to CAN based on external control commands, the data scheduling module on the SERDES control module side receives the data sent by the SERDES control module on the user bus interface and transmits the data to the data scheduling module on the CAN control module side. The data scheduling module on the CAN control module side then sends the data to the CAN control module, and finally the CAN control module completes the conversion of SERDES interface data to CAN interface data and outputs it.

[0054] When the transmission control module determines the data transmission direction to switch from CAN to SERDES based on external control commands, the data scheduling module on the CAN control module side receives the data sent by the CAN control module on the user bus interface and transmits the data to the data scheduling module on the SERDES control module side. The data scheduling module on the SERDES control module side then sends the data to the SERDES control module, which finally completes the conversion from CAN interface data to SERDES interface data and outputs it.

[0055] like Figure 1 As shown, when CAN protocol serial data is input to the receiving port RX of the CAN bus interface in the CAN control module, the bit stream timing controller of the CAN control module converts the CAN protocol serial data into parallel data, writes it into the receiving FIFO, and sends a data read request to the data management module.

[0056] After receiving the data read request, the data management module reads the data in the receive FIFO through the user bus interface of the CAN control module, sends it to the user bus interface of the SERDES control module, and sends a data read request to the SERDES control module.

[0057] After receiving a data read request, the SERDES control module reads the parallel data from the user bus interface of the SERDES control module. After encoding processing by the PCS controller and parallel-to-serial conversion processing by the PMA controller, it is converted into high-speed serial data of the SERDES protocol and output through the TXP and TXN ports of the SERDES bus interface.

[0058] When SERDES protocol serial data is input to the receive ports RXP and RXN of the SERDES bus interface in the SERDES control module, the PMA controller of the SERDES control module performs serial-to-parallel conversion on the SERDES protocol serial data, the PCS controller encodes the parallel data to be sent or decodes the received parallel data, writes it to the user bus interface of the SERDES control module, and sends a data read request to the data management module.

[0059] After receiving the data read request, the data management module reads the parallel data through the user bus interface of the SERDES control module, sends it to the user bus interface of the CAN control module, and sends a data read request to the CAN control module.

[0060] After receiving the data read request, the CAN control module reads the parallel data from the user bus interface of the CAN control module and writes it into the transmit FIFO. When the bit stream timing controller determines that the empty signal of the transmit FIFO is invalid, it enables the reading of the parallel data in the transmit FIFO, converts the parallel data into serial data of the CAN protocol, and outputs it through the TX port of the CAN bus interface.

[0061] Preferably, in another embodiment, the present invention can increase the number of CAN interfaces or SERDES interfaces by instantiating at least two CAN control modules and at least two SERDES control modules inside the FPGA, thereby realizing the conversion between SERDES data and CAN data under different interface requirements.

[0062] Each SERDES control module has its own independent SERDES bus interface TXP, TXN, RXP, and RXN, which are connected to different external SERDES devices. The user bus interface of each SERDES control module is connected to the independent signal interface of the scheduling module on the SERDES control module side of the data management module.

[0063] Each CAN control module's CAN bus interface has independent TX and RX, and is connected to different external CAN devices; each CAN control module's user bus interface is connected to the independent signal interface of the scheduling module on the CAN control module side within the data management module.

[0064] The transmission control module within the data management module receives external control commands to control the scheduling module on the SERDES control module side to receive data from each SERDES control module and to send data to be sent to each SERDES control module; the transmission control module within the data management module receives external control commands to control the scheduling module on the CAN control module side to receive data from each CAN control module and to send data to be sent to each CAN control module.

[0065] like Figure 2As shown, this embodiment instantiates two SERDES control modules. The TXP, TXN, RXP, and RXN pins of the SERDES bus interface in each SERDES control module are independent and can be connected to two different external SERDES devices simultaneously. The RDATA and TDATA pins on the user bus interfaces of both SERDES control modules are connected to the independent signal interfaces of the scheduling module on the SERDES control module side within the data management module.

[0066] The transmission control module within the data management module receives external control commands and controls the scheduling module on the SERDES control module side to receive RDATA from SERDES control module 1 or SERDES control module 2, and to send TDATA to SERDES control module 1 or SERDES control module 2.

[0067] This embodiment instantiates two CAN control modules. The TX and RX pins of each CAN control module's CAN bus interface are independent, allowing simultaneous connection to two different external CAN devices. The parallel data RDATA received and the parallel data TDATA transmitted on the user bus interfaces of both CAN control modules are connected to the independent signal interfaces of the scheduling module on the CAN control module side within the data management module.

[0068] The transmission control module within the data management module receives external control commands and controls the scheduling module on the CAN control module side to receive RDATA from CAN control module 1 or CAN control module 2, and to send TDATA to CAN control module 1 or CAN control module 2.

[0069] CAN control module 1 or CAN control module 2 sends the CAN protocol serial data received from the RX interface to SERDES control module 1 or SERDES control module 2, and then sends it out through the TXP and TXN interfaces. The process is the same as the corresponding process of instantiating a SERDES control module and a CAN control module.

[0070] SERDES control module 1 or SERDES control module 2 sends the SERDES protocol serial data received from the RXP and RXN interfaces to CAN control module 1 or CAN control module 2, and then sends it out via the TX interface. The process is the same as the corresponding process of instantiating a SERDES control module and a CAN control module.

[0071] The FPGA-based CAN to SERDES converter of this invention can simultaneously convert data received from the SERDES bus to CAN bus output and data received from the CAN bus to SERDES bus output, filling the technological gap in CAN to high-speed serial interface conversion. This allows devices that traditionally use CAN bus interfaces to be connected to systems with high-speed bus interfaces. Specifically, it has the following advantages:

[0072] 1. The core chip of the converter is implemented using FPGA, which enables high real-time data processing, reaching the nanosecond level;

[0073] 2. Integrate the CAN controller's functions into the FPGA and implement these functions through logic, thereby reducing hardware components and lowering the converter's cost;

[0074] 3. The number of CAN controllers can be increased or decreased as needed, providing scalability;

[0075] 4. The converter can convert between CAN interface and high-speed interface protocols, such as SERDES.

[0076] While the present invention has been disclosed above with reference to preferred embodiments, these embodiments are not intended to limit the invention. Any equivalent changes or modifications made without departing from the spirit and scope of the invention are also within the scope of protection of the invention. Therefore, the scope of protection of the present invention should be determined by the claims of this application.

Claims

1. A CAN to SERDES converter based on FPGA, realizing protocol conversion between CAN bus and SERDES bus, characterized in that, Includes SERDES control module, data management module and CAN control module; The SERDES control module includes a SERDES bus interface, a PMA controller, a PCS controller, and a user bus interface. The SERDES bus interface has receive ports RXP and RXN, and transmit ports TXP and TXN. The receive ports RXP and RXN receive high-speed serial data of the SERDES protocol to be converted into CAN protocol serial data, and the transmit ports TXP and TXN output the converted high-speed serial data of the SERDES protocol. The PMA controller is connected to the SERDES bus interface and performs serial-to-parallel conversion on the data to be converted. The PCS controller is connected to the PMA controller and encodes or decodes the data to be converted. The user bus interface connects the PCS controller and the data management module, and interacts with the data management module for data exchange. The data management module is connected between the SERDES control module and the CAN control module. It controls the data signal transmission between the SERDES control module and the CAN control module according to external control commands, and performs buffering and scheduling of the sent or received parallel data. The CAN control module includes a user bus interface, a transmit FIFO, a receive FIFO, a bit stream timing controller, and a CAN bus interface. The user bus interface interacts with the data management module. The CAN bus interface has a serial transmit port TX and a serial receive port RX. The transmit FIFO buffers the parallel data to be transmitted on the user bus interface. The bit stream timing controller converts the parallel data read from the transmit FIFO into CAN protocol serial data and outputs it to the serial transmit port TX of the CAN bus interface. The serial transmit port TX transmits CAN protocol serial data after converting SERDES protocol high-speed serial data; the serial receive port RX receives CAN protocol serial data to be converted into SERDES protocol high-speed serial data and transmits it to the bit stream timing controller; the bit stream timing controller converts the CAN protocol serial data into parallel data according to the CAN protocol and outputs it to the receive FIFO. The system receives parallel data output from the FIFO buffer bit stream timing controller and connects it to the user bus interface.

2. The CAN to SERDES converter based on FPGA implementation according to claim 1, characterized in that, The data management module includes a data scheduling module on the SERDES control module side, a data scheduling module on the CAN control module side, and a transmission control module. The data scheduling module on the SERDES control module side schedules the transmission and reception of data on the user bus interface of the SERDES control module; the data scheduling module on the CAN control module side schedules the transmission and reception of data on the user bus interface of the CAN control module; the transmission control module receives external control commands, determines the data transmission direction according to the external control commands, and performs data transmission between the data scheduling module on the SERDES control module side and the data scheduling module on the CAN control module side.

3. The CAN to SERDES converter based on FPGA implementation according to claim 2, characterized in that, When the transmission control module determines the data transmission direction to be from SERDES to CAN according to the external control command, the data scheduling module on the SERDES control module side receives the data sent by the SERDES control module on the user bus interface and transmits the data to the data scheduling module on the CAN control module side. The data scheduling module on the CAN control module side sends the data to the CAN control module. Finally, the CAN control module completes the conversion of SERDES interface data to CAN interface data and outputs it. When the transmission control module determines the data transmission direction to switch from CAN to SERDES based on external control commands, the data scheduling module on the CAN control module side receives the data sent by the CAN control module on the user bus interface and transmits the data to the data scheduling module on the SERDES control module side. The data scheduling module on the SERDES control module side then sends the data to the SERDES control module, which finally completes the conversion from CAN interface data to SERDES interface data and outputs it.

4. The CAN to SERDES converter based on FPGA implementation according to claim 1, characterized in that, When CAN protocol serial data is input to the receiving port RX of the CAN bus interface in the CAN control module, the bit stream timing controller of the CAN control module converts the CAN protocol serial data into parallel data, writes it into the receiving FIFO, and sends a data read request to the data management module. After receiving the data read request, the data management module reads the data in the receive FIFO through the user bus interface of the CAN control module, sends it to the user bus interface of the SERDES control module, and sends a data read request to the SERDES control module. After receiving a data read request, the SERDES control module reads the parallel data from the user bus interface of the SERDES control module. After encoding processing by the PCS controller and parallel-to-serial conversion processing by the PMA controller, it is converted into high-speed serial data of the SERDES protocol and output through the TXP and TXN ports of the SERDES bus interface.

5. The CAN to SERDES converter based on FPGA implementation according to claim 1, characterized in that, When SERDES protocol serial data is input to the receive ports RXP and RXN of the SERDES bus interface in the SERDES control module, the PMA controller of the SERDES control module performs serial-to-parallel conversion on the SERDES protocol serial data, the PCS controller encodes the parallel data to be sent or decodes the received parallel data, writes it to the user bus interface of the SERDES control module, and sends a data read request to the data management module. After receiving the data read request, the data management module reads the parallel data through the user bus interface of the SERDES control module, sends it to the user bus interface of the CAN control module, and sends a data read request to the CAN control module. After receiving the data read request, the CAN control module reads the parallel data from the user bus interface of the CAN control module and writes it into the transmit FIFO. When the bit stream timing controller determines that the empty signal of the transmit FIFO is invalid, it enables the reading of the parallel data in the transmit FIFO, converts the parallel data into serial data of the CAN protocol, and outputs it through the TX port of the CAN bus interface.

6. The CAN to SERDES converter based on FPGA implementation according to any one of claims 1-5, characterized in that, The CAN control module, SERDES control module, and data management module are implemented within the FPGA using RTL, IP cores, or schematic diagrams.

7. The CAN to SERDES converter based on FPGA implementation according to claim 6, characterized in that, The FPGA instantiates at least two CAN control modules and at least two SERDES control modules.

8. The CAN to SERDES converter based on FPGA implementation according to claim 7, characterized in that, Each SERDES control module has its own independent SERDES bus interface TXP, TXN, RXP, and RXN, which are connected to different external SERDES devices. The user bus interface of each SERDES control module is connected to the independent signal interface of the scheduling module on the SERDES control module side of the data management module. Each CAN control module's CAN bus interface has independent TX and RX, and is connected to different external CAN devices; each CAN control module's user bus interface is connected to the independent signal interface of the scheduling module on the CAN control module side within the data management module. The transmission control module within the data management module receives external control commands to control the scheduling module on the SERDES control module side to receive data from each SERDES control module and to send data to be sent to each SERDES control module; the transmission control module within the data management module receives external control commands to control the scheduling module on the CAN control module side to receive data from each CAN control module and to send data to be sent to each CAN control module.

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