A method and apparatus for finite state machine extraction of a digital integrated circuit

Abstract

The application provides a finite state machine extraction method and device of a digital integrated circuit, and the method comprises the following steps: compiling a hardware description language of the digital integrated circuit to obtain a syntax tree; analyzing the syntax tree to extract a data flow graph of the digital integrated circuit; processing the data flow graph to obtain a state transition table corresponding to a current state; and processing the state transition table corresponding to the current state to obtain an output mapping table of the finite state machine. Compared with the prior art, the application has a wider application scenario of the finite state machine.

Description

Technical Field

[0001] This invention relates to the field of integrated circuits, and in particular to a method and apparatus for extracting finite state machines from digital integrated circuits. Background Technology

[0002] In digital integrated circuit design, behavioral-level descriptions are typically used to define the data flow, logical behavior, and register behavior of circuits. Digital integrated circuits are categorized into combinational logic circuits and sequential logic circuits based on whether they contain memory components. Sequential logic circuits can be mathematically modeled using finite state machines (FSMs). Extracting the finite state machine from the behavioral-level description is crucial for better describing the state transition characteristics of sequential logic circuits and achieving automated logic synthesis optimization. However, existing finite state machine extraction algorithms can only model specific behavioral-level description methods, lacking universality and failing to extract complex behavioral-level or gate-level descriptions. This significantly limits the optimization effect of sequential logic circuit structures in subsequent logic synthesis processes. Summary of the Invention

[0003] The purpose of this invention is to provide a method and apparatus for extracting finite state machines for digital integrated circuits, which solves the problem that traditional finite state machine extraction algorithms have limited application scenarios.

[0004] To achieve the above and other related objectives, the present invention provides a method for extracting a finite state machine of a digital integrated circuit, comprising at least:

[0005] The hardware description language of digital integrated circuits is compiled to obtain a syntax tree;

[0006] The syntax tree is analyzed to extract the data flow graph of the digital integrated circuit;

[0007] The data flow graph is processed to obtain a state transition table corresponding to the current state;

[0008] The output mapping table of the finite state machine is obtained by processing the state transition table corresponding to the current state.

[0009] Optionally, a syntax tree can be obtained by compiling the hardware description language of the behavior or structure of the digital integrated circuit.

[0010] Optionally, a syntax tree is obtained by sequentially performing lexical analysis, syntax analysis, and semantic analysis on the hardware description language of digital integrated circuits.

[0011] Optionally, processing the data flow graph to obtain a state transition table corresponding to the current state includes:

[0012] Loop processing is performed on the data flow graph to obtain all signal loops and their signal transfer and output expressions;

[0013] The signals in each signal loop are processed to establish a state check queue with an initial state;

[0014] The state variables in the state check queue are checked until all state variable values ​​have been checked and the state transition table corresponding to the current state is obtained.

[0015] Optionally, the Johnson algorithm can be used to perform loop processing on the data flow graph to obtain all signal loops.

[0016] Optionally, the process of processing the signals in each signal loop to establish a state check queue with an initial state includes:

[0017] The signals in each signal loop are distinguished by signal type to obtain blocking assignment signals and non-blocking assignment signals;

[0018] The non-blocking assignment signal is defined as a loop state variable;

[0019] Set all loop state variables to zero as the initial state;

[0020] Establish a state check queue and add the initial state to the state check queue.

[0021] Optionally, a mapping table between the current state and the input / output is calculated based on the current state value in the state transition table corresponding to the current state and the output expression; and the current state and the output result are used as the output mapping table of the finite state machine.

[0022] Optionally, the method further includes recoding all current states in the output mapping table of the finite state machine to compress the state space.

[0023] To achieve the above and other related objectives, the present invention also provides a finite state machine extraction apparatus for digital integrated circuits, including a memory, a processor, and a program stored in the memory and executable on the processor. When the processor executes the program, it implements the steps of the finite state machine extraction method for digital integrated circuits described above.

[0024] As described above, the finite state machine extraction method and apparatus for digital integrated circuits of the present invention have the following beneficial effects:

[0025] This invention proposes a method and apparatus for extracting finite state machines (FSMs) from digital integrated circuits. For digital sequential circuits containing counters or mathematical operations, existing technologies cannot extract the state transitions described by the circuit. However, the proposed technique can model the entire state space composed of state variables, obtain numerical state transition results using logical operations, and transform counting and mathematical operations into state transition behaviors, thereby obtaining the finite state machine of the circuit. Therefore, this invention can extract finite state machines from more general digital integrated circuit hardware description languages ​​and perform state space optimization on the extracted finite state machines, without requiring specific three-stage or two-stage finite state machine description methods, thus enhancing the application scenarios of finite state machines. Attached Figure Description

[0026] Figure 1 The diagram shows a flowchart of the finite state machine extraction method for digital integrated circuits according to the present invention.

[0027] Figure 2 The diagram shown illustrates the compilation of a hardware description language into a syntax tree in a specific embodiment of the present invention.

[0028] Figure 3 The diagram shown illustrates the input-output relationship of a variable extracted by syntax tree analysis in a specific embodiment of the present invention.

[0029] Figure 4 The diagram shown is a schematic representation of the data flow graph of all variables obtained from syntax tree analysis in a specific embodiment of the present invention.

[0030] Figure 5 The diagram shown illustrates the division of a simple loop in the data stream in a specific embodiment of the present invention.

[0031] Figure 6 The diagram shown illustrates the extraction and merging of simple loops in a data stream in a specific embodiment of the present invention.

[0032] Figure 7 The diagram shown is a schematic diagram of the status check queue initialization in a specific embodiment of the present invention.

[0033] Figure 8 This is a schematic diagram illustrating the process of popping the initial state from the state check queue in a specific embodiment of the present invention.

[0034] Figure 9 The diagram shows the update method of the state variables corresponding to the loop state machine transition characteristic model in a specific embodiment of the present invention.

[0035] Figure 10 The diagram shown is a schematic representation of the input signal and the next state mapping table in a specific embodiment of the present invention.

[0036] Figure 11 The diagram shows a schematic representation of the mapping table between the input signal and the next state in a specific embodiment of the present invention.

[0037] Figure 12 The diagram shows the relationship between the optimized input expression and the next state in a specific embodiment of the present invention.

[0038] Figure 13 This is a schematic representation of the current state and input / output mapping in a specific embodiment of the present invention.

[0039] Figure 14 This diagram illustrates the recoding process of the state transition table corresponding to the current state in a specific embodiment of the present invention. Detailed Implementation

[0040] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0041] Please see Figures 1-14 It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0042] Method Implementation Examples:

[0043] This invention proposes a method for extracting finite state machines from digital integrated circuits, such as... Figure 1 This is a flowchart illustrating the finite state machine extraction method for digital integrated circuits according to the present invention. (Now, in conjunction with...) Figure 1 The technical solution of the finite state machine extraction method for digital integrated circuits of the present invention is described in detail. The finite state machine extraction method for digital integrated circuits includes at least the following:

[0044] S1, compiles the hardware description language of digital integrated circuits to obtain a syntax tree;

[0045] In a specific embodiment of the present invention, the hardware description language of the behavior or structure of the digital integrated circuit is compiled. The hardware description language is VHDL or Verilog. In this invention, Verilog hardware description language is used as an example demonstration. However, it should be noted that the subsequent steps are not limited by the type of hardware description language used.

[0046] The compilation process uses three steps—lexical analysis, syntax analysis, and semantic analysis—to obtain the syntax tree structure of the circuit description, such as... Figure 2 As shown. Specifically, during compilation, the hardware description language of digital integrated circuits undergoes lexical analysis, syntax analysis, and semantic analysis in sequence to obtain a syntax tree.

[0047] S2, Analyze the syntax tree to extract the data flow graph of the digital integrated circuit;

[0048] In a specific embodiment of the present invention, for Figure 2 The syntax tree obtained from the compiler is used for data flow analysis, and the input-output relationships and expressions of each variable are extracted and recorded in a table. After all variables have been processed, the data flow structure is naturally formed based on the input-output relationships of all variables; for example... Figure 3 The diagram shown is a schematic diagram of the input-output relationship of a variable obtained by analyzing and extracting a syntax tree in a specific embodiment of this invention, that is, a schematic diagram of extracting input and output signals from the syntax tree and converting them into data stream nodes; Figure 4 This is a schematic diagram of the data flow graph formed by analyzing the syntax tree to obtain the input-output relationship of all variables in a specific embodiment of the present invention, that is, the data flow graph obtained by converting the syntax tree of the overall digital integrated circuit.

[0049] S3, process the data flow graph to obtain a state transition table corresponding to the current state;

[0050] In a specific embodiment of the present invention, processing the data flow graph to obtain a state transition table corresponding to the current state includes:

[0051] S31, perform loop processing on the data flow graph to obtain all signal loops and their signal transfer expressions and output expressions;

[0052] It should be noted that in a data flow graph, a state transition can only be formed when variables form a loop, which is a finite state machine.

[0053] This invention employs the Johnson algorithm to perform loop processing on the data flow graph, specifically including:

[0054] (1) Extract all simple cycles from the data flow graph;

[0055] (2) Merge the simple rings that have intersection to obtain the loop structure.

[0056] In specific embodiments of the present invention, such as Figure 5 As shown, the detection and analysis process identifies all simple cycles (such as simple cycle 1 and simple cycle 2) in the data stream. Figure 5Simple cycles 1 and 2 share two common variables, namely, the intersection of two nodes. Therefore, by extracting all simple cycles from the graph, we can obtain the following: Figure 6 The simple rings 1 and 2 shown to the left of the middle arrow are then merged, resulting in a ring structure as follows: Figure 6 As shown to the right of the middle arrow.

[0057] S32, Process the signals in each signal loop to establish a state check queue with an initial state;

[0058] In a specific embodiment of the present invention, the process of processing the signals in each signal loop to establish a state check queue with an initial state includes:

[0059] The signals in each signal loop are distinguished by signal type to obtain blocking assignment signals and non-blocking assignment signals;

[0060] The non-blocking assignment signal is defined as a loop state variable;

[0061] Set all loop state variables to zero as the initial state;

[0062] Establish a state check queue and add the initial state to the state check queue.

[0063] Based on the signal type in the loop structure, signals are divided into blocking assignment signals and non-blocking assignment signals. The assignment of blocking assignment signals must be performed after the assignment of the previous level input signal variable is completed. Non-blocking assignment signals are assigned the value of the previous level input signal at the beginning of the current cycle. Since blocking assignment has combinational logic properties and non-blocking assignment has sequential logic properties, all non-blocking assignment variables are used as loop state variables to store the current state of the state machine. For actual physical circuits, since no values ​​are stored when the circuit is not powered on (i.e., the circuit is in an initial state of all zeros), all zeros also need to be used as the initial state for modeling when extracting the finite state machine. In other words, each non-blocking assignment variable in the signal loop is a state variable in the loop. After extracting and initializing the state variables, they are added to the state check queue as the starting point for subsequent loops. In a specific embodiment of this invention, a signal loop is as follows: Figure 7 As shown, the input signals are ln1 and ln2. Nodes A, B, and E in the loop structure are non-blocking assignment signals, that is, the combination of non-blocking assignment variables is [A,B,E]; C, D, and F in the loop structure are blocking assignment signals, that is, the blocking assignment variables are [C,D,F]; after setting all the states of the non-blocking variables to zero, the initial state [A,B,E] = [0,0,0], and the initial state is added to the state check queue.

[0064] S33, check the state variables in the state check queue until all state variable values ​​have been checked and the state transition table corresponding to the current state is obtained.

[0065] In a specific embodiment of the present invention, it specifically includes:

[0066] S331, take the initial state in the state check queue as the current state variable, and calculate the next state variable based on the current state variable, the input excitation of the signal loop and the corresponding signal transfer expression;

[0067] In a specific embodiment of the present invention, the process of calculating the next state variable based on the current state variable, the input excitation of the signal loop, and the corresponding signal transition expression includes:

[0068] (1) Establish a loop state machine transition characteristic model based on the signal transition expression corresponding to the signal loop;

[0069] (2) Use binary encoding to generate the input excitation of the signal loop;

[0070] (3) Calculate the values ​​of all blocking assignment signals based on the current state variables, the input excitation of the signal loop, and the loop state machine transition characteristic model;

[0071] (4) Calculate the value of the next state variable based on the value of the blocking assignment signal and the input excitation of the signal loop;

[0072] The state check loop begins, popping the first initial state from the state check queue as the current state variable. Figure 8 As shown, the current value of the state variable is used as the current value of the non-blocking assignment node; all input signals in the signal loop are acquired, and the input signal combinations are binary encoded to obtain the input stimulus; starting from the non-blocking assignment node, based on the binary encoding of all input signals, the blocking assignment nodes are processed level by level to obtain the values ​​of all blocking assignment nodes. Finally, based on the blocking assignment nodes, the input stimulus encoded by the input signals, the current state variable value, and the loop state machine transition characteristic model, the value of the next state variable is calculated and recorded as follows: Figure 10 The input signal to next state mapping table is shown. It should be noted that the calculation method differs depending on the loop state machine transition characteristic model. Figure 9 This is a schematic diagram illustrating the update method of the state variables corresponding to the loop state machine transition characteristic model according to a specific embodiment of the present invention.

[0073] S332, mark the mapping table between the input signal and the next state to perform logical minimization optimization to obtain the relationship between the input expression and the next state;

[0074] In this invention, the relationship between the input expression and the next state is the state transition table.

[0075] First, based on the mapping table between the input signal and the next state, mark the next state, such as... Figure 11 As shown. When In1 and In2 are [0,0] and [1,0] respectively, the state values ​​of A, B, and E are the same. Therefore, when marking the next state, the marking method is the same, which is S2.

[0076] Then, perform logical minimization optimization on each next state marker, such as... Figure 12 As shown, a binary decision tree optimization method is used to obtain the relationship between the input expression and the next state.

[0077] S333, add the optimized input expression and the relationship between the next state and the unchecked next state to the state check queue;

[0078] This invention records the optimized input expression and the next state relationship in a state transition table, completing the state transition extraction operation for the current state variable. Simultaneously, it adds all unprocessed next states to a state check queue, for example... Figure 9 If the next state S1 and the current state have the same value, then the state is not added to the state check queue. However, if the next state S2 has not been checked, then the state check queue is added to the state check queue.

[0079] S334, repeat steps S331-S333 until all state variable values ​​have been checked and the state transition table corresponding to the current state has been obtained; that is, pop the first element from the state check queue as the current state variable, complete the state extraction, logic minimization, and add the next state to the check queue, etc., until all next states have been checked and the state check queue is empty, then exit the loop.

[0080] S4, process the state transition table corresponding to the current state to obtain the output mapping table of finite states.

[0081] In a specific embodiment of the present invention, a mapping table between the current state and the input / output is calculated based on the current state value in the state transition table corresponding to the current state and the output expression; and the current state and the output result are used as the output mapping table of the finite state machine.

[0082] In a specific embodiment of the present invention, the above-described calculation method is used to calculate the output value using the current state value, the input value, and the output expression. The same logical minimization method as described above is used to optimize the mapping between the current state and the input / output, such as... Figure 13 As shown. The calculated results are then stored as the output mapping table of the finite state machine.

[0083] S5, recode all current states in the output mapping table of the finite state machine to compress the state space.

[0084] In a specific embodiment of the present invention, the output mapping table of finite states is traversed to obtain all possible current state values, and all possible current state values ​​obtained by the traversal are recoded, such as... Figure 14 As shown, for example, when defining state variables, the bit width of the state variable combination is 3, and the state space size is 2^3 = 8. However, after extraction, only 4 valid states remain. Therefore, all states need to be recoded to reduce the final state variable bit width to 2. It is important to note that the encoding process only affects the values ​​of the state variables and does not change the state transition relationships or output relationships. After recoding, other programs such as state flow analysis and logic synthesis optimization can use this finite state machine for circuit design analysis and optimization.

[0085] Device Example:

[0086] To achieve the above and other related objectives, the present invention provides a finite state machine extraction device for digital integrated circuits, comprising a memory, a processor, and a program stored in the memory and executable on the processor. When the processor executes the program, it implements the steps of the finite state machine extraction method for digital integrated circuits as claimed above.

[0087] The processor in this invention can be a general-purpose processor, including a central processing unit (CPU), a network processor (NP), etc., or it can be a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components. It can implement or execute the methods, steps, and logic block diagrams disclosed in the embodiments of this application. The general-purpose processor can be a microprocessor or any conventional processor.

[0088] The detailed process of the steps in the method for extracting the finite state machine of digital integrated circuits has been described in detail in the method embodiments, and will not be repeated here.

[0089] This invention has the following advantages and positive effects:

[0090] 1. This invention can extract finite state machines from more general digital integrated circuit hardware description languages ​​and perform state space optimization on the extracted finite state machines without requiring specific three-stage or two-stage finite state machine description methods.

[0091] 2. For digital sequential circuits containing counters or mathematical operations, existing technologies cannot extract the state transitions described by the circuit. However, the technology proposed in this invention can model the entire state space composed of state variables, obtain numerical state transition results using logical operations, and transform counting and mathematical operation behaviors into state transition behaviors, thereby obtaining the finite state machine of the circuit.

[0092] 3. For any variable defined in the hardware description language, the technology proposed in this invention can extract its state variable combination and optimize the encoding of the state variables, reduce the dimension of the state space, optimize the hidden state, and eliminate the need for the designer to estimate the state variable bit width in advance.

[0093] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A method for extracting the finite state machine of a digital integrated circuit, characterized in that, At least including: The hardware description language of digital integrated circuits is compiled to obtain a syntax tree; The syntax tree is analyzed to extract the data flow graph of the digital integrated circuit; The data flow graph is processed to obtain a state transition table corresponding to the current state; The output mapping table of the finite state machine is obtained by processing the state transition table corresponding to the current state. The process of processing the data flow graph to obtain the state transition table corresponding to the current state includes: Loop processing is performed on the data flow graph to obtain all signal loops and their signal transfer and output expressions; The signals in each signal loop are processed to establish a state check queue with an initial state; The state variables in the state check queue are checked until all state variable values ​​have been checked and the state transition table corresponding to the current state is obtained.

2. The finite state machine extraction method for digital integrated circuits according to claim 1, characterized in that, A syntax tree is obtained by compiling a hardware description language for the behavior or structure of a digital integrated circuit.

3. The finite state machine extraction method for digital integrated circuits according to claim 1, characterized in that, A syntax tree is obtained by sequentially performing lexical analysis, syntax analysis, and semantic analysis on the hardware description language of digital integrated circuits.

4. The finite state machine extraction method for digital integrated circuits according to claim 1, characterized in that, The Johnson algorithm is used to process the data flow graph to obtain all signal loops.

5. The finite state machine extraction method for digital integrated circuits according to claim 1, characterized in that, The process of processing the signals in each signal loop to establish a state check queue with an initial state includes: The signals in each signal loop are distinguished by signal type to obtain blocking assignment signals and non-blocking assignment signals; The non-blocking assignment signal is defined as a loop state variable; Set all loop state variables to zero as the initial state; Establish a state check queue and add the initial state to the state check queue.

6. The finite state machine extraction method for digital integrated circuits according to claim 1, wherein the current state and input-output mapping table are calculated based on the current state value in the state transition table corresponding to the current state and the output expression; and the current state and output result are used as the output mapping table of the finite state machine.

7. The finite state machine extraction method for digital integrated circuits according to claim 1, characterized in that, It also includes recoding all current states in the output mapping table of the finite state machine to compress the state space.

8. A finite state machine extraction device for digital integrated circuits, characterized in that, The method includes a memory, a processor, and a program stored in the memory and executable on the processor, wherein when the processor executes the program, it implements the steps of the finite state machine extraction method for digital integrated circuits according to any one of claims 1-7.

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