A method for generating a communication graph in a chip wiring

Abstract

The present application relates to the field of chip design, and particularly relates to a method for generating a connected graph in chip wiring, the present application uses a strategy network to perform prediction and generate a connected graph, and the process obtains edges to be added at each step by encoding and decoding input pin coordinates. A judgment network is used to predict the expected target function value of each group of pin coordinates, the judgment network performs graph representation on pin coordinates in the same encoding manner as the strategy network, and then linearly converts the graph representation into a prediction value. The prediction value is used as a label when training the strategy network, and the two networks are trained to minimize the target function, thereby optimizing the connected graph. This method effectively overcomes the performance limitations of heuristic methods, and through fine training, an optimized connected graph can be generated to improve the performance of bus length and time delay, and provides an effective solution for pin coordinate optimization.

Description

Technical Field

[0001] This invention relates to the field of chip design, and more specifically to a method for generating a connected graph in chip wiring. Background Technology

[0002] Connectivity graph design in chip routing plays a crucial role in chip design. It's a graphical representation used to describe how signals flow from sources into a given active pin network and connect all points with minimal cost. This "cost" can typically be many different design metrics, including but not limited to trace length, latency, and power consumption. In actual chip design, designers place various components on the chip panel and then connect the pins of these components using wires to form a complete circuit system. This process is called generating a connectivity graph, and the quality of this connectivity graph directly affects the performance and efficiency of the entire chip design. For example, a poorly designed connectivity graph may lead to increased signal transmission delays or require more energy to drive signals, both of which negatively impact the overall chip performance. Therefore, optimizing the connectivity graph design in chip routing is crucial for improving the performance and efficiency of the entire chip design. Furthermore, as modern integrated circuit designs become increasingly complex, the design and optimization of connectivity graphs in chip routing become more challenging, requiring more advanced design methods and technologies to address this.

[0003] The most effective existing technique is the SALT method proposed in 2019. This is a heuristic method with a complete theory and a relatively tight upper and lower bound, guaranteeing the worst-case result while also limiting the best-case result. In the connected graph design of chip routing, it is necessary to consider the case where connections can only be straight lines with rectangular sides and the possibility of generating additional auxiliary Steiner nodes, such as... Figure 1 As shown, this is an NP-hard problem. An NP-hard problem is one in which, in the worst case, all known algorithms require exponential time to find a solution, which is unacceptable for large-scale problems.

[0004] While the SALT method offers theoretical guarantees, in practice, generating connected graphs can suffer significant performance degradation because heuristic methods are essentially approximate solutions to NP-hard problems. For example, the connected graph may contain unnecessarily long lines, increasing chip area and signal transmission delay. Furthermore, the connection may not be optimal, potentially requiring more energy to drive signals and increasing power consumption.

[0005] On the other hand, as the size of the pin network increases, the computation time of the SALT method will increase significantly. This means that for large-scale pin networks, generating a connected graph using the SALT method may take a considerable amount of time. In situations where chip design cycles are typically very tight, this inefficiency can become a significant bottleneck, impacting the overall chip design schedule. Summary of the Invention

[0006] To address the above problems, this invention provides a method for generating a connected graph in chip wiring.

[0007] The method includes:

[0008] Step 1: For each sample, given n points, obtain the pin position coordinates V, where V = {v1, v2, ..., v...} n}, v1 represents the source node, v n Represents the last node;

[0009] Step 2: Use the transformer coding layer to obtain the global position feature representation X of the pin;

[0010] Step 3: Use the graph neural network in the policy network to update the global location feature representation X step by step. The updated representation obtained in step t-1 is X. t-1 ;

[0011] Step four: Aggregate node representations using the READOUT function. The directed graph representation obtained in step t-1 is Graph. t-1 ;

[0012] Step 5: Use the policy network to predict the probability e of the directed edge between node i and node j. i，j ;

[0013] Step 6: Represent the n*n predicted directed edges as probability values ​​between [0, 1] using the softmax function, and then form a probability matrix P from the obtained probability values. t ;

[0014] Step 7, convert the probability value matrix P t Setting the values ​​of unselectable edges to 0 yields the final probability matrix P′ used for edge selection. t The policy network directly selects P′ during the inference phase. t The edge with the highest probability is used as the current connection;

[0015] Step 8: Use the evaluation network to predict the expected objective function value for each set of pin coordinates. The evaluation network uses the same encoding method as the policy network to perform graph representation of the pin coordinates, and then linearly transforms the graph representation into a predicted value as the label when training the policy network.

[0016] Step 9: Define the training objective function Obj for the policy network. Train the policy network and the evaluator network by defining the loss functions for the policy network and the evaluator network to minimize the objective function Obj.

[0017] Furthermore, step two specifically includes:

[0018] The global location feature representation X is:

[0019] X = E_trans(V);

[0020] Here, E_trans is the transformer encoder structure.

[0021] Furthermore, step three specifically includes:

[0022] Let the output of the graph attention network be denoted as

[0023]

[0024] Among them, G t-1 A represents the directed graph structure generated in step t-1. m This is the matrix corresponding to the directed graph;

[0025] The final representation X after t-1 steps of graph neural network update t-1 for:

[0026]

[0027] Where M represents the number of matrix types corresponding to a directed graph.

[0028] Furthermore, the matrices corresponding to the directed graph are a first-order adjacency matrix, a second-order adjacency input matrix, and a second-order adjacency output matrix.

[0029]

[0030] Where A1 represents the first-order adjacency matrix of the directed graph, A2 represents the second-order adjacency input matrix of the directed graph, and A3 represents the second-order adjacency output matrix of the directed graph.

[0031] Furthermore, step four specifically includes:

[0032] The node representations are aggregated using the READOUT function to obtain the representation of the directed graph. t-1 :

[0033] Graph t-1 =READOUT(X t-1 );

[0034] Here, READOUT represents the READOUT function.

[0035] Furthermore, step five specifically includes:

[0036] The probability e of the directed edge between node i and node j i，j for:

[0037]

[0038] Here, mix() represents the associative function. This represents the node representation of node i after being updated by the graph neural network at step t-1. This represents the node representation of node j after being updated by the graph neural network at step t-1.

[0039] Furthermore, the objective function Obj mentioned in step nine is:

[0040] Obj = w1*WL + w2*PL;

[0041] Where WL is the bus length, PL is the longest path length, and w1 and w2 are freely adjustable balance parameters.

[0042] Furthermore, if the number of chip pins in the pin network is greater than 50 and less than 1000, the pin network is divided into small blocks, a connected graph is generated for each small block, and the small blocks are merged to obtain the final connected graph.

[0043] Furthermore, the division into smaller pieces specifically refers to:

[0044] Using a quadtree that depends on the data distribution, with the root node as the origin, the pin position farthest from the root node is used as the outermost boundary to obtain the circular boundary of the entire pin network diagram. The first layer is divided into four sub-blocks, the second layer into eight sub-blocks, and so on until there are no pins in the outermost layer. The number of layers is set according to the preset density requirements within the blocks, and the area of ​​each block is guaranteed to be equal during the division.

[0045] Furthermore, the merging of each small block specifically refers to:

[0046] Starting from any block on the outermost layer, the traversal is performed in the inorder traversal of the binary tree. The difference is that for the starting block x, the non-sibling blocks adjacent to each other on the same level are first found. Then, the two blocks are traversed in the inorder traversal clockwise and counterclockwise respectively until the first non-empty block is found. This non-empty block is connected to the two nearest pin pairs in the starting block. Then, this non-empty block is used as the new starting block and the traversal is performed again. This process is repeated to complete the merging of all sub-blocks.

[0047] One or more technical solutions provided in the embodiments of this application have at least the following technical effects or advantages:

[0048] The reinforcement learning method proposed in this invention, through encoder-decoder structures and refined training, can generate an optimized connected graph with optimized bus length and latency. This method achieves better performance than all existing methods, thus effectively solving the performance limitations of heuristic methods.

[0049] To address the challenges that artificial intelligence methods may encounter when processing large-scale pin networks, this invention proposes a partitioning and merging framework. By dividing the large-scale network into smaller blocks, applying reinforcement learning to each block, and then merging the results, this approach can reduce performance loss to some extent, thus better adapting to large-scale pin network designs. Attached Figure Description

[0050] Figure 1 This is a schematic diagram illustrating multi-objective optimization of connected graphs in chip routing, provided in an embodiment of the present invention.

[0051] Figure 2 The process for generating a rectangular Steiner tree based on a policy network and a judgment network provided in this embodiment of the invention;

[0052] Figure 3 A schematic diagram illustrating the transformation from a rectangular Steiner graph to a directed graph and the update of node representations provided in an embodiment of the present invention;

[0053] Figure 4 This is a schematic diagram of the second-order adjacency degree matrix and the second-order adjacency outgoing degree matrix provided in an embodiment of the present invention;

[0054] Figure 5 A schematic diagram of large-scale pin network breakdown provided in an embodiment of the present invention;

[0055] Figure 6 This is a schematic diagram of a method for splitting and merging large-scale pin networks provided in an embodiment of the present invention;

[0056] Figure 7 This is a flowchart of the encoding and decoding process in a policy network provided in an embodiment of the present invention;

[0057] Figure 8 A comparison of the longest paths generated by various methods for large-scale pin networks without splitting under different trade-off parameters provided in embodiments of the present invention;

[0058] Figure 9 This invention provides a comparison of the longest paths generated by various methods for large-scale pin network splitting under different trade-off parameters in embodiments of the invention. Detailed Implementation

[0059] The present invention will be described in detail below with reference to the accompanying drawings and specific embodiments. Before describing the technical solutions of each embodiment of the present invention in detail, the terms and terms involved will be explained. In this specification, components with the same name or the same reference numerals represent similar or the same structures and are limited to illustrative purposes.

[0060] This method proposes a reinforcement learning approach to generate a connected graph that balances bus length and latency. Through encoder-decoder structures and after careful training, it can achieve better performance than all current results. Furthermore, by leveraging the acceleration of neural network inference by GPU devices, its time efficiency is comparable to that of the SALT method.

[0061] Meanwhile, in order to address the shortcomings of artificial intelligence methods in adapting to large-scale pin networks, this invention proposes a partitioning and merging framework. By dividing the network into smaller blocks, applying the artificial intelligence method of this invention, and then merging them, performance loss can be reduced to some extent.

[0062] 1. Model Building

[0063] This invention utilizes reinforcement learning to generate a connected graph that balances bus length and latency. It employs a policy network to perform prediction and generate the connected graph. This process involves encoding and decoding the input pin coordinates to determine the edges to be added at each step. The training objective of the policy network is to generate a connected graph that minimizes a given objective function Obj, where Obj is:

[0064] Obj = w1*WL + w2*PL;

[0065] Where WL is the bus length, PL is the longest path length, and w1 and w2 are freely adjustable balancing parameters. Different balancing parameters will produce different trade-off results.

[0066] Since generating the optimal connected tree is an NP-complete problem, to avoid the significant time consumption of generating the optimal solution as a label, this invention uses a judge network to predict the expected objective function value for each set of pin coordinates. The judge network represents the pin coordinates graphically using the same encoding method as the policy network, and then linearly transforms the graphical representation into a predicted value. This predicted value is used as the label when training the policy network, and is not used by the judge network during the inference phase. Figure 2 As shown. In other words, during training, the policy network tries to make the objective function value of the connected graph it generates as close as possible to the prediction value given by the evaluator network. At the same time, the prediction value of the evaluator network also tries to get closer to the objective value of the connected graph generated by the policy network. This is a two-way approach.

[0067] This invention equates the longest path length to the delay of the entire circuit.

[0068] 2. Feature Extraction

[0069] In this invention, the features change as the number of execution steps increases, unlike previous feature extractors. This is to enable detailed feature extraction of the connected processes, such as... Figure 7 As shown, this invention uses a combination of graph neural networks and transformer encoders. The feature extraction method is described below.

[0070] For each sample, given n points (i.e., the number of pins in the sample is n), we obtain the pin position coordinates V, where V = {v1, v2, ..., v...} n The source node is defined as v1.

[0071] In the initial state, given a set of pin position coordinates, with no edges connecting them yet, a three-layer transformer encoding layer is used as an environment encoder to obtain the global position feature representation of the pins. The global position feature representation obtained from the environment encoder is used as the node feature, and then the policy network adds an edge at each step. This invention uses a graph neural network to update the node features and makes the next step selection based on the updated node features.

[0072] The global location feature representation X is:

[0073] X = E_trans(V);

[0074] Here, E_trans is the transformer encoder structure.

[0075] Then, for each edge added to the policy network, the graph neural network updates this feature to make more specific choices for the next step. The added edges are defined as right angles that are first vertical and then horizontal. To transform its special rectangular Steiner graph into a regular graph, a transformation method from rectangular Steiner edges to regular directed edges needs to be found, such as... Figure 3 As shown, edges that are first vertical and then horizontal are designated as directed edges. These two types can be transformed into each other, but the transformation result is not unique. After obtaining a regular directed graph, a graph neural network framework is used to update the node representation embeddings on this directed graph.

[0076] In this process, a Graph Attention Network (GAT) is used as the network for encoding updates. The output of the Graph Attention Network is denoted as...

[0077]

[0078] Among them, G t-1 A represents the directed graph structure generated in step t-1. mThe matrix corresponding to the directed graph is given by the present invention. Three types of matrices are used: a first-order adjacency matrix, a second-order adjacency input matrix, and a second-order adjacency output matrix, with m ∈ [1, 3].

[0079] The specific explanations of the second-order adjacency matrix and the second-order adjacency output matrix are as follows: Figure 4 As shown, these two matrices are tools for describing the connectivity relationships between nodes in a network. Figure 4 To the left of node V f Points to two nodes V i and V j V i and V j It is V f The second-order neighbor access degree of the neighbor. Figure 4 To the right of node V i and V j They all point to node V f V i and V j It is V f The second-order out-degree neighbor.

[0080] Therefore, the final representation X after the graph neural network update in the current step is... t-1 for:

[0081]

[0082] Where I represents the number of matrix types corresponding to the directed graph. For the updated representation X of the graph neural network in the current step of this invention... t-1 for:

[0083]

[0084] Where A1 represents the first-order adjacency matrix of the directed graph, A2 represents the second-order adjacency input matrix of the directed graph, and A3 represents the second-order adjacency output matrix of the directed graph.

[0085] Simultaneously, the node representations are aggregated using the READOUT function to obtain the representation of the directed graph. t-1 :

[0086] Graph t-1 =READOUT(X t-1 );

[0087] Here, READOUT represents the READOUT function.

[0088] 3. Decoding and Prediction

[0089] The representation X of the node at step t-1 is obtained during the feature extraction process. t-1 and the representation of a grapht-1 Then, decode and predict the edge that should be selected in the current t-th step.

[0090] If the number of sample pins is n, then there are a total of n*n directed edges considering directions. Representing these n*n directed edges as a combination of the pin representations at both ends and the graph representation, the directed edge e between node i and node j... i，j for:

[0091]

[0092] Here, mix() represents the associative function. In this invention, the average function is used as the associative function. This represents the node representation of node i after being updated by the graph neural network at step t-1. This represents the node representation of node j after being updated by the graph neural network at step t-1.

[0093] Then, the soffmax function is used to represent these n*n directed edges as probability values ​​between [0, 1], and the obtained probability values ​​are used to form a probability matrix P. t .

[0094] However, the generated connected graph contains some non-standard edges, such as self-loop edges and existing edges. To prevent these types of edges from being selected during prediction, a mask matrix of size n*n with elements of 0 and 1 is designed. Elements corresponding to selectable edges are set to 1, and elements corresponding to unselectable edges are set to 0. This mask matrix is ​​then compared with the probability matrix P. t Perform element-by-element multiplication, artificially setting the probability of unselectable edges to 0, to obtain the final probability matrix P′ used for edge selection. t During the reasoning phase, the edge with the highest probability is directly selected as the current connection.

[0095] If there are n pins in the pin network, the policy network needs to perform n-1 steps to generate the lead routing for connecting the pins. After performing n-1 steps, a fully connected directed graph is obtained. This directed graph needs to be converted back to the corresponding rectangular Steiner tree to serve as the final connection scheme for this set of pins.

[0096] 4. Model Training

[0097] The two processes described above complete the prediction through encoding and decoding. However, sufficient training is required before the prediction can be performed so that the policy network acquires appropriate parameters.

[0098] n-1 edges can connect n nodes, forming a directed tree. Assume the state S at step t-1 is... t-1 The probability of choosing a certain edge is p.t The probability P that the policy network generates the final valid connected graph is... tra for:

[0099]

[0100] Where θ are the model training parameters, and the model is defined as a function p θ In this model, at step t, the state S from the previous step is used as a reference. t-1 The probability of selecting edge is output as p. t State S t-1 That is, the subgraph structure already formed in step t-1. The final product of the probabilities of the n-1 edges, p. tra This is the probability value of the entire image generating a complete trajectory.

[0101] The policy network loss L(θ|V) is:

[0102] L(θ|V)=∑ tra∈J (C(V)-A(V,tra))p tra ;

[0103] Where C(V) is the prediction objective function of the evaluation network, A(V, tra) is the objective function value calculated from the connected graph generated by the policy network, tra represents the trajectory generated by a single graph, and J represents the trajectories generated by all graphs. Gradient ascent is performed on this loss to train the policy network.

[0104] For evaluating the network, the MSE loss function (Loss) is used:

[0105]

[0106] in, This represents the mean squared error. Gradient descent is performed on this loss function to train the evaluation network; both networks are updated simultaneously.

[0107] The training of policy networks and judge networks in reinforcement learning is common knowledge in the field, and will not be elaborated upon in this invention.

[0108] 5. Decomposition of large-scale pin networks

[0109] Large-scale pin networks refer to pin networks with more than 50 but less than 1000 pins. For such a scale, neural network algorithms are insufficient. They can be divided into smaller blocks, processed using the chip routing connectivity graph generation method proposed in this invention, and then merged. However, partitioning inevitably incurs some performance penalty; therefore, a suitable partitioning and merging method is crucial.

[0110] 5.1 Division

[0111] Using a quadtree that depends on the data distribution, with the root node as the origin, the outermost boundary is the pin position farthest from the root node, thus obtaining the circular boundary of the entire pin network diagram. Then, according to... Figure 5 The partitioning method involves dividing the area into four sub-blocks in the first layer, eight sub-blocks in the second layer, and so on until the outermost layer has no pins. The number of layers can be specified according to different density requirements within each block, ensuring that each block has an equal area. When the pin distribution is relatively uniform, the number of pins within each block is also approximately equal. After partitioning, the pin coordinates in the non-empty blocks are used to generate corresponding sub-graphs using the neural network method described in this invention.

[0112] 5.2 Merging

[0113] During merging, to avoid connecting to empty blocks, a zigzag search is used to join blocks, such as... Figure 6 As shown. Specifically, this method starts from any block on the outermost layer and traverses according to the inorder traversal of a binary tree. The difference is that for the starting block x, this method first finds the non-sibling blocks that are adjacent at the same level, and then performs clockwise and counterclockwise inorder traversals on the two blocks respectively until the first non-empty block is found. This non-empty block is then connected to the two nearest pin pairs in the starting block. Next, this non-empty block is used as the new starting block for traversal, thus completing the merging process of all sub-blocks and obtaining a complete pin connectivity graph.

[0114] 6. Effect Comparison

[0115] Using neural networks to generate the required tree achieves the best results among all current methods. Using a partitioning and merging approach to handle large-scale networks also helps to maintain performance to some extent. The results are shown below. Figure 8 As shown, Figure 8 The test was conducted on randomly generated 10k pin coordinates. Different points on the curve represent different trade-off parameters. The horizontal axis represents the line length, and the vertical axis represents the longest path. It can be seen that the present invention achieves the best trade-off effect, and can simultaneously reduce the longest path and bus length as much as possible.

[0116] The results of testing by splitting and then merging large-scale networks are as follows: Figure 9 As shown, although the performance of this method is slightly lower, it is still second only to the previous method. Furthermore, it has extremely high time efficiency because the generation of small connected graphs can be parallelized. Taking a chip with 1000 pins as an example, this method takes 70.33s to generate a connected graph, while the best performance of the existing methods takes 137.8s.

[0117] The above-described embodiments are merely preferred embodiments of the present invention and are not intended to limit the scope of the present invention. Various modifications and improvements made by those skilled in the art to the technical solutions of the present invention without departing from the spirit of the present invention should fall within the protection scope defined by the claims of the present invention.

Claims

1. A method for generating a connected graph in chip wiring, characterized in that, Includes the following steps: Step 1: For each sample, given n points, obtain the pin position coordinates V, where V = {v1, v2, ..., v...} n }, v1 represents the source node, v n Represents the last node; Step 2: Use the transformer coding layer to obtain the global position feature representation X of the pin; Step 3: Use the graph neural network in the policy network to update the global location feature representation X step by step. The updated representation obtained in step t-1 is X. t-1 ; Step four: Aggregate node representations using the READOUT function. The directed graph representation obtained in step t-1 is Graph. t-1 ; Step 5: Use the policy network to predict the probability e of the directed edge between node i and node j. i，j ; Step 6: Represent the n*n predicted directed edges as probability values ​​between [0, 1] using the softmax function, and then form a probability matrix P from the obtained probability values. t ; Step 7, convert the probability value matrix P t Setting the values ​​of unselectable edges to 0 yields the final probability matrix P′ used for edge selection. t The policy network directly selects P′ during the inference phase. t The edge with the highest probability is used as the current connection; Step 8: Use the evaluation network to predict the expected objective function value for each set of pin coordinates. The evaluation network uses the same encoding method as the policy network to perform graph representation of the pin coordinates, and then linearly transforms the graph representation into a predicted value as the label when training the policy network. Step 9: Define the training objective function obj for the policy network. Train the policy network and the evaluator network by defining the loss functions for the policy network and the evaluator network to minimize the objective function Obj.

2. The method for generating a connected graph in chip wiring according to claim 1, characterized in that, Step two specifically includes: The global location feature representation X is: X = E_trans(V); Here, E_trans is the transformer encoder structure.

3. The method for generating a connected graph in chip wiring according to claim 1, characterized in that, Step three specifically includes: Let the output of the graph attention network be denoted as Among them, G t-1 A represents the directed graph structure generated in step t-1. m This is the matrix corresponding to the directed graph; The final representation X after t-1 steps of graph neural network update t-1 for: Where M represents the number of matrix types corresponding to a directed graph.

4. The method for generating a connected graph in chip wiring according to claim 3, characterized in that, The matrices corresponding to the directed graph are a first-order adjacency matrix, a second-order adjacency input matrix, and a second-order adjacency output matrix; Where A1 represents the first-order adjacency matrix of the directed graph, A2 represents the second-order adjacency input matrix of the directed graph, and A3 represents the second-order adjacency output matrix of the directed graph.

5. The method for generating a connected graph in chip wiring according to claim 1, characterized in that, Step four specifically includes: The node representations are aggregated using the READOUT function to obtain the representation of the directed graph. t-1 : Graph t-1 =READOUT(X t-1 ); Here, READOUT represents the READOUT function.

6. The method for generating a connected graph in chip wiring according to claim 1, characterized in that, Step five specifically includes: The probability e of the directed edge between node i and node j i，j for: Here, mix() represents the associative function. This represents the node representation of node i after being updated by the graph neural network at step t-1. This represents the node representation of node j after being updated by the graph neural network at step t-1.

7. The method for generating a connected graph in chip wiring according to claim 1, characterized in that, The objective function Obj mentioned in step nine is: Obj = w1*WL + w2*PL; Where WL is the bus length, PL is the longest path length, and w1 and w2 are freely adjustable balance parameters.

8. The method for generating a connected graph in chip wiring according to claim 1, characterized in that, If the number of chip pins in the pin network is greater than 50 and less than 1000, the pin network is divided into small blocks, a connected graph is generated for each small block, and the small blocks are merged to obtain the final connected graph.

9. The method for generating a connected graph in chip wiring according to claim 8, characterized in that, The phrase "dividing it into smaller pieces" specifically refers to: Using a quadtree that depends on the data distribution, with the root node as the origin, the pin position farthest from the root node is used as the outermost boundary to obtain the circular boundary of the entire pin network diagram. The first layer is divided into four sub-blocks, the second layer into eight sub-blocks, and so on until there are no pins in the outermost layer. The number of layers is set according to the preset density requirements within the blocks, and the area of ​​each block is guaranteed to be equal during the division.

10. The method for generating a connected graph in chip wiring according to claim 9, characterized in that, The merging of each small block specifically refers to: Starting from any block on the outermost layer, the traversal is performed in the inorder traversal of the binary tree. The difference is that for the starting block x, the non-sibling blocks adjacent to each other on the same level are first found. Then, the two blocks are traversed in the inorder traversal clockwise and counterclockwise respectively until the first non-empty block is found. This non-empty block is connected to the two nearest pin pairs in the starting block. Then, this non-empty block is used as the new starting block and the traversal is performed again. This process is repeated to complete the merging of all sub-blocks.

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