Method and apparatus for detecting quality of design of ddr signals

Abstract

The embodiment of the application provides a method and device for detecting the design quality of a DDR signal, which comprises: storing DDR signal design information in an information storage area; obtaining and reading a DDR signal design drawing to group DDR signal patterns in the design drawing to obtain multiple groups of DDR signal patterns; obtaining the read equivalent length of each type of DDR signal, the first read difference threshold of the read equivalent length of different types of DDR signals, the second read difference threshold of the read equivalent length of the same type of DDR signal for each group of DDR signal patterns, and determining whether the DDR signal design drawing meets the DDR signal design information according to the difference between the read equivalent length and the equivalent length, the difference between the first read difference threshold and the first difference threshold, and the difference between the second read difference threshold and the second difference threshold. The technical problem of manually calculating the equivalent length of the DDR signal after adding a tab is solved.

Description

Technical Field

[0001] This application relates to the field of DDR hardware, and more specifically, to a method and apparatus for detecting the design quality of DDR signals. Background Technology

[0002] In DDR hardware design, due to limitations in PCB layout and routing, different lengths of package traces inside the chip, and different numbers of vias on a single DDR signal line in the same group, there may be a delay in signal transmission time due to unequal lengths of DDR signal traces.

[0003] As signal rates increase, timing requirements become more stringent. Existing routing designs with equal physical trace lengths are insufficient to meet the timing demands of high-speed signals. Therefore, to ensure signal quality, designs require the inclusion of tabs on DDR signals to compensate for insufficient DDR trace lengths. However, different chip specifications impose different rules on the equivalent length relationships between signals within DDR signal groups, such as control signals (CS_n\RAS_n\CAS_n\WE_n), clock signals (CK\CKE), address signals (BG\BA\A0-A15), and data signals (DM\DQ\DQS). Furthermore, a relatively lenient equal-length relationship must be maintained between the data signal DQS and the clock signal CLK.

[0004] The current solution requires PCB design engineers to manually calculate the equivalent length of the DDR signal after adding tabs, and to perform rule checks according to different signal groups. This operation is labor-intensive and very easy to overlook, making it difficult to guarantee design quality. Summary of the Invention

[0005] This application provides a method and apparatus for detecting the design quality of DDR signals, which at least solves the problem in the related art that the design quality of DDR signals requires manual inspection by engineers, which is labor-intensive, easy to overlook, and difficult to guarantee design quality.

[0006] According to some embodiments of this application, a method for detecting the design quality of DDR signals is provided, comprising: storing DDR signal design information in an information storage area, the DDR signal design information including the equivalent length of various types of DDR signals, a first difference threshold for the equivalent length of different types of DDR signals, and a second difference threshold for the equivalent length of the same type of DDR signals; acquiring and reading DDR signal design drawings, grouping the DDR signal graphics in the design drawings to obtain multiple groups of the DDR signal graphics; for each group of the DDR signal graphics, acquiring the read equivalent length of each type of DDR signal, and the first read difference threshold for the read equivalent length of different types of DDR signals, and the second read difference threshold for the read equivalent length of the same type of DDR signals, and determining whether the DDR signal design drawings meet the DDR signal design information based on the difference between the read equivalent length and the equivalent length, the difference between the first read difference threshold and the first difference threshold, and the difference between the second read difference threshold and the second difference threshold.

[0007] According to some embodiments of this application, the step of acquiring and reading DDR signal design drawings and grouping the DDR signal graphics in the design drawings to obtain multiple groups of the DDR signal graphics includes: acquiring the filename of each DDR signal graphic in the design drawings, wherein the filename is stored in the design document; and grouping the DDR signal graphics according to the filename to obtain multiple groups of the DDR signal graphics.

[0008] According to some embodiments of this application, obtaining the filenames of each DDR signal graphic in the design drawing includes: generating a first built-in function; and using the first built-in function to read the design document to obtain the filenames of each DDR signal graphic in the design drawing.

[0009] According to some embodiments of this application, obtaining the equivalent read length of each type of DDR signal includes: generating a second built-in function; using the second built-in function to read the DDR signal pattern to obtain the physical signal length of the corresponding DDR signal; reading the Tab size-related values ​​in the DDR signal pattern, the Tab size-related values ​​including the number of Tabs and the equivalent length of a single Tab; and determining the equivalent read length of the DDR signal based on the physical signal length of the DDR signal and the Tab size-related values ​​in the DDR signal pattern.

[0010] According to some embodiments of this application, reading the Tab size-related values ​​in the DDR signal pattern includes: determining whether the DDR signal corresponding to the DDR signal pattern has a Tab attribute identifier, wherein the Tab attribute identifier indicates that a Tab is set for the DDR signal; and if the DDR signal has the Tab attribute identifier, obtaining the Tab size-related values ​​in the DDR signal pattern corresponding to the DDR signal.

[0011] According to some embodiments of this application, for each group of DDR signal patterns, obtaining the equivalent read length of each type of DDR signal includes: for each group of DDR signal patterns, including the DDR signal patterns belonging to that group in the list ddridlist = {id1, id2, id3 to idn}; performing loop processing on the list ddridlist = {id1, id2, id3 to idn}, using the element variable itemi to represent the i-th element in the list ddridlist, and using a third built-in function to obtain the chip pin connected to the DDR signal corresponding to the DDR signal pattern represented by the element variable itemi, and determining the type of the corresponding DDR signal according to the chip pin to obtain the list newgroup1, the list newgroup1 including multiple (signal type m idm idn), indicating that the type of the DDR signal corresponding to idm and idn is signal type m; looping to obtain idi in the list newgroup1, obtaining the physical signal length lengthi of each DDR signal, and then obtaining the equivalent read length of each DDR signal. EQlengthi = lengthi + couti × k, where couti represents the number of tabs and k represents the equivalent length of a single tab. After obtaining the equivalent length of each type of DDR signal for each group of DDR signal patterns, the method further includes: considering the equivalent length EQlengthi of each DDR signal, constructing a list newnetlist = {DDR group name, signal type m, idi, signal network name, lengthi, couti, EQlengthi}, and after the list newnetlist of the DDR signal patterns for that group is constructed, setting couti = 0, and processing the next group of DDR signal patterns.

[0012] According to some embodiments of this application, the method further includes: using a first identifier to represent a DDR signal that conforms to the DDR signal design information; using a second identifier to represent a DDR signal that does not conform to the DDR signal design information; using a third identifier to represent that all the DDR signals in a group conform to the DDR signal design information; and using a fourth identifier to represent that at least one DDR signal in a group does not conform to the DDR signal design information.

[0013] According to some embodiments of this application, the method further includes: displaying the DDR signal graphic corresponding to the DDR signal represented by the second identifier in a first display area with a first preset color; and displaying the DDR signal graphic corresponding to the DDR signal group represented by the fourth identifier in a second display area with a second preset color.

[0014] According to some embodiments of this application, the method further includes: receiving and responding to a first preset operation acting on the DDR signal graphic displayed in the first preset color, binding a first highlight function, the first highlight function being used to highlight the DDR signal graphic in the DDR signal design drawing; receiving and responding to a second preset operation acting on the DDR signal graphic displayed in the second preset color, binding a second highlight function, the second highlight function being used to highlight the DDR signal graphic in the DDR signal design drawing.

[0015] Some embodiments of this application also provide an apparatus for detecting the design quality of DDR signals, comprising: a storage module for storing DDR signal design information in an information storage area, the DDR signal design information including the equivalent length of various types of DDR signals, a first difference threshold for the equivalent length of different types of DDR signals, and a second difference threshold for the equivalent length of the same type of DDR signals; a grouping module for acquiring and reading DDR signal design drawings, grouping the DDR signal graphics in the design drawings to obtain multiple groups of the DDR signal graphics; and a processing module for acquiring, for each group of the DDR signal graphics, the read equivalent length of each type of DDR signal, the first read difference threshold for the read equivalent length of different types of DDR signals, and the second read difference threshold for the read equivalent length of the same type of DDR signals, and determining whether the DDR signal design drawing meets the DDR signal design information based on the difference between the read equivalent length and the equivalent length, the difference between the first read difference threshold and the first difference threshold, and the difference between the second read difference threshold and the second difference threshold.

[0016] According to some embodiments of this application, a computer-readable storage medium is also provided, wherein a computer program is stored in the computer program, and the computer program is configured to perform the steps in any of the above method embodiments when it is run.

[0017] According to some embodiments of this application, an electronic device is also provided, including a memory and a processor, wherein the memory stores a computer program, and the processor is configured to run the computer program to perform the steps in any of the above method embodiments.

[0018] This application utilizes a method to store DDR signal design information in an information storage area. This information includes the equivalent lengths of various types of DDR signals, a first difference threshold for the equivalent lengths of different types of DDR signals, and a second difference threshold for the equivalent lengths of the same type of DDR signals. The method involves acquiring and reading DDR signal design drawings, grouping the DDR signal graphics in the drawings to obtain multiple sets of DDR signal graphics. For each set of DDR signal graphics, the method acquires the equivalent length of each type of DDR signal, the first read difference threshold for the equivalent lengths of different types of DDR signals, and the second read difference threshold for the equivalent lengths of the same type of DDR signals. Based on the differences between the equivalent lengths, the first read difference threshold, and the second read difference threshold, the method determines whether the DDR signal design drawings meet the DDR signal design information. By pre-storing the DDR signal design information and subsequently reading the drawings to obtain the actual design results, the method determines whether the drawings meet the design rules, thus determining the design quality of the DDR signals. This eliminates the need for manual inspection by engineers, reduces the likelihood of omissions, and ensures design quality. Attached Figure Description

[0019] Figure 1 This is a hardware structure block diagram of a terminal device for performing a method for detecting the design quality of DDR signals according to an embodiment of this application;

[0020] Figure 2 This is a flowchart of a first method for detecting the design quality of DDR signals according to an embodiment of this application;

[0021] Figure 3 This is a schematic diagram of a first front-end page design according to an embodiment of this application;

[0022] Figure 4 This is a schematic diagram of a second front-end page design according to an embodiment of this application;

[0023] Figure 5 This is a flowchart of a second method for detecting the design quality of DDR signals according to an embodiment of this application;

[0024] Figure 6 This is a structural block diagram of an apparatus for detecting the design quality of DDR signals according to an embodiment of this application. Detailed Implementation

[0025] The embodiments of this application will be described in detail below with reference to the accompanying drawings and examples.

[0026] It should be noted that the terms "first," "second," etc., in the specification, claims, and drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence.

[0027] The methods and embodiments provided in this application can be executed in terminal devices or similar computing devices, server devices or similar computing devices. Taking running on a server device or terminal device as an example, Figure 1 This is a hardware structure block diagram of a terminal device server equipment for a method of detecting the design quality of DDR signals according to an embodiment of this application. Figure 1 As shown, the server device terminal device may include one or more ( Figure 1 Only one is shown in the diagram. A processor 102 (which may include, but is not limited to, a microprocessor MCU or a programmable logic device FPGA, etc.) and a memory 104 for storing data are also shown. The server terminal device may further include a transmission device 106 for communication functions and an input / output device 108. Those skilled in the art will understand that... Figure 1 The structure shown is for illustrative purposes only and does not limit the structure of the server equipment terminal device described above. For example, the server equipment terminal device may also include components that are more... Figure 1 The more or fewer components shown, or having the same Figure 1 The different configurations shown.

[0028] The memory 104 can be used to store computer programs, such as application software programs and modules, like the computer program corresponding to the method for detecting DDR signal design quality in this embodiment. The processor 102 executes various functional applications and data processing by running the computer program stored in the memory 104, thus implementing the aforementioned method. The memory 104 may include high-speed random access memory and may also include non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memory. In some instances, the memory 104 may further include memory remotely located relative to the processor 102, and these remote memories can be connected to terminal devices via a network. Examples of such networks include, but are not limited to, the Internet, corporate intranets, local area networks, mobile communication networks, and combinations thereof.

[0029] The transmission device 106 is used to receive or send data via a network. Specific examples of the network described above may include a wireless network provided by the communication provider of the terminal device. In one example, the transmission device 106 includes a Network Interface Controller (NIC), which can connect to other network devices via a base station to communicate with the Internet. In another example, the transmission device 106 may be a Radio Frequency (RF) module used for wireless communication with the Internet.

[0030] This embodiment provides a method for detecting the design quality of DDR signals. Figure 2 This is a flowchart of a method for detecting the design quality of DDR signals according to an embodiment of this application, such as... Figure 2 As shown, the process includes the following steps:

[0031] Step S202: Store DDR signal design information in the information storage area. The DDR signal design information includes the equivalent length of various types of DDR signals, the first difference threshold of the equivalent length of different types of DDR signals, and the second difference threshold of the equivalent length of the same type of DDR signals.

[0032] The equivalent length of the DDR signal is the length after adding Tabs. Tabs refer to a wiring method that adds copper foil of a specific shape and size to the trace according to certain rules.

[0033] DDR signals come in various types, such as control signals (CS_n\RAS_n\CAS_n\WE_n), clock signals (CK\CKE), address signals (BG\BA\A0-A15), and data signals (DM\DQ\DQS).

[0034] For example, the equivalent length difference threshold between differential signals is denoted as DP2DN, the equivalent length difference threshold between DQS and DQ signals is denoted as DQS2DQ, the difference between DQS and DQS is denoted as DQS2DQS, the difference between DQ and DQ is denoted as DQ2DQ, and the equivalent length difference threshold between command signals is denoted as the initial value of ECC2ECC.

[0035] Step S204: Obtain and read the DDR signal design drawing, group the DDR signal graphics in the design drawing, and obtain multiple groups of DDR signal graphics;

[0036] The above-mentioned DDR signal design drawings are electronic drawings designed using circuit design software before being fabricated into PCBs. By reading the DDR signal design drawings, the bar-shaped graphics in the DDR signal design drawings can be identified, and the bar-shaped images represent the corresponding DDR signals.

[0037] The above grouping approach facilitates the execution of subsequent quality determination steps;

[0038] Step S206: For each group of DDR signal patterns, obtain the equivalent read length of each type of DDR signal, the first read difference threshold of the equivalent read length of different types of DDR signals, and the second read difference threshold of the equivalent read length of the same type of DDR signals. Determine whether the DDR signal design drawing meets the DDR signal design information based on the difference between the equivalent read length and the equivalent length, the difference between the first read difference threshold and the first difference threshold, and the difference between the second read difference threshold and the second difference threshold.

[0039] Since the DDR signal pattern corresponds to the DDR signal, by reading the DDR signal pattern, the equivalent reading length of each type of DDR signal, the first reading difference threshold of the equivalent reading length of different types of DDR signals, and the second reading difference threshold of the equivalent reading length of the same type of DDR signal can be obtained. Then, it can be compared with the initial rules set during the design process stored in the DDR signal design information.

[0040] Specifically, the determination of whether the DDR signal design drawing meets the DDR signal design information is based on the difference between the read equivalent length and the equivalent length, the difference between the first read difference threshold and the first difference threshold, and the difference between the second read difference threshold and the second difference threshold. This can be interpreted as follows: if the difference between the read equivalent length and the equivalent length is zero or close to zero, the difference between the first read difference threshold and the first difference threshold is zero or close to zero, and the difference between the second read difference threshold and the second difference threshold is zero or close to zero, i.e. the difference is small, it is determined that the actual DDR signal design drawing meets the design requirements, i.e., the DDR signal design quality meets the requirements.

[0041] The method for detecting the design quality of DDR signals in this application involves storing DDR signal design information in an information storage area. This information includes the equivalent length of various types of DDR signals, a first difference threshold for the equivalent length of different types of DDR signals, and a second difference threshold for the equivalent length of DDR signals of the same type. The method then acquires and reads DDR signal design drawings, groups the DDR signal graphics in the drawings, and obtains multiple groups of DDR signal graphics. For each group of DDR signal graphics, the method acquires the read equivalent length of each type of DDR signal, the first read difference threshold for the read equivalent length of different types of DDR signals, and the second read difference threshold for the read equivalent length of the same type of DDR signal. Based on the differences between the read equivalent lengths, the first read difference threshold, and the second read difference threshold, the method determines whether the DDR signal design drawing meets the DDR signal design information. By pre-storing the DDR signal design information and subsequently reading the drawings to obtain the actual design results, the method determines whether the drawings meet the design rules, thus determining the design quality of the DDR signals. This eliminates the need for manual inspection by engineers, reduces the likelihood of omissions, improves work efficiency, and ensures design quality.

[0042] Specifically, in step S104, the DDR signal design drawing is acquired and read, and the DDR signal graphics in the design drawing are grouped to obtain multiple groups of DDR signal graphics, including:

[0043] Step S1041: Obtain the filename of each DDR signal graphic in the design drawing, and store the filename in the design document;

[0044] The design document is the design document for DDR signal design drawings, which stores information about the DDR signal design drawings; the design document is an electronic document, and the file names of each DDR signal graphic in the design drawings can be obtained by reading the design document;

[0045] Furthermore, design documents can be in formats such as XML for easier reading;

[0046] Step S1042: Group the DDR signal graphics according to the file name to obtain multiple groups of DDR signal graphics.

[0047] For example, DDR signal patterns whose filenames begin with the character 'A' are grouped together, DDR signal patterns whose filenames include the character 'B' as the first character are grouped together, and DDR signal patterns whose filenames include the character 'C' as the first character are grouped together. Grouping is achieved by reading the filenames.

[0048] Specifically, obtaining the filenames of each DDR signal graphic in the design drawings includes: generating a first built-in function; and using the first built-in function to read the design document to obtain the filenames of each DDR signal graphic in the design drawings. The first built-in function is a character recognition function, meaning that the filenames of each DDR signal graphic in the design drawings are obtained by calling the character recognition function.

[0049] Specifically, the equivalent read length of each type of DDR signal is obtained.

[0050] This includes: generating a second built-in function; using the second built-in function to read the DDR signal graph to obtain the physical signal length of the corresponding DDR signal;

[0051] The second built-in function is a function with graphic recognition capabilities. It identifies the DDR signal graphic and then, based on the principle of proportion, determines the physical signal length of the DDR signal according to the length of the DDR signal graphic. If the DDR signal design drawing and the actual PCB are in a 1:1 ratio, the length of the DDR signal graphic is directly determined as the physical signal length of the DDR signal. If the DDR signal design drawing and the actual PCB are in a 1:2 ratio, twice the length of the DDR signal graphic is determined as the physical signal length of the DDR signal. If the DDR signal design drawing and the actual PCB are in a 2:1 ratio, half the length of the DDR signal graphic is determined as the physical signal length of the DDR signal.

[0052] Furthermore, the second built-in function includes an image recognition function, which includes an edge recognition algorithm. The edge recognition algorithm is used to identify the outline of the image, and then the length of the image is determined based on the number of pixels in the outline of the image, thereby determining the physical signal length of the DDR signal.

[0053] Read the tab size-related values ​​in the DDR signal graph. The tab size-related values ​​include the number of tabs and the equivalent length of a single tab.

[0054] The equivalent length of the DDR signal read is determined based on the physical signal length of the DDR signal and the tab size values ​​in the DDR signal graph.

[0055] Specifically, the equivalent length of the DDR signal is obtained by multiplying the number of tabs by the equivalent length of a single tab and adding the physical signal length of the DDR signal. By determining the physical signal length of the DDR signal, the number of tabs, and the equivalent length of a single tab, the accurate determination of the equivalent length of the DDR signal can be achieved.

[0056] In this embodiment of the application, reading the tab size-related values ​​in the DDR signal graph includes:

[0057] Determine whether the DDR signal corresponding to the DDR signal graphic has a Tab attribute identifier. The Tab attribute identifier indicates that the DDR signal has a Tab set; that is, a DDR signal without a Tab added does not have a Tab attribute identifier.

[0058] When a DDR signal has a Tab attribute identifier, obtain the Tab size-related values ​​in the DDR signal graph corresponding to the DDR signal.

[0059] In addition, the Tab attribute identifier can also indicate the number of Tabs added to the DDR signal, and then combined with the equivalent length of 1 tab, the total length of the Tab can be determined.

[0060] Since there are many DDR signals in a single DDR hardware device, a Tab attribute identifier is set to quickly and accurately determine the equivalent length of DDR signals with added Tabs.

[0061] Specifically, for each group of DDR signal patterns, the equivalent read length of each type of DDR signal is obtained, including:

[0062] For each group of DDR signal patterns, the DDR signal patterns belonging to that group are added to the list ddridlist = {id1, id2, id3 to idn}. The list ddridlist = {id1, id2, id3 to idn} is iterated over, with the element variable itemi representing the i-th element in the list ddridlist. A third built-in function is used to obtain the chip pins connected to the DDR signal patterns represented by the element variable itemi. Based on the chip pins, the type of the corresponding DDR signal is determined to obtain the list newgroup1. List newgroup1 includes multiple (signal types m idm) idn), indicating that the type of DDR signal corresponding to idm and idn is signal type m; iteratively obtains idi in list newgroup1, obtains the physical signal length lengthi of each DDR signal, and then obtains the read equivalent length EQlengthi = lengthi + couti × k of each DDR signal, where couti represents the number of tabs and k represents the equivalent length of a single tab; after obtaining the read equivalent length of each type of DDR signal for each group of DDR signal graphics, the method also includes: considering the read equivalent length EQlengthi of each DDR signal, constructing a list newnetlist = {DDR group name, signal type m, idi, signal network name, lengthi, couti, EQlengthi}, and after the list newnetlist of the DDR signal graphics for this group is constructed, setting couti = 0, and proceeding to process the next group of DDR signal graphics.

[0063] The above loop determines the type of DDR signal and the equivalent read length for each group of DDR signal patterns.

[0064] Furthermore, the method also includes: using a first identifier to represent a DDR signal that conforms to the DDR signal design information; for example, the first identifier is flag=1; using a second identifier to represent a DDR signal that does not conform to the DDR signal design information; for example, the second identifier is flag=0; using a third identifier to represent that all DDR signals in a group conform to the DDR signal design information; for example, the third identifier is okflag=1; and using a fourth identifier to represent that at least one DDR signal in a group does not conform to the DDR signal design information; for example, the fourth identifier is okflag=0.

[0065] By setting identifiers, DDR signals that meet the DDR signal design requirements and those that do not can be distinguished; DDR signal groups that meet the DDR signal design requirements and those that do not can be distinguished; this facilitates the quick selection of DDR signals and DDR signal groups that do not meet the DDR signal design requirements for subsequent modification.

[0066] Furthermore, the method also includes: displaying the DDR signal graphic corresponding to the DDR signal represented by the second identifier in a first display area using a first preset color; and displaying the DDR signal graphic corresponding to the DDR signal group represented by the fourth identifier in a second display area using a second preset color. Figure 3 As shown, the first display area displays the DDR signal graphic corresponding to the DDR signal represented by the second identifier, and the second display area displays the DDR signal graphic corresponding to the DDR signal group represented by the fourth identifier.

[0067] like Figure 3 As shown, the display page also includes: a DDR signal grouping list display area, a rule setting area, and a button operation area. The DDR signal grouping list display area shows DDR signals in a list format, allowing multiple groups of DDR signals to be displayed in one list. The rule setting area allows users to input DDR signal design information, and the button operation area provides buttons for selection, scrolling, and other operations.

[0068] The front end displays the initial value, but it can be modified. PCB engineers can modify the initial values ​​of relevant rules in the rule settings area when performing DDR signal design quality checks.

[0069] like Figure 4 As shown, the display page also includes a test result list display area, which displays list information, such as the display list newnetlist = {DDR group name, signal type 1, idi, signal network name, lengthi, couti, EQlengthi}. The display column corresponding to the DDR signal that does not meet the design requirements can be displayed in red to indicate it.

[0070] By displaying DDR signals and DDR signal groups that do not meet the DDR signal design requirements in a preset area, engineers can easily make modifications later.

[0071] In this embodiment of the application, the method further includes:

[0072] Receive and respond to a first preset operation applied to a DDR signal graphic displayed in a first preset color, and bind a first highlight function, which is used to highlight the DDR signal graphic in the DDR signal design drawing;

[0073] Receive and respond to a second preset operation applied to a DDR signal graphic displayed in a second preset color, and bind a second highlight function, which is used to highlight the DDR signal graphic in the DDR signal design drawing.

[0074] The first preset operation and the second preset operation can be a single click operation, a double click operation, etc.; the first preset color and the second preset color can be red, yellow, etc.

[0075] As described above, in response to the operator's preset operation, the DDR signal that needs to be modified is selected and linked through the highlighting function. This highlights the DDR signal graphic in the DDR signal design drawing, allowing the operator to directly view the DDR signal that does not meet the design requirements in the DDR signal design drawing for modification.

[0076] The entities that perform the above steps can be servers, terminals, etc., but are not limited to these.

[0077] The execution order of steps S102 and S104 can be interchanged; that is, step S104 can be executed first, and then step S102 can be executed.

[0078] Figure 5 A flowchart illustrating a specific method for detecting DDR signal quality is shown. Figure 5 As shown, it includes: a Tab attribute recording module, in which a tab attribute identifier is set, which can be recorded as GRAFT and the attribute type is DDRTYPE;

[0079] The DDR signal design rule setting module stores DDR signal design data. Specifically, it sets the tab size value, the equivalent length k of one tab, and the relationship between the equivalent lengths of different signal categories within different DDR signal groups to meet the rule settings, based on the general DDR signal design specifications.

[0080] The system includes modules for DDR signal grouping, DDR signal group classification and preprocessing, and DDR signal group equivalent length calculation. These modules determine whether the design requirements are met. Data preprocessing specifically includes:

[0081] Step 1: When PCB engineers design DDR signals, DDR signal group names all start with M. Therefore, the built-in function is used to obtain all groups in the current design document and add all group names whose names start with M to the list DDRGroup = {group1, group2, group3...}.

[0082] Step 2: Process DDR signals in a loop, grouping them into DDRGroups. (To ensure signal quality, DDR signals must meet the design rules not only for the equivalent length between groups, but also for the different signal lengths within a group.)

[0083] a. Taking one of the DDR signal groups as an example, denoted as group1, obtain the IDs of all DDR signals belonging to group1 and add them to the list ddridlist = {id1, id2, id3...};

[0084] b. Iterate through `ddridlist` again, taking each element as `itemi`. Use built-in functions to obtain the chip pins of the DDR signal network connected to `itemi` to determine the type of the DDR signal `itemi` (the pins corresponding to the chip signals are fixed; it's either a data signal DQS / DQ, a clock signal CLK, or a command signal CS / CA). Classifying by network name can lead to naming inconsistencies that prevent this method from working. Therefore, determining the type based on the connected chip pins is more accurate. This achieves secondary classification of signals within DDR signal groups through chip pin identification, resulting in `newgroup1 = {(signal type 1 id1 id3...), (signal type 2 id2 id4 id5)...}`.

[0085] Step 3: Calculate the equivalent length of the design tab for each DDR signal group. Taking newgroup1 as an example:

[0086] a. Loop through the signal idi in newgroup1 and use the built-in function to get the physical signal length lengthi;

[0087] b. Determine whether the signal idi has the Tab attribute identifier DDRTYPE set. If it is set, obtain all the Tab size related values ​​on the signal and compare them with the tab size related values ​​in the rule setting module. If they are not equal, mark the signal with the incorrect design size identifier and highlight it in red to remind the engineer when it is displayed later.

[0088] If they are equal, the quantity is accumulated and recorded as couti. Finally, the equivalent length of the signal is EQlengthi = lengthi + couti * k. The signal information is added to a new list newnetlist = {DDR group name, signal type 1, idi, signal network name, lengthi, couti, EQlengthi}. After the calculation is completed, couti = 0, and the calculation of the next group of signals continues.

[0089] Then, the processed data matching design rules are checked, specifically including:

[0090] Step 1: Obtain the signal type of newnetlist and the inspection rules set according to the signal type. If the requirements are met, the flag is set to 1.

[0091] Step 2: For clock differential signals, it is necessary to obtain the network names DP and DN and perform secondary grouping. The difference between the equivalent lengths is recorded as DP2DNvalue. It is compared with the set DP2DN threshold. If the condition is not met, the flag is set to 0.

[0092] Step 3: For signal types including DQS and DQ signals, not only must the DQS signals themselves meet the set rules, but the DQ and DQS signals must also meet fixed design rules. First, group the DQS signals as differential signals, subtract the equivalent lengths within each differential signal, and record the difference as DQS2DQSvalue. Compare this with the set DQS2DQS threshold. For signals that do not meet the rules, set a non-compliance flag (flag = 0). Then, sort the equivalent lengths of the DQS signal subgroups, take the largest DQS signal length as the target value, subtract it from the equivalent length of each DQ signal subgroup (recorded as DQ2DQSvalue), and compare this with the set DQ2DQS threshold. For signals that do not meet the rules, change the flag to 0.

[0093] Step 4: For groups with only DQ signals, sort the newnetlist in descending order of EQlength, take the signal with the smallest EQlength as the target signal, and repeat the operation on the newnetlist. Calculate the difference between the newnetlist and the target signal, and record it as DQ2DQvalue. Compare it with the DQ2DQ threshold set by the rule. Modify flag=0 for signals that do not meet the requirements.

[0094] Step 5: For groups of signals containing only control signals, the chip select signal CS needs to be selected. <0> Select the chip select signal CS as the target value. <0> The method involves retrieving signal groups of type CS from the `newnetlist`, and then using built-in functions to split each signal network name using "<" and ">", resulting in a list of two elements. For example, if the network name is "M_G_CPU1_SA_CS",... <0> After splitting the data using "<" and ">", a list {"M_G_CPU1_SA_CS" "0"} is obtained. The signal with the second element being 0 is the target signal for this DDR group. The newnetlist operation is iterated and the difference between the newnetlist operation and the target signal is calculated, denoted as ECC2ECCvalue. This value is then compared with the ECC2ECC threshold set by the rule. Signals that do not meet the threshold are modified with flag=0. In other words, the target signal within the control signal group is obtained by splitting the data using special symbols.

[0095] Step 6: The above results are recorded in the list resultlist = {DDR group name, signal ID, signal network name, signal length, number of signal setting tabs, signal equivalent length, DQS2DQSvalue, DP2DNvalue, DQ2DQSvalue, ECC2ECCvalue, flag}, where DQS2DQSvalue, DP2DNvalue, DQ2DQSvalue, and ECC2ECCvalue are recorded as "NA" if the DDR signal group is not involved.

[0096] Step 7: Set the DDR signal group to conform to the design rules, reorganize and generate a new DDR group DDRGrouplist1. If all signals in the group conform to the design rules, okflag = 1; otherwise, it is 0. DDRGrouplist1 = {DDR group name, okflag}.

[0097] Next, we will process the front-end display:

[0098] Since there are numerous DDR signals on the PCB board, displaying them all in a list would be cumbersome for PCB engineers. Therefore, during the initial loading of the front-end, a request is sent to the server backend to retrieve the DDR signal group DDRGrouplist1. This request is then processed by a built-in function on the page, highlighting data with the okflag flag equal to 0 in red. Engineers can select the DDR signal groups they wish to view and click the view button. The results display area then requests data from the backend for the selected signal groups from the results list. Upon receiving this request, the page identifies the flag, highlights those with a flag equal to 0 in red, and binds this to a built-in highlighting function. PCB engineers can then directly highlight these signals on the board during analysis.

[0099] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods according to the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk) and includes several instructions to cause a terminal device (which may be a mobile phone, computer, server, or network device, etc.) to execute the methods of the various embodiments of this application.

[0100] This embodiment also provides an apparatus for detecting the design quality of DDR signals. This apparatus is used to implement the above embodiments and preferred embodiments, and details already described will not be repeated. As used below, the term "module" can be a combination of software and / or hardware that implements a predetermined function. Although the apparatus described in the following embodiments is preferably implemented in software, hardware implementation, or a combination of software and hardware, is also possible and contemplated.

[0101] Figure 6 This is a structural block diagram of an apparatus for detecting the design quality of DDR signals according to an embodiment of this application, as shown below. Figure 6 As shown, the device includes:

[0102] Storage module 61 is used to store DDR signal design information in the information storage area. The DDR signal design information includes the equivalent length of various types of DDR signals, a first difference threshold of the equivalent length of different types of DDR signals, and a second difference threshold of the equivalent length of the same type of DDR signals.

[0103] Grouping module 62 is used to acquire and read DDR signal design drawings, group the DDR signal graphics in the design drawings, and obtain multiple groups of DDR signal graphics.

[0104] The processing module 63 is used to obtain the equivalent read length of each type of DDR signal for each group of DDR signal patterns, as well as the first read difference threshold of the equivalent read length of different types of DDR signals and the second read difference threshold of the equivalent read length of the same type of DDR signals. Based on the difference between the equivalent read length and the equivalent length, the difference between the first read difference threshold and the first difference threshold, and the difference between the second read difference threshold and the second difference threshold, the DDR signal design drawing meets the DDR signal design information.

[0105] The apparatus for detecting the design quality of DDR signals disclosed in this application comprises a storage module that stores DDR signal design information in an information storage area. This information includes the equivalent lengths of various types of DDR signals, a first difference threshold for the equivalent lengths of different types of DDR signals, and a second difference threshold for the equivalent lengths of DDR signals of the same type. A grouping module acquires and reads DDR signal design drawings, groups the DDR signal graphics in the design drawings, and obtains multiple groups of DDR signal graphics. For each group of DDR signal graphics, a processing module acquires the read equivalent lengths of each type of DDR signal, the first read difference threshold for the read equivalent lengths of different types of DDR signals, and the second read difference threshold for the read equivalent lengths of the same type of DDR signals. Based on the differences between the read equivalent lengths, the first read difference threshold, and the second read difference threshold, it determines whether the DDR signal design drawings meet the DDR signal design information. By pre-storing DDR signal design information and subsequently reading the drawings to obtain the actual design results, the apparatus determines whether the drawings meet the design rules, thus determining the design quality of the DDR signals. This eliminates the need for manual inspection by engineers, reduces the likelihood of omissions, and ensures design quality.

[0106] In this embodiment, the grouping module includes a first acquisition submodule and a grouping submodule. The first acquisition submodule is used to acquire the filenames of each DDR signal graphic in the design drawing, and the filenames are stored in the design document. The grouping submodule is used to group the DDR signal graphics according to the filenames to obtain multiple groups of DDR signal graphics. For example, DDR signal graphics whose filenames begin with the character 'A' are grouped together, DDR signal graphics whose filenames include the character 'B' as the first character are grouped together, and DDR signal graphics whose filenames include the character 'C' as the first character are grouped together. Grouping is achieved by reading the filenames.

[0107] In this embodiment, the first acquisition submodule includes a first generation submodule and a first reading submodule. The first generation submodule is used to generate a first built-in function; the first reading submodule is used to read the design document using the first built-in function to obtain the filenames of each DDR signal graphic in the design drawing. Specifically, obtaining the filenames of each DDR signal graphic in the design drawing includes: generating the first built-in function; and using the first built-in function to read the design document to obtain the filenames of each DDR signal graphic in the design drawing. The first built-in function is a character recognition function, that is, the filenames of each DDR signal graphic in the design drawing are obtained by calling the character recognition function.

[0108] In this embodiment, the processing module includes a second acquisition submodule, which is used to acquire the equivalent read length of various types of DDR signals. The second acquisition submodule includes a second generation submodule, a second reading submodule, a third reading submodule, and a first determination submodule. The second generation submodule is used to generate a second built-in function. The second reading submodule is used to read the DDR signal pattern using the second built-in function to obtain the physical signal length of the corresponding DDR signal. The third reading submodule is used to read the tab size-related values ​​in the DDR signal pattern, including the number of tabs and the equivalent length of a single tab. The first determination submodule is used to determine the equivalent read length of the DDR signal based on the physical signal length of the DDR signal and the tab size-related values ​​in the DDR signal pattern. Specifically, the equivalent read length of the DDR signal is obtained by multiplying the number of tabs by the equivalent length of a single tab and adding the physical signal length of the DDR signal. By determining the physical signal length of the DDR signal, as well as the number of tabs and the equivalent length of a single tab, the accurate determination of the equivalent read length of the DDR signal is achieved.

[0109] In this embodiment, the third reading submodule includes a second determining submodule and a third acquiring submodule. The second determining submodule is used to determine whether the DDR signal corresponding to the DDR signal pattern has a Tab attribute identifier, where the Tab attribute identifier indicates that a Tab has been set for the DDR signal. The third acquiring submodule is used to acquire the Tab size-related values ​​in the DDR signal pattern corresponding to the DDR signal when the DDR signal has a Tab attribute identifier. Since there are many DDR signals in a DDR hardware, a Tab attribute identifier is set to achieve fast and accurate determination of the equivalent length of the DDR signal with added Tab.

[0110] In this embodiment of the application, the processing module includes a second acquisition submodule, which is used to acquire the equivalent read length of each type of DDR signal for each group of DDR signal patterns. Specifically, the second acquisition submodule is used to perform the following steps:

[0111] For each group of DDR signal patterns, the DDR signal patterns belonging to that group are recorded in the list ddridlist = {id1, id2, id3 to idn};

[0112] The list ddridlist = {id1, id2, id3 to idn} is iterated, with the element variable itemi representing the i-th element in the list ddridlist. A third built-in function is used to obtain the chip pin connected to the DDR signal corresponding to the DDR signal pattern represented by the element variable itemi. The type of the corresponding DDR signal is determined according to the chip pin to obtain the list newgroup1. The list newgroup1 includes multiple (signal type midmidn), indicating that the type of the DDR signal corresponding to idm and idn is signal type m.

[0113] Loop through the idi in the list newgroup1, obtain the physical signal length lengthi of each DDR signal, and then obtain the read equivalent length EQlengthi = lengthi + couti × k of each DDR signal, where couti represents the number of tabs and k represents the equivalent length of a single tab.

[0114] The aforementioned device further includes a construction module, which is used to, after obtaining the equivalent read length of each type of DDR signal for each group of DDR signal patterns, consider the equivalent read length EQlengthi of each DDR signal and construct a list newnetlist = {DDR group name, signal type m, idi, signal network name, lengthi, couti, EQlengthi}, and after the list newnetlist of the group of DDR signal patterns is constructed, set Couti = 0 and proceed to process the next group of DDR signal patterns.

[0115] In this embodiment, the device further includes a first representation unit, a second representation unit, a third representation unit, and a fourth representation unit. The first representation unit is used to represent DDR signals that conform to DDR signal design information using a first identifier; the second representation unit is used to represent DDR signals that do not conform to DDR signal design information using a second identifier; the third representation unit is used to represent all DDR signals in a group that conform to DDR signal design information using a third identifier; and the fourth representation unit is used to represent at least one DDR signal in a group that does not conform to DDR signal design information using a fourth identifier. By setting identifiers, DDR signals that conform to DDR signal design requirements and DDR signals that do not conform to DDR signal design requirements are distinguished; groups of DDR signals that conform to DDR signal design requirements and groups of DDR signals that do not conform to DDR signal design requirements are distinguished; this facilitates the quick selection of DDR signals and groups of DDR signals that do not conform to DDR signal design requirements for subsequent modification.

[0116] In this embodiment, the device further includes a first display unit and a second display unit. The first display unit displays the DDR signal graphic corresponding to the DDR signal represented by the second identifier in a first display area using a first preset color. The second display unit displays the DDR signal graphic corresponding to the DDR signal group represented by the fourth identifier in a second display area using a second preset color. By displaying DDR signals and DDR signal groups that do not meet the DDR signal design requirements in the preset area, it is convenient for engineers to make modifications later.

[0117] In this embodiment, the device further includes a third display unit and a fourth display unit. The third display unit receives and responds to a first preset operation applied to a DDR signal graphic displayed in a first preset color, and binds a first highlight function. The first highlight function highlights the DDR signal graphic in the DDR signal design drawing. The fourth display unit receives and responds to a second preset operation applied to a DDR signal graphic displayed in a second preset color, and binds a second highlight function. The second highlight function highlights the DDR signal graphic in the DDR signal design drawing. As described above, in response to the operator's preset operation, the DDR signal to be modified is selected, linked through the highlight function, and the DDR signal graphic in the DDR signal design drawing is highlighted. This allows the operator to directly view DDR signals that do not meet design requirements in the DDR signal design drawing for modification.

[0118] It should be noted that the above modules can be implemented by software or hardware. For the latter, they can be implemented in the following ways, but are not limited to: all the above modules are located in the same processor; or, the above modules are located in different processors in any combination.

[0119] Embodiments of this application also provide a computer-readable storage medium storing a computer program, wherein the computer program is configured to execute the steps in any of the above method embodiments when run.

[0120] In one exemplary embodiment, the aforementioned computer-readable storage medium may include, but is not limited to, various media capable of storing computer programs, such as a USB flash drive, read-only memory (ROM), random access memory (RAM), portable hard disk, magnetic disk, or optical disk.

[0121] Embodiments of this application also provide an electronic device, including a memory and a processor, wherein the memory stores a computer program and the processor is configured to run the computer program to perform the steps in any of the above method embodiments.

[0122] In one exemplary embodiment, the electronic device may further include a transmission device and an input / output device, wherein the transmission device is connected to the processor and the input / output device is connected to the processor.

[0123] Specific examples in this embodiment can be found in the examples described in the above embodiments and exemplary implementations, and will not be repeated here.

[0124] Obviously, those skilled in the art should understand that the modules or steps of this application described above can be implemented using general-purpose computing devices. They can be centralized on a single computing device or distributed across a network of multiple computing devices. They can be implemented using computer-executable program code, and thus can be stored in a storage device for execution by a computing device. In some cases, the steps shown or described can be performed in a different order than those presented here, or they can be fabricated as separate integrated circuit modules, or multiple modules or steps can be fabricated as a single integrated circuit module. Thus, this application is not limited to any particular combination of hardware and software.

[0125] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the principles of this application should be included within the protection scope of this application.

Claims

1. A method for detecting the design quality of DDR signals, characterized in that, include: The DDR signal design information is stored in the information storage area. The DDR signal design information includes the equivalent length of various types of DDR signals, the first difference threshold of the equivalent length of different types of DDR signals, and the second difference threshold of the equivalent length of the same type of DDR signals. Acquire and read DDR signal design drawings, group the DDR signal graphics in the design drawings, and obtain multiple groups of the DDR signal graphics. For each group of DDR signal patterns, the equivalent read length of each type of DDR signal, a first read difference threshold for the equivalent read length of different types of DDR signals, and a second read difference threshold for the equivalent read length of the same type of DDR signals are obtained. Based on the difference between the equivalent read length and the equivalent length, the difference between the first read difference threshold and the first difference threshold, and the difference between the second read difference threshold and the second difference threshold, it is determined whether the DDR signal design drawing meets the DDR signal design information. The step of obtaining the equivalent read length of each type of DDR signal includes: generating a second built-in function; using the second built-in function to read the DDR signal pattern to obtain the physical signal length of the corresponding DDR signal; reading the tab size-related values ​​in the DDR signal pattern, the tab size-related values ​​including the number of tabs and the equivalent length of a single tab; and determining the equivalent read length of the DDR signal based on the physical signal length of the DDR signal and the tab size-related values ​​in the DDR signal pattern. The step of reading the Tab size-related values ​​in the DDR signal pattern includes: determining whether the DDR signal corresponding to the DDR signal pattern has a Tab attribute identifier, wherein the Tab attribute identifier indicates that a Tab is set for the DDR signal; and if the DDR signal has the Tab attribute identifier, obtaining the Tab size-related values ​​in the DDR signal pattern corresponding to the DDR signal. For each group of DDR signal patterns, obtain the equivalent read length of each type of DDR signal, including: For each group of DDR signal patterns, the DDR signal patterns belonging to that group are added to the list ddridlist={id1, id2, id3 to idn}. The list ddridlist={id1, id2, id3 to idn} is iterated, with the element variable itemi representing the i-th element in the list ddridlist. A third built-in function is used to obtain the chip pin connected to the DDR signal corresponding to the DDR signal pattern represented by the element variable itemi. The type of the corresponding DDR signal is determined according to the chip pin to obtain the list newgroup1. The list newgroup1 includes multiple {signal type m idmidn}, indicating that the type of the DDR signal corresponding to idm and idn is signal type m. The idi in the list newgroup1 is iterated, the physical signal length lengthi of each DDR signal is obtained, and then the read equivalent length EQlengthi=lengthi+couti×k of each DDR signal is obtained, where couti represents the number of tabs and k represents the equivalent length of a single tab.

2. The method according to claim 1, characterized in that, The process of acquiring and reading DDR signal design drawings involves grouping the DDR signal graphics in the design drawings to obtain multiple groups of DDR signal graphics, including: Obtain the filenames of each DDR signal graphic in the design drawings, and store the filenames in the design document; The DDR signal patterns are grouped according to the file names to obtain multiple groups of DDR signal patterns.

3. The method according to claim 2, characterized in that, The step of obtaining the filenames of each DDR signal graphic in the design drawing includes: Generate the first built-in function; The first built-in function is used to read the design document to obtain the filenames of each DDR signal graphic in the design drawing.

4. The method according to claim 1, characterized in that, After obtaining the equivalent read length of each type of DDR signal for each group of DDR signal patterns, the method further includes: Considering the equivalent length EQlengthi of each DDR signal, construct a list newnetlist={DDR group name, signal type m, idi, signal network name, lengthi, couti, EQlengthi}. After the list newnetlist of the DDR signal patterns for this group is constructed, set couti=0 and proceed to process the next group of DDR signal patterns.

5. The method according to claim 2, characterized in that, The method further includes: The first identifier is used to represent the DDR signal that conforms to the DDR signal design information; A second identifier is used to indicate a DDR signal that does not conform to the DDR signal design information; The third identifier indicates that all the DDR signals in a group conform to the DDR signal design information; The fourth identifier indicates that at least one of the DDR signals in a group does not conform to the DDR signal design information.

6. The method according to claim 5, characterized in that, The method further includes: The DDR signal graphic corresponding to the DDR signal represented by the second identifier is displayed in the first display area in a first preset color; The DDR signal graphic corresponding to the DDR signal group represented by the fourth identifier is displayed in the second display area in a second preset color.

7. The method according to claim 6, characterized in that, The method further includes: Receive and respond to a first preset operation applied to the DDR signal graphic displayed in the first preset color, and bind a first highlight function, the first highlight function being used to highlight the DDR signal graphic in the DDR signal design drawing; Receive and respond to a second preset operation applied to the DDR signal graphic displayed in the second preset color, and bind a second highlight function, the second highlight function being used to highlight the DDR signal graphic in the DDR signal design drawing.

8. A device for detecting the design quality of DDR signals, characterized in that, include: The storage module is used to store DDR signal design information in the information storage area. The DDR signal design information includes the equivalent length of various types of DDR signals, a first difference threshold of the equivalent length of different types of DDR signals, and a second difference threshold of the equivalent length of the same type of DDR signals. The grouping module is used to acquire and read DDR signal design drawings, group the DDR signal graphics in the design drawings, and obtain multiple groups of the DDR signal graphics. The processing module is used to obtain, for each group of DDR signal patterns, the equivalent read length of each type of DDR signal, a first read difference threshold for the equivalent read length of different types of DDR signals, and a second read difference threshold for the equivalent read length of the same type of DDR signals, and to determine whether the DDR signal design drawing meets the DDR signal design information based on the difference between the equivalent read length and the equivalent length, the difference between the first read difference threshold and the first difference threshold, and the difference between the second read difference threshold and the second difference threshold. The processing module includes a second acquisition submodule, which is used to acquire the equivalent read length of various types of DDR signals. The second acquisition submodule includes a second generation submodule, a second reading submodule, a third reading submodule, and a first determination submodule. The second generation submodule is used to generate a second built-in function. The second reading submodule is used to read the DDR signal pattern using the second built-in function to obtain the corresponding physical signal length of the DDR signal. The third reading submodule is used to read the tab size-related values ​​in the DDR signal pattern, where the tab size-related values ​​include the number of tabs and the equivalent length of a single tab. The first determination submodule is used to determine the equivalent read length of the DDR signal based on the physical signal length of the DDR signal and the tab size-related values ​​in the DDR signal pattern. The third reading submodule includes a second determining submodule and a third acquiring submodule. The second determining submodule is used to determine whether the DDR signal corresponding to the DDR signal graphic has a Tab attribute identifier, and the Tab attribute identifier indicates that a Tab is set for the DDR signal. The third acquiring submodule is used to acquire the Tab size-related value in the DDR signal graphic corresponding to the DDR signal when the DDR signal has the Tab attribute identifier. The second acquisition submodule is used to perform the following steps: For each group of DDR signal patterns, the DDR signal patterns belonging to that group are counted in the list ddridlist={id1, id2, id3 to idn}; the list ddridlist={id1, id2, id3 to idn} is iteratively processed, with the element variable itemi representing the i-th element in the list ddridlist, and the third built-in function is used to obtain the chip pin connected to the DDR signal corresponding to the DDR signal pattern represented by the element variable itemi, and the type of the corresponding DDR signal is determined according to the chip pin to obtain the list newgroup1, the list newgroup1 including multiple {signal type m idm idn}, indicating that the type of the DDR signal corresponding to idm and idn is signal type m; the idi in the list newgroup1 is iteratively obtained, the physical signal length lengthi of each DDR signal is obtained, and then the equivalent reading length EQlengthi=lengthi+couti×k of each DDR signal is obtained, where couti represents the number of tabs and k represents the equivalent length of a single tab.

9. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program, wherein the computer program, when executed by a processor, implements the steps of the method described in any one of claims 1 to 7.

10. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, When the processor executes the computer program, it implements the steps of the method described in any one of claims 1 to 7.

Images