Display driving device and data transmission method thereof

Abstract

The present disclosure relates to a display driving apparatus and a data transmission method thereof, which respectively transmit to a plurality of display driver ICs by using a MIPI interface of a point-to-multipoint (Multi-drop) method. The method according to an embodiment of the present disclosure can include a step of acquiring display data and command data, a step of respectively transmitting the display data and the command data to a plurality of display driver ICs by using a MIPI interface of a point-to-multipoint (Multi-drop) method, and a step of independently controlling sub-pixels corresponding to each of the plurality of display driver ICs based on the display data and the command data.

Description

Technical Field

[0001] This invention relates to a display device and a data transmission method thereof. Background Technology

[0002] With the development of the information society, the demand for display devices for displaying images is increasing in various forms, and various types of display devices such as liquid crystal displays and organic light-emitting diode displays are being adopted.

[0003] Furthermore, a display device capable of performing touch-based input processing is provided, taking into account user convenience and device characteristics. This touch-based input processing capability is applicable not only to portable terminals such as smart terminals, but also to various electronic instruments such as laptops, monitors, and home appliances.

[0004] In existing display devices based on current technology, the interface of the monochrome backplane uses Serial Peripheral Interface (SPI) or Quad Serial Peripheral Interface (QSPI) to drive the display. However, this has the following problems: due to the limitations of SPI and QSPI in data transmission speed, the maximum speed can only be achieved in the tens of Mbps range, and display devices driven in this way are driven with low resolution and low frame rate.

[0005] To drive display devices with high resolution and high frame rate, speeds of hundreds of Mbps to several Gbps are required. However, existing display devices using technologies such as SPI and QSPI cannot achieve speeds of hundreds of Mbps to several Gbps.

[0006] The above background technology refers to technical information held by the inventors in order to derive the present invention or obtained in the process of deriving the present invention. It cannot be said to be publicly known technology that must have been disclosed to the general public before the application of this invention.

[0007] Existing technical documents

[0008] Patent documents

[0009] (Patent Document 1) Korean Patent Registration No. 10-2189928 (December 4, 2020) Summary of the Invention

[0010] The technical problem to be solved by the present invention

[0011] The purpose of this invention is to provide a display driver device and its data transmission method that uses a point-to-multipoint (multi-drop) Mobile Industry Processor Interface (MIPI) to transmit data to multiple display driver ICs respectively.

[0012] The problems to be solved by this invention are not limited to those described above. Other problems and advantages of this invention not mentioned can be understood through the following description and will become clearer through embodiments of this invention. Furthermore, it is understood that the problems and advantages to be solved by this invention can be achieved through the means and combinations shown within the scope of the claims.

[0013] Technical solution

[0014] As a technical means to solve the above-mentioned technical problems, the first aspect of this disclosure can provide a data transmission method for a display driver device, comprising: the steps of acquiring display data and command data; the steps of transmitting the display data and the command data to a plurality of display driver ICs respectively using a point-to-multipoint (multi-drop) MIPI interface; and the steps of independently controlling sub-pixels corresponding to each of the plurality of display driver ICs based on the display data and the command data.

[0015] A second aspect of this disclosure provides a display driving device comprising: a plurality of display driving ICs that independently control each of a plurality of sub-pixels based on display data and instruction data, wherein the plurality of display driving ICs receive the display data and the instruction data through a multi-point MIPI interface.

[0016] In addition, other methods, other systems for implementing the present invention, and computer-readable recording media storing computer programs for performing said methods may also be provided.

[0017] Other aspects, features, and advantages, besides those described above, will become clear from the following drawings, the scope of the claims, and the detailed description of the invention.

[0018] Beneficial effects

[0019] According to the above-mentioned problem-solving methods of this disclosure, display data and command data can be acquired, and the display data and command data can be transmitted to multiple display driver ICs respectively by using a point-to-multipoint (multi-drop) MIPI interface. Based on the display data and command data, the sub-pixels corresponding to each of the multiple display driver ICs can be independently controlled, thereby driving the display with high resolution and high frame rate. Attached Figure Description

[0020] Figure 1a This is a block diagram illustrating an example of a data processing system according to one embodiment.

[0021] Figure 1b This is a block diagram illustrating another example of a data processing system according to one embodiment.

[0022] Figure 2 This is a block diagram illustrating an example of a display driving device according to an embodiment.

[0023] Figure 3 This is a flowchart illustrating an example of a data transmission method of a display driving device according to an embodiment.

[0024] Figure 4 This is a block diagram illustrating an example of a data transmission method for a conventional display driver.

[0025] Figure 5a This is a block diagram illustrating an example of a data transmission method of a display driving device according to an embodiment.

[0026] Figure 5b This is a block diagram illustrating another example of a data transmission method of a display driving device according to one embodiment.

[0027] Figure 6 This is a block diagram illustrating an example of the transmission mode and receiving mode of a display driving device according to an embodiment.

[0028] Figure 7 This is a block diagram illustrating an example of the TX mode of a display driver according to an embodiment.

[0029] Figure 8 This is a block diagram illustrating another example of the TX mode of a display driver according to one embodiment.

[0030] Figure 9 This is a block diagram illustrating an example of the RX mode of a display driver according to an embodiment. Specific Implementation

[0032] The various embodiments of this disclosure will now be described in conjunction with the accompanying drawings. These various embodiments can be varied and implemented in many ways, with specific embodiments illustrated in the drawings and related detailed descriptions. However, it should be understood that this is not intended to limit the various embodiments of this disclosure to specific implementations, but rather to include all modifications and / or equivalents to substitutions within the spirit and technical scope of the various embodiments of this disclosure. Similar reference numerals are used for similar constituent elements in relation to the drawings.

[0033] The expressions "comprising" or "may include," as used in the various embodiments of this disclosure, refer to the presence of the corresponding function, operation, or constituent element in this disclosure, and do not limit the addition of more than one function, operation, or constituent element. Furthermore, it should be understood that in the various embodiments of this disclosure, terms such as "comprising" or "having" are used to indicate the presence of the features, numbers, steps, operations, constituent elements, components, or combinations thereof described in the specification, and do not preclude the existence or additional possibility of more than one other feature or number, step, operation, constituent element, component, or combination thereof.

[0034] In various embodiments of this disclosure, expressions such as "or" include any and all combinations of the words listed together. For example, "A or B" may include A, may include B, or may include both A and B.

[0035] The terms "first," "second," "firstly," and "secondarily," as used in the various embodiments of this disclosure, may modify multiple constituent elements in various embodiments but do not limit these constituent elements. For example, the expressions do not limit the order and / or importance of the corresponding multiple constituent elements. The expressions can be used to distinguish one constituent element from another. For example, a first user equipment and a second user equipment are both user equipment, representing different user equipment. For example, without departing from the scope of the various embodiments of this disclosure, a first constituent element may be referred to as a second constituent element, and similarly, a second constituent element may also be referred to as a first constituent element.

[0036] When a component is described as "connected" or "coupled" to another component, it means that the component is directly connected or coupled to the other component, but it can also be understood as meaning that there are other new components between the two components. Conversely, when a component is described as "directly connected" or "directly coupled" to another component, it can be understood as meaning that there are no other new components between the two components.

[0037] In embodiments of this disclosure, terms such as "module," "unit," and "part" are used to refer to constituent elements that perform at least one function or operation, which can be implemented as hardware, software, or a combination of hardware and software. Furthermore, multiple "modules," "units," and "parts," in addition to being implemented as individual specific hardware, can be integrated into at least one processor by integrating at least one module or chip.

[0038] The terminology used in the various embodiments of this disclosure is for illustrative purposes only and is not intended to limit the scope of the various embodiments of this disclosure. Unless the context clearly distinguishes them, singular expressions include plural expressions.

[0039] Some embodiments of this disclosure can be represented as a plurality of functional blocks and various processing steps. Some or all of these multiple functional blocks can be implemented as various numbers of hardware and / or software configurations performing multiple specific functions. For example, the multiple functional blocks of this disclosure can be implemented by more than one microprocessor, or by a circuit configuration for a specified function. Furthermore, for example, the multiple functional blocks of this disclosure can be implemented as various programming or scripting languages. The multiple functional blocks can be implemented as an algorithm executed in more than one processor. Furthermore, this disclosure can employ existing technologies for electronic environment setting, signal processing, and / or data processing, etc. Terms such as "mechanism," "element," "method," and "configuration" can be used broadly and are not limited to mechanical and physical configurations.

[0040] Furthermore, the connecting lines or connecting members between the constituent elements shown in the accompanying drawings are merely examples of functional connections and / or physical or electrical connections. In actual devices, the connections between constituent elements can be represented by various functional connections, physical connections, or electrical connections that can be substituted or added.

[0041] Unless otherwise defined, all terms used herein, including technical or scientific terms, shall have the same meaning as commonly understood by one of ordinary skill in the art to which the various embodiments of this disclosure pertain.

[0042] Terms such as those defined in commonly used dictionaries should be interpreted as having the same meaning as the relevant art in the context, and should not be interpreted as having an ideal or overly formal meaning unless explicitly defined in the various embodiments of this disclosure.

[0043] Various embodiments of the present invention will be described in detail below using the accompanying drawings.

[0044] Figure 1a This is a block diagram illustrating an example of a data processing system according to one embodiment.

[0045] Reference Figure 1a The data processing system 100 includes a host 200, an external memory 262, a camera 272, a display driver IC 300, and a display panel 400. In this specification, the combination of the display driver IC 300 and the display panel 400 is collectively referred to as a display driver device.

[0046] The data processing system 100 refers to a system that can process video streams (e.g., static display data or dynamic display data) and display the processed video streams (or display data) on the display panel 30.

[0047] The data processing system 100 can be implemented as a smartphone, tablet PC, digital camera, camcorder, personal digital assistant (PDA), portable multimedia player (PMP), mobile internet device (MID), or wearable computer, but is not limited to these.

[0048] The host 200 can support a video stream interface. Supporting a video stream interface means that the host 200 is configured to support the video stream interface in hardware, or that the host 200 supports the video stream interface in hardware through its firmware (or software). For example, when the host 200 only supports Mobile Industry Processor Interface (MIPI) video mode, the data processing system 100 can support the video stream interface. As another example, when the host 200 can support both MIPI video mode and MIPI command mode, if the host 200 is configured to only support MIPI video mode through firmware (or software), then the data processing system 100 can support the video stream interface.

[0049] On the other hand, the host 200 can control the display driver IC 300.

[0050] The host 200 can be implemented as a system on chip (SoC), an application processor (AP), or a mobile application processor.

[0051] The host 200 includes a bus 201, a central processing unit 210, an image type detector 220, an image processing circuit 230, an interrupt detector 240, a transmission interface 250, a storage controller 260, and a camera interface 270.

[0052] CPU210 can control each component (220, 230, 240, 250, 260 and / or 270) via bus 201.

[0053] CPU 210 can execute firmware (or software) that configures host 200 to support video streaming interfaces. The firmware can be loaded into host 200 from external storage 262. As an example, CPU 210 may include more than one core.

[0054] The image type detector 220 can determine whether the image data to be transmitted to the display driver IC 300 is still image data or moving image data, and control the transmission of the image data (or "display data") based on the determination result. That is, the image type detector 220 can determine whether to transmit the image data to the image processing circuit 230.

[0055] As an example, when the image data output from the external memory 262 or the camera 272 is still image data, the image type detector 220 can transmit the image data to the image processing circuit 230.

[0056] As another example, when the corresponding image data output from the external memory 262 or the camera 272 is dynamic image data, the image type detector 220 can transmit the corresponding image data to the image processing circuit 230.

[0057] Therefore, since the image type detector 220 can send only the image data that needs to be transmitted to the display driver IC 300 (or the image data that needs to be updated in the display panel 400) to the image processing circuit 230, the image type detector 220 has the effect of preventing the transmission of unnecessary image data.

[0058] Although Figure 3An embodiment is shown in which the image type detector 220 is configured between the bus 201 and the image processing circuit 230. However, according to the embodiment, the image processing circuit 230 may also be configured between the bus and the image type detector 220.

[0059] Image processing circuit 230 can convert image data output from image type detector 220 into a format that can be processed by transmission interface 250.

[0060] Interrupt detector 240 can detect the interrupt instruction INT output from display driver IC 300 and generate a detection signal. The detection signal may be the same as or different from the interrupt instruction INT, but since the detection signal is related to the interrupt instruction INT, both the detection signal and the interrupt signal are represented by "INT" in this specification and are collectively referred to as the interrupt instruction.

[0061] As an example, the transmitting interface 250 can perform functions that support a video streaming interface. The transmitting interface 250 converts the image data output from the image processing circuit 230 into a video stream DPAC, and adjusts the transmission timing of the video stream DPAC based on the interrupt instruction INT.

[0062] At this time, the video stream DPAC can include multiple synchronization signals and data. The multiple synchronization signals can represent multiple signals related to the vertical synchronization signal, horizontal synchronization signal, and data enable signal to be recovered in the display driver IC 300.

[0063] Therefore, the interrupt instruction INT can perform the function of a control signal, which controls the transmission timing of the video stream DPAC to be transmitted to the display driver IC300.

[0064] As an example, when the data processing system 100 supports MIPI, the interrupt instruction INT can be a TE signal that can prevent the tearing effect (TE).

[0065] As another example, when the data processing system 100 supports an embedded display port (eDP), the interrupt instruction INT can represent a control signal that can be output from the display driver IC 300 and control the transmission timing of the video stream DPAC.

[0066] The transmit interface 250 can support MIPI, eDP or high-speed serial interface.

[0067] The storage controller 260 can interface with the host 200 and the external memory 262 to exchange image data. For example, under the control of the storage controller 260, image data output from the host 200 can be stored in the external memory 262, and image data output from the external memory 262 can be transmitted to the bus 201.

[0068] External storage 262 may be dynamic random access memory (DRAM), solid state drive (SSD), multimedia card (MMC), embedded multimedia card (eMMC), USB flash drive, or universal flash storage (UFS).

[0069] Figure 1a The external memory 262 shown can represent a collection of memories of different types. Therefore, external memory 262 can collectively represent DRAM and eMMC. As an example, an operating system can be loaded from the eMMC and executed from the DRAM. When external memory 262 represents a collection of multiple memories, memory controller 260 can represent a collection of multiple memory controllers capable of controlling multiple memories of different types.

[0070] The camera interface 270 can transmit image data output from the camera 272 to the bus 201. For example, the camera 272 can be implemented as a complementary metal-oxide-semiconductor (CMOS) image sensor.

[0071] The host 200 may also include one or more wireless interfaces that can communicate wirelessly with other devices. Therefore, the host 200 can receive image data wirelessly via one or more wireless interfaces, such as Wi-Fi, wireless networks, or Long Term Evolution (LTE).

[0072] In addition, the data processing system 100 can also support camera 2.0.

[0073] As described above, whenever it is necessary to transmit the video stream DPAC to the display driver IC 300, the host 200, which is configured to support the video stream interface, can transmit the video stream DPAC to the display driver IC 300 through the video stream interface according to the interrupt instruction INT output from the display driver IC 300.

[0074] The host 200 and the display driver IC 300 can be interconnected via a first transmission line (or channel) for transmitting the video stream DPAC and a second transmission line (or channel) for transmitting the clock CLKm. For example, the video stream DPAC can be transmitted synchronously with the clock CLKm. The video stream DPAC and the clock CLKm can each represent multiple differential signals.

[0075] The display driver IC 300 includes a receiver interface 310, a data controller 320, a timing controller 340, and an oscillator 350.

[0076] The receiving interface 310 can receive the video stream DPAC and clock CLKm output from the host 200. As an example, the receiving interface 310 can use the clock CLKm to recover data DATA, which can bypass the data controller 320. That is, data DATA and clock CLKm are transmitted to the data controller 320. In this invention, the vertical synchronization signal Vsync and the horizontal synchronization signal Hsync may not be used to process data DATA. As another example, the receiving interface 310 can use the clock CLKm to recover the vertical synchronization signal Vsync, the horizontal synchronization signal Hsync, the data enable signal DE, and data DATA from the video stream DPAC, which can bypass the data controller 320, but is not limited to this. In this case, the data enable signal DE serves as an indication signal for valid data; when the data enable signal DE is activated, the data is valid; when the data enable signal DE is deactivated, the data is invalid.

[0077] On the other hand, the data controller 320 uses the clock CLK to generate a data enable signal DE′, and transmits the data enable signal DE′ and the data DATA to the timing controller 340. The data enable signal DE′ can perform the function of an indicator signal used to indicate the valid range of the data DATA.

[0078] Oscillator 350 generates an internal clock fosc. Timing controller 340 can generate multiple control signals (e.g., CLK, iVsync, and iHsync) based on the internal clock fosc.

[0079] The timing controller 340 includes an interrupt instruction generator 341, a control signal generator 343, and an image processing module 345.

[0080] Interrupt instruction generator 341 periodically generates interrupt instructions INT based on the internal clock fosc. For example, the frequency of interrupt instruction INT can be 60 Bps. When the data processing system 100 supports MIPI, interrupt instruction generator 341 can function as a TE signal generator to generate TE signals, acting as the interrupt instruction INT.

[0081] As an example, the control signal generator 343 can generate a clock CLK based on the internal clock fosc. The clock CLK can be generated using the internal clock fosc, and the frequency of the clock CLK can be the same as or different from the frequency of the internal clock fosc.

[0082] As another example, the control signal generator 343 can further generate an internal vertical synchronization signal iVsync and an internal horizontal synchronization signal iHsync based on the internal clock fosc. The internal vertical synchronization signal iVsync can be a vertical synchronization signal related to the display of display data DDATA, and the internal horizontal synchronization signal iHsync can be a horizontal synchronization signal related to the display of display data DDATA.

[0083] The image processing module 345 can receive clock CLK, data enable signal DE′ and data DATA, and use clock CLK and data enable signal DE′ to process and read data DATA. As a result of the processing, it can generate data enable signal DDE and display data DDATA.

[0084] The data enable signal DDE can function as an indicator signal to indicate the valid range of the displayed data DDATA.

[0085] For example, the image processing module 345 can perform image enhancement and / or image editing functions. For example, the image processing module 345 can adjust the brightness, contrast, saturation, or sharpness of the data DATA, and generate display data DDATA corresponding to the adjustment results.

[0086] The line buffer 360 or shift register can receive the data enable signal DDE and the display data DDATA, and transmit the corresponding signals to the display panel 400.

[0087] For example, the line buffer 360 can write analog signals corresponding to the display data DDATA, and scan the written signals to transmit them to multiple data lines configured on the display panel 400.

[0088] Specifically, the line buffer 360 can write data DDATA in response to the clock CLK and the periodically activated data enable signal DDE. More specifically, the line buffer 360 can write data DDATA when the data enable signal DDE is activated or enabled.

[0089] As an example, the line buffer 360 can perform a scan operation in response to the internal vertical synchronization signal iVsync and the internal horizontal synchronization signal iHsync. The scan operation refers to the operation of the line buffer 360 reading data DATA and transmitting the read data DATA to the display panel 400.

[0090] The line buffer 360 can be written with data DDATA. Specifically, the line buffer 360 can be written with data DATA whenever the data enable signal DDE is activated.

[0091] The display panel 400 can be a Memory Inside Pixel (MIP) panel. That is, the multiple pixels included in the display panel 400 can each include memory within themselves.

[0092] At this time, the line buffer 360 can respond to the internal horizontal synchronization signal iHsync, scan the stored data DATA and transmit it to the display panel 400. Specifically, whenever the internal horizontal synchronization signal iHsync is deactivated, the line buffer 360 can read and scan the written data and transmit it to the display panel 400, and the display panel 400 writes the data into the memory within the pixel.

[0093] Display panel 400 can read and display data DATA stored in the memory within the pixels in response to the internal horizontal synchronization signal iHsync. Specifically, whenever the internal horizontal synchronization signal iHsync is activated, display panel 400 can display the written data.

[0094] The display panel 400 can display images using m-bit digital image signals capable of displaying 1 to 2m grayscale. The display panel 400 may include multiple pixels PX arranged in a prescribed pattern, such as a matrix, zigzag, or other patterns. Each pixel PX can emit a single color, such as red, blue, green, or white. Pixel PX can also emit colors other than red, blue, green, and white.

[0095] A pixel (PX) may include a light-emitting element. The light-emitting element may be a self-emissive element. For example, the light-emitting element may be a light-emitting diode (LED). The light-emitting element may be a light-emitting diode (LED) with a micrometer to nanometer unit size. The light-emitting element may emit a single peak wavelength or multiple peak wavelengths.

[0096] The pixel (PX) may also include pixel circuitry connected to the light-emitting element. The pixel circuitry may include at least one thin-film transistor and at least one capacitor, etc. The pixel circuitry may be implemented using a semiconductor stack-up structure on a substrate.

[0097] A pixel (PX) can be operated on a frame-by-frame basis. A frame can consist of multiple subframes. Each subframe can include a data writing period and an illumination period. During the data writing period, a specified number of bits of digital data can be stored in the memory included in the pixel (PX). During the illumination period, the specified number of bits of digital data stored is read synchronously with a clock signal, and the digital data is converted into a PWM signal, enabling the pixel (PX) to display grayscale. The illumination period of a subframe can be the sum of the time allocated to each bit of digital data.

[0098] However, the display panel 400 of the present invention is not limited thereto and can be implemented in various ways, such as a thin-film transistor liquid-crystal display (TFT-LCD), a light-emitting diode (LED) display, an organic light-emitting diode (OLED) display, an active-matrix organic light-emitting diode (AMOLED) display, or a flexible display, etc.

[0099] Figure 1b This is a block diagram illustrating another example of a data processing system according to one embodiment.

[0100] Figure 1b The data processing system 1 refers to a system that processes display data and command data, and displays the processed display data and command data on the display panel 30.

[0101] Host 10 includes a transmission interface 11. For ease of explanation, Figure 1b The diagram shows host 10 including a transmit interface 11, but it is not limited thereto. As an example, host 10 may include interfaces not present in... Figure 1b The diagram shows the bus, CPU, image type detector, image processing circuit, interrupt detector, storage controller, and camera interface.

[0102] on the other hand, Figure 1b The host 10, transmit interface 11 and bus (not shown), CPU, image type detector, image processing circuit, interrupt detector, storage controller and camera interface are connected to Figure 1aThe host 200, bus 201, CPU (central processing unit) 210, image type detector 220, image processing circuit 230, interrupt detector 240, transmit interface 250, storage controller 260 and camera interface 270 correspond to each other, so repeated descriptions are omitted.

[0103] The host 10 includes a transmit interface 11, and the display driver IC 20 includes a receive interface 21. The host 10 and the display driver IC 20 are connected via a high-speed data interface. The host 10 transmits data through the transmit interface 11, and the display driver IC 20 receives data through the receive interface 21. The data may include display data and / or command data.

[0104] High-speed data interfaces can use MIPI (Mobile Industry Processor Interface). MIPI, as a serial interface specification for connecting processors and peripheral devices, is a standard developed by the MIPI Alliance. For example, MIPI D-PHY is a high-speed digital serial interface, and MIPI D-PHY DSI (Display Serial Interface) corresponds to the display protocol standard specification (spec) based on D-PHY.

[0105] The display driver IC 20 includes a receiver interface 21 and a logic controller 22. For ease of explanation, in... Figure 1b The diagram shows a display driver IC 20 including a receiver interface 21 and a logic controller 22, but it is not limited thereto. As an example, the display driver IC 20 may include components not shown in the diagram. Figure 1b The data controller, timing controller, and oscillator are shown in the figure.

[0106] on the other hand, Figure 1b The display driver IC 20, receiver interface 21, data controller (not shown), timing controller, and oscillator are shown. Figure 1a The display driver IC 300, receiver interface 310, data controller 320, timing controller 340 and oscillator 350 correspond to each other, so repeated descriptions are omitted.

[0107] The logic controller 22 outputs a control signal corresponding to the displayed data, and outputs a signal that drives one or more sub-pixels in the display panel connected to the logic controller in response to the control signal.

[0108] On the other hand, the logic controller 22 may include a data controller, a timing controller, and an oscillator. The operation of the data controller, timing controller, and oscillator described below can also be implemented by a single device (e.g., the logic controller 22).

[0109] Figure 2 This is a block diagram illustrating another example of a display driving device according to one embodiment.

[0110] Reference Figure 2 According to one embodiment, the display device 101 may include a display panel 30, a scanning drive circuit 130, a data drive circuit 140, and a control unit 150. The display panel 30 has a... Figure 1b The display panel 30 has the same configuration, so repeated descriptions are omitted. On the other hand, Figure 1b The logic controller 22 may include a scan drive circuit 130, a data drive circuit 140, and a control unit 150, and the operation of the scan drive circuit 130, the data drive circuit 140, and the control unit 150 described below may also be implemented by a single device (e.g., the logic controller 22).

[0111] The display panel 30 may include multiple pixels. These pixels can be arranged in a matrix of m x n (where m and n are natural numbers). However, the pattern of the multiple pixels can be arranged in various patterns, such as a zigzag pattern, according to other embodiments.

[0112] Each pixel may include more than one light-emitting element. The light-emitting element may be a light-emitting diode (LED). The LED may be a micro LED with a size of less than 80µm. A pixel can output various colors through multiple light-emitting elements having different colors from each other. For example, a pixel may include light-emitting elements composed of red, green, and blue. As another example, if a white light-emitting element can be further included, it can replace any one of the red, green, or blue light-emitting elements. In embodiments that include multiple light-emitting elements in a pixel, each light-emitting element included in a pixel may be referred to as a "subpixel (SP)". For example, a subpixel may include subpixel R, subpixel G, and subpixel B.

[0113] Each subpixel (SP) 31 can store data related to the brightness, or gradation, of the color to be output during an image frame.

[0114] Each pixel may include a pixel driving circuit for driving the light-emitting element included in the pixel, i.e., driving the sub-pixel SP. The pixel driving circuit can drive the sub-pixel to turn on or off by signals output from the scan driving circuit 130 and / or the data driving circuit 140. As an example, the pixel driving circuit may include at least one transistor, at least one capacitor, etc. The pixel driving circuit is connected by implementing it on a semiconductor crystal and forming a light-emitting element and a stacked structure, or by arranging it on the side of the light-emitting element, thereby controlling the light emission of the light-emitting element.

[0115] The display panel 30 can be implemented as one of the following: LCD (liquid crystal display), LED (light emitting diode) display, micro LED (micro LED) display, OLED (organic LED) display, active-matrix organic light-emitting diode (AMOLED) display, electrochromic display device (ECD) display, digital micromirror device (DMD), actuated mirror device (AMD), grating light valve (GLV), plasma display panel (PDP), electroluminescent display (ELD), and vacuum fluorescent display (VFD). In addition, it can be implemented as other types of flat panel displays or flexible displays.

[0116] On the other hand, the display panel 111 may include one or more scan lines (SL1~SLm) arranged along a first direction and one or more data lines (DL1~DLn) arranged along a second direction. Here, the first direction refers to either a row direction or a column direction, and the second direction refers to either a column direction or a row direction. For example, the first direction may be a row direction, and the second direction may be a column direction. For another example, the first direction may be a column direction, and the second direction may be a row direction.

[0117] On the other hand, sub-pixels SP can be located at the intersection of one or more scan lines (SL1~SLm) and one or more data lines (DL1~DLn). Each sub-pixel SP can be connected to any scan line SLk and any data line DLk. One or more scan lines (SL1~SLm) can be connected to the scan drive circuit 130, and one or more data lines (DL1~DLn) can be connected to the data drive circuit 140.

[0118] The scan driving circuit 130 can output a signal (hereinafter referred to as the first signal) for driving one or more sub-pixels SP connected to any one of the more than one scan lines (SL1~SLm). Preferably, the scan driving circuit 130 can sequentially select one or more scan lines (SL1~SLm). As an example, during the first scan driving period, the sub-pixel SP connected to the first scan line (SL1) can be driven, and during the second scan driving period, the sub-pixel SP connected to the second scan line SL2 can be driven.

[0119] The data driving circuit 140 can output a grayscale-related signal (hereinafter referred to as the second signal) to each sub-pixel SP through one or more data lines (DL1~DLn). For example, Figure 2 As shown, a data line can be connected to more than one sub-pixel SP in the vertical direction, but grayscale-related signals can only be input to multiple sub-pixels SP connected to the scan line selected by the scan drive circuit 130.

[0120] The control unit 150 can output control signals to execute the operations of the scan drive circuit 130 and the data drive circuit 140. The control unit 150 can output control signals corresponding to display data equivalent to an image frame to the scan drive circuit 130 or the data drive circuit 140. The control unit 150 can determine the pulse width modulation (PWM) duty cycle (PWM ON DUTY) representing the light-emitting time interval of the LED within a frame interval. On the other hand, the scan drive circuit 130 and the data drive circuit 140, in order to execute various control logics, can include processors, application-specific integrated circuits (ASICs), other chipsets, logic circuits, registers, communication modems, data processing devices, etc., known in the art to which this invention pertains. Furthermore, when the control logic is implemented as software, the scan drive circuit 130 and the data drive circuit 140 can be implemented as a collection of program modules. In this case, the program modules can be stored in a memory device and executed by a processor.

[0121] In order for a computer to read and execute a program implemented as a program, the program may include code encoded in computer languages ​​such as C / C++, C#, JAVA, Python, and machine language, which can be read by the computer's processor (CPU) through the computer's device interface. This code may include functional code related to functions that define the necessary functions for executing these methods, and control code related to the execution steps required by the computer processor to perform multiple functions according to prescribed steps. Furthermore, this code may also include additional information required by the computer processor to perform multiple functions, and memory reference code indicating the location (address) of media in the computer's internal or external memory. Additionally, when the computer processor needs to communicate with a remote computer or server to perform multiple functions, the code may also include communication-related code regarding how to use the computer's communication module to communicate with the remote computer or server, and which information or media needs to be sent and received during communication.

[0122] Storage media containing programs refer to media that store data semi-permanently and can be read by a device, rather than media that store data for short periods, such as registers or cache memory. Specifically, examples of storage media include, but are not limited to, ROM, RAM, CD-ROM, magnetic tape, floppy disks, and optical data storage devices. That is, programs can be stored on various recording media on various servers accessible to a computer or on various recording media on a user's computer. Furthermore, storage media can be distributed across computer systems connected via a network, and computer-readable code can be stored in a distributed manner.

[0123] Figure 3 This is a flowchart illustrating an example of a data transmission method of a display driving device according to an embodiment.

[0124] Reference Figure 3 According to one embodiment, the display driver device can acquire display data and instruction data, and transmit the display data and instruction data to multiple display driver ICs respectively by using a point-to-multipoint (Multi-drop) MIPI interface, and transmit data by independently controlling the sub-pixels corresponding to each of the multiple display driver ICs based on the display data and instruction data.

[0125] In step 3101, display data and instruction data are acquired. As one example, the host can acquire display data and instruction data. As another example, the host can acquire display data and instruction data by generating them. As yet another example, the host can acquire display data and instruction data by receiving them from an external device (not shown), but is not limited to these methods.

[0126] In step 3202, display data and instruction data are transmitted separately to multiple display driver ICs using a point-to-multipoint (multi-drop) MIPI interface. For example, the host can transmit display data and instruction data to multiple display driver ICs via a single wire using the MIPI interface.

[0127] Reference Figure 4 , 5a Section 5b describes the data transmission method of the display driver.

[0128] Figure 4 This is a block diagram illustrating an example of a data transmission method for a conventional display driver.

[0129] Reference Figure 4 Data is transmitted from the transmit interface 11 within the host 10 to the first display driver IC 2010, the second display driver IC 2020, and the third display driver IC 2030 via multiple lines. Furthermore, based on the response request from the host 10, each of the first receive interface 2110 of the first display driver IC 2010, the second receive interface 2120 of the second display driver IC 2020, and the third receive interface 2130 of the third display driver IC 2030 responds by transmitting response data to the host 10.

[0130] Response data may include, but is not limited to, instruction data transmitted by the host.

[0131] In conventional display driver devices, an SPI or QSPI interface is used to transmit data to each of multiple display driver ICs via multiple lines. The first display driver IC 2010 corresponds to sub-pixel R, the second display driver IC 2020 corresponds to sub-pixel G, and the third display driver IC 2030 corresponds to sub-pixel B. Sub-pixels R, G, and B are included within a sub-pixel. Specifically, data corresponding to sub-pixel R is transmitted from the transmit interface 11 within the host 10 to the first receive interface 2110 within the first display driver IC 2010 via the first line 1201; data corresponding to sub-pixel G is transmitted from the transmit interface 11 within the host 10 to the second receive interface 2120 within the second display driver IC 2020 via the second line 1202; and data corresponding to sub-pixel B is transmitted from the transmit interface 11 within the host 10 to the third receive interface 2130 within the third display driver IC 2030 via the third line 1203. The host 10 transmits data corresponding to sub-pixel R to the first display driver IC 2010 corresponding to sub-pixel R, to the second display driver IC 2020 corresponding to sub-pixel G, and to the third display driver IC 2030 corresponding to sub-pixel B. However, conventional display driver devices using SPI or QSPI interfaces suffer from limited data transmission speeds, often reaching tens of Mbps.

[0132] Figure 5a This is a block diagram illustrating an example of a data transmission method of a display driving device according to an embodiment.

[0133] Referring to 5a, data is transmitted from the transmit interface 11 within the host 10 to the first display driver IC 2010, the second display driver IC 2020, and the third display driver IC 2030 via a single wire. Furthermore, based on the response request from the host 10, each of the first receive interface 2110 of the first display driver IC 2010, the second receive interface 2120 of the second display driver IC 2020, and the third receive interface 2130 of the third display driver IC 2030 uses a MIPI interface to transmit response data to the host 10 in a Bus TurnAround (BTA) manner to respond.

[0134] In a display driver device according to one embodiment, a MIPI interface is used to transmit data via a single wire to each of a plurality of display driver ICs using a multi-point method. Specifically, integrated data is transmitted from the transmit interface 11 in the host 10 to the first receive interface 2110 in the first display driver IC 2010 via a single wire 1204; integrated data is transmitted from the transmit interface 11 in the host 10 to the second receive interface 2120 in the second display driver IC 2020 via a single wire 1204; and integrated data is transmitted from the transmit interface 11 in the host 10 to the third receive interface 2130 in the third display driver IC 2030 via a single wire 1204. The host 10 transmits integrated data corresponding to sub-pixels R, G, and B to the first display driver IC 2010, the second display driver IC 2020, and the third display driver IC 2030 via the single wire 1204. Furthermore, based on the response request from host 10, each of the following interfaces—the first receiving interface 2110 of the first display driver IC 2010, the second receiving interface 2120 of the second display driver IC 2020, and the third receiving interface 2130 of the third display driver IC 2030—uses a MIPI interface to transmit response data to host 10 via a single wire in BTA (Bus Turn Around) mode. To prevent data loss due to transmission of response data via a single wire to host 10, when the first receiving interface 2110 transmits response data, the second receiving interface 2120 and the third receiving interface 2130 do not transmit response data. Similarly, when the second receiving interface 2120 transmits response data, the first receiving interface 2110 and the third receiving interface 2130 do not transmit response data. And when the third receiving interface 2130 transmits response data, the first receiving interface 2110 and the second receiving interface 2120 do not transmit response data.

[0135] According to one embodiment of the present invention, a maximum data transfer speed of several GBps can be achieved by using a multi-point MIPI interface and transmitting data via a single line.

[0136] Figure 5b This is a block diagram illustrating an example of a data transmission method of a display driving device according to an embodiment.

[0137] Reference Figure 5bData is transmitted from the transmit interface 11 within the host 10 to the first display driver IC 2010, the second display driver IC 2020, and the third display driver IC 2030 via a single wire. Furthermore, based on the response request from the host 10, each of the first receive interface 2110 of the first display driver IC 2010, the second receive interface 2120 of the second display driver IC 2020, and the third receive interface 2130 of the third display driver IC 2030 responds by transmitting response data to the host 10 in a point-to-point manner using an SPI interface. Figure 5b In a display driver device according to one embodiment, each of the first receiving interface 2110, the second receiving interface 2120 and the third receiving interface 2130 uses an SPI interface to transmit response data to the host in a point-to-point manner through multiple lines, thereby enabling simultaneous transmission of response data.

[0138] Refer again Figure 3 In step 3303, based on the display data and the instruction data, the sub-pixels corresponding to each of the plurality of display driver ICs are independently controlled. Specifically, each of the plurality of display driver ICs includes a receiving interface that receives display data and instruction data, and each of the plurality of display driver ICs includes a logic controller that selectively writes display data and instruction data, thereby controlling the sub-pixels.

[0139] On the other hand, existing technologies use multiple lines to transmit data from the host to each of the multiple display driver ICs in a point-to-point manner. However, according to an embodiment of the present invention, when using a single line to transmit data in a multi-point manner, each of the multiple display driver ICs, in order to selectively write data, first receives selection data and then writes instruction data, or the instruction data can be configured to correspond to each of the multiple display driver ICs. Details will be described below.

[0140] First, each of the multiple display driver ICs includes a receiving interface that receives display data and instruction data. As described above, the receiving interface of each of the multiple display driver ICs uses a multi-point MIPI interface to receive display data and instruction data via a single wire.

[0141] On the other hand, each of the plurality of display driver ICs includes a receiving interface that can receive selection data for selectively writing display data and instruction data. Unlike conventional display driver devices, the display driver device according to one embodiment transmits and receives display data and instruction data via a single wire, thus the same data is sent to each of the plurality of display driver ICs. According to one embodiment of the present invention, the logic controller included in each of the plurality of display driver ICs can control sub-pixels by selectively writing the same data sent to each of the plurality of display driver ICs.

[0142] As an example, the receiving interface receives selection data for selectively writing display data and instruction data, and the logic controller selectively writes display data and instruction data based on the selection data, thereby controlling the sub-pixel. As an example, the selection data may be password data for the logic controller corresponding to sub-pixel R to write the received instruction data. The logic controller within the display driver IC corresponding to sub-pixel R can control sub-pixel R by receiving the password data corresponding to sub-pixel R and selectively writing instruction data. The instruction data is data that can be written by the display driver ICs corresponding to sub-pixel R, sub-pixel G, and sub-pixel B. By receiving the password data for the display driver IC corresponding to sub-pixel R to write, and writing instruction data only through the display driver IC corresponding to sub-pixel R, sub-pixel R is controlled.

[0143] As another example, the instruction data may include common instruction data applied to sub-pixels R, G, and B included in the sub-pixel, first instruction data applied only to sub-pixel R, second instruction data applied only to sub-pixel G, and third instruction data applied only to sub-pixel B. Even if multiple display driver ICs receive the same instruction data, the logic controller can selectively write the first to third instruction data to control the sub-pixels. The first instruction data is written only through the display driver IC corresponding to sub-pixel R, the second instruction data is written only through the display driver IC corresponding to sub-pixel G, and the third instruction data is written only through the display driver IC corresponding to sub-pixel B.

[0144] On the other hand, based on the host's response request, the receiving interface can respond by transmitting the response data to the host.

[0145] As an example, based on the host's response request, the receiving interface can respond by transmitting response data via a single wire using the MIPI interface in BTA (Bus Turn Around) mode. Specifically, the receiving interface can respond by transmitting response data to the host via a single wire using the same MIPI interface that the host uses to transmit display data and command data.

[0146] As another example, based on the host's response request, the receiving interface can respond by transmitting response data to the host in a point-to-point manner via multiple lines using the SPI interface. Specifically, the receiving interface can respond by transmitting response data to the host via multiple lines using the SPI interface, instead of using the MIPI interface used by the host to transmit display data and command data.

[0147] As another example, when the receiving interface included in each of the multiple display driver ICs receives selection data for selectively writing display data and instruction data, each receiving interface can respond to the host by transmitting response data to the host via a single wire in BTA (BusTurn Around) mode through the MIPI interface that the host also uses to transmit display data and instruction data.

[0148] As another example, when the receiving interface included in each of the multiple display driver ICs receives selection data for selectively writing display data and instruction data, each receiving interface can respond to the host by transmitting response data to the host via multiple lines using the SPI interface, based on the host's response request.

[0149] As another example, when the receiving interface of each of the multiple display driver ICs receives instruction data including common instruction data applied to sub-pixels R, G, and B included in the sub-pixel, first instruction data applied only to sub-pixel R, second instruction data applied only to sub-pixel G, and third instruction data applied only to sub-pixel B, each receiving interface can respond to the host's response request by transmitting response data to the host via multiple lines using the SPI interface.

[0150] Reference Figures 6 to 9 To illustrate an example of the TX mode and RX mode of a display driver device according to an embodiment.

[0151] Figure 6 This is a block diagram illustrating an example of the TX mode and RX mode of a display driver device according to an embodiment.

[0152] TX mode 401 refers to transmitting display data and command data from host 10 to the receiving interface 21 included in each of the multiple display driver ICs. RX mode 402 refers to the receiving interface 21 responding to host 10 by transmitting response data based on a response request from host 10. The response data may include command data received by the receiving interface 21.

[0153] Figure 7 This is a block diagram illustrating an example of the TX mode of a display driver according to an embodiment.

[0154] Reference Figure 7 The host 10 uses a multi-point MIPI interface to transmit display data and instruction data to the receiving interface 21 via a single wire. Each of the multiple display driver ICs includes a logic controller that selectively writes the display data and instruction data received by the receiving interface to control sub-pixels. The following will describe the situation where the logic controller of each of the multiple display driver ICs selectively writes the display data and instruction data received by the receiving interface.

[0155] Figure 8 This is a block diagram illustrating another example of the TX mode of a display driver according to one embodiment.

[0156] Reference Figure 8 It can be confirmed that Case 1 (Case 1) 801 to Case 7 (Case 7) 807 are in TX mode.

[0157] In Case 1 801, the sub-pixels corresponding to each of the plurality of display driver ICs are independently controlled by writing display data and instruction data to the first logic controller corresponding to the first receiving interface, the second logic controller corresponding to the second receiving interface, and the third logic controller corresponding to the third receiving interface.

[0158] As an example, the first, second, and third logic controllers can selectively write display data and instruction data based on selection data, thereby independently controlling the sub-pixels corresponding to each of the multiple display driver ICs. The selection data can be configured as {(Display Command 91h Send: Red Chip Select Enable)), (Display Command 92h Send: Green Chip Select Enable)), (Display Command 93h Send: Blue Chip Select Enable))}. Based on the selection data, the logic controllers corresponding to sub-pixel R, sub-pixel G, and sub-pixel B are all enabled, allowing the writing of display data and instruction data.

[0159] As another example, the first, second, and third logic controllers can independently control a sub-pixel corresponding to each of the plurality of display driver ICs by selectively writing instructions, including common instruction data applied to sub-pixels R, G, and B included in the sub-pixel, first instruction data applied only to sub-pixel R, second instruction data applied only to sub-pixel G, and third instruction data applied only to sub-pixel B. Sub-pixels R, G, and B can be controlled by writing common instruction data to all three logic controllers. Sub-pixels R can be controlled only by writing first instruction data to the first logic controller corresponding to sub-pixel R. Sub-pixels G can be controlled only by writing second instruction data to the second logic controller corresponding to sub-pixel G. Sub-pixels B can be controlled only by writing third instruction data to the third logic controller corresponding to sub-pixel B.

[0160] In Case 2 802, data and instruction data are written through the first logic controller and the second logic controller to independently control the sub-pixels corresponding to each of the multiple display driver ICs.

[0161] As an example, the first and second logic controllers can independently control the sub-pixels corresponding to each of the multiple display driver ICs by writing display data and instruction data based on selection data. The selection data can be configured as {(Display Command 91h Send: Red Chip Select Enable), (Display Command 92h Send: Green Chip Select Enable), (Display Command 96h Send: Blue Chip Select Disable))}. Based on the selection data, the logic controller corresponding to sub-pixel R and the logic controller corresponding to sub-pixel G are turned on, and the logic controller corresponding to sub-pixel B is turned off. Sub-pixels R and G are controlled by writing display data and instruction data to the logic controllers corresponding to sub-pixels R and G. Since the logic controller corresponding to sub-pixel B is turned off and cannot write display data and instruction data, sub-pixel B is not controlled by display data and instruction data.

[0162] As another example, the first and second logic controllers can independently control a sub-pixel corresponding to each of the plurality of display driver ICs by selectively writing instructions, including first instruction data applicable only to sub-pixel R and second instruction data applicable only to sub-pixel G. Sub-pixel R can be controlled solely by writing the first instruction data through the first logic controller corresponding to sub-pixel R. Sub-pixel G can be controlled solely by writing the second instruction data through the second logic controller corresponding to sub-pixel G.

[0163] In Case 3 803, the first logic controller and the third logic controller independently control the sub-pixels corresponding to each of the multiple display driver ICs by writing data and instruction data.

[0164] As an example, the first and third logic controllers can independently control the sub-pixels corresponding to each of the multiple display driver ICs by selectively writing display data and instruction data based on selection data. The selection data can be configured as {(Display Command 91h Send: Red Chip Select Enable), (Display Command 93h Send: Blue Chip Select Enable), (Display Command 95h Send: Green Chip Select Disable)}. Based on the selection data, the logic controller corresponding to sub-pixel R and the logic controller corresponding to sub-pixel B are turned on, and the logic controller corresponding to sub-pixel G is turned off. Sub-pixels R and B are controlled by writing display data and instruction data to the logic controllers corresponding to sub-pixels R and B. Since the logic controller corresponding to sub-pixel G is turned off and cannot write display data and instruction data, sub-pixel G is not controlled by the display data and instruction data.

[0165] As another example, the first logic controller and the third logic controller independently control a sub-pixel corresponding to each of the plurality of display driver ICs by selectively writing instructions, including first instruction data applied only to sub-pixel R and third instruction data applied only to sub-pixel B. Sub-pixel R is controlled only by writing the first instruction data through the first logic controller corresponding to sub-pixel R. Sub-pixel B is controlled only by writing the third instruction data through the third logic controller corresponding to sub-pixel B.

[0166] In Case 4 804, the second and third logic controllers independently control the sub-pixels corresponding to each of the multiple display driver ICs by writing data and instruction data.

[0167] As an example, the second and third logic controllers can independently control the sub-pixels corresponding to each of the multiple display driver ICs by selectively writing display data and instruction data based on selection data. The selection data can be configured as {(Display Command 92h Send: Green Chip Select Enable), (Display Command 93h Send: Blue Chip Select Enable), (Display Command 94h Send: Red Chip Select Disable))}. Based on the selection data, the logic controller corresponding to sub-pixel G and the logic controller corresponding to sub-pixel B are turned on, and the logic controller corresponding to sub-pixel R is turned off. Sub-pixels G and B are controlled by writing display data and instruction data to the logic controllers corresponding to sub-pixels G and B. Since the logic controller corresponding to sub-pixel R is turned off and cannot write display data and instruction data, sub-pixel R is not controlled by display data and instruction data.

[0168] As another example, the second and third logic controllers can independently control a sub-pixel corresponding to each of the plurality of display driver ICs by selectively writing instructions, including second instruction data applied only to sub-pixel G and third instruction data applied only to sub-pixel B. Sub-pixel G is controlled only by writing the second instruction data through the first logic controller corresponding to sub-pixel G. Sub-pixel B is controlled only by writing the third instruction data through the second logic controller corresponding to sub-pixel B.

[0169] In the case of Case 5 805, the first logic controller independently controls the sub-pixels corresponding to each of the multiple display driver ICs by writing data and instruction data.

[0170] As an example, the first logic controller can independently control the sub-pixels corresponding to each of the multiple display driver ICs by selectively writing display data and instruction data based on selection data. The selection data can be configured as {(Display Command 91h Send: Red Chip Select Enable), (Display Command 95h Send: Green Chip Select Disable), (Display Command 96h Send: Blue Chip Select Disable))}. Based on the selection data, the logic controller corresponding to sub-pixel R is turned on, while the logic controllers corresponding to sub-pixel G and sub-pixel B are turned off. Sub-pixel R is controlled by writing display data and instruction data to the logic controller corresponding to sub-pixel R. Since the logic controllers corresponding to sub-pixel G and sub-pixel B are turned off and cannot write display data and instruction data, sub-pixels G and B are not controlled by the display data and instruction data.

[0171] As another example, the first logic controller selectively writes instructions, including first instruction data applicable only to sub-pixel R, to independently control the sub-pixel corresponding to each of the plurality of display driver ICs. Sub-pixel R is controlled solely by writing the first instruction data to the first logic controller corresponding to sub-pixel R.

[0172] In the case of Case 6 806, the second logic controller independently controls the sub-pixels corresponding to each of the multiple display driver ICs by writing data and instruction data.

[0173] As an example, the second logic controller can independently control the sub-pixels corresponding to each of the multiple display driver ICs by selectively writing display data and instruction data based on selection data. The selection data can be configured as {(Display Command 92h Send: Green Chip Select Enable), (Display Command 94h Send: Red Chip Select Disable), (Display Command 96h Send: Blue Chip Select Disable))}. Based on the selection data, the logic controller corresponding to sub-pixel G is turned on, while the logic controllers corresponding to sub-pixel R and sub-pixel B are turned off. Sub-pixel G is controlled by writing display data and instruction data to the logic controller corresponding to sub-pixel G. Since the logic controllers corresponding to sub-pixel R and sub-pixel B are turned off and cannot write display data and instruction data, sub-pixels R and B are not controlled by the display data and instruction data.

[0174] As another example, the second logic controller can independently control a sub-pixel corresponding to each of a plurality of display driver ICs by selectively writing instructions, including second instruction data applicable only to sub-pixel G. Sub-pixel G is controlled solely by writing second instruction data to the second logic controller corresponding to sub-pixel G.

[0175] In the case of Case 7 807, the third logic controller independently controls the sub-pixels corresponding to each of the multiple display driver ICs by writing data and instruction data.

[0176] As an example, the third logic controller can independently control the sub-pixels corresponding to each of the multiple display driver ICs by selectively writing display data and instruction data based on selection data. The selection data can be configured as {(Display Command 93h Send: Blue Chip Select Enable), (Display Command 94h Send: Red Chip Select Disable), (Display Command 95h Send: Green Chip Select Disable))}. Based on the selection data, the logic controller corresponding to sub-pixel B is turned on, while the logic controllers corresponding to sub-pixel R and sub-pixel G are turned off. Sub-pixel B is controlled by writing display data and instruction data through the logic controller corresponding to sub-pixel B. Since the logic controllers corresponding to sub-pixel R and sub-pixel G are turned off and cannot write display data and instruction data, sub-pixels R and G are not controlled by the display data and instruction data.

[0177] As another example, the third logic controller can independently control a sub-pixel that corresponds to each of a plurality of display driver ICs by selectively writing instructions, including third instruction data that applies only to sub-pixel B. Sub-pixel B is controlled only by writing third instruction data only to the third logic controller corresponding to sub-pixel B.

[0178] Figure 9 This is a block diagram illustrating an example of the RX mode of a display driver according to an embodiment.

[0179] Reference Figure 9 This confirms Case 1 901 to Case 3 903 in RX mode.

[0180] In Case 1 901, the first receiving interface responds by transmitting response data to the host via a host-based response request. As an example, the first receiving interface can respond by transmitting response data via a single wire in BTA (Bus Turn Around) mode using the MIPI interface through a host-based response request. In this case, the second and third receiving interfaces do not transmit response data during the first receiving interface's response. The host's response request can be configured as {(Display Command 91h Send: Red Chip SelectEnable)), (Display Command 95h Send: Green Chip Select Disable)), (Display Command 96h Send: Blue Chip Select Disable)), (Display Command 97h and parameter data 01h)}. As another example, the first receiving interface can respond by transmitting response data in a point-to-point manner via multiple lines using the SPI interface based on the host's response request. In this case, the second and third receiving interfaces can respond by transmitting response data via lines different from the SPI interface used by the first receiving interface.

[0181] In Case 2 902, the second receiving interface responds by transmitting response data to the host via a host-based response request. As an example, the second receiving interface can respond by transmitting response data via a single wire in BTA (Bus Turn Around) mode using the MIPI interface through a host-based response request. In this case, the first and third receiving interfaces do not transmit response data during the second receiving interface's response. The host's response request can be configured as {(Display Command 92h Send: Green Chip SelectEnable)), (Display Command 94h Send: Red Chip Select Disable)), (Display Command 96h Send: Blue Chip Select Disable)), (Display Command 97h and parameter data 02h))}. As another example, the second receiving interface can respond to a host-based response request by transmitting response data in a point-to-point manner via multiple lines using the SPI interface. In this case, the first and third receiving interfaces can respond by transmitting response data using lines different from the SPI interface used by the second receiving interface.

[0182] In Case 3 903, the third receiving interface responds by transmitting response data to the host via a host-based response request. As an example, the third receiving interface can respond by transmitting response data via a single wire in BTA (Bus Turn Around) mode using the MIPI interface through a host-based response request. In this case, the first and second receiving interfaces do not transmit response data during the third receiving interface's response. The host's response request can be configured as {(Display Command 93h Send : Blue Chip SelectEnable)), (Display Command 94h Send : Red Chip SelectDisable)), (Display Command 95h Send : Green Chip SelectDisable)), (Display Command 97h and para data 03h))}. As another example, the third receiving interface can respond to a host-based response request by using an SPI interface to transmit response data in a point-to-point manner via multiple lines. In this case, the first and second receiving interfaces can respond by transmitting response data using lines different from the SPI interface used by the third receiving interface.

[0183] As described above, according to one embodiment, the display driver device acquires display data and command data, transmits the display data and command data to multiple display driver ICs respectively using a point-to-multipoint (Multi-drop) MIPI interface, and independently controls the sub-pixels corresponding to each of the multiple display driver ICs based on the display data and command data, thereby driving the display with high resolution and high frame rate.

[0184] On the other hand, a display driving device according to one embodiment can be a display driving device comprising a plurality of display driving ICs that independently control each of a plurality of sub-pixels based on display data and instruction data, wherein the plurality of display driving ICs receive display data and instruction data using a multi-point MIPI interface. A display driving device according to another embodiment can be a display driving device that further includes a host for transmitting display data and instruction data to the plurality of display driving ICs. A display driving device according to yet another embodiment can be a display driving device that further includes a display panel comprising a plurality of sub-pixels. A display driving device according to yet another embodiment can be a display driving device comprising: a receiving interface for each of the plurality of display driving ICs to receive display data and instruction data; and a logic controller for controlling the sub-pixels by writing the display data and instruction data.

[0185] On the other hand, the method can be written as a computer-executable program and implemented in a general-purpose digital computer that runs the program using a computer-readable recording medium. Furthermore, the data structures used in the method can be recorded in a computer-readable recording medium in various ways. The computer-readable recording medium includes storage media such as magnetic storage media (e.g., ROM, RAM, USB, floppy disk, hard disk, etc.) and optical reading media (e.g., CD-ROM, DVD, etc.).

[0186] Those skilled in the art related to this embodiment will understand that it is implemented in modified forms without departing from the basic characteristics described above. Therefore, the disclosed method should be considered illustratively rather than limitingly, and the scope of the claims should be understood to appear within the scope of the patent claims, not in the description itself, and includes all differences within its equivalent scope.

Claims

1. A data transmission method for a display driving device, characterized in that, include: The steps to obtain display data and instruction data; The step involves using a multi-point mobile industrial processor interface to transmit the display data and the instruction data to multiple display driver chips via a single line, so that the same display data and the same instruction data are transmitted to each of the multiple display driver chips. as well as The steps of independently controlling the sub-pixels corresponding to each of the plurality of display driver chips based on the display data and the instruction data; The sub-pixel includes sub-pixels R, G, and B contained within a single pixel, and the plurality of display driver chips correspond to sub-pixels R, G, and B, respectively. The control steps include: The steps include receiving the display data, the instruction data, and selection data for selectively writing the display data and the instruction data through the receiving interface included in each of the plurality of display driver chips; and The logic controller included in each of the plurality of display driver chips controls the sub-pixels by selectively writing the display data and the instruction data based on the selection data.

2. The method according to claim 1, characterized in that, The instruction data includes: Common instruction data applied to sub-pixel R, sub-pixel G, and sub-pixel B; first instruction data applied only to sub-pixel R; second instruction data applied only to sub-pixel G; and third instruction data applied only to sub-pixel B.

3. The method according to claim 1, characterized in that, Also includes: The receiving interface performs the response step by transmitting response data to the host based on the host's response request.

4. The method according to claim 3, characterized in that, The response steps include: The receiving interface performs the response step by transmitting the response data in a bus-turning manner using the mobile industrial processor interface.

5. The method according to claim 3, characterized in that, The response steps include: The receiving interface performs the response step by transmitting the response data in a point-to-point manner using a serial peripheral interface.

6. A display driving device, characterized in that, include: Multiple display driver chips independently control each of the multiple sub-pixels based on display data and instruction data. The plurality of display driver chips receive the display data and the instruction data via a single line using a multi-point mobile industrial processor interface, and each of the plurality of display driver chips receives the same display data and the same instruction data; The plurality of sub-pixels includes sub-pixels R, G, and B contained within a single pixel, and the plurality of display driver chips correspond to sub-pixels R, G, and B, respectively. Each of the plurality of display driver chips includes: A receiving interface configured to receive the display data, the instruction data, and selection data for selectively writing the display data and the instruction data; and A logic controller configured to control the sub-pixels by selectively writing the display data and the instruction data based on the selection data.

7. The display driving device according to claim 6, characterized in that, Also includes: The host is used to transmit the display data and the instruction data to the plurality of display driver chips.

8. The display driving device according to claim 6, characterized in that, Also includes: The display panel includes the plurality of sub-pixels.

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