Gate driving circuit and display panel

Abstract

The application discloses a gate driving circuit and a display panel. The gate driving circuit comprises a plurality of shift registers. The shift register comprises a stage transmission signal selection module, a pull-up control module, a pulse number reduction module, a first inversion module, a first output module, a second output module and a pressure increasing module. The pressure increasing module is connected in series between the second electrode of the second transistor and the low potential line. When the first transistor is turned on, the potential of the second electrode of the second transistor can be improved, the on-state current of the second transistor is reduced, the pulse amplitude of the second gate driving signal can be improved and stabilized, and simultaneously, the negative bias of the threshold voltage of the second transistor can be improved by improving the potential of the second electrode of the second transistor, so that the negative bias range of the threshold voltage of the second transistor is increased, the abnormality of the second gate driving signal is avoided, and the reliability of the gate driving circuit is improved.

Description

Technical Field

[0001] This application relates to the field of display technology, specifically to a gate driving circuit and a display panel. Background Technology

[0002] In display panels, gate drive circuits are typically used to provide corresponding gate drive signals for different transistors, and the stability of these gate drive signals is particularly critical to the operational stability of the transistors.

[0003] However, the pulse amplitude of the gate drive signal provided by the gate drive circuit is relatively small, which can easily lead to undesirable situations when driving the corresponding transistors in the pixel circuit, thereby reducing the reliability of the gate drive circuit. Summary of the Invention

[0004] This application provides a gate driving circuit and a display panel to alleviate the technical problem of small pulse amplitude of the gate driving signal.

[0005] In a first aspect, this application provides a gate driving circuit, which includes multiple shift registers. Each shift register includes a stage signal selection module, a pull-up control module, a pulse count reduction module, a first inverting module, a first output module, a second output module, and a boosting module. The stage signal selection module is electrically connected between a first wiring and a first node. The pull-up control module controls the potential of a second node based on the potential of the first node and the potential of a first clock signal. The pulse count reduction module is electrically connected between the second node and a third node, and its control terminal is electrically connected to a reset line. The first inverting module is connected to the first... Between the second node and the fourth node; the first output module outputs a first gate drive signal based on the potential of the third node and the potential of the fourth node; the second output module includes a P-channel first transistor and an N-channel second transistor, the first terminal of the first transistor is electrically connected to the high potential line, and the gate of the first transistor is electrically connected to the second node; the first terminal of the second transistor is electrically connected to the second terminal of the first transistor to output a second gate drive signal, and the gate of the second transistor is electrically connected to the gate of the first transistor; the boost module is connected in series between the second terminal of the second transistor and the low potential line, and the control terminal of the boost module is electrically connected to the gate of the second transistor.

[0006] In some embodiments, the boost module includes at least one transistor connected in series between the second terminal of the second transistor and the low potential line, and each gate of the at least one transistor is electrically connected to the gate of the second transistor.

[0007] In some embodiments, at least one transistor includes a third transistor, the first terminal of the third transistor being electrically connected to the second terminal of the second transistor, the second terminal of the third transistor being electrically connected to a low-potential line, the gate of the third transistor being electrically connected to the gate of the second transistor, and the channel type of the third transistor being the same as that of the second transistor.

[0008] In some embodiments, the gate of the second transistor and the gate of the third transistor both include a first gate and a second gate, and the second node is electrically connected to the first gate of the second transistor, the second gate of the second transistor, the first gate of the third transistor, and the second gate of the third transistor.

[0009] In some embodiments, when the third transistor is turned on, the potential of the second terminal of the second transistor is less than or equal to -6.7V; both the second and third transistors are indium gallium zinc oxide thin-film transistors.

[0010] In some embodiments, the channel width-to-length ratio of the third transistor is greater than or equal to 8.57 and less than or equal to 20; both the second and third transistors are indium gallium zinc oxide thin-film transistors.

[0011] In some embodiments, at least one transistor further includes a fourth transistor, the first terminal of which is electrically connected to the second terminal of the third transistor, the second terminal of which is electrically connected to a low-potential line, the gate of which is electrically connected to the gate of the second transistor, and the channel type of the fourth transistor is the same as that of the third transistor.

[0012] In some embodiments, the boost module is used to raise the potential of the second electrode of the second transistor when the potential of the second node is low.

[0013] In some implementations, the boost module is used to increase and stabilize the high potential of the second gate drive signal.

[0014] Secondly, this application provides a display panel, which includes a pixel circuit and a gate driving circuit as described in at least one of the above embodiments. The pixel circuit includes a write transistor for controlling the input of a data signal and a compensation transistor for controlling the input of a data signal to the gate of the driving transistor. The output terminal of the first output module is electrically connected to the gate of the write transistor, and the output terminal of the second output module is electrically connected to the gate of the compensation transistor.

[0015] The gate drive circuit and display panel provided in this application, by connecting a booster module in series between the second electrode of the second transistor and the low potential line, can increase the potential of the second electrode of the second transistor when the first transistor is turned on, reduce the on-state current of the second transistor, and improve and stabilize the pulse amplitude of the second gate drive signal. Simultaneously, by increasing the potential of the second electrode of the second transistor, the negative bias of the threshold voltage of the second transistor can be improved, thereby increasing the negative bias range of the threshold voltage of the second transistor, avoiding abnormalities in the second gate drive signal, and thus improving the reliability of the gate drive circuit.

[0016] Furthermore, the second gate drive signal with a larger number of pulses can be output through the stage transmission signal selection module, the pull-up control module, and the second output module. At the same time, the second gate drive signal can also be selected as the stage transmission signal between different shift registers. Moreover, the first gate drive signal with a smaller number of pulses can also be output through the stage transmission signal selection module, the pull-up control module, the pulse number reduction module, the first inverting module, and the first output module. This can meet the needs of the corresponding pixel circuit for the pulses of the gate drive signal in terms of time and number in one frame, thereby driving the pixel circuit to achieve image quality display. Attached Figure Description

[0017] The technical solution and other beneficial effects of this application will become apparent from the following detailed description of specific embodiments in conjunction with the accompanying drawings.

[0018] Figure 1 This is a schematic diagram of the gate drive circuit in the related technology.

[0019] Figure 2 for Figure 1 The diagram shows the timing sequence of some nodes in the gate drive circuit.

[0020] Figure 3 This is a schematic diagram of the gate drive circuit provided in an embodiment of this application.

[0021] Figure 4 for Figure 3 The diagram shows the timing sequence of some nodes in the gate drive circuit.

[0022] Figure 5 This is a schematic diagram illustrating the relationship between delay time and output voltage of a transistor with different channel lengths, as provided in the embodiments of this application.

[0023] Figure 6 This is a schematic diagram illustrating the relationship between the delay time and the voltage at node B of the transistor provided in this application under different channel lengths.

[0024] Figure 7 for Figure 3The timing diagram of the gate drive circuit is shown.

[0025] Figure 8 for Figure 3 The gate drive circuit shown is in Figure 7 A schematic diagram of the first stage of the process.

[0026] Figure 9 for Figure 3 The gate drive circuit shown is in Figure 7 A schematic diagram of the second stage of the process.

[0027] Figure 10 for Figure 3 The gate drive circuit shown is in Figure 7 A schematic diagram of the third stage of the process.

[0028] Figure 11 for Figure 3 The gate drive circuit shown is in Figure 7 A schematic diagram of the fourth stage of the process.

[0029] Figure 12 for Figure 3 The gate drive circuit shown is in Figure 7 A schematic diagram of the fifth stage of the process.

[0030] Figure 13 for Figure 3 The gate drive circuit shown is in Figure 7 A schematic diagram of the sixth stage of the process.

[0031] Figure 14 for Figure 3 The gate drive circuit shown is in Figure 7 A schematic diagram of the seventh stage of the process.

[0032] Figure 15 for Figure 3 The gate drive circuit shown is in Figure 7 A schematic diagram of the eighth stage of the process.

[0033] Figure 16 for Figure 3 The gate drive circuit shown is in Figure 7 A schematic diagram of the ninth stage of the process.

[0034] Figure 17 for Figure 3 The gate drive circuit shown is in Figure 7 A schematic diagram of the tenth stage.

[0035] Figure 18 for Figure 3 The gate drive circuit shown is in Figure 7 A schematic diagram of the eleventh stage.

[0036] Figure 19 for Figure 3 The diagram shows a cascaded structure between different shift registers in the gate drive circuit.

[0037] Figure 20 This is a schematic diagram of the structure of the display panel provided in an embodiment of this application.

[0038] Figure 21 for Figure 20 The diagram shows the structure of the pixel circuit in the display panel.

[0039] Figure 22 for Figure 21 The timing diagram of the pixel circuit is shown. Detailed Implementation

[0040] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0041] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Features thus defined as "first" or "second" may explicitly or implicitly include one or more of the stated features. In the description of this invention, "a plurality of" means two or more unless otherwise explicitly specified.

[0042] Please see Figure 1 , Figure 2 , Figure 1 This is a schematic diagram of a gate drive circuit in the related art. The gate drive circuit includes at least one of the following: a stage signal selection module 10, a pull-up control module 20, a pulse number reduction module 30, a first inverting module 50, a first output module 46, a second output module 70, a leakage protection module 80, and a feedback module 90.

[0043] The first output module 46 includes a pull-up module 40 and a pull-down module 60. The first output module 46 outputs a first gate drive signal. The second output module 70 outputs a second gate drive signal.

[0044] For a detailed description of the gate drive circuit, please refer to the following related description.

[0045] However, during application, the inventors discovered an anomaly in the output stability of the gate drive circuit. For example, the high potential of the second gate drive signal was not as high as expected and showed a significant dip. After extensive investigation, it was found that this was due to a coupling relationship between the first output module 46 and the second output module 70. In other words, Figure 1 In the gate drive circuit shown, when both the first output module 46 and the second output module 70 are present, a specific problem arises: the high potential of the second gate drive signal is not as high as expected. This further leads to... Figure 1 The gate drive circuit shown cannot simultaneously meet the output requirements of the first gate drive signal and the second gate drive signal.

[0046] Specifically, Figure 2 for Figure 1 The diagram shows the timing sequence of some nodes in the gate drive circuit. Figure 1 The gate drive circuit shown is at a low potential at the second node K, for example... Figure 2 When the voltage is -4.578V, the first transistor T9 is turned on and the second transistor T10 is turned off, which can output a high-potential second gate drive signal.

[0047] However, since the potential of node B, i.e., the potential of the low-potential signal, is... Figure 2 As shown, with a voltage of -8V, the gate-source voltage difference Vgs of the second transistor T10 is 3.422V, resulting in a relatively small leakage current. This means that the high potential of the second gate drive signal can only be maintained at... Figure 2 The voltage is 7.302V, which is insufficient to achieve the desired pulse amplitude. In other words, the pulse amplitude of the second gate drive signal is relatively small.

[0048] In view of this, this embodiment provides a gate driving circuit, please refer to... Figures 1 to 22 ,like Figure 3 As shown, the gate drive circuit includes multiple shift registers, and the shift registers include at least one of the following: a stage signal selection module 10, a pull-up control module 20, a pulse number reduction module 30, a first inverting module 50, a first output module 46, a second output module 70, and a boost module 72.

[0049] The cascade signal selection module 10 is electrically connected between the first wiring and the first node O.

[0050] The pull-up control module 20 controls the potential of the second node K based on the potential of the first node O and the potential of the first clock signal.

[0051] The pulse count reduction module 30 is electrically connected between the second node K and the third node Q, and the control terminal of the pulse count reduction module 30 is electrically connected to the reset line.

[0052] The first inverting module 50 is connected between the second node K and the fourth node P.

[0053] The first output module 46 outputs the first gate drive signal based on the potential of the third node Q and the potential of the fourth node P.

[0054] The second output module 70 includes a P-channel first transistor T9 and an N-channel second transistor T10. The first terminal of the first transistor T9 is electrically connected to a high-potential line, and the gate of the first transistor T9 is electrically connected to a second node K. The first terminal of the second transistor T10 is electrically connected to the second terminal of the first transistor T9 to output a second gate drive signal, and the gate of the second transistor T10 is electrically connected to the gate of the first transistor T9.

[0055] The boost module 72 is connected in series between the second terminal of the second transistor T10 and the low potential line, and the control terminal of the boost module 72 is electrically connected to the gate of the second transistor T10.

[0056] It is understood that the gate drive circuit provided in this embodiment, by connecting the boost module 72 in series between the second terminal of the second transistor T10 and the low potential line, can increase the potential of the second terminal of the second transistor T10 and reduce the on-state current of the second transistor T10 when the first transistor T9 is turned on, thereby increasing and stabilizing the pulse amplitude of the second gate drive signal. Simultaneously, by increasing the potential of the second terminal of the second transistor T10, the negative bias of the threshold voltage of the second transistor T10 can be improved, thereby increasing the negative bias range of the threshold voltage of the second transistor T10, avoiding abnormalities in the second gate drive signal, and thus improving the reliability of the gate drive circuit.

[0057] It should be noted that, in this embodiment, the booster module 72 can raise the potential of the second terminal of the second transistor T10 when the potential of the second node K is low, thereby reducing the on-state current or leakage current of the second transistor T10. Compared to the case where leakage current exists, the potential of the second gate drive signal can be increased and stabilized. Alternatively, in this embodiment, the booster module 72 can increase and stabilize the high potential of the second gate drive signal.

[0058] by Figure 4 For example, with Figure 2 In contrast, the potential of the second node K remained unchanged, while the potential of node B changed from... Figure 2 -8V was raised to Figure 4 The voltage level shown is -5.505V. The high potential of the second gate drive signal is determined by... Figure 2 The 7.302V was raised to Figure 4The voltage is 7.465V as shown. Understandably, in this case, the second gate drive signal can make the transistor it controls more conductive and stable, thereby improving the reliability or stability of the gate drive circuit.

[0059] In one embodiment, the boost module 72 includes at least one transistor, which is connected in series between the second terminal of the second transistor T10 and the low potential line, and each gate of the at least one transistor is electrically connected to the gate of the second transistor T10.

[0060] It should be noted that in this embodiment, the boost module 72 may include one or more transistors connected in series. Each additional transistor can raise the potential of node B. As the number of transistors increases, the leakage current of the second transistor T10 will be smaller, thereby making it easier to maintain the high potential of the second gate drive signal.

[0061] In one embodiment, at least one transistor includes a third transistor T15, the first terminal of the third transistor T15 being electrically connected to the second terminal of the second transistor T10, the second terminal of the third transistor T15 being electrically connected to a low potential line, the gate of the third transistor T15 being electrically connected to the gate of the second transistor T10, and the channel type of the third transistor T15 being the same as that of the second transistor T10.

[0062] It should be noted that when the second node K is at a low potential, the third transistor T15 is in the off state but has a certain leakage current. There is a resistance between the first and second terminals of the third transistor T15. The potential of the low potential signal is raised to a higher potential after passing through the third transistor T15, which makes the gate-source voltage difference of the second transistor T10 even lower, and thus makes the on-state current of the second transistor T10 even smaller.

[0063] In one embodiment, the gate of the second transistor T10 and the gate of the third transistor T15 both include a first gate and a second gate, and the second node K is electrically connected to the first gate of the second transistor T10, the second gate of the second transistor T10, the first gate of the third transistor T15, and the second gate of the third transistor T15.

[0064] It should be noted that in this embodiment, the second transistor T10 and the third transistor T15 can both be dual-gate thin-film transistors, which can not only improve the control capability of the current flowing through them, but also reduce the drift amplitude of the threshold voltage.

[0065] In one embodiment, such as Figure 5As shown, a problem arises when the falling edge delay of the second gate drive signal exceeds 1µs, especially when the number of stages in the gate drive circuit exceeds 200. Research has revealed that increasing the channel width (W) of the third transistor T15 while keeping its channel length (L) constant (e.g., L = 3.5µm) reduces the falling edge delay of the second gate drive signal and lowers the high potential (output voltage) of the second gate drive signal. Based on these considerations, with the channel length of the third transistor T15 unchanged, the channel width of the third transistor T15 should be greater than or equal to 30µm and less than or equal to 70µm; that is, the channel width-to-length ratio of the third transistor T15 should be greater than or equal to 8.57 and less than or equal to 20 (e.g., 8.6, 8.8, 9, 10, 11, 12, 15, 18, etc.). The larger this channel width-to-length ratio, the smaller the falling edge delay of the second gate drive signal.

[0066] Among them, the second transistor T10 and the third transistor T15 are both indium gallium zinc oxide thin film transistors. It can be understood that the above-mentioned channel width and channel length have been found to be more suitable for indium gallium zinc oxide thin film transistors after further research.

[0067] In one embodiment, when the third transistor T15 is turned on, the potential of the second terminal of the second transistor T10 is less than or equal to -6.7V; both the second transistor T10 and the third transistor T15 are indium gallium zinc oxide thin film transistors.

[0068] It should be noted that the second transistor T10 and the third transistor T15 use the same channel material and can be manufactured through the same process, which simplifies the process.

[0069] like Figure 6 As shown, with the increase in the channel width of the third transistor T15, the lower the potential of node B, the higher the voltage of the second gate drive signal; conversely, the higher the potential of node B, the greater the delay time of the falling edge of the second gate drive signal. Therefore, considering that the delay time of the falling edge of the second gate drive signal is greater than 1µs and that problems may arise when the number of stages in the gate drive circuit exceeds 200, the potential of node B is determined to be ≤-6.7V.

[0070] In one embodiment, at least one transistor further includes a fourth transistor (not shown), the first terminal of the fourth transistor being electrically connected to the second terminal of the third transistor T15, the second terminal of the fourth transistor being electrically connected to a low potential line, the gate of the fourth transistor being electrically connected to the gate of the second transistor T10, and the channel type of the fourth transistor being the same as that of the third transistor T15.

[0071] It should be noted that in this embodiment, the boost module 72 includes two transistors, a third transistor T15 and a fourth transistor, which can further raise the potential of node B, thereby further reducing the leakage current of the second transistor T10.

[0072] In other embodiments, the boost module 72 may also include three, four or more transistors connected in series to continuously reduce the leakage current of the second transistor T10.

[0073] In other embodiments, a booster module 72 can also be connected in series between transistor T1 and the low potential line, and a booster module 72 can also be connected in series between transistor R13 and the low potential line. The specific connection relationship can refer to the connection relationship between the second transistor T10 and the low potential line, which can achieve the same effect.

[0074] In one embodiment, the second output module 70 outputs a second gate drive signal according to the potential of the second node K, wherein the number of pulses of the second gate drive signal in a frame is greater than the number of pulses of the first gate drive signal in a frame.

[0075] It should be noted that the gate driving circuit provided in this embodiment can output a second gate driving signal with a larger number of pulses through the stage transmission signal selection module 10, the pull-up control module 20, and the second output module 70. At the same time, the second gate driving signal can also be selected as the stage transmission signal between different shift registers. Furthermore, through the stage transmission signal selection module 10, the pull-up control module 20, the pulse number reduction module 30, the first inverting module 50, and the first output module 46, a first gate driving signal with a smaller number of pulses can be output. This can meet the needs of the corresponding pixel circuit for the pulses of the gate driving signal in terms of time and number in one frame, thereby driving the pixel circuit to achieve image quality display.

[0076] The input terminal of the stage transmission signal selection module 10 is electrically connected to the start control line or the NYth stage positive pulse gate drive line, where N is an integer greater than or equal to 1 and Y is an integer greater than or equal to 1.

[0077] The input terminal of the pull-up control module 20 is electrically connected to the output terminal of the cascade signal selection module 10, and the control terminal of the pull-up control module 20 is electrically connected to the first clock line.

[0078] The input terminal of the pulse number reduction module 30 is electrically connected to the output terminal of the pull-up control module 20, and the control terminal of the pulse number reduction module 30 is electrically connected to the reset line.

[0079] The control terminal of the pull-up module 40 is electrically connected to the output terminal of the pulse number reduction module 30, the input terminal of the pull-up module 40 is electrically connected to the second clock line, and the output terminal of the pull-up module 40 is electrically connected to the Nth negative pulse gate drive line. The input terminal of the first inverting module 50 is electrically connected to the output terminal of the pull-up control module 20.

[0080] The control terminal of the pull-down module 60 is electrically connected to the output terminal of the first inverting module 50, the input terminal of the pull-down module 60 is electrically connected to the high-potential line, and the output terminal of the pull-down module 60 is electrically connected to the Nth negative pulse gate drive line.

[0081] The input terminal of the second output module 70 is electrically connected to the input terminal of the pull-up control module 20, and the output terminal of the second output module 70 is electrically connected to the Nth positive pulse gate drive line. The number of positive pulses output by the Nth positive pulse gate drive line in one frame is greater than the number of negative pulses output by the Nth negative pulse gate drive line in one frame.

[0082] In one embodiment, the first output module 46 includes a pull-up module 40 and a pull-down module 60.

[0083] It should be noted that the first wiring can be either a start control line or the NY-th positive pulse gate drive line; where the first wiring is a start control line when NY is less than or equal to 0. The N-th positive pulse gate drive line, which is also the second gate drive line, is used to transmit the N-th positive pulse gate drive signal Nout[N], i.e., the second gate drive signal. The N-th negative pulse gate drive line, which is also the first gate drive line, is used to transmit the N-th negative pulse gate drive signal Pout[N], i.e., the first gate drive signal.

[0084] In one embodiment, the pulse number reduction module 30 includes a transistor T11, one of the source or drain of transistor T11 is electrically connected to the output terminal of the pull-up control module 20, the other of the source or drain of transistor T11 is electrically connected to the control terminal of the pull-up module 40, and the gate of transistor T11 is electrically connected to the reset line; wherein, transistor T11 is a P-channel thin film transistor; the reset line is the NXth positive pulse gate drive line, where X is an integer greater than or equal to 2.

[0085] It should be noted that the output terminal of the pull-up control module 20 is the second node K. The control terminal of the pull-up module 40 is the third node Q. The other of the source or drain terminals of transistor T11 is node W. The pulse reduction module 30 is used to reduce the double pulses appearing in the second node K in a frame to the single pulses appearing in the third node Q in a frame; specifically, it eliminates the first pulse appearing in the second node K in a frame, while retaining the second pulse appearing in the same frame.

[0086] In one embodiment, the ratio of the channel width of transistor T11 to the channel length of transistor T11 is greater than or equal to 0.5 and less than or equal to 1.5.

[0087] It should be noted that this embodiment helps to ensure the output stability of the Nth negative pulse gate drive signal Pout[N], and avoids the coupling pull-down phenomenon before the negative pulse arrives.

[0088] In one embodiment, the pulse number reduction module 30 further includes a first capacitor C2, one end of which is electrically connected to the gate of transistor T11, and the other end of which is electrically connected to the source or drain of transistor T11.

[0089] It should be noted that this embodiment is beneficial for further improving the output stability of the Nth-level negative pulse gate drive signal Pout[N].

[0090] In one embodiment, the pull-up module 40 includes a pull-up transistor T6 and a second capacitor C1. The gate of the pull-up transistor T6 is electrically connected to one of the sources or drains of the transistor T11. One of the sources or drains of the pull-up transistor T6 is electrically connected to a second clock line, and the other of the sources or drains of the pull-up transistor T6 is electrically connected to the Nth negative pulse gate drive line. One end of the second capacitor C1 is electrically connected to the gate of the pull-up transistor T6, and the other end of the second capacitor C1 is electrically connected to the other of the sources or drains of the pull-up transistor T6. The ratio of the capacitance of the first capacitor C2 to that of the second capacitor C1 is greater than or equal to 0.5.

[0091] It should be noted that the ratio of the capacitance of the first capacitor C2 to the capacitance of the second capacitor C1 in this embodiment is designed to further ensure the output stability of the Nth negative pulse gate drive signal Pout[N] and avoid the coupling pull-down phenomenon before the arrival of the negative pulse.

[0092] Specifically, the capacitance of the first capacitor C2 can be greater than or equal to 50fF. The capacitance of the second capacitor C1 can be greater than or equal to 100fF.

[0093] The ratio of the channel width to the channel length of the pull-up transistor T6 is greater than 30:1, which helps to further ensure the output stability of the Nth negative pulse gate drive signal Pout[N]. The pull-up transistor T6 can be a P-channel thin-film transistor.

[0094] In one embodiment, the cascade signal selection module 10 includes transistors T13 and T12. One of the sources or drains of transistor T13 is electrically connected to a low-potential line, and the other of the sources or drains of transistor T13 is electrically connected to the input terminal of the pull-up control module 20. The first gate of transistor T13 is electrically connected to the start control line or the NY-level positive pulse gate drive line, and the first gate of transistor T13 is electrically connected to the second gate of transistor T13. Transistor T13 is an N-channel thin-film transistor. One of the sources or drains of transistor T12 is electrically connected to a high-potential line, and the other of the sources or drains of transistor T12 is electrically connected to the other of the sources or drains of transistor T13. The gate of transistor T12 is electrically connected to the first gate of transistor T13. Transistor T12 is a P-channel thin-film transistor.

[0095] It should be noted that in this embodiment, the stage transmission signal selection module 10 not only has an inverse function, that is, the input signal and the output signal have opposite potentials at the same time, but also serves to make the Nth stage positive pulse gate drive signal Nout[N] serve as the stage transmission signal between shift registers. Otherwise, stage transmission cannot be achieved between shift registers, which will cause the gate drive circuit to fail to provide the corresponding gate drive signal normally.

[0096] The ratio of the channel width to the channel length of transistor T13 is greater than 2:1. The ratio of the channel width to the channel length of transistor T12 ranges from 0.5:1 to 3:1.

[0097] The high-potential line is used to transmit the high-potential signal VGH, which can control the N-channel thin-film transistor to turn on or the P-channel thin-film transistor to turn off. The low-potential line is used to transmit the low-potential signal VGL, which can control the P-channel thin-film transistor to turn on or the N-channel thin-film transistor to turn off.

[0098] In one embodiment, the pull-up control module 20 includes a pull-up control transistor T2, one of the source or drain of the pull-up control transistor T2 is electrically connected to the output terminal of the transmission signal selection module 10, the other of the source or drain of the pull-up control transistor T2 is electrically connected to the input terminal of the pulse number reduction module 30, and the gate of the pull-up control transistor T2 is electrically connected to the first clock line.

[0099] It should be noted that the pull-up control transistor T2 can be a P-channel thin-film transistor. The ratio of the channel width to the channel length of the pull-up control transistor T2 ranges from 0.5:1 to 3:1.

[0100] In one embodiment, the first inverting module 50 includes transistor T3 and transistor T1. One of the sources or drains of transistor T3 is electrically connected to a high-potential line, the other of the sources or drains of transistor T3 is electrically connected to one of the sources or drains of transistor T1 and the control terminal of the pull-down module 60, the other of the sources or drains of transistor T1 is electrically connected to a low-potential line, and the output terminal of the pull-up control module 20 is electrically connected to the gate of transistor T3, the first gate of transistor T1, and the second gate of transistor T1.

[0101] It should be noted that transistor T3 is a P-channel thin-film transistor, and transistor T1 is a dual-gate N-channel thin-film transistor. This improves the dynamic performance of transistors T3 and T1, and consequently enhances the dynamic performance of the first inverting module 50.

[0102] The ratio of the channel width to the channel length of transistor T3 ranges from 0.5:1 to 3:1. The ratio of the channel width to the channel length of transistor T1 is greater than or equal to 2:1.

[0103] In one embodiment, the pull-down module 60 includes a pull-down transistor T7, one of the source or drain of the pull-down transistor T7 is electrically connected to a high-potential line, the other of the source or drain of the pull-down transistor T7 is electrically connected to the Nth negative pulse gate drive line, and the gate of the pull-down transistor T7 is electrically connected to the output terminal of the first inverting module 50, i.e., the fourth node P.

[0104] It should be noted that the pull-down transistor T7 can be a P-channel thin-film transistor. With the combined action of the pull-down module 60 and the pull-up module 40, the required Nth-level negative pulse gate drive signal Pout[N] can be modulated.

[0105] The ratio of the channel width to the channel length of the pull-down transistor T7 is greater than or equal to 30:1.

[0106] In one embodiment, the first transistor T9 is a P-channel thin-film transistor. The second transistor T10 is a dual-gate N-channel thin-film transistor. This improves the dynamic performance of the first transistor T9 and the second transistor T10, thereby improving the dynamic performance of the second output module 70.

[0107] The ratio of the channel width to the channel length of the first transistor T9 is greater than or equal to 30:1. The ratio of the channel width to the channel length of the second transistor T10 is greater than or equal to 30:1.

[0108] In one embodiment, the Nth-stage shift register further includes a leakage protection module 80, one end of which is electrically connected to the output of the pulse number reduction module 30, the other end of which is electrically connected to the control terminal of the pull-up module 40, and the control terminal of the leakage protection module 80 is electrically connected to the low-potential line.

[0109] It should be noted that the leakage protection module 80 can be used to prevent the charge of the third node Q from flowing to the node W, which helps to maintain the potential stability of the third node Q.

[0110] In one embodiment, the leakage protection module 80 includes a leakage protection transistor T8, one of the source or drain of the leakage protection transistor T8 is electrically connected to the output terminal of the pulse number reduction module 30, the other of the source or drain of the leakage protection transistor T8 is electrically connected to the control terminal of the pull-up module 40, and the gate of the leakage protection transistor T8 is electrically connected to a low potential line.

[0111] It should be noted that the leakage protection transistor T8 can be a P-channel thin-film transistor or an N-channel thin-film transistor. In the latter case, the gate of the leakage protection transistor T8 needs to be electrically connected to the high-potential line.

[0112] The ratio of the channel width to the channel length of the leakage protection transistor T8 ranges from 0.5:1 to 3:1.

[0113] In one embodiment, the Nth-stage shift register further includes a feedback module 90, which includes transistors T4 and T5. One of the sources or drains of transistor T4 is electrically connected to the output of pull-up control module 20, the gate of transistor T4 is electrically connected to the second clock line, the other of the sources or drains of transistor T4 is electrically connected to one of the sources or drains of transistor T5, the other of the sources or drains of transistor T5 is electrically connected to the high-potential line, and the gate of transistor T5 is electrically connected to the output of the first inverting module 50.

[0114] The ratio of the channel width to the channel length of transistor T4 ranges from 0.5:1 to 3:1. The ratio of the channel width to the channel length of transistor T5 also ranges from 0.5:1 to 3:1.

[0115] It should be noted that the feedback module 90 can maintain the second node K at a high potential based on the potential of the fourth node P and the potential of the second clock line. That is, when the fourth node P is at a low potential and the second clock signal CK is at a low potential, the high potential line can control the potential of the second node K to the potential of the high potential signal VGH.

[0116] It should be noted that the Nth positive pulse gate drive line is used to transmit the Nth positive pulse gate drive signal Nout[N]. The Nth negative pulse gate drive line is used to transmit the Nth negative pulse gate drive signal Pout[N]. The first clock line is used to transmit the first clock signal XCK. The second clock line is used to transmit the second clock signal CK. The start control line is used to transmit the start control signal STV. The NYth positive pulse gate drive line is used to transmit the NYth positive pulse gate drive signal Nout[NY]. The NXth positive pulse gate drive line is used to transmit the NXth positive pulse gate drive signal Nout[NX]. The reset line is used to transmit the reset signal RST.

[0117] The operation of the aforementioned shift register within a frame may include, for example: Figure 7 The following stages are shown:

[0118] Phase 1 S1: As Figure 7 , Figure 8 As shown, the start control signal STV, reset signal RST, and second clock signal CK are all at low potential, the first clock signal XCK is at high potential, the first node O, the second node K, and the third node Q are all at high potential, the fourth node P is at low potential, the Nth stage positive pulse gate drive signal Nout[N] is at low potential, and the Nth stage negative pulse gate drive signal Pout[N] is at high potential.

[0119] Phase 2 S2: As Figure 7 , Figure 9 As shown, the start control signal STV, reset signal RST, and first clock signal XCK are all at low potential, the second clock signal CK is at high potential, the first node O, the second node K, and the third node Q are all at high potential, the fourth node P is at low potential, the Nth stage positive pulse gate drive signal Nout[N] is at low potential, and the Nth stage negative pulse gate drive signal Pout[N] is at high potential.

[0120] Phase 3 S3: As Figure 7 , Figure 10 As shown, the start control signal STV and the first clock signal XCK are both at a low potential, the reset signal RST and the second clock signal CK are both at a high potential, the first node O, the second node K and the third node Q are both at a high potential, the fourth node P is at a low potential, the Nth positive pulse gate drive signal Nout[N] is at a low potential, and the Nth negative pulse gate drive signal Pout[N] is at a high potential.

[0121] Phase 4 S4: such as Figure 7 , Figure 11As shown, the start control signal STV and the second clock signal CK are both at low potential, the reset signal RST and the first clock signal XCK are both at high potential, the first node O, the second node K and the third node Q are both at high potential, the fourth node P is at low potential, the Nth positive pulse gate drive signal Nout[N] is at low potential, and the Nth negative pulse gate drive signal Pout[N] is at high potential.

[0122] Phase 5 S5: As Figure 7 , Figure 12 As shown, the reset signal RST and the second clock signal CK are both at low potential, the start control signal STV and the first clock signal XCK are both at high potential, the second node K and the third node Q are both at high potential, the first node O and the fourth node P are both at low potential, the Nth positive pulse gate drive signal Nout[N] is at low potential, and the Nth negative pulse gate drive signal Pout[N] is at high potential.

[0123] Phase 6 (S6): (e.g.) Figure 7 , Figure 13 As shown, the first clock signal XCK is at a low potential, the reset signal RST, the start control signal STV, and the second clock signal CK are all at a high potential, the second node K and the first node O are both at a low potential, the third node Q and the fourth node P are both at a high potential, the Nth positive pulse gate drive signal Nout[N] is at a high potential, and the Nth negative pulse gate drive signal Pout[N] is at a high potential.

[0124] Stage 7 (S7): Figure 7 , Figure 14 As shown, the start control signal STV and the second clock signal CK are both at low potential, the reset signal RST and the first clock signal XCK are both at high potential, the second node K is at low potential, the first node O, the third node Q and the fourth node P are all at high potential, the Nth positive pulse gate drive signal Nout[N] is at high potential, and the Nth negative pulse gate drive signal Pout[N] is at high potential.

[0125] Stage 8 S8: As Figure 7 , Figure 15 As shown, the reset signal RST, the start control signal STV, and the first clock signal XCK are all at a low potential, the second clock signal CK is at a high potential, the fourth node P is at a low potential, the third node Q and the second node K are both at a high potential, the Nth stage positive pulse gate drive signal Nout[N] is at a low potential, and the Nth stage negative pulse gate drive signal Pout[N] is at a high potential.

[0126] Stage 9 S9: As Figure 7 , Figure 16As shown, the reset signal RST and the second clock signal CK are both at low potential, the start control signal STV and the first clock signal XCK are at high potential, the first node O and the fourth node P are at low potential, the third node Q and the second node K are both at high potential, the Nth positive pulse gate drive signal Nout[N] is at low potential, and the Nth negative pulse gate drive signal Pout[N] is at high potential.

[0127] Stage 10 S10: As Figure 7 , Figure 17 As shown, the reset signal RST and the first clock signal XCK are both at a low level, the start control signal STV and the second clock signal CK are at a high level, the first node O, the third node Q, and the second node K are at a low level, the fourth node P is at a high level, the Nth positive pulse gate drive signal Nout[N] is at a high level, and the Nth negative pulse gate drive signal Pout[N] is at a high level.

[0128] Phase 11 S11: As Figure 7 , Figure 18 As shown, the start control signal STV, reset signal RST, and second clock signal CK are all at low potential, the first clock signal XCK is at high potential, the third node Q and the second node K are at low potential, the first node O and the fourth node P are at high potential, the Nth stage positive pulse gate drive signal Nout[N] is at high potential, and the Nth stage negative pulse gate drive signal Pout[N] is at low potential.

[0129] It should be noted that, Figures 8 to 18 The "cross" in the diagram indicates that the transistor it covers is in the off state, while the transistors not covered by the "cross" are in the on state. Figures 8 to 18 The dashed arrow in the diagram indicates the direction of the current.

[0130] since Figure 7 As can be seen from the data, the Nth-level positive pulse gate drive signal Nout[N] has a first positive pulse and a second positive pulse in sequence in one frame; the Nth-level negative pulse gate drive signal Pout[N] has a first negative pulse in one frame.

[0131] In a frame, the duration of the second positive pulse is longer than the duration of the first negative pulse, and the duration of the first negative pulse is within the duration of the second positive pulse.

[0132] Specifically, the falling edge of the second positive pulse and the rising edge of the first negative pulse occur at the same time.

[0133] In one embodiment, the phase difference between the first clock signal XCK and the second clock signal CK is 180°; a falling edge of the second clock signal CK, a falling edge of the second positive pulse, and a rising edge of the first negative pulse are all located within the duration of a positive pulse of the first clock signal XCK.

[0134] Figure 19 for Figure 3 The diagram shows a cascaded structure of different shift registers in a gate drive circuit. From top to bottom, the shift registers are arranged as follows: first shift register 101, second shift register 102, third shift register 103, fourth shift register 104, fifth shift register 105, sixth shift register 106, and so on. A first clock line is electrically connected to each shift register, and a second clock line is also electrically connected to each shift register.

[0135] The first shift register 101 outputs the corresponding first-stage negative pulse gate drive signal Pout[1] and first-stage positive pulse gate drive signal Nout[1] through the first-stage negative pulse gate drive line and the first-stage positive pulse gate drive line, respectively.

[0136] The second shift register 102 outputs the corresponding second-stage negative pulse gate drive signal Pout[2] and second-stage positive pulse gate drive signal Nout[2] through the second-stage negative pulse gate drive line and the second-stage positive pulse gate drive line, respectively.

[0137] The third shift register 103 outputs the corresponding third-level negative pulse gate drive signal Pout[3] and the third-level positive pulse gate drive signal Nout3 through the third-level negative pulse gate drive line and the third-level positive pulse gate drive line, respectively.

[0138] The fourth shift register 104 outputs the corresponding fourth-level negative pulse gate drive signal Pout[4] and fourth-level positive pulse gate drive signal Nout4 through the fourth-level negative pulse gate drive line and the fourth-level positive pulse gate drive line, respectively.

[0139] The fifth shift register 105 outputs the corresponding fifth-level negative pulse gate drive signal Pout[5] and fifth-level positive pulse gate drive signal Nout5 through the fifth-level negative pulse gate drive line and the fifth-level positive pulse gate drive line, respectively.

[0140] The sixth shift register 106 outputs the corresponding sixth-level negative pulse gate drive signal Pout[6] and sixth-level positive pulse gate drive signal Nout6] through the sixth-level negative pulse gate drive line and the sixth-level positive pulse gate drive line, respectively. The other shift registers can be deduced in the same way.

[0141] The input terminal (IN) of the intermediate signal selection module 10 in the first shift register 101 is electrically connected to the start control line to receive the start control signal STV. The input terminals (IN) of the intermediate signal selection modules 10 in other shift registers are all connected to the positive pulse gate drive signal of the previous stage. For example, the input terminal (IN) of the intermediate signal selection module 10 in the second shift register 102 is connected to the first stage positive pulse gate drive signal Nout[1], the input terminal (IN) of the intermediate signal selection module 10 in the third shift register 103 is connected to the second stage positive pulse gate drive signal Nout[2], the input terminal (IN) of the intermediate signal selection module 10 in the fourth shift register 104 is connected to the third stage positive pulse gate drive signal Nout[3], the input terminal (IN) of the intermediate signal selection module 10 in the fifth shift register 105 is connected to the fourth stage positive pulse gate drive signal Nout[4], and the input terminal (IN) of the intermediate signal selection module 10 in the sixth shift register 106 is connected to the fifth stage positive pulse gate drive signal Nout[5]. The others can be deduced in the same way.

[0142] The control terminal of the pulse number reduction module 30 in the fifth shift register 105 is connected to the first-stage positive pulse gate drive signal Nout[1], and the control terminal of the pulse number reduction module 30 in the sixth shift register 106 is connected to the second-stage positive pulse gate drive signal Nout[2]. The others can be deduced in the same way. Among them, X can also be 3, 4, 5, 6, 7, etc. Here, we take X equal to 4 as an example for explanation.

[0143] The outputs of the first shift register 101 to the fourth shift register 104 are not used to drive the corresponding pixel circuits for display, but are connected to dummy pixels or left floating. The outputs of the fifth shift register 105 are electrically connected to the pixel circuits of the first row, and the outputs of the sixth shift register 106 are electrically connected to the pixel circuits of the second row, and so on.

[0144] It should be noted that, since the outputs of some shift registers are connected to virtual pixels or are floating, the outputs of the Nth-level shift register are not connected to the Nth row of pixel circuits. Instead, the number of rows of pixel circuits to be connected needs to be determined based on the number of shift registers connected to virtual pixels or floating.

[0145] Figure 20The image above is a schematic diagram of the structure of a display panel in conventional technology. On the left side of the display area (AA area) (non-display area or bezel area), there are gate driving circuits for providing light emission control signal EM, gate driving signal Nscan1, and gate driving signal Pscan, respectively. On the right side of the display area (AA area) (non-display area or bezel area), there are gate driving circuits for providing gate driving signal Pscan, gate driving signal Nscan2, and gate driving signal Pscan2, respectively.

[0146] Each gate drive signal Pscan drives one row of pixel circuitry. Gate drive signals Nscan1 and Nscan2 operate in the same way as Pscan, but one Nscan1 / Nscan2 signal needs to drive two rows of pixel circuitry. In actual operation, to achieve a narrower bezel, both the gate drive circuits for outputting gate drive signal Nscan1 and Nscan2 are configured for single-sided driving. However, this results in a decrease in the driving capability of these two gate drive circuits and an increase in power consumption.

[0147] In view of this, this embodiment will Figure 3 The gate drive circuit shown is configured as follows: Figure 20 The lower part of the diagram shows a dual-drive system, which means that a [missing information - likely a specific type of drive] is set on each side of the AA area. Figure 3 The gate drive circuit in the circuit allows for simultaneous input of the corresponding gate drive signal from both ends of each gate drive line. This not only improves the driving capability of the Nth-level negative pulse gate drive signal Pout[N] and the positive pulse gate drive signal Nout, but also reduces power consumption and the bezel space occupied, which is beneficial for the development of narrower bezel solutions.

[0148] The positive pulse gate drive signal Nout includes the Nth level positive pulse gate drive signal Nout[N] and the NLth level positive pulse gate drive signal Nout[NL]. L can be an integer greater than or equal to 1, such as 2, 3, 4, 5, 6, etc.

[0149] In one embodiment, this embodiment provides a display panel, which includes the gate driving circuit and pixel circuit of at least one embodiment above, and a row of pixel circuits is electrically connected to the Nth positive pulse gate driving line and the Nth negative pulse gate driving line.

[0150] It is understood that, since the display panel provided in this embodiment includes the gate driving circuit of at least one of the above embodiments, it can also increase the potential of the second terminal of the second transistor T10 and reduce the on-state current of the second transistor T10 when the first transistor T9 is turned on by connecting the boost module 72 in series between the second terminal of the second transistor T10 and the low potential line, thereby increasing and stabilizing the pulse amplitude of the second gate driving signal. Simultaneously, by increasing the potential of the second terminal of the second transistor T10, the negative bias of the threshold voltage of the second transistor T10 can be improved, thereby increasing the negative bias range of the threshold voltage of the second transistor T10, avoiding abnormalities in the second gate driving signal, and thus improving the reliability of the gate driving circuit or the display panel.

[0151] Furthermore, the second gate drive signal with a larger number of pulses can be output through the stage transmission signal selection module 10, the pull-up control module 20, and the second output module 70. At the same time, the second gate drive signal can also be selected as the stage transmission signal between different shift registers. Moreover, the first gate drive signal with a smaller number of pulses can be output through the stage transmission signal selection module 10, the pull-up control module 20, the pulse number reduction module 30, the first inverting module 50, and the first output module 46. This can meet the needs of the corresponding pixel circuit for the pulses of the gate drive signal in terms of time and number in one frame, thereby driving the pixel circuit to achieve image quality display.

[0152] Figure 21 for Figure 20 The schematic diagram of the pixel circuit in the display panel shown illustrates that... Figure 3 The gate drive circuit shown can be Figure 21 The pixel circuit shown provides the corresponding Nth positive pulse gate drive signal Nout[N], NLth positive pulse gate drive signal Nout[NL], and Nth negative pulse gate drive signal Pout[N].

[0153] Figure 21 The pixel circuit shown may include at least one of the following: a write transistor T2P, a drive transistor T1P, a first light-emitting control transistor T5P, a second light-emitting control transistor T6P, a first initialization transistor T4P, a second initialization transistor T7P, a third initialization transistor T8P, a compensation transistor T3P, a light-emitting device D1, a storage capacitor Cst, and a bootstrap capacitor Cboost.

[0154] The first power line is electrically connected to the first terminal of the first light-emitting control transistor T5P and one end of the storage capacitor Cst. The second terminal of the first light-emitting control transistor T5P is electrically connected to the first terminal of the driving transistor T1P and the first terminal of the write transistor T2P. The second terminal of the driving transistor T1P is electrically connected to the first terminal of the compensation transistor T3P and the first terminal of the second light-emitting control transistor T6P. The second terminal of the second light-emitting control transistor T6P is electrically connected to the first terminal of the second initialization transistor T7P and the anode of the light-emitting device D1. The cathode of the light-emitting device D1 is electrically connected to the second power line. The light-emitting control line is electrically connected to the gate of the first light-emitting control transistor T5P and the gate of the second light-emitting control transistor T6P. The second terminal of the write transistor T2P is electrically connected to the data line. The gate of the write transistor T2P is electrically connected to the Nth negative pulse gate drive line (first gate drive line) and one end of the bootstrap capacitor Cboost. The second terminal of the second initialization transistor T7P is electrically connected to the second initialization line. The gate of the second initialization transistor T7P is electrically connected to the third gate drive line. The second terminal of the compensation transistor T3P is electrically connected to the gate of the driving transistor T1P, and the gate of the compensation transistor T3P is electrically connected to the Nth-level positive pulse gate drive line (the second gate drive line). The gate of the driving transistor T1P is electrically connected to the other end of the storage capacitor Cst, the other end of the bootstrap capacitor Cboost, and the first terminal of the first initialization transistor T4P. The second terminal of the first initialization transistor T4P is electrically connected to the first initialization line, and the gate of the first initialization transistor T4P is electrically connected to the NLth-level positive pulse gate drive line (the second gate drive line). The first terminal of the third initialization transistor T8P is electrically connected to the first terminal of the driving transistor T1P, and the second terminal of the third initialization transistor T8P is electrically connected to the third initialization line. The gate of the third initialization transistor T8P shares the third gate drive line with the gate of the second initialization transistor T7P.

[0155] It should be noted that the second initialization line can also be replaced with the first initialization line, which can reduce the number of traces required for the pixel circuit and help increase the density of the pixel circuit in the display panel.

[0156] In this configuration, the first electrode can be either the source or the drain, and the second electrode can be either the source or the drain. For example, when the first electrode is the source, the second electrode is the drain; or, when the first electrode is the drain, the second electrode is the source.

[0157] The system includes the following components: a first power line for transmitting the positive power signal VDD, a second power line for transmitting the negative power signal VSS (with the potential of VDD higher than that of VSS), a data line for transmitting the data signal Data, a light emission control line for transmitting the light emission control signal EM, a first initialization line for transmitting the first initialization signal Vi1, a second initialization line for transmitting the second initialization signal, a third initialization line for transmitting the third initialization signal Vi3, a first gate drive line for transmitting the Nth-level negative pulse gate drive signal Pout[N], a second gate drive line for transmitting the Nth-level positive pulse gate drive signal Nout[N], a third gate drive line for transmitting the gate drive signal Pscan2.

[0158] Figure 21 The timing sequence of the pixel circuit shown in one frame is as follows: Figure 22 As shown, under the combined drive of the Nth-level negative pulse gate drive signal Pout[N], the gate drive signal Pscan2, the NLth-level positive pulse gate drive signal Nout[NL], the Nth-level positive pulse gate drive signal Nout[N], and the light emission control signal EM, Figure 21 The pixel circuit shown can display normally.

[0159] Among them, the Nth level negative pulse gate drive signal Pout[N], the NLth level positive pulse gate drive signal Nout[NL], and the Nth level positive pulse gate drive signal Nout[N] can be derived from... Figure 3 The gate drive circuit shown is used to provide this.

[0160] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0161] The gate driving circuit and display panel provided in the embodiments of this application have been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of this application. The description of the above embodiments is only for the purpose of helping to understand the technical solutions and core ideas of this application. Those skilled in the art should understand that they can still modify the technical solutions described in the foregoing embodiments or make equivalent substitutions for some of the technical features. These modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A gate driving circuit, characterized in that, The gate drive circuit includes multiple shift registers, the shift registers including: A cascaded signal selection module, wherein the cascaded signal selection module is electrically connected between the first wiring and the first node; A pull-up control module controls the potential of the second node based on the potential of the first node and the potential of the first clock signal; A pulse count reduction module is electrically connected between the second node and the third node, and the control terminal of the pulse count reduction module is electrically connected to the reset line. A first inverter module is connected between the second node and the fourth node; The first output module outputs a first gate drive signal based on the potential of the third node and the potential of the fourth node. The second output module includes a P-channel first transistor and an N-channel second transistor. The first terminal of the first transistor is electrically connected to a high-potential line, and the gate of the first transistor is electrically connected to the second node. The first terminal of the second transistor is electrically connected to the second terminal of the first transistor to output a second gate drive signal, and the gate of the second transistor is electrically connected to the gate of the first transistor. A boosting module is connected in series between the second terminal of the second transistor and the low potential line, and the control terminal of the boosting module is electrically connected to the gate of the second transistor.

2. The gate driving circuit according to claim 1, characterized in that, The boost module includes at least one transistor, which is connected in series between the second terminal of the second transistor and the low potential line, and each gate of the at least one transistor is electrically connected to the gate of the second transistor.

3. The gate driving circuit according to claim 2, characterized in that, The at least one transistor includes a third transistor, the first terminal of the third transistor is electrically connected to the second terminal of the second transistor, the second terminal of the third transistor is electrically connected to the low potential line, the gate of the third transistor is electrically connected to the gate of the second transistor, and the channel type of the third transistor is the same as that of the second transistor.

4. The gate driving circuit according to claim 3, characterized in that, The gate of the second transistor and the gate of the third transistor both include a first gate and a second gate. The second node is electrically connected to the first gate of the second transistor, the second gate of the second transistor, the first gate of the third transistor, and the second gate of the third transistor.

5. The gate driving circuit according to claim 4, characterized in that, When the third transistor is turned on, the potential of the second terminal of the second transistor is less than or equal to -6.7V; both the second transistor and the third transistor are indium gallium zinc oxide thin film transistors.

6. The gate driving circuit according to claim 4, characterized in that, The channel width-to-length ratio of the third transistor is greater than or equal to 8.57 and less than or equal to 20; both the second transistor and the third transistor are indium gallium zinc oxide thin film transistors.

7. The gate driving circuit according to claim 3, characterized in that, The at least one transistor further includes a fourth transistor, the first terminal of the fourth transistor being electrically connected to the second terminal of the third transistor, the second terminal of the fourth transistor being electrically connected to the low potential line, the gate of the fourth transistor being electrically connected to the gate of the second transistor, and the channel type of the fourth transistor being the same as that of the third transistor.

8. The gate driving circuit according to any one of claims 1-7, characterized in that, The boost module is used to raise the potential of the second electrode of the second transistor when the potential of the second node is low.

9. The gate driving circuit according to any one of claims 1-7, characterized in that, The boost module is used to increase and stabilize the high potential of the second gate drive signal.

10. A display panel, characterized in that, The display panel includes: Pixel circuit, the pixel circuit including a write transistor for controlling data signal input and a compensation transistor for controlling the data signal input to the gate of a drive transistor; and In the gate driving circuit according to any one of claims 1-9, the output terminal of the first output module is electrically connected to the gate of the write transistor, and the output terminal of the second output module is electrically connected to the gate of the compensation transistor.

Images