Pixel compensation circuit, pixel compensation method and display panel

Abstract

This application provides a pixel compensation circuit, a pixel compensation method, and a display panel, relating to the field of display technology. It solves the problems of numerous scanning signal lines and complex timing in current compensation circuits. The pixel compensation circuit of this application includes a first switching transistor, a driving transistor, a compensation transistor, a second switching transistor, a third switching transistor, a first reset transistor, a second reset transistor, a capacitor, and a light-emitting device. Through the function of the first and second reset transistors, the gate terminal of the driving transistor can be reset more thoroughly, which is beneficial to improving the circuit compensation capability. Furthermore, the structure of the pixel compensation circuit of this application uses fewer control signal lines, which is more conducive to the realization of narrow bezel products.

Description

Technical Field

[0001] This application relates to the field of display technology, specifically to a pixel compensation circuit, a pixel compensation method, and a display panel. Background Technology

[0002] Traditional liquid crystal displays (LCDs) are voltage-driven devices, while organic light-emitting diodes (OLEDs), mini-LEDs, and micro-LEDs are current-driven. OLEDs are more sensitive to electrical variations in thin-film transistors (TFTs). The uniformity of the threshold voltage (Vth) of the driving transistors in the display panel and the drift of Vth under forward bias stress both affect the accuracy and uniformity of the image display. To address the Vth offset problem, a compensation circuit design is introduced.

[0003] Large-size panels employ external compensation schemes, which are relatively expensive. In contrast, small-to-medium-sized low-temperature polysilicon (LTPS) thin-film transistor liquid crystal display panels typically use internal compensation circuits. For example, some manufacturers currently use 7T3C internal compensation circuits, while others use 6T3C internal compensation circuits, both of which can achieve internal Vth compensation. However, some 6T3C internal compensation circuits lack sufficient reset capability and require additional light-emitting control signal lines during the reset phase to reset the drain of the driving transistor. Summary of the Invention

[0004] This application provides a pixel compensation circuit, a pixel compensation method, and a display panel that can compensate for the threshold voltage in the driving transistor and uses fewer light-emitting control signal lines.

[0005] On one hand, this application provides a pixel compensation circuit, including a first switching transistor, a driving transistor, a compensation transistor, a second switching transistor, a third switching transistor, a first reset transistor, a second reset transistor, a capacitor, and a light-emitting device;

[0006] The gate of the first switching transistor is electrically connected to the first-stage scan line, the source of the first switching transistor is electrically connected to the data line, and the drain of the first switching transistor is electrically connected to the first node. The first-stage scan line is used to provide a first scan signal, and the data line is used to provide a data signal.

[0007] The gate of the driving transistor is electrically connected to the third node, the source of the driving transistor is electrically connected to the second node, and the drain of the driving transistor is electrically connected to the first node.

[0008] The gate of the compensation transistor is electrically connected to the second-stage scan line, the source of the compensation transistor is electrically connected to the second node, and the drain of the compensation transistor is electrically connected to the third node. The second-stage scan line is used to provide a second scan signal.

[0009] The second switching transistor includes a first control terminal and a second control terminal. The first control terminal is electrically connected to the first-stage scan line, and the second control terminal is electrically connected to the control signal line. The input terminal of the second switching transistor is electrically connected to the positive terminal of the power supply, and the output terminal of the second switching transistor is electrically connected to the second node.

[0010] The gate of the third switching transistor is electrically connected to the control signal line, the source of the third switching transistor is electrically connected to the first node, the drain of the third switching transistor is electrically connected to the light-emitting device and forms a fourth node at the electrical connection point, and the other end of the light-emitting device is electrically connected to the negative terminal of the power supply.

[0011] The gate of the first reset transistor is electrically connected to the first-level scan line, the source of the first reset transistor is electrically connected to the third node, and the drain of the first reset transistor is electrically connected to the reset signal line, forming a fifth node at the connection point.

[0012] The gate of the second reset transistor is electrically connected to the first scan line, the source of the second reset transistor is electrically connected to the fifth node, and the drain of the second reset transistor is electrically connected to the fourth node.

[0013] In one possible implementation of this application, the first-level scan line and the second-level scan line are parallel and shared scan signal lines.

[0014] In one possible implementation of this application, the second-level scan line, the first-level scan line, and the control signal line are combined to correspond sequentially to the reset stage, the data writing stage, and the light emission stage.

[0015] In one possible implementation of this application, during the reset phase, the first-level scan line is at a high level, the second-level scan line is at a low level, and the control signal line is at a low level.

[0016] In one possible implementation of this application, the second switching transistor, the first reset transistor, and the second reset transistor are all in the on state, while the first switching transistor, the third switching transistor, and the compensation transistor are all in the off state.

[0017] In one possible implementation of this application, during the data writing stage, the first-level scan line is at a low level, the second-level scan line is at a high level, and the control signal line is at a low level.

[0018] In one possible implementation of this application, during the data writing phase, both the first switching transistor and the compensation transistor are in the ON state, while the second switching transistor, the first reset transistor, the second reset transistor, and the third switching transistor are all in the OFF state.

[0019] In one possible implementation of this application, during the light emission stage, the first-level scan line, the second-level scan line, and the control signal line are all at a high level.

[0020] In one possible implementation of this application, during the light-emitting stage, the second switching transistor, the third switching transistor, the first switching transistor, the compensation transistor, the first reset transistor, and the second reset transistor are all in the on state.

[0021] On the other hand, this application provides a pixel compensation method, the pixel compensation method comprising:

[0022] Provide the pixel compensation circuit as described above;

[0023] Upon entering the reset phase, the first-level scan line provides a high level, the second-level scan line provides a low level, the control signal line provides a low level, the second switching transistor, the first reset transistor, and the second reset transistor are all in the on state, the first switching transistor, the third switching transistor, and the compensation transistor are all in the off state, the second node is written with a positive power supply voltage, and the fifth and third nodes are written with a reset voltage.

[0024] Upon entering the data writing stage, the first-level scan line provides a low level, the second-level scan line provides a high level, the control signal line provides a low level, the first switching transistor and the compensation transistor are both in the on state, the second switching transistor, the first reset transistor, the second reset transistor and the third switching transistor are all in the off state, the first node writes the data signal, and the voltage of the third node changes to the first voltage, where is the data signal input by the data line, and is the threshold voltage of the driving transistor;

[0025] Upon entering the light-emitting stage, the first-level scan line, the second-level scan line, and the control signal line all provide a high level. The second switching transistor, the third switching transistor, the first switching transistor, the compensation transistor, the first reset transistor, and the second reset transistor are all in the on state. The first voltage of the third node is consumed. The first voltage includes the threshold voltage of the driving transistor, and the light-emitting device emits light.

[0026] On the other hand, this application provides a display panel, which includes the pixel compensation circuit as described or employs the pixel compensation method as described.

[0027] This application adds a first reset transistor. During the reset phase, the gate of the driving transistor is reset more thoroughly through the action of the first and second reset transistors, which helps to improve the circuit compensation capability. Since the second switching transistor includes a first control terminal and a second control terminal, during the reset phase, the back channel of the second switching transistor is opened at the same time, and the positive terminal of the power supply is input to the drain of the driving transistor to prepare for the next compensation cycle. Therefore, this application can compensate for the drain effect of the pre-reset driving transistor T2 while using fewer control signal lines EM, which is more conducive to the realization of narrow bezel products. Attached Figure Description

[0028] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0029] Figure 1 This is a circuit diagram of a pixel compensation circuit provided in an embodiment of this application;

[0030] Figure 2 This is a timing diagram of a pixel compensation circuit provided in an embodiment of this application;

[0031] Figure 3 This is a circuit diagram of a pixel compensation circuit provided in an embodiment of this application;

[0032] Figure 4 This is a timing diagram of a pixel compensation circuit provided in an embodiment of this application. Detailed Implementation

[0033] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0034] In the description of this invention, it should be understood that the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, features defined as "first" or "second" may explicitly or implicitly include one or more of the stated features. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0035] In this application, the term "exemplary" is used to mean "serving as an example, illustration, or description." Any embodiment described as "exemplary" in this application is not necessarily to be construed as being more preferred or advantageous than other embodiments. The following description is provided to enable any person skilled in the art to make and use the invention. Details are set forth in the following description for purposes of explanation. It should be understood that those skilled in the art will recognize that the invention can be made without using these specific details. In other instances, well-known structures and processes will not be described in detail to avoid obscuring the description of the invention with unnecessary detail. Therefore, the invention is not intended to be limited to the embodiments shown, but is consistent with the broadest scope of the principles and features disclosed in this application.

[0036] This application provides a pixel compensation circuit, a pixel compensation method, and a display panel, which will be described in detail below.

[0037] like Figure 1 As shown, this is a schematic diagram of an embodiment of the pixel compensation circuit in this application. The pixel compensation circuit includes a first switching transistor T3, a driving transistor T2, a compensation transistor T5, a second switching transistor T1, a third switching transistor T4, a first reset transistor T6, a second reset transistor T7, a capacitor C1, and a light-emitting device LED.

[0038] Among them, the first switching transistor T3 is a control switching transistor used to control the writing of data signals into the pixel compensation circuit, the driving transistor T2 is a driving transistor used to drive the light-emitting device LED to emit light, the compensation transistor T5 is a compensation transistor used to compensate the threshold voltage in the driving transistor T2, the second switching transistor T1 and the third switching transistor T4 are control switching transistors used to control the light-emitting device LED to emit light, and the first reset transistor T6 and the second reset transistor T7 are second reset transistors used to control the reset of the pixel compensation circuit.

[0039] The gate of the first switching transistor T3 is electrically connected to the first-stage scan line GN-1, the source of the first switching transistor T3 is electrically connected to the data line Vdata, and the drain of the first switching transistor T3 is electrically connected to the first node Vm. The first-stage scan line GN-1 is used to provide the first scan signal, and the data line Vdata is used to provide the data signal.

[0040] The gate of driving transistor T2 is electrically connected to the third node Vg, the source of driving transistor T2 is electrically connected to the second node Vn, and the drain of driving transistor T2 is electrically connected to the first node Vm.

[0041] The gate of compensation transistor T5 is electrically connected to the second-stage scan line GN, the source of compensation transistor T5 is electrically connected to the second node Vn, and the drain of compensation transistor T5 is electrically connected to the third node Vg. The second-stage scan line GN is used to provide the second scan signal.

[0042] In the pixel compensation circuit structure, the first-level scan line GN-1 and the second-level scan line GN are parallel and independently transmitting scan signal lines. In this embodiment, the first-level scan line GN-1 and the second-level scan line GN can also be shared. Therefore, the required row scan level transmission signal is less, which further reduces the failure problem caused by leakage current in the circuit, improves the overall stability of the display panel driving circuit, and further reduces the number of array substrate row driving (GateDriver On Array, GOA) circuits, thereby helping to reduce the product bezel width and realize narrow bezel products.

[0043] In this embodiment, the second switching transistor T1 is a four-terminal driver device with a first control terminal and a second control terminal. Specifically, the first control terminal of the second switching transistor T1 is electrically connected to the first-level scan line GN-1, the second control terminal of the second switching transistor T1 is electrically connected to the control signal line EM, the input terminal of the second switching transistor T1 is electrically connected to the positive power supply VDD, and the output terminal of the second switching transistor T1 is electrically connected to the second node Vn.

[0044] The gate of the third switching transistor T4 is electrically connected to the control signal line EM, the source of the third switching transistor T4 is electrically connected to the first node Vm, the drain of the third switching transistor is electrically connected to the light-emitting device LED and forms the fourth node Vs at the electrical connection point, and the other end of the light-emitting device LED is electrically connected to the negative terminal of the power supply VSS.

[0045] The gate of the first reset transistor T6 is electrically connected to the first-stage scan line GN-1, the source of the first reset transistor T6 is electrically connected to the third node Vg, and the drain of the first reset transistor T6 is electrically connected to the reset signal line Vini, forming the fifth node Va at the connection point.

[0046] The gate of the second reset transistor T7 is electrically connected to the first-level scan line GN-1, the source of the second reset transistor T7 is electrically connected to the fifth node Va, and the drain of the second reset transistor T7 is electrically connected to the fourth node Vs.

[0047] The storage capacitor C1 is electrically connected between the third node Vg and the fourth node Vs.

[0048] In summary, the pixel compensation circuit of this embodiment adopts a 7T1C architecture. The first switching transistor T3, the driving transistor T2, the compensation transistor T5, the second switching transistor T1, the third switching transistor T4, the first reset transistor T6, and the second reset transistor T7 can all be N-channel thin film transistors (TFTs), N-channel amorphous silicon transistors (a-Si), N-channel low-temperature polysilicon transistors (N-LTPS), or N-channel metal-oxide-semiconductor field-effect transistors (MOSFETs), or P-channel thin film transistors, P-channel low-temperature polysilicon transistors (P-LTPS), P-channel metal-oxide-semiconductor field-effect transistors, etc. This embodiment does not make specific limitations on these.

[0049] In this embodiment, the driving transistor T2 serves as the driving transistor in the pixel compensation circuit for driving the LED light-emitting device. The pixel compensation circuit proposed in this application can compensate for the threshold voltage of the driving transistor (i.e., driving transistor T2). In this embodiment, the second-level scan line GN, the first-level scan line GN-1, the reset signal line Vini, and the control signal line EM are all controlled by an external timing controller.

[0050] In the pixel compensation circuit of this application, compared with the existing pixel compensation circuit, a first reset transistor T6 is added. During the reset phase, through the action of the first reset transistor T6 and the second reset transistor T7, the gate terminal of the driving transistor T2 is reset more thoroughly, which is beneficial to improving the circuit compensation capability. At the same time, the back channel of the second switching transistor T1 is opened, and VDD is input to the drain of the driving transistor T2 to prepare for the next compensation cycle. Therefore, compared with the existing 6T1C architecture, this application can compensate for the drain effect of the pre-reset driving transistor T2 while using fewer control signal lines EM.

[0051] In this embodiment, as Figure 2 As shown, the combination of the second-stage scan line GN, the first-stage scan line GN-1, and the control signal line EM corresponds sequentially to the reset stage, the data writing stage, and the light emission stage. The potential changes during the reset, data writing, and light emission stages, and how to compensate for the threshold voltage of the driving transistor, will be analyzed in detail below.

[0052] During the reset phase, the first-level scan line GN-1 is at a high level, the second-level scan line GN is at a low level, and the control signal line EM is at a low level.

[0053] During this stage, the first-stage scan line GN-1, which is electrically connected to the gates of the second switching transistor T1, the first reset transistor T6, and the second reset transistor T7, is at a high level, and the second switching transistor T1, the first reset transistor T6, and the second reset transistor T7 are all in the on state. The second-stage scan line GN, which is electrically connected to the gates of the first switching transistor T3 and the compensation transistor T5, is at a low level, and the first switching transistor T3 and the compensation transistor T5 are in the off state. The control signal line EM, which is electrically connected to the third switching transistor T4, is at a low level, and the third switching transistor T4 is in the off state.

[0054] Therefore, at this time, the second node Vn writes the positive power supply voltage VDD, the fifth node Va and the third node Vg write the reset voltage Vini, and the light-emitting device LED does not emit light.

[0055] During the data writing phase, the first-level scan line GN-1 is at a low level, the second-level scan line GN is at a high level, and the control signal line EM is at a low level.

[0056] The first-stage scan line GN-1, which is electrically connected to the gates of the second switching transistor T1, the first reset transistor T6, and the second reset transistor T7, is at a low level. At this time, the second switching transistor T1, the first reset transistor T6, and the second reset transistor T7 are all in the off state. The second-stage scan line GN, which is electrically connected to the gates of the first switching transistor T3 and the compensation transistor T5, is at a high level. At this time, the first switching transistor T3 and the compensation transistor T5 are in the on state. The control signal line EM, which is electrically connected to the third switching transistor T4, is at a low level. At this time, the third switching transistor T4 is in the off state.

[0057] Therefore, at this time, the first node Vm writes the data signal Vdata, and the positive power supply voltage VDD written by the second node Vn during the reset phase begins to discharge until the gate-source voltage of the driving transistor T2 changes to the threshold voltage Vth of the driving transistor T2, and the driving transistor T2 is turned off. At this time, the voltage change of the third node Vg is the drain voltage Vd of the driving transistor T2 (that is, the sum of the data signal Vdata at the first node Vm and the threshold voltage Vth of the driving transistor T2). That is, the voltage of the third node Vg changes to the first voltage V1, V1 = Vdata + Vth. After decreasing to this voltage, the voltage of the third node Vg no longer changes. At this moment, the voltage of the third node Vg contains the threshold voltage Vth information of the driving transistor T2. Since the driving transistor T2 and the third switching transistor T4 are still in the off state, the light-emitting device LED does not emit light.

[0058] During the light emission stage, the first-level scan line GN-1, the second-level scan line GN, and the control signal line EM are all at a high level.

[0059] Since the first-level scan line GN-1, the second-level scan line GN, and the control signal line EM are all at high level, the second switching transistor T1 and the third switching transistor T4 are both in the on state. Before the light-emitting stage, the voltage at the gate of the driving transistor T2 is the voltage of the third node Vg, i.e., the first voltage V1, V1 = Vdata + Vth. The voltage of the fourth node Vs is the reset voltage. When the timing changes to the light-emitting stage, the source-drain voltage T2_Vgs of the driving transistor T2 is the voltage difference between the third node Vg and the fourth node Vs. Therefore, the source-drain voltage T2_Vgs of the driving transistor T2 at this moment is = Vdata + Vth - Vini, where Vdata is the data signal input by the data line Vdata, Vth is the threshold voltage of the driving transistor T2, and Vini is the reset voltage. The driving transistor T2 is turned on, and the first voltage V1 of the third node Vg is consumed. Since the first voltage V1 includes the threshold voltage Vth of the driving transistor T2, the light-emitting device LED emits light.

[0060] The current flowing through the LED is Ioled = k*(Vdata - Vini). 2 , k can be a parameter related to the size of each switch or the carrier mobility, etc., and is not specifically limited here. Therefore, the current value passing through the light-emitting device LED is independent of the threshold voltage of the driving transistor, thus achieving compensation for the threshold voltage of the driving transistor.

[0061] In another embodiment of this application, such as Figure 3 As shown, the pixel compensation circuit also includes a third switching transistor T8 and a storage capacitor C2. The source of the third switching transistor T8 is electrically connected to the data line Vdata, and the drain of the third switching transistor T8 is electrically connected to the source of the first switching transistor T3. One end of the storage capacitor C2 is electrically connected to the connection point between the third switching transistor T8 and the first switching transistor T3, and the other end of the storage capacitor C2 is grounded.

[0062] and Figure 1 The pixel compensation circuit proposed in the previous embodiment differs in that the first switching transistor T3, the third switching transistor T8, and the storage capacitor C2 together constitute a global light-emitting unit, and the global signal lines (nth level scan line GN, scan line Scan, write signal line WR, and control signal line EM) in the display driving circuit are used as driving signal lines, which further facilitates the reduction of product bezel width and the realization of narrow bezel products.

[0063] like Figure 4 As mentioned above, during the normal transmission process of the second-level scan line GN, Vdata will be written to the connection point between the third switching transistor T8 and the first switching transistor T3, and then participate in compensation when the write signal line WR is turned on, thereby further improving the compensation capability of the pixel compensation circuit.

[0064] In another embodiment of this application, a pixel compensation method is also provided, such as... Figure 1 and Figure 2 As shown, pixel compensation methods include 101 to 104:

[0065] 101. Provide a pixel compensation circuit as described above;

[0066] The pixel compensation circuit includes a first switching transistor T3, a driving transistor T2, a compensation transistor T5, a second switching transistor T1, a third switching transistor T4, a first reset transistor T6, a second reset transistor T7, a capacitor C1, and a light-emitting device LED.

[0067] 102. Upon entering the reset phase, the first-stage scan line GN-1 provides a high level, the second-stage scan line GN provides a low level, the control signal line EM provides a low level, the second switching transistor T1, the first reset transistor T6, and the second reset transistor T7 are all in the on state, the first switching transistor T3, the third switching transistor T4, and the compensation transistor T5 are all in the off state, the second node Vn is written with the positive power supply voltage VDD, and the fifth node Va and the third node Vg are written with the reset voltage Vini.

[0068] 103. Entering the data writing stage, the first-level scan line GN-1 provides a low level, the second-level scan line GN provides a high level, the control signal line EM provides a low level, the first switching transistor T3 and the compensation transistor T5 are both in the on state, the second switching transistor T1, the first reset transistor T6, the second reset transistor T7 and the third switching transistor T4 are all in the off state, the first node Vm writes the data signal, and the voltage of the third node Vg changes to the first voltage V1, V1 = Data + Vth, where Data is the data signal input by the data line Vdata, and Vth is the threshold voltage of the driving transistor T2.

[0069] 104. Upon entering the light-emitting stage, the first-level scan line GN-1, the second-level scan line GN, and the control signal line EM all provide a high level. The second switching transistor T1, the third switching transistor T4, the first switching transistor T3, the compensation transistor T5, the first reset transistor T6, and the second reset transistor T7 are all in the on state. The first voltage V1 of the third node Vg is consumed. The first voltage V1 includes the threshold voltage Vth of the driving transistor T2, and the light-emitting device LED emits light.

[0070] Therefore, the current value passing through the LED is independent of the threshold voltage of the driving transistor, thus achieving compensation for the threshold voltage of the driving transistor.

[0071] In another embodiment of this application, a display panel is provided, which includes the pixel compensation circuit described above.

[0072] The pixel compensation circuit, pixel compensation method, and display panel provided in the embodiments of this application have been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only for the purpose of helping to understand the method and core ideas of the present invention. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of the present invention. Therefore, the content of this specification should not be construed as a limitation of the present invention.

Claims

1. A pixel compensation circuit, characterized in that, It includes a first switching transistor, a driving transistor, a compensation transistor, a second switching transistor, a third switching transistor, a first reset transistor, a second reset transistor, a capacitor, and a light-emitting device; The gate of the first switching transistor is electrically connected to the first-stage scan line, the source of the first switching transistor is electrically connected to the data line, and the drain of the first switching transistor is electrically connected to the first node. The first-stage scan line is used to provide a first scan signal, and the data line is used to provide a data signal. The gate of the driving transistor is electrically connected to the third node, the source of the driving transistor is electrically connected to the second node, and the drain of the driving transistor is electrically connected to the first node. The gate of the compensation transistor is electrically connected to the second-stage scan line, the source of the compensation transistor is electrically connected to the second node, and the drain of the compensation transistor is electrically connected to the third node. The second-stage scan line is used to provide a second scan signal. The second switching transistor includes a first control terminal and a second control terminal. The first control terminal is electrically connected to the first-stage scan line, and the second control terminal is electrically connected to the control signal line. The input terminal of the second switching transistor is electrically connected to the positive terminal of the power supply, and the output terminal of the second switching transistor is electrically connected to the second node. The gate of the third switching transistor is electrically connected to the control signal line, the source of the third switching transistor is electrically connected to the first node, the drain of the third switching transistor is electrically connected to the light-emitting device and forms a fourth node at the electrical connection point, and the other end of the light-emitting device is electrically connected to the negative terminal of the power supply. The gate of the first reset transistor is electrically connected to the first-level scan line, the source of the first reset transistor is electrically connected to the third node, and the drain of the first reset transistor is electrically connected to the reset signal line, forming a fifth node at the connection point. The gate of the second reset transistor is electrically connected to the first scan line, the source of the second reset transistor is electrically connected to the fifth node, and the drain of the second reset transistor is electrically connected to the fourth node. The capacitor is electrically connected between the third node and the fourth node.

2. The pixel compensation circuit as described in claim 1, characterized in that, The first-level scan line and the second-level scan line are parallel scan signal lines.

3. The pixel compensation circuit as described in claim 1, characterized in that, The second-level scan line, the first-level scan line, and the control signal line are combined to correspond to the reset stage, the data writing stage, and the light emission stage, respectively.

4. The pixel compensation circuit as described in claim 3, characterized in that, During the reset phase, the first scan line is at a high level, the second scan line is at a low level, and the control signal line is at a low level.

5. The pixel compensation circuit as described in claim 4, characterized in that, During the reset phase, the second switching transistor, the first reset transistor, and the second reset transistor are all in the ON state, while the first switching transistor, the third switching transistor, and the compensation transistor are all in the OFF state.

6. The pixel compensation circuit as described in claim 5, characterized in that, During the data writing phase, the first-level scan line is at a low level, the second-level scan line is at a high level, and the control signal line is at a low level.

7. The pixel compensation circuit as described in claim 6, characterized in that, During the data writing phase, the first switching transistor and the compensation transistor are both in the on state, while the second switching transistor, the first reset transistor, the second reset transistor, and the third switching transistor are all in the off state.

8. The pixel compensation circuit as described in claim 7, characterized in that, During the light emission stage, the first-level scan line, the second-level scan line, and the control signal line are all at a high level.

9. The pixel compensation circuit as described in claim 8, characterized in that, During the light-emitting phase, the second switching transistor, the third switching transistor, the first switching transistor, the compensation transistor, the first reset transistor, and the second reset transistor are all in the on state.

10. A pixel compensation method, characterized in that, The pixel compensation method includes: Provide the pixel compensation circuit as described in claim 1; Upon entering the reset phase, the first-level scan line provides a high level, the second-level scan line provides a low level, the control signal line provides a low level, the second switching transistor, the first reset transistor, and the second reset transistor are all in the on state, the first switching transistor, the third switching transistor, and the compensation transistor are all in the off state, the second node is written with a positive power supply voltage, and the fifth and third nodes are written with a reset voltage. Upon entering the data writing stage, the first-level scan line provides a low level, the second-level scan line provides a high level, the control signal line provides a low level, the first switching transistor and the compensation transistor are both in the on state, the second switching transistor, the first reset transistor, the second reset transistor and the third switching transistor are all in the off state, the first node writes the data signal, and the voltage of the third node changes to the first voltage, where is the data signal input by the data line, and is the threshold voltage of the driving transistor; Upon entering the light-emitting stage, the first-level scan line, the second-level scan line, and the control signal line all provide a high level. The second switching transistor, the third switching transistor, the first switching transistor, the compensation transistor, the first reset transistor, and the second reset transistor are all in the on state. The first voltage of the third node is consumed. The first voltage includes the threshold voltage of the driving transistor, and the light-emitting device emits light.

11. A display panel, characterized in that, The display panel includes a pixel compensation circuit as described in any one of claims 1 to 9 or employs a pixel compensation method as described in claim 10.

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