Gate driving circuit and display panel

Abstract

The application discloses a gate driving circuit and a display panel. The gate driving circuit comprises: a pull-up control module, configured to perform first pre-charging according to a previous stage signal; a random addressing module, configured to perform second pre-charging according to the previous stage signal and a random addressing signal; a pull-up module, configured to output a detection signal line, a current stage signal and a scan signal line according to a detection signal, a first clock signal and a second clock signal; a pull-down module, configured to release the charge of the first pre-charging according to a next stage signal and a first low potential; an inverter module, connected to a high potential signal and the random addressing signal; and a pull-down maintaining module, configured to maintain the output of the current stage signal and the scan signal line according to the high potential signal, and maintain the output of the detection signal line according to the high potential signal and the random addressing signal. The application performs voltage detection compensation in the pixel charging process, and does not need an additional blank time for voltage detection.

Description

Technical Field

[0001] This application relates to the field of display technology, specifically to a gate driving circuit and a display panel. Background Technology

[0002] To improve the display effect of OLED, pixel compensation technologies, including voltage compensation, current compensation, and digital compensation, have been continuously developed. Voltage compensation is further divided into internal compensation and external compensation based on its compensation principle. Internal compensation, which requires complex pixel circuits such as 6T2C and 7T1C, is difficult to improve resolution and has limited compensation effect, making it suitable for small and medium-sized display products. As TV products continue to evolve towards higher refresh rates, higher resolutions, and higher image quality, external compensation has become the mainstream compensation technology. External compensation refers to providing timing for detection compensation through the gate drive circuit. It uses an external drive system to collect voltage data containing threshold voltage or mobility of the pixel drive transistor, calculates the threshold voltage and mobility changes, and then corrects the data to compensate for the impact of threshold voltage or mobility changes on luminous brightness. Therefore, developing a GOA (Gate Driven on Array) circuit with detection compensation function is an essential technical reserve for obtaining high-end OLED products. For example, LG Display adds random addressing units and uses random signals and pull-up control signals to complete random row selection tasks. Then, it outputs detection waveforms during blank time. In order to obtain accurate detection results, the blank time is relatively long, which reduces the time for each row of gate signals to write data. This has a particularly serious impact on high refresh rate products. Summary of the Invention

[0003] This application provides a gate driving circuit and a display panel that performs voltage detection compensation during pixel charging, eliminating the need for additional blank time for voltage detection and reducing the limitation on the display panel refresh rate.

[0004] In a first aspect, embodiments of this application provide a gate driving circuit, including:

[0005] The pull-up control module is connected to the previous level transmission signal and is used to perform the first pre-charge according to the previous level transmission signal;

[0006] A random addressing module, connected to the upstream transmission signal and the random addressing signal, is used to perform a second pre-charge based on the upstream transmission signal and the random addressing signal;

[0007] The pull-up module is electrically connected to the pull-up control module and the random addressing module, and is connected to the detection signal, the first clock signal and the second clock signal. It is used to output the detection signal line, the current transmission signal and the scan signal line according to the detection signal, the first clock signal and the second clock signal after the first precharge and the second precharge.

[0008] The pull-down module is electrically connected to the pull-up control module, and is connected to the next-level transmission signal and the first low potential, for releasing the first pre-charged charge according to the next-level transmission signal and the first low potential;

[0009] The inverter module is electrically connected to the pull-up control module and the random addressing module, and is connected to the high-potential signal and the random addressing signal;

[0010] A pull-down sustaining module, electrically connected to the inverter module, is used to maintain the current cascade signal and the output of the scan signal line according to the high potential signal when the first pre-charged charge is released, and to maintain the output of the detection signal line according to the high potential signal and the random addressing signal.

[0011] In some embodiments, the pull-up control module includes:

[0012] The pull-up control transistor has its gate and the first terminal of its source and drain connected to the previous stage for signal transmission, and its second terminal of its source and drain connected to the first node.

[0013] A pull-up control capacitor is connected at one end to the first node and at the other end to the current transmission signal.

[0014] In some embodiments, the random addressing module includes:

[0015] A random addressing transistor, with its gate connected to the random addressing signal, its first source-drain terminal connected to the previous stage transmission signal, and its second source-drain terminal connected to the second node;

[0016] A randomly located capacitor is connected at one end to the second node and at the other end to the detection signal line.

[0017] In some embodiments, the pull-up module includes:

[0018] The first pull-up transistor has its gate connected to the first node, and its first source-drain terminal connected to the first clock signal, and its second source-drain terminal connected to the current transmission signal.

[0019] The second pull-up transistor has its gate connected to the first node, its first source and drain terminals connected to the second clock signal, and its second source and drain terminals connected to the scan signal line.

[0020] The third pull-up transistor has its gate connected to the second node, its first source-drain terminal connected to the detection signal, and its second source-drain terminal connected to the detection signal line.

[0021] In some embodiments, the drop-down module includes:

[0022] The pull-down transistor has its gate connected to the next stage for signal transmission, its first source / drain terminal connected to the first node, and its second source / drain terminal connected to the first low potential.

[0023] In some embodiments, the inverter module includes:

[0024] The first inverter unit is connected to the high potential signal, the second low potential, the first node, and the third node, wherein the second low potential is the same as the first low potential.

[0025] The first inverter transistor has its gate connected to the first node, its first source and drain terminals connected to the second low potential, and its second source and drain terminals connected to the third node.

[0026] The second inverter transistor has its gate connected to the previous stage for signal transmission, its first source-drain terminal connected to the first low potential, and its second source-drain terminal connected to the third node.

[0027] The second inverter unit is connected to the high-potential signal, the second low-potential signal, the second node, and the fourth node;

[0028] The third inverter transistor has its gate connected to the second node, its first source-drain terminal connected to the second low potential, and its second source-drain terminal connected to the fourth node.

[0029] The fourth inverter transistor has its gate connected to the random addressing signal, its first source-drain terminal connected to the first low potential, and its second source-drain terminal connected to the fourth node.

[0030] In some embodiments, the pull-down sustaining module includes:

[0031] The first pull-down sustaining transistor has its gate connected to the third node, its first source-drain terminal connected to the current stage transmission signal, and its second source-drain terminal connected to the first low potential.

[0032] The second pull-down sustaining transistor has its gate connected to the third node, its first source-drain terminal connected to the scan signal line, and its second source-drain terminal connected to the third low potential.

[0033] The third pull-down sustaining transistor has its gate connected to the fourth node, its first source-drain terminal connected to the detection signal line, and its second source-drain terminal connected to the third low potential.

[0034] In some embodiments, the driving timing of the gate driving circuit includes:

[0035] During the pre-charging phase, the next-stage transmission signal is set to a low potential, the previous-stage transmission signal and the random addressing signal are set to a high potential, the pull-up control transistor is turned on to perform a first pre-charge on the pull-up control capacitor, and the random addressing transistor is turned on to perform a second pre-charge on the random addressing capacitor; after the first pre-charge, the first pull-up transistor, the second pull-up transistor, and the first inverter transistor are turned on, and the first clock signal and the second clock signal are set to a low potential; after the second pre-charge, the third pull-up transistor and the third inverter transistor are turned on, and the detection signal is set to a low potential.

[0036] During the scanning waveform output stage, the previous stage transmission signal, the random addressing signal, and the next stage transmission signal are set to low potential, the first clock signal, the second clock signal, and the detection signal are set to high potential, and the current stage transmission signal, the scanning signal line, and the detection signal line are raised to high potential.

[0037] During the scanning waveform reset phase, the next stage transmission signal is set to a high potential, the pull-down transistor is turned on to release the charge of the pull-up control capacitor in the first pre-charge, the potential of the first node drops to the first low potential, the first pull-up transistor, the second pull-up transistor and the first inverter transistor are turned off, and the first pull-down sustaining transistor and the second pull-down sustaining transistor are turned on.

[0038] During the random detection and reset phase, the random addressing signal is set to a high potential, the previous stage transmission signal and the next stage transmission signal are set to a low potential, the random addressing transistor is turned on to release the charge of the random addressing capacitor in the second pre-charge, and the fourth inverter transistor is turned on; when the random addressing signal is set to a low potential, the third inverter transistor is turned off, and the third pull-down sustaining transistor is turned on.

[0039] Secondly, this application provides a display panel, including a pixel driving circuit and a gate driving circuit as described in any one of the above claims, wherein the pixel driving circuit and the gate driving circuit are electrically connected, and the pixel driving circuit includes:

[0040] The driving transistor has its gate connected to the fifth node, its first source-drain terminal connected to the first voltage signal, and its second source-drain terminal connected to the sixth node.

[0041] A storage capacitor, one end of which is connected to the fifth node and the other end of which is connected to the sixth node;

[0042] The first scanning transistor has its gate connected to the scanning signal line, its first source-drain terminal connected to the fifth node, and its second source-drain terminal connected to the data voltage signal.

[0043] The second scanning transistor has its gate connected to the scanning signal line, its first source-drain terminal connected to the second voltage signal, and its second source-drain terminal connected to the sixth node. The difference between the first data voltage used for detection in the data voltage signal and the second voltage signal is greater than the threshold voltage of the driving transistor.

[0044] The detection transistor has its gate connected to the detection signal line, its first source-drain terminal connected to the sixth node, and its second source-drain terminal connected to the detection voltage signal.

[0045] The detection capacitor has one end connected to the detection voltage signal and the other end grounded.

[0046] The detection switch is connected to the detection voltage signal at one end and to the controller at the other end.

[0047] In some embodiments, the driving timing of the gate driving circuit includes:

[0048] During the data voltage writing phase, the scan signal line and the detection signal line are set to high potential, the first scan transistor, the second scan transistor and the detection transistor are turned on, the fifth node writes the first data voltage for detection, and the sixth node is reset to the second voltage signal;

[0049] During the voltage coupling phase, the scanning signal line is set to a low potential, the first scanning transistor and the second scanning transistor are turned off, the driving transistor is turned on, the potentials of the fifth node and the sixth node are raised, and the capacitance is stored in the storage capacitor and the detection capacitor.

[0050] During the detection phase, the detection switch is turned on, the controller records the target voltage of the sixth node, determines the compensation data voltage based on the target voltage and the second voltage signal, and writes the compensation data voltage into the data voltage signal.

[0051] The gate drive circuit and display panel provided in this application embodiment set the phase of the random address signal LSP to be consistent with the previous stage transmission signal Count(n-1), so that voltage detection compensation is performed during pixel charging without the need for additional blank time for voltage detection, thereby reducing the limitation on the refresh rate of the display panel. Attached Figure Description

[0052] The technical solution and other beneficial effects of this application will become apparent from the following detailed description of specific embodiments in conjunction with the accompanying drawings.

[0053] Figure 1 This is a schematic diagram of the connection of the gate driving circuit in one embodiment of this application;

[0054] Figure 2 This is a schematic diagram of the connection of the gate driving circuit in one embodiment of this application;

[0055] Figure 3 This is a timing diagram of the gate driving circuit in one embodiment of this application;

[0056] Figure 4 This is a schematic diagram of the connection of the pixel driving circuit in one embodiment of this application;

[0057] Figure 5 This is a timing diagram of the pixel driving circuit in one embodiment of this application;

[0058] Figure 6 This is a simulation diagram of random detection of the gate drive circuit in one embodiment of this application.

[0059] Icon labels:

[0060] 110. Pull-up control module; 120. Random addressing module; 130. Pull-up module; 140. Pull-down module; 150. Inverter module; 160. Pull-down sustaining module. Detailed Implementation

[0061] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0062] In the description of this application, it should be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," and "counterclockwise," etc., indicating orientation or positional relationships based on the orientation or positional relationships shown in the accompanying drawings, are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, features defined with "first" and "second" may explicitly or implicitly include one or more of the stated features. In the description of this application, "a plurality of" means two or more, unless otherwise explicitly specified.

[0063] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection, an electrical connection, or a connection that allows communication between them; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication between two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.

[0064] In this application, unless otherwise expressly specified and limited, "above" or "below" the second feature can include direct contact between the first and second features, or contact between the first and second features through another feature between them. Furthermore, "above," "over," and "on top" of the second feature includes the first feature being directly above or diagonally above the second feature, or simply indicates that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature includes the first feature being directly below or diagonally below the second feature, or simply indicates that the first feature is at a lower horizontal level than the second feature.

[0065] The following disclosure provides many different embodiments or examples for implementing different structures of this application. To simplify the disclosure, specific examples of components and arrangements are described below. Of course, these are merely examples and are not intended to limit the scope of this application. Furthermore, reference numerals and / or letters may be repeated in different examples; such repetition is for simplification and clarity and does not in itself indicate a relationship between the various embodiments and / or arrangements discussed. In addition, various specific examples of processes and materials are provided in this application, but those skilled in the art will recognize the application of other processes and / or the use of other materials.

[0066] Please see Figure 1 and Figure 2 This application provides a gate driving circuit, which includes a pull-up control module 110, a random addressing module 120, a pull-up module 130, a pull-down module 140, an inverter module 150, and a pull-down sustaining module 160.

[0067] The pull-up control module 110 is connected to the previous stage transmission signal Count(n-1) and is used to perform a first pre-charge based on the previous stage transmission signal Count(n-1). The random addressing module 120 is connected to the previous stage transmission signal Count(n-1) and the random addressing signal LSP. If the phase of the random addressing signal LSP is consistent with the previous stage transmission signal Count(n-1) (both are high potential), then the row of pixels is selected for detection. The random addressing module 120 is used to perform a second pre-charge based on the previous stage transmission signal Count(n-1) and the random addressing signal LSP. Specifically, any row or multiple rows of pixels in the display panel are randomly selected as target row pixels and written into the random addressing signal LSP. Then, the data voltage signal of the target row pixel is detected and compensated according to the detection method of this embodiment. The random signal and the pull-up control signal work together to complete the random row selection task during pixel charging. Furthermore, this random detection does not require additional blank time, thus increasing the charging time for each row of pixels, which is beneficial for the design of high refresh rate products.

[0068] The pull-up module 130 is electrically connected to the pull-up control module 110 and the random addressing module 120. The pull-up module 130 is connected to the detection signal Vse, the first clock signal CKA and the second clock signal CKB. It is used to output the detection signal line RD(n) according to the detection signal Vse after the second precharge, output the current stage transmission signal Count(n) according to the first clock signal CKA after the first precharge, and output the scan signal line WR(n) according to the second clock signal CKB after the first precharge.

[0069] The pull-down module 140 is electrically connected to the pull-up control module 110, and is connected to the next-level transmission signal Count(n+1) and the first low potential VGL1, for releasing the first pre-charged charge according to the next-level transmission signal Count(n+1) and the first low potential VGL1.

[0070] Inverter module 150 is electrically connected to pull-up control module 110 and random addressing module 120, and is connected to high-level signal VGH and random addressing signal LSP. Pull-down sustaining module 160 is electrically connected to inverter module 150, and is used to maintain the output of current stage transmission signal Count(n) and scan signal line WR(n) according to high-level signal VGH when releasing the first pre-charged charge, and to maintain the output of detection signal line RD(n) according to high-level signal VGH and random addressing signal LSP.

[0071] In this embodiment, the phase of the random addressing signal LSP is set to be consistent with the previous stage transmission signal Count(n-1), so that voltage detection compensation is performed during pixel charging without the need for additional blank time for voltage detection, thus reducing the limitation on the refresh rate of the display panel.

[0072] In one embodiment, the pull-up control module 110 includes pull-up control transistors T11A and T11B, and pull-up control capacitor C1. The pull-up control transistors T11A and T11B are connected in series. The gates of both pull-up control transistors T11A and T11B are connected to the previous stage transmission signal Count(n-1). The remaining end of the source and drain of pull-up control transistor T11A is connected to the previous stage transmission signal Count(n-1). The remaining end of the source and drain of pull-up control transistor T11B is connected to the first node Q. One end of pull-up control capacitor C1 is connected to the first node Q, and the other end of pull-up control capacitor C1 is connected to the current stage transmission signal Count(n).

[0073] In one embodiment, the random addressing module 120 includes random addressing transistors T61A and T61B, and a random addressing capacitor C2. T61A and T61B are connected in series. The gates of both T61A and T61B are connected to the random addressing signal LSP. The remaining end of the source-drain junction of random addressing transistor T61A is connected to the previous stage transmission signal Count(n-1), and the remaining end of the source-drain junction of random addressing transistor T61B is connected to the second node M. One end of the random addressing capacitor C2 is connected to the second node M, and the other end of the random addressing capacitor C2 is connected to the detection signal line RD(n). Furthermore, the random addressing module 120 also includes another random addressing transistor T62. The gate of this other random addressing transistor T62 is connected to the second node M. The first end of the source-drain junction of this other random addressing transistor T62 is connected to the high-voltage signal VGH, and the second end of the source-drain junction of this other random addressing transistor T62 is connected between random addressing transistors T61A and T61B.

[0074] In one embodiment, the pull-up module 130 includes a first pull-up transistor T21, a second pull-up transistor T22, and a third pull-up transistor T23. The gate of the first pull-up transistor T21 is connected to a first node Q, the first terminal of its source-drain junction is connected to a first clock signal CKA, and the second terminal of its source-drain junction is connected to the current stage signal Count(n). The gate of the second pull-up transistor T22 is connected to the first node Q, the first terminal of its source-drain junction is connected to a second clock signal CKB, and the second terminal of its source-drain junction is connected to a scan signal line WR(n). The gate of the third pull-up transistor T23 is connected to a second node M, the first terminal of its source-drain junction is connected to a detection signal Vse, and the second terminal of its source-drain junction is connected to a detection signal line RD(n).

[0075] In one embodiment, the pull-down module 140 includes pull-down transistors T41A and T41B, which are connected in series. The gates of both pull-down transistors T41A and T41B are connected to the next stage transmission signal Count(n+1). The remaining end of the source and drain of pull-down transistor T41A is connected to the first node Q, and the remaining end of the source and drain of pull-down transistor T41B is connected to the first low potential VGL1.

[0076] In addition, the pull-down module 140 also includes first pull-down transistors T42A and T42B, and second pull-down transistors T43A and T43B. The first pull-down transistors T42A and T42B are connected in series. The gates of both first pull-down transistors T42A and T42B are connected to the first pull-down signal VST. The remaining source and drain terminals of the first pull-down transistor T42A are connected to the first node Q, and the remaining source and drain terminals of the first pull-down transistor T42B are connected to the first low potential VGL1. The second pull-down transistors T43A and T43B are connected in series. The gates of both second pull-down transistors T43A and T43B are connected to the third node QB1. The remaining source and drain terminals of the second pull-down transistor T43A are connected to the first node Q, and the remaining source and drain terminals of the second pull-down transistor T43B are connected to the first low potential VGL1.

[0077] In one embodiment, inverter module 150 includes a first inverter unit, a first inverter transistor T54, a second inverter transistor T55, a second inverter unit, a third inverter transistor T59, and a fourth inverter transistor T510.

[0078] The first inverter unit includes fifth inverter transistors T51_1 and T51_2, a sixth inverter transistor T52, and a seventh inverter transistor T53. Fifth inverter transistors T51_1 and T51_2 are connected in series. The gates of both fifth inverter transistors T51_1 and T51_2 are connected to a high-level signal VGH. The remaining source-drain terminals of fifth inverter transistor T51_1 are connected to the high-level signal VGH, and the remaining source-drain terminals of fifth inverter transistor T51_2 are connected to the gate of seventh inverter transistor T53. The first drain terminal of seventh inverter transistor T53 is connected to the high-level signal VGH, and the second drain terminal of seventh inverter transistor T53 is connected to the third node QB1. The gate of the sixth inverter transistor T52 is connected to the first node Q, the first terminal of the source and drain of the sixth inverter transistor T52 is connected to the second low potential VGL3, and the second terminal of the source and drain of the sixth inverter transistor T52 is connected to the gate of the seventh inverter transistor T53.

[0079] The gate of the first inverter transistor T54 is connected to the first node Q. The first terminal of the source-drain junction of the first inverter transistor T54 is connected to the second low potential VGL3. The second terminal of the source-drain junction of the first inverter transistor T54 is connected to the third node QB1. The second low potential VGL3 has the same potential as the first low potential VGL1. The gate of the second inverter transistor T55 is connected to the previous stage's signal Count(n-1). The first terminal of the source-drain junction of the second inverter transistor T55 is connected to the first low potential VGL1. The second terminal of the source-drain junction of the second inverter transistor T55 is connected to the third node QB1.

[0080] The second inverter unit includes eighth inverter transistors T56_1 and T56_2, a ninth inverter transistor T57, and a tenth inverter transistor T58. Eighth inverter transistors T56_1 and T56_2 are connected in series. The gates of both eighth inverter transistors T56_1 and T56_2 are connected to a high-level signal VGH. The remaining source-drain terminals of eighth inverter transistor T56_1 are connected to the high-level signal VGH, and the remaining source-drain terminals of eighth inverter transistor T56_2 are connected to the gate of the tenth inverter transistor T58. The first drain terminal of the tenth inverter transistor T58 is connected to the high-level signal VGH, and the second drain terminal of the tenth inverter transistor T58 is connected to the fourth node QB2. The gate of the ninth inverter transistor T57 is connected to the second node M, the first terminal of the source and drain of the ninth inverter transistor T57 is connected to the second low potential VGL3, and the second terminal of the source and drain of the ninth inverter transistor T57 is connected to the gate of the tenth inverter transistor T58.

[0081] The gate of the third inverter transistor T59 is connected to the second node M, the first terminal of the source-drain junction of the third inverter transistor T59 is connected to the second low potential VGL3, and the second terminal of the source-drain junction of the third inverter transistor T59 is connected to the fourth node QB2. The gate of the fourth inverter transistor T510 is connected to the random address signal LSP, the first terminal of the source-drain junction of the fourth inverter transistor T510 is connected to the first low potential VGL1, and the second terminal of the source-drain junction of the fourth inverter transistor T510 is connected to the fourth node QB2.

[0082] In one embodiment, the pull-down sustaining module 160 includes a first pull-down sustaining transistor T31, a second pull-down sustaining transistor T32, and a third pull-down sustaining transistor T33. The gate of the first pull-down sustaining transistor T31 is connected to a third node QB1, the first terminal of its source-drain junction is connected to the current stage signal Count(n), and the second terminal of its source-drain junction is connected to a first low potential VGL1. The gate of the second pull-down sustaining transistor T32 is connected to the third node QB1, the first terminal of its source-drain junction is connected to the scan signal line WR(n), and the second terminal of its source-drain junction is connected to a third low potential VGL2. The gate of the third pull-down sustaining transistor T33 is connected to a fourth node QB2, the first terminal of its source-drain junction is connected to the detection signal line RD(n), and the second terminal of its source-drain junction is connected to the third low potential VGL2.

[0083] In one embodiment, the gate drive circuit further includes a feedback voltage module, which includes feedback voltage transistors T71 and T72 connected in series. The gates of both feedback voltage transistors T71 and T72 are connected to the first node Q. The remaining end of the source and drain of feedback voltage transistor T71 is connected to a high-potential signal VGH, and the remaining end of the source and drain of feedback voltage transistor T72 is connected between pull-up control transistors T11A and T11B.

[0084] In one embodiment, such as Figure 3 As shown, the driving timing of the gate drive circuit includes:

[0085] During the pre-charge phase T1, the next-level transmission signal Count(n+1) is set to a low potential, while the previous-level transmission signal Count(n-1) and the random addressing signal LSP are set to a high potential. This selects the pixel in that row for voltage mobility detection and compensation. The previous-level transmission signal Count(n-1) turns on pull-up control transistors T11A and T11B, performing a first pre-charge on pull-up control capacitor C1, raising the Q potential of the first node, and storing the charge in pull-up control capacitor C1. The random addressing signal LSP turns on random addressing transistors T61A and T61B, performing a second pre-charge on random addressing capacitor C2, raising the M potential of the second node, and storing the charge in random addressing capacitor C2. Since the Q potential of the first node rises after the first pre-charge, the first pull-up transistor T21 and the second pull-up transistor T22 are turned on. At this time, the first clock signal CKA and the second clock signal CKB are set to a low potential, correspondingly, the current transmission signal Count(n) and the scan signal line WR(n) are also at a low potential. When the Q potential of the first node rises, the sixth inverter transistor T52 and the first inverter transistor T54 turn on, the gate of the seventh inverter transistor T53 is at the first low potential VGL1, and the seventh inverter transistor T53 turns off. The potential of the third node QB1 is pulled down to the first low potential VGL1, and the first pull-down holding transistor T31 and the second pull-down holding transistor T32 turn off. After the second precharge, the M potential of the second node rises, and the third pull-up transistor T23 turns on. At this time, the detection signal Vse is set to a low potential, and the corresponding detection signal line RD(n) is also at a low potential. When the M potential of the second node rises, the ninth inverter transistor T57 and the third inverter transistor T59 turn on, the gate of the tenth inverter transistor T58 is at the second low potential VGL3, and the tenth inverter transistor T58 turns off. The potential of the fourth node QB2 is pulled down to the second low potential VGL3, and the third pull-down holding transistor T33 turns off. The second low potential VGL3 is the same as the first low potential VGL1.

[0086] During the scanning waveform output stage T2, the previous stage transmission signal Count(n-1), the random addressing signal LSP, and the next stage transmission signal Count(n+1) are set to low potential, while the first clock signal CKA and the second clock signal CKB are set to high potential. Correspondingly, the current stage transmission signal Count(n) and the scanning signal line WR(n) are raised from low potential to high potential. Due to the bootstrap effect of the pull-up control capacitor C1, the potential of the first node Q point is raised again, which simultaneously improves the driving capability of the first pull-up transistor T21 and the second pull-up transistor T22. When the detection signal Vse appears in conjunction with the random addressing signal LSP, the detection signal Vse outputs a wide pulse signal consistent with the detection waveform. At this time, the detection signal Vse is set to high potential, and correspondingly, the detection signal line RD(n) is raised from low potential to high potential. Due to the bootstrap effect of the random addressing capacitor C2, the potential of the second node M point is raised again, maintaining the output of the wide pulse signal of the detection signal line RD(n).

[0087] During the scan waveform reset phase T3, the next stage transmission signal Count(n+1) is set to a high potential, pull-down transistors T41A and T41B are turned on, releasing the charge of the pull-up control capacitor C1 in the first pre-charge. The potential of the first node Q drops to the first low potential VGL1, turning off the first pull-up transistor T21, the second pull-up transistor T22, the sixth inverter transistor T52, and the first inverter transistor T54. The gate of the seventh inverter transistor T53 is at a high potential signal VGH, and the seventh inverter transistor T53 is turned on. The potential of the third node QB1 rises to the high potential signal VGH, and the first pull-down holding transistor T31 and the second pull-down holding transistor T32 are turned on. The current stage transmission signal Count(n) is at the first low potential VGL1, and the scan signal line WR(n) is at the third low potential VGL2. During this phase, the output of the K detection waveform is completed when the detection signal Vse potential decreases.

[0088] During the random detection reset phase T4, the random addressing signal LSP is set to a high level, while the previous stage transmission signal Count(n-1) and the next stage transmission signal Count(n+1) are set to a low level. Random addressing transistors T61A and T61B are turned on, releasing the charge from the random addressing capacitor C2 in the second pre-charge stage, pulling the potential of the second node M low. The fourth inverter transistor T510 is turned on, and the potential of the fourth node QB2 is the first low level VGL1. When the random addressing signal LSP is set to a low level, due to the low potential of the second node M, the ninth inverter transistor T57 and the third inverter transistor T59 are turned off, the gate of the tenth inverter transistor T58 is at a high level signal VGH, the tenth inverter transistor T58 is turned on, the potential of the fourth node QB2 rises to the high level signal VGH, the third pull-down holding transistor T33 is turned on, and the potential of the detection signal line RD(n) is the third low level VGL2.

[0089] This embodiment can generate a wide pulse waveform with random detection function while generating the scanning waveform of the normal display screen. Moreover, this random detection does not require additional blank time, so the charging time of each row of pixels can be increased, which is beneficial to the design of high refresh rate products.

[0090] This application provides a display panel, including a pixel driving circuit and a gate driving circuit as described in any of the above embodiments. The pixel driving circuit and the gate driving circuit are electrically connected, such as... Figure 4 As shown, the pixel driving circuit includes a driving transistor T1, a storage capacitor Cst, a first scanning transistor T2, a second scanning transistor T3, a detection transistor T4, a detection capacitor Csen, and a detection switch Sam.

[0091] The gate of driving transistor T1 is connected to the fifth node G, the first terminal of the source-drain junction of driving transistor T1 is connected to the first voltage signal VDD, and the second terminal of the source-drain junction of driving transistor T1 is connected to the sixth node S. One end of storage capacitor Cst is connected to the fifth node G, and the other end of storage capacitor Cst is connected to the sixth node S.

[0092] The gate of the first scanning transistor T2 is connected to the scan signal line WR. The first terminal of the source-drain junction of the first scanning transistor T2 is connected to the fifth node G, and the second terminal of the source-drain junction of the first scanning transistor T2 is connected to the data voltage signal Vdata. The gate of the second scanning transistor T3 is connected to the scan signal line WR. The first terminal of the source-drain junction of the second scanning transistor T3 is connected to the second voltage signal Vini, and the second terminal of the source-drain junction of the second scanning transistor T3 is connected to the sixth node S. The difference between the first data voltage used for detection in the data voltage signal Vdata and the second voltage signal Vini is greater than the threshold voltage of the driving transistor T1. The scan signal line WR is the signal WR(n) input from the gate driving circuit to the pixel driving circuit.

[0093] The gate of detection transistor T4 is connected to the detection signal line RD. The first terminal of the source-drain junction of detection transistor T4 is connected to the sixth node S, and the second terminal of the source-drain junction of detection transistor T4 is connected to the detection voltage signal Vsense. One end of detection capacitor Csen is connected to the detection voltage signal Vsense, and the other end of detection capacitor Csen is grounded. One end of detection switch Sam is connected to the detection voltage signal Vsense, and the other end of detection switch Sam is connected to the controller ADC (analog-to-digital converter). The detection signal line RD is the signal RD(n) input from the gate drive circuit to the pixel drive circuit.

[0094] In one embodiment, such as Figure 5 As shown, the driving timing of the pixel driving circuit includes:

[0095] In the data voltage writing stage S1, the scan signal line WR and the detection signal line RD are set to high potential. The first scan transistor T2, the second scan transistor T3, and the detection transistor T2 are turned on. The fifth node G writes the first data voltage V1 used for detection, and the sixth node S is reset to the second voltage signal Vini, that is, Vg voltage is V1, and Vs voltage is Vini. Among them, the difference between the first data voltage used for detection and the second voltage signal Vini in the data voltage signal Vdata is greater than the threshold voltage of the driving transistor T1, that is, V1 - Vini > Vth.

[0096] In voltage coupling stage S2, where Vg is coupled to Vs, the scan signal line WR is set to a low potential, and the first scan transistor T2 and the second scan transistor T3 are turned off. Since V1 - Vini > Vth, the driving transistor T1 is turned on, and the first voltage signal VDD charges the sixth node S, causing the potential of the sixth node S to gradually rise. Simultaneously, the capacitance is stored in the storage capacitor Cst and the detection capacitor Csen. Due to the capacitive coupling between Vg and Vs, the potential of the fifth node G rises synchronously.

[0097] In detection phase S3, the detection switch Sam is turned on. The controller, i.e., the analog-to-digital converter (ADC), records the target voltage of the sixth node S. Based on the target voltage and the second voltage signal Vini, the voltage change value ΔVs2 of the sixth node S is determined. The voltage change value ΔVs2 is compared with the voltage change value ΔVs1 determined during the last detection of the pixel in this row to determine the compensation data voltage. The compensation data voltage is then written into the data voltage signal Vdata to drive the pixel, achieving the purpose of mobility compensation. If this is the first detection and compensation for the pixel in this row, the detection compensation parameters are pre-calibrated and can be directly obtained. The detection compensation parameters include the voltage change value ΔVs and the mobility.

[0098] The detection principle is as follows: the driving transistor T1 operates in the saturation region, and its current formula is (1), C ox The capacitance per unit area of ​​the insulating layer driving transistor T1 can be expressed as C. ox =ε / d, where ε is the dielectric constant of the insulating layer of the driving transistor T1, d is the thickness of the insulating layer of the driving transistor T1, μ is the field-induced mobility of the driving transistor T1, and W / L is the aspect ratio of the driving transistor T1. The amount of charge stored in the detection capacitor Csen can be expressed by formula (2), therefore the formula for the saturation current of the driving transistor T1 is related to the rate of rise of the potential at point Vs. As shown in formula (4), the change in the value of k, which includes mobility, is positively correlated with the change in voltage at point Vs.

[0099] Therefore, the voltage change value ΔVs2 of the sixth node S of the target row pixel, the voltage change value ΔVs1 of the sixth node S detected in the previous target row pixel, and the mobility k1 detected in the previous target row pixel are substituted into formula (4) to obtain the mobility k2 of the target row pixel. In order to maintain the uniformity of brightness, the purpose of pixel compensation is to ensure that the current flowing through the driving transistor T1 is stable, that is, the current I2 of the target row pixel is the same as the current I1 of the previous target row pixel. Since Vth is a constant value and Vgs is the voltage difference between the fifth node G and the sixth node S, Vgs2 of the target row pixel is obtained by combining formula (1) based on Vgs1, k1 of the previous target row pixel compensation and k2 of the current target row pixel. The data voltage is compensated based on Vgs2.

[0100]

[0101] C sen *ΔV s =I*t…(2)

[0102]

[0103]

[0104] To verify the feasibility of the GOA circuit and random detection, a simulation architecture was built based on a 31-inch 4K product. The pulse width of the scan data line WR was set to 3.7µs, the pulse width of the detection signal line RD for random detection was set to 100µs, the detection data voltage was set to 1.8V, the Vini voltage was set to 1.2V, and the VDD and VSS voltages were set to 17V and 0V respectively, ensuring that the T1 transistor was operating in the saturation region and the OLED was not turned on.

[0105] After a series of simulation experiments, the results are as follows: Figure 6As shown, WR and RD are the gate waveforms of the GOA output used for writing data and detection, respectively, indicating that the GOA circuit has the functions of normal display and random detection; Vg and Vs points record the voltage change curves of points g and s during the detection process. From the curves, it can be seen that when transistors T2 and T3 are turned off, the voltages of points g and s rise linearly. To verify the accuracy of the detection process, we changed the mobility values ​​in the TFT model to 13, 10.4, and 6.5 cm² / V / s, and their IV characteristic curves are shown in the figure. We used the T1 transistor in the pixel with different mobility values ​​to represent the mobility change, and recorded the change curves of Vg and Vs under different mobility values. It is known that when the initial mobility is 13 cm² / V / s, the voltage change of Vs is 1.803V. If the mobility change is 10.4 cm² / V / s, according to formula (4), the detected mobility is 10.8 cm² / V / s, with an error of 3.8%. If the mobility change is 6.5 cm² / V / s, the detected value is 6.7 cm² / V / s, with an error of only 3.1%, indicating the accuracy of the detection method.

[0106] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0107] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0108] The foregoing has provided a detailed description of a gate driving circuit and display panel provided in the embodiments of this application. Specific examples have been used to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only for the purpose of helping to understand the method and core ideas of the present invention. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of the present invention. Therefore, the content of this specification should not be construed as a limitation of the present invention.

Claims

1. A gate driving circuit, characterized in that, include: The pull-up control module is connected to the previous level transmission signal and is used to perform the first pre-charge according to the previous level transmission signal; A random addressing module, connected to the upstream transmission signal and the random addressing signal, is used to perform a second pre-charge based on the upstream transmission signal and the random addressing signal; The pull-up module is electrically connected to the pull-up control module and the random addressing module, and is connected to the detection signal, the first clock signal and the second clock signal. It is used to output the detection signal line, the current transmission signal and the scan signal line according to the detection signal, the first clock signal and the second clock signal after the first precharge and the second precharge. The pull-down module is electrically connected to the pull-up control module, and is connected to the next-level transmission signal and the first low potential, for releasing the first pre-charged charge according to the next-level transmission signal and the first low potential; The inverter module is electrically connected to the pull-up control module and the random addressing module, and is connected to the high-potential signal and the random addressing signal; A pull-down sustaining module, electrically connected to the inverter module, is used to maintain the current cascade signal and the output of the scan signal line according to the high potential signal when the first pre-charged charge is released, and to maintain the output of the detection signal line according to the high potential signal and the random addressing signal.

2. The gate driving circuit as described in claim 1, characterized in that, The pull-up control module includes: The pull-up control transistor has its gate and the first terminal of its source and drain connected to the previous stage for signal transmission, and its second terminal of its source and drain connected to the first node. A pull-up control capacitor is connected at one end to the first node and at the other end to the current transmission signal.

3. The gate driving circuit as described in claim 2, characterized in that, The random location module includes: A random addressing transistor, with its gate connected to the random addressing signal, its first source-drain terminal connected to the previous stage transmission signal, and its second source-drain terminal connected to the second node; A randomly located capacitor is connected at one end to the second node and at the other end to the detection signal line.

4. The gate driving circuit as described in claim 3, characterized in that, The pull-up module includes: The first pull-up transistor has its gate connected to the first node, and its first source-drain terminal connected to the first clock signal, and its second source-drain terminal connected to the current transmission signal. The second pull-up transistor has its gate connected to the first node, its first source and drain terminals connected to the second clock signal, and its second source and drain terminals connected to the scan signal line. The third pull-up transistor has its gate connected to the second node, its first source-drain terminal connected to the detection signal, and its second source-drain terminal connected to the detection signal line.

5. The gate driving circuit as described in claim 4, characterized in that, The drop-down module includes: The pull-down transistor has its gate connected to the next stage for signal transmission, its first source / drain terminal connected to the first node, and its second source / drain terminal connected to the first low potential.

6. The gate driving circuit as described in claim 5, characterized in that, The inverter module includes: The first inverter unit is connected to the high potential signal, the second low potential, the first node, and the third node, wherein the second low potential is the same as the first low potential. The first inverter transistor has its gate connected to the first node, its first source and drain terminals connected to the second low potential, and its second source and drain terminals connected to the third node. The second inverter transistor has its gate connected to the previous stage for signal transmission, its first source-drain terminal connected to the first low potential, and its second source-drain terminal connected to the third node. The second inverter unit is connected to the high-potential signal, the second low-potential signal, the second node, and the fourth node; The third inverter transistor has its gate connected to the second node, its first source-drain terminal connected to the second low potential, and its second source-drain terminal connected to the fourth node. The fourth inverter transistor has its gate connected to the random addressing signal, its first source-drain terminal connected to the first low potential, and its second source-drain terminal connected to the fourth node.

7. The gate drive circuit of claim 6, wherein the pull-down sustaining module comprises: The first pull-down sustaining transistor has its gate connected to the third node, its first source-drain terminal connected to the current stage transmission signal, and its second source-drain terminal connected to the first low potential. The second pull-down sustaining transistor has its gate connected to the third node, its first source-drain terminal connected to the scan signal line, and its second source-drain terminal connected to the third low potential. The third pull-down sustaining transistor has its gate connected to the fourth node, its first source-drain terminal connected to the detection signal line, and its second source-drain terminal connected to the third low potential.

8. The gate driving circuit as described in claim 7, characterized in that, The driving timing of the gate driving circuit includes: During the pre-charging phase, the next-stage transmission signal is set to a low potential, the previous-stage transmission signal and the random addressing signal are set to a high potential, the pull-up control transistor is turned on to perform a first pre-charge on the pull-up control capacitor, and the random addressing transistor is turned on to perform a second pre-charge on the random addressing capacitor; after the first pre-charge, the first pull-up transistor, the second pull-up transistor, and the first inverter transistor are turned on, and the first clock signal and the second clock signal are set to a low potential; after the second pre-charge, the third pull-up transistor and the third inverter transistor are turned on, and the detection signal is set to a low potential. During the scanning waveform output stage, the previous stage transmission signal, the random addressing signal, and the next stage transmission signal are set to low potential, the first clock signal, the second clock signal, and the detection signal are set to high potential, and the current stage transmission signal, the scanning signal line, and the detection signal line are raised to high potential. During the scanning waveform reset phase, the next stage transmission signal is set to a high potential, the pull-down transistor is turned on to release the charge of the pull-up control capacitor in the first pre-charge, the potential of the first node drops to the first low potential, the first pull-up transistor, the second pull-up transistor and the first inverter transistor are turned off, and the first pull-down sustaining transistor and the second pull-down sustaining transistor are turned on. During the random detection and reset phase, the random addressing signal is set to a high potential, the previous stage transmission signal and the next stage transmission signal are set to a low potential, the random addressing transistor is turned on to release the charge of the random addressing capacitor in the second pre-charge, and the fourth inverter transistor is turned on; when the random addressing signal is set to a low potential, the third inverter transistor is turned off, and the third pull-down sustaining transistor is turned on.

9. A display panel, characterized in that, The pixel driving circuit includes a pixel driving circuit and a gate driving circuit as described in any one of claims 1-8, wherein the pixel driving circuit and the gate driving circuit are electrically connected, and the pixel driving circuit includes: The driving transistor has its gate connected to the fifth node, its first source-drain terminal connected to the first voltage signal, and its second source-drain terminal connected to the sixth node. A storage capacitor, one end of which is connected to the fifth node and the other end of which is connected to the sixth node; The first scanning transistor has its gate connected to the scanning signal line, its first source-drain terminal connected to the fifth node, and its second source-drain terminal connected to the data voltage signal. The second scanning transistor has its gate connected to the scanning signal line, its first source-drain terminal connected to the second voltage signal, and its second source-drain terminal connected to the sixth node. The difference between the first data voltage used for detection in the data voltage signal and the second voltage signal is greater than the threshold voltage of the driving transistor. The detection transistor has its gate connected to the detection signal line, its first source-drain terminal connected to the sixth node, and its second source-drain terminal connected to the detection voltage signal. The detection capacitor has one end connected to the detection voltage signal and the other end grounded. The detection switch has one end connected to the detection voltage signal and the other end connected to the controller.

10. The display panel as claimed in claim 9, characterized in that, The driving timing of the gate driving circuit includes: During the data voltage writing phase, the scan signal line and the detection signal line are set to high potential, the first scan transistor, the second scan transistor and the detection transistor are turned on, the fifth node writes the first data voltage for detection, and the sixth node is reset to the second voltage signal; During the voltage coupling phase, the scanning signal line is set to a low potential, the first scanning transistor and the second scanning transistor are turned off, the driving transistor is turned on, the potentials of the fifth node and the sixth node are raised, and the capacitance is stored in the storage capacitor and the detection capacitor. During the detection phase, the detection switch is turned on, the controller records the target voltage of the sixth node, determines the compensation data voltage based on the target voltage and the second voltage signal, and writes the compensation data voltage into the data voltage signal.

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