Gate driving circuit, display panel

Abstract

The application provides a gate drive circuit and a display panel. The gate drive circuit comprises a first node pull-down module, a second node pull-down module, a second node maintaining module and an output module. The first node pull-down module lowers the potential of the first node according to a first clock signal, a second clock signal and a first voltage; the second node pull-down module lowers the potential of the second node according to the second clock signal and a pull-down control signal, so that a variable of a signal output end of the gate drive circuit is coupled to the second node; the second node maintaining module maintains the potential of the second node according to the first clock signal, the second clock signal and the pull-down control signal; and the output module controls the signal output end to output a gate control signal according to the potentials of the first node and the second node. The display panel comprises a plurality of sub-pixels and a plurality of gate drive circuits.

Description

Technical Field

[0001] This invention relates to the field of display technology, and more specifically to a gate driving circuit and a display panel. Background Technology

[0002] In existing gate drive circuits (such as...) Figure 1 As shown), capacitor C3 is often used to maintain the gate potential of the pull-down output transistor To2. However, when the pull-down output transistor To2 is a P-type transistor, since the gate-source voltage difference must be less than the threshold voltage for the P-type transistor to conduct, there will be a voltage drop problem when the existing gate drive circuit outputs the required gate control signal Scan. That is, when the gate potential of the pull-down output transistor To2 is L+|Vth| and the drain potential is a low potential L, the source potential (i.e., the signal output terminal OUT) of the pull-down output transistor To2 must be L+2|Vth| to satisfy the conduction condition Vgs<Vth, so that the pull-down output transistor To2 conducts. This results in a voltage drop of 2|Vth| at the output, and the voltage corresponding to VGL cannot be directly output (i.e., as shown). Figure 2 As shown, the output waveform has a tail of L+2|Vth|, and the output waveform can only output the voltage corresponding to VGL when the clock signal XCK is low. Summary of the Invention

[0003] This invention provides a gate driving circuit and a display panel that can maintain the potential of the second node and improve the problem of voltage loss in the gate control signal output by the gate driving circuit.

[0004] This invention provides a gate driving circuit, including a first node pull-down module, a second node pull-down module, a second node maintenance module, and an output module.

[0005] The first node pull-down module is electrically connected to the first clock signal line, the second clock signal line, the first voltage terminal and the first node. The first node pull-down module is configured to pull down the potential of the first node according to the first clock signal transmitted by the first clock signal line, the second clock signal transmitted by the second clock signal line and the first voltage transmitted by the first voltage terminal.

[0006] The second node pull-down module is electrically connected to the first clock signal line, the pull-down control line and the second node. The second node pull-down module is configured to pull down the potential of the second node according to the pull-down control signal transmitted by the first clock signal and the pull-down control line, so that the variable of the signal output terminal of the gate drive circuit is coupled to the second node.

[0007] The second node maintenance module is electrically connected to the first clock signal line, the second clock signal line, the pull-down control line, and the second node. The second node maintenance module is configured to maintain the potential of the second node according to the first clock signal, the second clock signal, and the pull-down control signal.

[0008] The output module is electrically connected to the first node and the second node, and the output module is configured to control the output of a gate control signal at the signal output terminal according to the potential of the first node and the second node.

[0009] Optionally, in some embodiments of the present invention, the output module includes a pull-up output transistor, a pull-down output transistor, and a first capacitor. The control terminal of the pull-up output transistor is electrically connected to the first node, the input terminal of the pull-up output transistor is electrically connected to the second voltage terminal, and the output terminal of the pull-up output transistor is electrically connected to the signal output terminal; the control terminal of the pull-down output transistor is electrically connected to the second node, the input terminal of the pull-down output transistor is electrically connected to the first voltage terminal, and the output terminal of the pull-down output transistor is electrically connected to the signal output terminal; the first capacitor is connected in series between the first node and the second voltage terminal.

[0010] Optionally, in some embodiments of the present invention, the second node pull-down module includes a first transistor and a second transistor. The control terminal of the first transistor is electrically connected to the first clock signal line, and the input terminal of the first transistor is electrically connected to the pull-down control line; the control terminal of the second transistor is electrically connected to the first voltage terminal, the input terminal of the second transistor is electrically connected to the output terminal of the first transistor, and the output terminal of the second transistor is electrically connected to the second node.

[0011] Optionally, in some embodiments of the present invention, the second node maintenance module includes a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, and a seventh transistor.

[0012] The control terminal of the third transistor is electrically connected to the first clock signal line, and the input terminal of the third transistor is electrically connected to the pull-down control line; the control terminal of the fourth transistor is electrically connected to the first voltage terminal, and the input terminal of the fourth transistor is electrically connected to the output terminal of the third transistor; the control terminal of the fifth transistor is electrically connected to the output terminal of the fourth transistor, the input terminal of the fifth transistor is electrically connected to the control terminal of the fifth transistor, and the output terminal of the fifth transistor is electrically connected to the second node; the control terminal of the sixth transistor is electrically connected to the control terminal of the fifth transistor, and the input terminal of the sixth transistor is electrically connected to the second clock signal line; the control terminal and input terminal of the seventh transistor are electrically connected to the output terminal of the sixth transistor, and the output terminal of the seventh transistor is electrically connected to the control terminal of the fifth transistor.

[0013] Optionally, in some embodiments of the present invention, the first node pull-down module includes an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor, and a second capacitor. The control terminal of the eighth transistor is electrically connected to the first clock signal line, and the input terminal of the eighth transistor is electrically connected to the first voltage terminal. The control terminal of the ninth transistor is electrically connected to the first voltage terminal, and the input terminal of the ninth transistor is electrically connected to the output terminal of the eighth transistor. The control terminal of the tenth transistor is electrically connected to the output terminal of the ninth transistor, and the input terminal of the tenth transistor is electrically connected to the second clock signal line. The control terminal of the eleventh transistor is electrically connected to the second clock signal line, and the input terminal of the eleventh transistor is electrically connected to the output terminal of the tenth transistor. The output terminal of the eleventh transistor is electrically connected to the first node. The second capacitor is connected in series between the control terminal and the output terminal of the tenth transistor.

[0014] Optionally, in some embodiments of the present invention, the second node maintenance module further includes a twelfth transistor, the control terminal of the twelfth transistor being electrically connected to the output terminal of the eighth transistor, the input terminal of the twelfth transistor being electrically connected to a second voltage terminal, and the output terminal of the twelfth transistor being electrically connected to the control terminal of the seventh transistor.

[0015] Optionally, in some embodiments of the present invention, the gate driving circuit further includes a first node pull-up module, the first node pull-up module including a thirteenth transistor, the control terminal of the thirteenth transistor being electrically connected to the output terminal of the first transistor, the input terminal of the thirteenth transistor being electrically connected to a second voltage terminal, and the output terminal of the thirteenth transistor being electrically connected to the first node.

[0016] Optionally, in some embodiments of the present invention, the first node pull-down module further includes a fourteenth transistor, the control terminal of the fourteenth transistor being electrically connected to the output terminal of the first transistor, the input terminal of the fourteenth transistor being electrically connected to the first clock signal line, and the output terminal of the fourteenth transistor being electrically connected to the output terminal of the eighth transistor.

[0017] Optionally, in some embodiments of the present invention, the gate driving circuit further includes a reset module, the reset module including a reset transistor, the control terminal of the reset transistor being electrically connected to a reset control line, the input terminal of the reset transistor being electrically connected to a second voltage terminal, and the output terminal of the reset transistor being electrically connected to the output terminal of the first transistor.

[0018] The present invention also provides a display panel including a plurality of gate driving circuits as described above; and a plurality of sub-pixels, wherein the plurality of sub-pixels are electrically connected to the plurality of gate driving circuits.

[0019] This invention provides a gate driving circuit and a display panel. The gate driving circuit includes a first node pull-down module, a second node pull-down module, a second node holding module, and an output module. The first node pull-down module pulls down the potential of the first node according to a first clock signal, a second clock signal, and a first voltage. The second node pull-down module pulls down the potential of the second node according to a second clock signal and a pull-down control signal, so that the variable at the signal output terminal of the gate driving circuit is coupled to the second node. The second node holding module holds the potential of the second node according to the first clock signal, the second clock signal, and the pull-down control signal. The output module outputs a gate control signal according to the potential control signal of the first and second nodes. By including the second node pull-down module in the gate driving circuit, when the potential of the second node is pulled down, the variable at the signal output terminal can be coupled to the second node, further pulling down the potential of the second node, thereby reducing the voltage loss of the gate control signal output by the output module. By setting the second node holding module, the potential of the second node can be maintained at a low potential after being pulled down. The display panel includes multiple sub-pixels and multiple gate driving circuits. Attached Figure Description

[0020] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0021] Figure 1 This is a schematic diagram of an existing gate drive circuit;

[0022] Figure 2 Is with Figure 1 The corresponding timing diagram;

[0023] Figure 3 This is a schematic diagram of the gate driving circuit provided in an embodiment of the present invention;

[0024] Figure 4 This is provided by the embodiments of the present invention. Figure 3 The timing diagram corresponding to the gate drive circuit shown;

[0025] Figure 5 This is a schematic diagram of a display panel provided in an embodiment of the present invention. Detailed Implementation

[0026] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention. Furthermore, it should be understood that the specific embodiments described herein are only for illustration and explanation of the present invention and are not intended to limit the present invention. In the present invention, unless otherwise stated, directional terms such as "upper" and "lower" generally refer to the upper and lower positions of the device in actual use or operation, specifically the drawing directions in the accompanying drawings; while "inner" and "outer" refer to the outline of the device.

[0027] Specifically, such as Figure 3 This is a schematic diagram of the gate driving circuit provided in an embodiment of the present invention. The embodiment of the present invention provides a gate driving circuit, including a first node pull-down module 100, a second node pull-down module 200, a second node maintenance module 300, and an output module 400.

[0028] The first node pull-down module 100 is electrically connected to the first clock signal line CKL1, the second clock signal line CKL2, the first voltage terminal VGL, and the first node N1. The first node pull-down module 100 is configured to pull down the potential of the first node N1 according to the first clock signal CK transmitted by the first clock signal line CKL1, the second clock signal XCK transmitted by the second clock signal line CKL2, and the first voltage transmitted by the first voltage terminal VGL.

[0029] The second node pull-down module 200 is electrically connected to the first clock signal line CKL1, the pull-down control line InL and the second node N2. The second node pull-down module 200 is configured to pull down the potential of the second node N2 according to the pull-down control signal In transmitted by the first clock signal CK and the pull-down control line InL, so that the variable of the signal output terminal Out of the gate drive circuit is coupled to the second node N2.

[0030] The second node maintenance module 300 is electrically connected to the first clock signal line CKL1, the second clock signal line CKL2, the pull-down control line InL and the second node N2. The second node maintenance module 300 is configured to maintain the potential of the second node N2 according to the first clock signal CK, the second clock signal CK and the pull-down control signal InL.

[0031] The output module 400 is electrically connected to the first node N1 and the second node N2. The output module 400 is configured to control the output gate control signal Scan at the signal output terminal Out according to the potentials of the first node N1 and the second node N2.

[0032] By configuring the second node pull-down module 200, when the potential of the second node N2 is pulled low, the variable at the signal output terminal Out can be coupled to the second node N2 to further pull down the potential of the second node N2. This allows the output module 400 to quickly transmit the first voltage to the signal output terminal Out according to the potential of the second node N2, thereby shortening the time for the gate control signal Scan to change from high to low and avoiding the voltage loss of 2|Vth| that occurs when the gate control signal Scan changes from high to low. Here, Vth is the threshold voltage of the pull-down output transistor To2 included in the output module 400.

[0033] Alternatively, please continue reading Figure 3 The output module 400 includes a pull-up output transistor To1, a pull-down output transistor To2, and a first capacitor C1.

[0034] The control terminal of the pull-up output transistor To1 is electrically connected to the first node N1, the input terminal of the pull-up output transistor To1 is electrically connected to the second voltage terminal VGH, and the output terminal of the pull-up output transistor To1 is electrically connected to the signal output terminal Out. The pull-up output transistor To1 transmits the second voltage output from the second voltage terminal VGH to the signal output terminal Out according to the potential of the first node N1.

[0035] The control terminal of the pull-down output transistor To2 is electrically connected to the second node N2, the input terminal of the pull-down output transistor To2 is electrically connected to the first voltage terminal VGL, and the output terminal of the pull-down output transistor To2 is electrically connected to the signal output terminal Out. The pull-down output transistor To2 transmits the first voltage output from the first voltage terminal VGL to the signal output terminal Out according to the potential of the second node N2.

[0036] The first capacitor C1 is connected in series between the first node N1 and the second voltage terminal VGH, and the first capacitor C1 is used to maintain the potential of the first node N1.

[0037] Optionally, the first voltage is less than the second voltage, so that when the pull-down output transistor To2 is turned on, the gate control signal Scan output by the gate drive circuit is pulled down from the first voltage to the second voltage.

[0038] Alternatively, please continue reading Figure 3 The second node pull-down module 200 includes a first transistor T1 and a second transistor T2.

[0039] The control terminal of the first transistor T1 is electrically connected to the first clock signal line CKL1, the input terminal of the first transistor T1 is electrically connected to the pull-down control line InL, and the output terminal of the first transistor T1 is electrically connected to the input terminal of the second transistor T2. The first transistor T1 transmits the pull-down control signal In to the input terminal of the second transistor T2 according to the first clock signal CK.

[0040] The control terminal of the second transistor T2 is electrically connected to the first voltage terminal VGL, and the output terminal of the second transistor T2 is electrically connected to the second node N2. The second transistor T2 is used to make the potential of the second node N2 the sum of the first voltage and the threshold voltage of the second transistor T2 when the pull-down control signal In is transmitted to the input terminal of the second transistor T2.

[0041] Alternatively, please continue reading Figure 3 The second node maintenance module 300 includes a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, and a seventh transistor T7.

[0042] The control terminal of the third transistor T3 is electrically connected to the first clock signal line CKL1, the input terminal of the third transistor T3 is electrically connected to the pull-down control line InL, and the output terminal of the third transistor T3 is electrically connected to the input terminal of the fourth transistor T4. The third transistor T3 transmits the pull-down control signal In to the input terminal of the fourth transistor T4 according to the first clock signal CK.

[0043] The control terminal of the fourth transistor T4 is electrically connected to the first voltage terminal VGL, and the output terminal of the fourth transistor T4 is electrically connected to the control terminal of the fifth transistor T5. The fourth transistor T4 is used to transmit the pull-down control signal In to the control terminal of the fifth transistor T5 to control the conduction and cutoff of the fifth transistor T5.

[0044] The input terminal of the fifth transistor T5 is electrically connected to the control terminal of the fifth transistor T5, and the output terminal of the fifth transistor T5 is electrically connected to the second node N2; the fifth transistor T5 is used to make the potential of the second node N2 the sum of the first voltage and the threshold voltage of the fifth transistor T5 when the pull-down control signal In is transmitted to the input terminal of the fifth transistor T5.

[0045] The control terminal of the sixth transistor T6 is electrically connected to the control terminal of the fifth transistor T5. The input terminal of the sixth transistor T6 is electrically connected to the second clock signal line CKL2. The output terminal of the sixth transistor T6 is electrically connected to the control terminal and input terminal of the seventh transistor T7. The output terminal of the seventh transistor T7 is electrically connected to the control terminal of the fifth transistor T5. The sixth transistor T6 transmits the second clock signal XCK to the control terminals of the seventh transistor T7 and the fifth transistor T5 according to the pull-down control signal In.

[0046] Alternatively, please continue reading Figure 3 The first node pull-down module 100 includes an eighth transistor T8, a ninth transistor T9, a tenth transistor T10, an eleventh transistor T11, and a second capacitor C2.

[0047] The control terminal of the eighth transistor T8 is electrically connected to the first clock signal line CKL1, the input terminal of the eighth transistor T8 is electrically connected to the first voltage terminal VGL, and the output terminal of the eighth transistor T8 is electrically connected to the input terminal of the ninth transistor T9.

[0048] The control terminal of the ninth transistor T9 is electrically connected to the first voltage terminal VGL, and the output terminal of the ninth transistor T9 is electrically connected to the control terminal of the tenth transistor T10.

[0049] The input terminal of the tenth transistor T10 is electrically connected to the second clock signal line CKL2, and the output terminal of the tenth transistor T10 is electrically connected to the input terminal of the eleventh transistor T11.

[0050] The control terminal of the eleventh transistor T11 is electrically connected to the second clock signal line CKL2, and the output terminal of the eleventh transistor T11 is electrically connected to the first node N1.

[0051] The second capacitor C2 is connected in series between the control terminal of the tenth transistor T10 and the output terminal of the tenth transistor T10.

[0052] Alternatively, please continue reading Figure 3 The second node maintenance module 300 further includes a twelfth transistor T12. The control terminal of the twelfth transistor T12 is electrically connected to the output terminal of the eighth transistor T8. The input terminal of the twelfth transistor T12 is electrically connected to the second voltage terminal VGH. The output terminal of the twelfth transistor T12 is electrically connected to the control terminal of the seventh transistor T7. The twelfth transistor T12 controls the conduction or cutoff of the seventh transistor T7 through the second voltage.

[0053] Alternatively, please continue reading Figure 3 The gate drive circuit further includes a first node pull-up module 500, which includes a thirteenth transistor T13. The control terminal of the thirteenth transistor T13 is electrically connected to the output terminal of the first transistor T1, the input terminal of the thirteenth transistor T13 is electrically connected to the second voltage terminal VGH, and the output terminal of the thirteenth transistor T13 is electrically connected to the first node N1. The thirteenth transistor T13 pulls up the potential of the first node N1 through the second voltage.

[0054] Alternatively, please continue reading Figure 3 The first node pull-down module 100 further includes a fourteenth transistor T14. The control terminal of the fourteenth transistor T14 is electrically connected to the output terminal of the first transistor T1, the input terminal of the fourteenth transistor T14 is electrically connected to the first clock signal line CKL1, and the output terminal of the fourteenth transistor T14 is electrically connected to the output terminal of the eighth transistor T8.

[0055] Optionally, the fourteenth transistor is a dual-gate transistor to reduce leakage current.

[0056] Alternatively, please continue reading Figure 3The gate drive circuit further includes a reset module 600, which includes a reset transistor Tin. The control terminal of the reset transistor Tin is electrically connected to the reset control line RL, the input terminal of the reset transistor Tin is electrically connected to the second voltage terminal VGH, and the output terminal of the reset transistor Tin is electrically connected to the output terminal of the first transistor T1. The reset transistor Tin resets the potential of the output terminal of the first transistor T1 according to the reset control signal Rst transmitted by the reset control line RL.

[0057] Figure 4 This is provided by the embodiments of the present invention. Figure 3 The timing diagram corresponding to the gate drive circuit shown is illustrated below. Taking the example that all transistors included in the gate drive circuit are P-type transistors, the working principle of the gate drive circuit is explained as follows.

[0058] In the first stage t1: the second clock signal XCK and the pull-down control signal In are at low level, and the first clock signal CK and the reset control signal Rst are at high level.

[0059] The eleventh transistor T11 is turned on according to the second clock signal XCK. The control terminal of the tenth transistor T10 is turned on because it has maintained a low level in the previous stage. The input terminal of the tenth transistor T10 transmits the second clock signal XCK to the first node N1, so that the pull-up output transistor To1 is turned on. The second voltage is output to the signal output terminal Out through the pull-up output transistor To1. The second clock signal XCK is coupled to the control terminal of the twelfth transistor T12 through the second capacitor C2, so that the twelfth transistor T12 is turned on. The second voltage is transmitted to the control terminal of the seventh transistor T7 through the twelfth transistor T12, so that the seventh transistor T7 is turned off. The reset transistor Tin is turned off according to the reset control signal Rst. The first transistor T1, the third transistor T3, and the eighth transistor T8 are turned off according to the first clock signal CK. The control terminals of the fifth transistor T5, the sixth transistor T6, the thirteenth transistor T13, the fourteenth transistor T14, and the pull-down output transistor To2 are turned off because they have maintained a high level in the previous stage.

[0060] In the second stage t2, the pull-down control signal In is low, and the first clock signal CK, the second clock signal XCK, and the reset control signal Rst are high.

[0061] The eleventh transistor T11 is turned off according to the second clock signal XCK, the first capacitor C1 keeps the pull-up output transistor To1 on, and the second voltage is output to the signal output terminal Out through the pull-up output transistor To1. The reset transistor Tin is turned off according to the reset control signal Rst, the first transistor T1, the third transistor T3 and the eighth transistor T8 are turned off according to the first clock signal CK, and the fifth transistor T5, the sixth transistor T6, the dual-gate seventh transistor T7, the thirteenth transistor T13, the fourteenth transistor T14 and the pull-down output transistor To2 remain off.

[0062] In the third stage t3: the first clock signal CK and the pull-down control signal In are at low level, and the second clock signal XCK and the reset control signal Rst are at high level.

[0063] The first transistor T1, the third transistor T3, and the eighth transistor T8 are turned on. The pull-down control signal In is transmitted via the first transistor T1 to the control terminals of the pull-down output transistor To2, the thirteenth transistor T13, and the fourteenth transistor T14, causing the potential of the control terminal of the pull-down output transistor To2 to become the sum of the first voltage and the threshold voltage of the third transistor T3 (i.e., L + |Vth - T3|). The turn-on of the third transistor T3 causes the fifth transistor T5 and the sixth transistor T6 to turn on, and the potential of the control terminal of the fifth transistor T5 to become the sum of the first voltage and the threshold voltage of the fourth transistor T4. Since a P-type transistor needs to satisfy a gate-source voltage difference of less than a threshold voltage to turn on, when the potential of the control terminal of the pull-down output transistor To2 is the sum of the first voltage and the threshold voltage of the third transistor T3, the potential of the signal output terminal Out needs to be the sum of twice the first voltage and the threshold voltage of the third transistor T3 (i.e., L + 2|Vth - T3|) to turn on. Therefore, the signal output terminal Out changes from the second voltage of the second stage t2 to L+2|Vth_T3| of the third stage t3, resulting in a voltage change of L+2|Vth_T3|-H at the signal output terminal Out. This voltage change at the signal output terminal Out is coupled to the control terminal of the pull-down output transistor To2 via the parasitic capacitance between the gate and source, causing the potential of the control terminal of the pull-down output transistor To2 to be pulled down from L+|Vth_T3| to a lower potential. This allows the pull-down output transistor To2 to be fully turned on, and the first voltage can be output to the signal output terminal Out via the pull-down output transistor To2. This prevents a 2|Vth| voltage loss when the gate control signal Scan output by the gate drive circuit is converted from the second voltage to the first voltage. The fourteenth transistor T14 and the eighth transistor T8 are turned on, causing the tenth transistor T10 and the twelfth transistor T12 to turn on. The twelfth transistor T12 and the sixth transistor T6 are turned on, causing the seventh transistor T7 to turn off. The thirteenth transistor T13 is turned on, causing the second voltage to be transmitted to the control terminal of the pull-up output transistor To1, thereby controlling the pull-up output transistor To1 to turn off. Here, H represents the voltage value corresponding to the first voltage, L represents the voltage value corresponding to the second voltage, and Vth_T3 represents the threshold voltage of the third transistor T3.

[0064] In the fourth stage t4, the pull-down control signal In is low, while the first clock signal CK, the second clock signal XCK, and the reset control signal Rst are high.

[0065] The first transistor T1, the third transistor T3, and the eighth transistor T8 are turned off according to the first clock signal CK, and the eleventh transistor T11 is turned off according to the second clock signal XCK. The first capacitor C1 keeps the pull-up output transistor To1 off, while the thirteenth transistor T13 and the pull-down output transistor To2 remain on. The first voltage is transmitted to the signal output terminal Out. The fifth transistor T5, the sixth transistor T6, the tenth transistor T10, and the fourteenth transistor T14 remain on. The first clock signal CK charges the second capacitor C2, raising the potential of the control terminals of the tenth transistor T10 and the twelfth transistor T12. The second clock signal XCK is transmitted via the sixth transistor T6 to the control terminal of the seventh transistor T7, causing the seventh transistor T7 to turn off. The reset transistor Tin is turned off according to the reset control signal Rst.

[0066] In the fifth stage t5, the second clock signal XCK and the pull-down control signal In are at a low level, while the first clock signal CK and the reset control signal Rst are at a high level.

[0067] The fifth transistor T5 and the sixth transistor T6 remain on (i.e., the potential of the control terminals of the fifth transistor T5 and the sixth transistor T6 is the sum of the first voltage and the threshold voltage of the fourth transistor T4, L+|Vth_T4|). Therefore, the second clock signal XCK, through the sixth transistor T6, causes the potential of the control terminal of the seventh transistor T7 to become L+2|Vth_T4|. Thus, the voltage change generated by the control terminal of the seventh transistor T7 changing from the high level H1 of the fourth stage t4 to L+|Vth_T4| of the fifth stage t5 is L+2|Vth_T4|-H1. The voltage change at the control terminal of the seventh transistor T7 is coupled to the potentials of the control terminals of the fifth transistor T5 and the sixth transistor T6 via the gate-source parasitic capacitance and gate-drain parasitic capacitance of the seventh transistor T7 itself. This causes the potentials of the control terminals of the fifth transistor T5 and the sixth transistor T6 to change from the original L+|Vth_T4 to a lower potential, which in turn causes the potential of the control terminal of the seventh transistor T7 to decrease further from L+2|Vth_T4|. Then, the potentials of the control terminals of the fifth transistor T5 and the sixth transistor T6 are coupled again via the gate-source parasitic capacitance and gate-drain parasitic capacitance of the seventh transistor T7 itself, causing the potentials of the control terminals of the fifth transistor T5 and the sixth transistor T6 to decrease further. Since the control terminal and input terminal of the fifth transistor T5 are shorted, the control terminal and input terminal of the fifth transistor T5 are at the same potential. The potential of the control terminal of the pull-down output transistor To2 can be coupled through the gate-source parasitic capacitance and gate-drain parasitic capacitance of the fifth transistor T5 itself, so that the potential of the control terminal of the pull-down output transistor To2 is further reduced, thereby ensuring that the signal output terminal Out can stably output a low level for a long time.

[0068] like Figure 5 This is a schematic diagram of a display panel provided in an embodiment of the present invention. The present invention also provides a display panel including a plurality of gate driving circuits as described above; and a plurality of sub-pixels, wherein the plurality of sub-pixels are electrically connected to the plurality of gate driving circuits.

[0069] Optionally, multiple gate driving circuits are cascaded, and multiple sub-pixels are electrically connected to multiple gate driving circuits through multiple gate control lines.

[0070] It is understood that the display panel includes liquid crystal display panels, self-emissive display panels (including light-emitting devices such as organic light-emitting diodes, sub-millimeter light-emitting diodes, and micro light-emitting diodes).

[0071] This document uses specific examples to illustrate the principles and implementation methods of the present invention. The descriptions of the above embodiments are only for the purpose of helping to understand the method and core ideas of the present invention. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of the present invention. Therefore, the content of this specification should not be construed as a limitation of the present invention.

Claims

1. A gate driving circuit, characterized in that, include: The first node pull-down module is electrically connected to the first clock signal line, the second clock signal line, the first voltage terminal and the first node, and is configured to pull down the potential of the first node according to the first clock signal transmitted by the first clock signal line, the second clock signal transmitted by the second clock signal line and the first voltage transmitted by the first voltage terminal; The second node pull-down module is electrically connected to the first clock signal line, the pull-down control line and the second node, and is configured to pull down the potential of the second node according to the pull-down control signal transmitted by the first clock signal and the pull-down control line, so that the variable of the signal output terminal of the gate drive circuit is coupled to the second node. The second node maintenance module is electrically connected to the first clock signal line, the second clock signal line, the pull-down control line, and the second node, and is configured to maintain the potential of the second node according to the first clock signal, the second clock signal, and the pull-down control signal. as well as The output module, electrically connected to the first node and the second node, is configured to output a gate control signal at the signal output terminal based on the potentials of the first node and the second node.

2. The gate driving circuit according to claim 1, characterized in that, The output module includes: A pull-up output transistor, wherein the control terminal of the pull-up output transistor is electrically connected to the first node, the input terminal of the pull-up output transistor is electrically connected to the second voltage terminal, and the output terminal of the pull-up output transistor is electrically connected to the signal output terminal; A pull-down output transistor, wherein the control terminal of the pull-down output transistor is electrically connected to the second node, the input terminal of the pull-down output transistor is electrically connected to the first voltage terminal, and the output terminal of the pull-down output transistor is electrically connected to the signal output terminal; and The first capacitor is connected in series between the first node and the second voltage terminal.

3. The gate driving circuit according to claim 1, characterized in that, The second node dropdown module includes: The first transistor has its control terminal electrically connected to the first clock signal line and its input terminal electrically connected to the pull-down control line. The second transistor has its control terminal electrically connected to the first voltage terminal, its input terminal electrically connected to the output terminal of the first transistor, and its output terminal electrically connected to the second node.

4. The gate driving circuit according to claim 3, characterized in that, The second node maintenance module includes: The third transistor, the control terminal of which is electrically connected to the first clock signal line, and the input terminal of which is electrically connected to the pull-down control line; The fourth transistor has its control terminal electrically connected to the first voltage terminal and its input terminal electrically connected to the output terminal of the third transistor. The fifth transistor has its control terminal electrically connected to the output terminal of the fourth transistor, its input terminal electrically connected to the control terminal of the fifth transistor, and its output terminal electrically connected to the second node. The sixth transistor has its control terminal electrically connected to the control terminal of the fifth transistor, and its input terminal electrically connected to the second clock signal line. The seventh transistor has its control terminal and input terminal electrically connected to the output terminal of the sixth transistor, and its output terminal is electrically connected to the control terminal of the fifth transistor.

5. The gate driving circuit according to claim 4, characterized in that, The first node dropdown module includes: The eighth transistor has its control terminal electrically connected to the first clock signal line and its input terminal electrically connected to the first voltage terminal. The ninth transistor has its control terminal electrically connected to the first voltage terminal and its input terminal electrically connected to the output terminal of the eighth transistor. The tenth transistor has its control terminal electrically connected to the output terminal of the ninth transistor, and its input terminal electrically connected to the second clock signal line. The eleventh transistor, wherein its control terminal is electrically connected to the second clock signal line, its input terminal is electrically connected to the output terminal of the tenth transistor, and its output terminal is electrically connected to the first node; and The second capacitor is connected in series between the control terminal and the output terminal of the tenth transistor.

6. The gate driving circuit according to claim 5, characterized in that, The second node maintenance module also includes: The twelfth transistor has its control terminal electrically connected to the output terminal of the eighth transistor, its input terminal electrically connected to the second voltage terminal, and its output terminal electrically connected to the control terminal of the seventh transistor.

7. The gate driving circuit according to claim 5, characterized in that, The gate driving circuit further includes: The first node pull-up module includes a thirteenth transistor. The control terminal of the thirteenth transistor is electrically connected to the output terminal of the first transistor, the input terminal of the thirteenth transistor is electrically connected to a second voltage terminal, and the output terminal of the thirteenth transistor is electrically connected to the first node.

8. The gate driving circuit according to claim 5, characterized in that, The first node dropdown module also includes: The fourteenth transistor has its control terminal electrically connected to the output terminal of the first transistor, its input terminal electrically connected to the first clock signal line, and its output terminal electrically connected to the output terminal of the eighth transistor.

9. The gate driving circuit according to claim 8, characterized in that, The gate driving circuit further includes: A reset module includes a reset transistor, the control terminal of which is electrically connected to a reset control line, the input terminal of which is electrically connected to a second voltage terminal, and the output terminal of which is electrically connected to the output terminal of a first transistor.

10. A display panel, characterized in that, include: Multiple gate drive circuits as described in any one of claims 1 to 9; as well as Multiple sub-pixels are electrically connected to multiple gate drive circuits.

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