Display device

Abstract

Display device. A display device according to an embodiment of the disclosure includes a display panel including a display area provided with a plurality of pixels and a non-display area provided around the display area, a gate driver providing a scan signal and a light emission control signal to the display panel, and a controller driving the display panel according to a refresh rate. The plurality of pixels include a light emitting element and a pixel circuit driving the light emitting element. The pixel circuit is driven in a set including at least one refresh period and at least one hold period in low frequency driving. When a gray scale of an image changes, the controller dynamically controls the refresh rate during at least one set while changing and supplying a bias voltage during at least one hold period.

Description

Technical Field

[0001] This disclosure relates to a display device, and more specifically, for example, but not limited to, a display device using a variable refresh rate (VRR) mode, and this disclosure aims to reduce flicker at screen switching points by reducing the occurrence of brightness differences at points in time when the grayscale of an image changes (especially when the display device is driven at a low frequency in VRR mode). Background Technology

[0002] Organic light-emitting diodes (OLEDs) or display devices that use light-emitting elements such as OLEDs can be driven by various driving frequencies.

[0003] Recently, variable refresh rate (VRR) has also been requested as one of the various functions required for display devices. VRR is a technique that drives pixels by increasing the refresh rate at points where high-speed driving is required, while driving the display device at a constant frequency. Alternatively, VRR can be used to drive pixels by decreasing the refresh rate at points where power consumption must be reduced or low-speed driving is required.

[0004] The descriptions provided in the Background section should not be considered prior art simply because they are mentioned in or associated with the Background section. The Background section may include information describing one or more aspects of the subject matter art. Summary of the Invention

[0005] Because of flickering caused by changes in image grayscale (especially when the display is driven at a low frequency in VRR mode), viewers may perceive screen transitions unnaturally. Therefore, it is necessary to prevent viewers from perceiving flickering caused by screen transitions.

[0006] Therefore, embodiments of this disclosure lie in a display device that substantially eliminates one or more problems caused by the limitations and disadvantages of the prior art.

[0007] This disclosure relates to a display device using a variable refresh rate (VRR) mode. One aspect of this disclosure is to reduce flicker at screen switching points by reducing the occurrence of brightness differences at the time points of image grayscale changes.

[0008] Additional features and aspects will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practicing the inventive ideas provided herein. Other features and aspects of the inventive idea may be realized and obtained by means of structures particularly pointed out in the written description, or structures derived therefrom, the claims, and the drawings.

[0009] To realize these and other aspects of the inventive concept as specifically implemented and summarized herein, a display device includes: a display panel comprising a display area having a plurality of pixels and a non-display area surrounding the display area; a gate driver providing scan signals and light emission control signals to the display panel; and a controller driving the display panel according to a refresh rate. The plurality of pixels includes light-emitting elements and pixel circuitry driving the light-emitting elements. In low-frequency driving, the pixel circuitry is driven in a set including at least one refresh cycle and at least one hold cycle. When the grayscale of an image changes, the controller dynamically controls the refresh rate during at least one set of cycles, while simultaneously changing and providing a bias voltage during at least one hold cycle.

[0010] The technical problems to be overcome in this document are not limited to those mentioned above. Those skilled in the art will clearly understand from the following description other technical problems not mentioned.

[0011] It should be understood that the above general description and the following detailed description are exemplary and explanatory, and are intended to provide further explanation of the claimed inventive concept. Attached Figure Description

[0012] The accompanying drawings may be included to provide a further understanding of this disclosure and may be incorporated into and constitute a part of this disclosure. The drawings illustrate embodiments of this disclosure and, together with the description, serve to explain the various principles of this disclosure.

[0013] Figure 1 This is a block diagram schematically illustrating a display device according to an exemplary embodiment of the present disclosure; Figure 2 This is a cross-sectional view showing a stacked display device according to an exemplary embodiment of the present disclosure; Figure 3 This is a view illustrating the configuration of the gate driver in a display device according to an exemplary embodiment of the present disclosure; Figure 4 This is a view showing pixel circuitry in a display device according to an exemplary embodiment of the present disclosure; Figures 5A to 5C This is for describing exemplary embodiments according to this disclosure. Figure 4 A view showing the operation of the scan signal and the light emission control signal during the refresh cycle and the hold cycle in the pixel circuit shown; Figure 6 This is a view used to describe a multi-refresh drive when a low-frequency drive is executed in VRR mode according to an exemplary embodiment of this disclosure; Figures 7 to 10 This is a view used to describe a brightness deviation compensation driving method in a display device according to an exemplary embodiment of the present disclosure; and Figure 11 This is a view illustrating the effect of applying a brightness deviation compensation drive according to an exemplary embodiment of the present disclosure.

[0014] Throughout the accompanying drawings and detailed description, unless otherwise stated, the same reference numerals should be understood to refer to the same elements, features, and structures. For clarity, illustrative purposes, the relative dimensions and descriptions of these elements may be enlarged.

[0015] Figure Labels

[0016] 100: Display panel

[0017] 200: Controller

[0018] 300: Gate driver

[0019] 400: Data Drive

[0020] 500: Power supply Detailed Implementation

[0021] Reference will now be made in detail to embodiments of this disclosure, examples of which are illustrated in the accompanying drawings. In the following description, detailed descriptions of well-known functions or configurations relevant to this document will be omitted where such obscuration of the essential points of the inventive concept is deemed unnecessary. The described progression of processing steps and / or operations is illustrative; however, the order of steps and / or operations is not limited to the order set forth herein and can be varied as is known in the art, except for steps and / or operations that must occur in a specific order. The names of the various elements used in the following description may be chosen solely for convenience in writing the specification and may differ from the names used in actual products.

[0022] The features, advantages, and implementations of this disclosure will become more apparent from the detailed embodiments described below and the accompanying drawings. However, this disclosure is not limited to the embodiments disclosed below, but is implemented in various different forms. The embodiments provide the full scope of this disclosure and are intended only to enable those skilled in the art to fully understand the scope of this disclosure. This disclosure is defined solely by the scope of the appended claims. Throughout this disclosure, the same reference numerals correspond to the same elements.

[0023] The shapes, dimensions, ratios, angles, quantities, etc., shown in the accompanying drawings to illustrate various exemplary embodiments of this disclosure are given by way of example only. Therefore, this disclosure is not limited to the illustrations in the drawings.

[0024] Any implementation described in this document as an “example” should not be interpreted as being more preferred or advantageous than other implementations.

[0025] When interpreting a component, the component is interpreted as including a range of errors or tolerances, even if there is no explicit description of such a range of errors or tolerances.

[0026] In the description of various embodiments of this disclosure, when describing positional relationships, for example, when the positional relationship between two components is described as such as "above," "over," "below," and "next to," one or more other components may be located between the two components unless more restrictive terms such as "exactly" or "directly" are used. For example, when one element or layer is disposed "above" another element or layer, a third layer or element may be inserted in between.

[0027] The phrase "connected to" or "linked to" another component includes cases where a component is directly connected to or linked to another component, as well as cases where yet another component is inserted in between. Conversely, the phrase "directly connected to" or "directly linked to" another component indicates that no other component is inserted in between. The term "and / or" includes each of the mentioned items and one or more combinations thereof.

[0028] The terminology used in this specification is used only to describe specific embodiments of this disclosure and is not restrictive. Unless otherwise specified, singular expressions in this specification include their plural forms. The terms "comprising," "having," and "including" as used in this specification are intended to designate the features, quantities, steps, operations, components, parts, or any combination thereof mentioned in the specification, and are not intended to exclude the presence or addition of at least one other feature, quantity, step, operation, component, part, or any combination thereof.

[0029] While terms such as first, second, A, B, (a), and (b) can be used to describe various components, components are not limited by these terms. These terms are only used to distinguish one component from others.

[0030] The term “at least one” should be understood to include any and all combinations of one or more associated listed items. For example, “at least one of the first element, the second element, and the third element” means a combination of all three listed elements, a combination of any two of the three elements, and each individual element, i.e., the first element, the second element, or the third element.

[0031] Therefore, within the spirit and scope of this disclosure, the first component described below can be the second component. Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. Furthermore, common terms as defined in dictionaries should not be ideally or over-interpreted unless they are clearly and specifically defined in this application.

[0032] Figure 1 This is a block diagram schematically illustrating a display device according to an exemplary embodiment of the present disclosure.

[0033] Reference Figure 1 The display device 10 includes: a display panel 100 including a plurality of pixels P; a controller 200; a gate driver 300 providing a gate signal to each of the plurality of pixels P; a data driver 400 providing a data signal to each of the plurality of pixels P; and a power supply 500 providing the power required to drive the pixels to each of the plurality of pixels P. However, embodiments of this disclosure are not limited to such examples.

[0034] Figure 2 This is a cross-sectional view illustrating a stacked display device according to an exemplary embodiment of the present disclosure.

[0035] Reference Figure 2 The display panel 100 includes a display area AA (see...) Figure 2 ) and non-display area NA (see Figure 2 Pixel P is located in display area AA. Non-display area NA is configured to be adjacent to or surround display area AA. Gate driver 300 and data driver 400 are disposed in non-display area NA. However, the implementation is not limited to this. For example, at least one of gate driver 300 and data driver 400 may be separately disposed from and connected to display panel 100. Alternatively, at least a portion of at least one of gate driver 300 and data driver 400 may be disposed in display area AA.

[0036] In the display panel 100, multiple gate lines GL and multiple data lines DL intersect each other, and each of the multiple pixels P is connected to the gate lines GL and data lines DL. Specifically, a pixel P receives a gate signal from the gate driver 300 via the gate line GL, receives a data signal from the data driver 400 via the data line DL, and receives a high-level drive voltage EVDD and a low-level drive voltage EVSS from the power supply 500.

[0037] Here, the gate line GL provides the scan signal SC and / or the light emission control signal EM, and the data line DL provides the data voltage Vdata. Furthermore, according to various embodiments, the gate line GL may include multiple scan lines SCL for providing the scan signal SC and / or a light emission control signal line EML for providing the light emission control signal EM. Additionally, the multiple pixels P may further include a power supply line VL, and may receive a bias voltage Vobs and initialization voltages Var and Vini.

[0038] In addition, such as Figure 2 As shown, each pixel in pixel P may include a light-emitting element EL and a pixel circuit that controls the driving of the light-emitting element EL. Here, the light-emitting element EL may include an anode 171, a cathode 173, and a light-emitting layer 172 located between the anode 171 and the cathode 173.

[0039] Pixel circuitry may include switching elements, driving elements, and / or capacitors. Here, the switching and driving elements may be composed of thin-film transistors. In the pixel circuitry, the driving element controls the amount of light emitted by the light-emitting element EL by controlling the amount of current supplied to the light-emitting element EL according to the data voltage. Furthermore, the switching element operates the pixel circuitry by receiving scan signals SC provided through multiple scan lines SCL and / or light-emitting control signals EM provided through the light-emitting control signal line EML.

[0040] Display panel 100 can be implemented as a non-transmissive display panel or a transmissive display panel. Transmissive display panels can be applied to transparent display devices in which an image is displayed on the screen and real objects in the background are visible. Display panel 100 can be manufactured as a flexible display panel, wherein pixels P are disposed on a flexible substrate (such as a plastic substrate, metal substrate, etc.) or a rigid display panel. For example, a flexible display panel can be implemented using a panel with a plastic substrate (e.g., an OLED panel). In flexible displays, the size and shape of the screen can be changed by rolling, folding, and bending the flexible display panel.

[0041] Each pixel in pixel P can be divided into red, green, and blue pixels for color implementation. Alternatively, each pixel in pixel P may also include a white pixel. Each pixel in pixel P includes pixel circuitry. The color of pixel P is not limited to this. For example, pixel P can also be divided into magenta, yellow, and cyan pixels, or combinations of other colors.

[0042] As an example, a touch sensor can be disposed on the display panel 100. Touch input can be sensed by using a separate touch sensor, or by sensing through a pixel P. The touch sensor can be implemented as an on-cell type or add-on type touch sensor disposed on the screen of the display panel 100, or as an in-cell type touch sensor embedded in the display panel 100.

[0043] The controller 200 appropriately processes externally input image data (RGB) according to the size and resolution of the display panel 100, and provides the processed image data to the data driver 400. The controller 200 generates a gate control signal GCS and a data control signal DCS using (e.g., externally input) synchronization signals (e.g., a dot clock signal CLK, a data enable signal DE, a horizontal synchronization signal Hsync, and a vertical synchronization signal Vsync). The generated gate control signal GCS and data control signal DCS are provided to the gate driver 300 and the data driver 400, respectively, thereby controlling the gate driver 300 and the data driver 400.

[0044] The controller 200 can be configured by being connected to various processors (e.g., microprocessors, mobile processors, application processors, etc., depending on the device to which it is installed).

[0045] The host system can be, for example, any of a television (TV) system, set-top box, navigation system, personal computer (PC), home theater system, mobile device, wearable device, and vehicle system. However, embodiments of this disclosure are not limited to these examples.

[0046] The controller 200 can multiply the input frame rate by "i" and control the operating timing of the display panel driver at a frame rate of input frame rate × "i" (where "i" is a positive integer greater than 0) Hz. In the National Television Standards Committee (NTSC) method, the input frame rate is 60 Hz, while in the Phase-Alternating Line (PAL) method, the input frame rate is 50 Hz. However, the implementation is not limited to these. The input frame rate can be any frame rate other than 50 Hz or 60 Hz.

[0047] The controller 200 generates signals that allow pixel P to be driven at various refresh rates. That is, the controller 200 generates drive-related signals that enable pixel P to be driven in variable refresh rate (VRR) mode or in a manner switchable between a first refresh rate and a second refresh rate. For example, the controller 200 can drive pixel P at various refresh rates by simply changing the speed of the clock signal, by generating a synchronization signal and producing horizontal or vertical blanking, or by driving the gate driver 300 in a mask-like manner.

[0048] Based on the timing signals Vsync, Hsync, CLK, and DE received from the host system, the controller 200 generates a gate control signal GCS for controlling the operating timing of the gate driver 300 and a data control signal DCS for controlling the operating timing of the data driver 400. The controller 200 synchronizes the gate driver 300 and the data driver 400 by controlling the operating timing of the display panel driver.

[0049] The voltage level of the gate control signal GCS output from controller 200 can be converted into gate-on voltage VGL and / or VEL and gate-off voltage VGH and / or VEH by a level shifter (not shown), and supplied to gate driver 300. The level shifter converts the low-level voltage of the gate control signal GCS into a gate low voltage VGL, and the high-level voltage of the gate control signal GCS into a gate high voltage VGH. The gate control signal GCS may include at least a start pulse, a shift clock, a reset signal, an initialization signal, etc.

[0050] The gate driver 300 provides a scan signal SC to the gate line GL according to the gate control signal GCS provided from the controller 200. The gate driver 300 may be disposed on one or both sides of the display panel 100 in a gate-in-panel (GIP) manner. However, the implementation is not limited to this. As an example, the gate driver 300 may be implemented by a chip-on-film (COF) method in which the components are mounted on a film connected to the display panel 100.

[0051] Under the control of the controller 200, the gate driver 300 sequentially outputs the gate signal to multiple gate lines GL. The gate driver 300 can also provide the gate signal to the gate lines GL sequentially by using a shift register to shift the gate signal.

[0052] In an organic light-emitting display device, the gate signal may include a light-emitting control signal EM and / or a scan signal SC. The scan signal SC includes a scan pulse that transitions between a gate on-voltage VGL and a gate off-voltage VGH. The light-emitting control signal EM may include a light-emitting control signal pulse that transitions between a gate on-voltage VEL and a gate off-voltage VEH.

[0053] The scan pulse is synchronized with the data voltage Vdata and selects the pixel P on the line where data is to be written. The emission control signal EM defines the emission time of pixel P.

[0054] The gate driver 300 may include a light emission control signal driver 310 and / or at least one scan driver 320.

[0055] The light emission control signal driver 310 outputs a light emission control signal pulse in response to the start pulse and shift clock from the controller 200, and shifts the light emission control signal pulse sequentially according to the shift clock.

[0056] At least one scan driver 320 outputs a scan pulse in response to a start pulse and a shift clock from the controller 200, and shifts the scan pulse according to the shift clock timing.

[0057] The data driver 400 converts image data RGB into data voltage Vdata according to the data control signal DCS provided from the controller 200, and provides the converted data voltage Vdata to the pixel P through the data line DL according to the timing of the scan signal applied through the gate line GL.

[0058] Despite Figure 1 In this diagram, the data driver 400 is shown arranged in one form on one side of the display panel 100, but the number and position of the data drivers 400 are not limited thereto.

[0059] For example, the data driver 400 may consist of multiple integrated circuits (ICs) and may be divided into multiple parts disposed on one side of the display panel 100. Furthermore, the data driver 400 may be connected to bonding pads of the display panel 100 via tape automated bonding (TAB) or chip-on-glass (COG) methods. Alternatively, the data driver 400 may be directly disposed on the display panel 100. Alternatively, the data driver 400 may be integrated and arranged on the display panel 100. Alternatively, the data driver 400 may be implemented using a chip-on-film (COF) method. In this case, the data driver 400 may be mounted on a film connected to the display panel 100 and may be electrically connected to the display panel 100 via wires on the film.

[0060] Power supply 500 generates the DC power required to drive the pixel array and display panel driver of display panel 100 using a DC-DC converter. The DC-DC converter may include a charge pump, regulator, buck converter, boost converter, programmable gamma integrated circuit (P-GMA IC), etc. Power supply 500 receives a DC input voltage applied from a host system (not shown) and can generate gate on-state voltages VGL and VEL, gate off-state voltages VGH and VEH, high-level drive voltage EVDD, low-level drive voltage EVSS, etc. Gate on-state voltages VGL and VEL and gate off-state voltages VGH and VEH are supplied to a level shifter (not shown) and gate driver 300. One or more of the high-level drive voltage EVDD, low-level drive voltage EVSS, initialization voltage Vini, and reference voltage Vref (e.g., commonly or separately) are supplied to pixel P. The high-level drive voltage EVDD can be set to a voltage higher than the low-level drive voltage EVSS, initialization voltage Vini, and reference voltage Vref.

[0061] Figure 2 This is a cross-sectional view illustrating a stacked display device according to an exemplary embodiment of the present disclosure.

[0062] Reference Figure 2 A thin-film transistor (TFT) for driving the light-emitting element (EL) can be disposed in a display area AA on a substrate 101. The TFT may include a semiconductor layer 115, a gate 125, a source 140, a drain 140, and a second insulating layer 120 located between the gate 125 and the semiconductor layer 115. The TFT may be a driving transistor DT (see...). Figure 4 For ease of description, only the driving transistor DT, which can be included in various thin-film transistors in the display device 10, is shown. However, other thin-film transistors, such as switching transistors, may also be included in the display device 10. Furthermore, although the thin-film transistor TFT with a coplanar structure has been described in this disclosure, the thin-film transistor can also be implemented with another structure, such as an interlaced structure, and is not limited thereto.

[0063] The driving transistor DT receives a high-potential driving voltage EVDD in response to the data signal supplied to its gate 125, and controls the current supplied to the light-emitting element EL, thereby controlling the amount of light emitted by the light-emitting element EL. The driving transistor DT can supply a constant current until the voltage charged into the storage capacitor (not shown) supplies the data signal for the next frame, allowing the light-emitting element EL to continue emitting light. A high-potential power line can be formed parallel to the data line.

[0064] like Figure 2 As shown, a thin-film transistor (TFT) may include a semiconductor layer 115 disposed on a substrate 101 (e.g., on a first insulating layer 110 on the substrate 101), a gate 125 overlapping the semiconductor layer 115 and interposed therebetween with a second insulating layer 120, and a source 140 and a drain 140 disposed on a third insulating layer 135 and in contact with the semiconductor layer 115.

[0065] Semiconductor layer 115 can be the region forming a channel when driving a thin-film transistor (TFT). Semiconductor layer 115 can be a polycrystalline semiconductor. The polycrystalline semiconductor can be formed from low-temperature polysilicon (LTPS) with high mobility, but is not limited thereto. For example, semiconductor layer 115 can be formed from or include oxide semiconductors, but is not limited thereto. Alternatively, semiconductor layer 115 can be formed from various inorganic or organic semiconductors such as amorphous silicon (a-Si), polycrystalline silicon (poly-Si), or pentacene, but is not limited thereto. When semiconductor layer 115 is formed from or includes oxide semiconductors, it has an excellent effect of preventing leakage current, thereby reducing or minimizing the brightness change of sub-pixels.

[0066] Semiconductor layer 115 may be formed on first insulating layer 110. Semiconductor layer 115 may include a channel region, a source region, and a drain region. The channel region may overlap with gate 125, with a second insulating layer 120 therebetween, and the channel region may be formed between source 140 and drain 140. The source region is electrically connected to source 140 through contact holes passing through second insulating layer 120 and third insulating layer 135. The drain region is electrically connected to drain 140 through contact holes passing through second insulating layer 120 and third insulating layer 135. First insulating layer 110 and / or buffer layer 105 may optionally be disposed between semiconductor layer 115 and substrate 101. Buffer layer 105 may reduce the permeation of moisture and / or oxygen that has already penetrated into substrate 101, and may be formed of a single layer or multiple layers. For example, buffer layer 105 may include a-Si, silicon nitride (SiNx), or silicon oxide (SiOx), but is not limited thereto. However, the implementation is not limited to this. For example, the buffer layer 105 can be formed from multiple layers of the same or different materials. Depending on the type and material of the substrate 101, the structure and type of the thin-film transistor, etc., the buffer layer 105 may be omitted.

[0067] The first insulating layer 110 protects the semiconductor layer 115 and can prevent various types of defects introduced from the substrate 101.

[0068] The buffer layer 105 may consist of at least one layer. The uppermost layer of the buffer layer 105 in contact with the first insulating layer 110 may be made of a material with etching characteristics different from those of the first insulating layer 110, the second insulating layer 120, the third insulating layer 135, and the other layers of the buffer layer 105. The uppermost layer of the buffer layer 105 in contact with the first insulating layer 110 may be made of either silicon nitride (SiNx) or silicon oxide (SiOx). The first insulating layer 110, the second insulating layer 120, the third insulating layer 135, and the other layers of the buffer layer 105 may be made of the other of silicon nitride (SiNx) and silicon oxide (SiOx). For example, the uppermost layer of the buffer layer 105 in contact with the first insulating layer 110 may be made of silicon nitride (SiNx), and the first insulating layer 110, the second insulating layer 120, the third insulating layer 135, and the other layers of the buffer layer 105 may be made of silicon oxide (SiOx), but is not limited thereto. Other materials may also be used for the buffer layer 105, the first insulating layer 110, the second insulating layer 120, and the third insulating layer 135.

[0069] A gate 125 is formed on a second insulating layer 120 and may overlap with a channel region of a semiconductor layer 115, with the second insulating layer 120 inserted between them. The gate 125 may be formed of a first conductive material, which may be a single layer or multiple layers made of any one or more of magnesium (Mg), molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or alloys thereof. However, the material of the gate is not limited to this. For example, the gate 125 may also be formed as a single layer or multiple layers made of other conductive materials, such as transparent conductive oxides like indium tin oxide (ITO) or indium zinc oxide (IZO).

[0070] The source 140 can be connected to the exposed source region of the semiconductor layer 115 through contact holes passing through the second insulating layer 120 and the third insulating layer 135. The drain 140 faces the source 140 and can be connected to the drain region of the semiconductor layer 115 through contact holes passing through the second insulating layer 120 and the third insulating layer 135. These source and drain electrodes 140 can be formed of a second conductive material, which can be a single layer or multiple layers made of any one or more elements such as magnesium (Mg), molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy containing two or more of these elements. However, the source and drain electrodes are not limited to this. For example, these source and drain electrodes 140 can also be formed of a single layer or multiple layers made of other conductive materials.

[0071] A connecting electrode 155 may be disposed between the first intermediate layer 150 and the second intermediate layer 160. The connecting electrode 155 may be exposed through a connecting electrode contact hole 156 passing through the protective layer 145 and the first intermediate layer 150, and may be connected to the drain electrode 140. The connecting electrode 155 may be made of the same or similar material as the drain electrode 140 (e.g., a material with low resistivity), for example, the connecting electrode 155 may be made of a conductive material such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or alloys thereof. However, the connecting electrode is not limited to this. The connecting electrode 155 may be omitted. In this case, the anode 171 of the light-emitting element EL may be directly connected to the drain electrode 140.

[0072] Reference Figure 2 The light-emitting element EL, including the light-emitting layer 172, can be disposed on the second intermediate layer 160 and the embankment layer 165. The light-emitting element EL may include an anode 171, at least one light-emitting layer 172 formed on the anode 171, and a cathode 173 formed on the light-emitting layer 172.

[0073] The anode 171 can be disposed on the first intermediate layer 150 through a contact hole passing through the second intermediate layer 160, and can be electrically connected to the connection electrode 155 exposed on the top of the second intermediate layer 160.

[0074] The anode 171 of each pixel is formed to be exposed through the dam layer 165. The dam layer 165 may be formed of an opaque material (e.g., black) to prevent or reduce optical interference between adjacent pixels. In this case, the dam layer 165 may include, but is not limited to, a light-shielding material made of at least one of colored pigments, organic black pigments, and carbon pigments.

[0075] Reference Figure 2At least one light-emitting layer 172 may be formed on the anode 171 of the light-emitting region provided by the embankment layer 165. The at least one light-emitting layer 172 may include at least one of various layers, such as a hole transport layer, a hole injection layer, a hole blocking layer, a light-emitting layer 172, an electron injection layer, an electron blocking layer, and an electron transport layer located on the anode 171. The light-emitting layer 172 may be formed by stacking layers in a sequential or reverse order according to the light emission direction. The hole transport layer, hole injection layer, hole blocking layer, electron injection layer, electron blocking layer, and electron transport layer may be common layers formed together in multiple sub-pixels. Furthermore, the light-emitting layer 172 may include a first light-emitting stack and a second light-emitting stack facing each other, with a charge-generating layer inserted between them. The charge-generating layer may have a PN junction structure and may include an N-type charge-generating layer and a P-type charge-generating layer. In this case, the light-emitting layer 172 of one of the first and second light-emitting stacks generates blue light, and the other light-emitting layer 172 of the other light-emitting stack generates yellow-green light. Therefore, white light can be generated through the first and second light-emitting layers. The implementation is not limited to this. For example, depending on the purpose of the display device, light of colors other than white can be generated through the first and second light-emitting layers or more layers. Since the white light generated from the light-emitting layers is incident on a color filter located above or below the light-emitting layer 172, a color image can be realized. As another example, a color image can be realized by generating colored light corresponding to each pixel in each light-emitting layer 172 without a separate color filter. For example, the light-emitting layer 172 of a red pixel can generate red light, the light-emitting layer 172 of a green pixel can generate green light, and the light-emitting layer 172 of a blue pixel can generate blue light.

[0076] Reference Figure 2 The cathode 173 is formed facing the anode 171, with a light-emitting layer 172 inserted therebetween. As an example, the cathode 173 can receive a high-potential drive voltage EVDD.

[0077] The encapsulation layer 180 can reduce or prevent external moisture or oxygen from penetrating into the light-emitting element (EL), which is susceptible to external moisture or oxygen. For this purpose, the encapsulation layer 180 may include, but is not limited to, an inorganic encapsulation layer consisting of at least one layer and / or an organic encapsulation layer consisting of at least one layer. In this disclosure, a structure of the encapsulation layer 180 in which a first encapsulation layer 181, a second encapsulation layer 182, and a third encapsulation layer 183 are sequentially stacked will be used as an example.

[0078] A first encapsulation layer 181 is formed on a substrate 101 on which a cathode 173 is formed to suppress the penetration of moisture or oxygen. A third encapsulation layer 183 is formed on a substrate 101 on which a second encapsulation layer 182 is formed, and may be formed together with the first encapsulation layer 181 to surround the top, bottom, and side surfaces of the second encapsulation layer 182. The first encapsulation layer 181 and the third encapsulation layer 183 can reduce, minimize, or prevent the penetration of external moisture or oxygen into the light-emitting element EL. The first encapsulation layer 181 and the third encapsulation layer 183 may be made of an inorganic insulating material (e.g., silicon nitride (SiNx), silicon oxide (SiOx), silicon oxynitride (SiNxOy), or aluminum oxide (Al)) that can be deposited at low temperatures. x O y The process can be made, but is not limited to, the first encapsulation layer 181 and the third encapsulation layer 183. Since the first encapsulation layer 181 and the third encapsulation layer 183 are deposited in a low-temperature atmospheric environment, damage to the light-emitting element EL, which is susceptible to the effects of a high-temperature atmospheric environment, can be reduced or prevented during the deposition process of the first encapsulation layer 181 and the third encapsulation layer 183.

[0079] The second encapsulation layer 182 can serve as a buffer layer, reducing or minimizing stress between layers caused, for example, by bending of the display device 10, and smoothing out step differences between layers. The second encapsulation layer 182 is formed on the substrate 101 on which the first encapsulation layer 181 is formed, but is not limited to, a non-photosensitive organic insulating material (such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, and polyethylene or silicon carbide (SiOxCy)) or a photosensitive organic insulating material (such as photosensitive acrylic). When the second encapsulation layer 182 is formed by inkjet printing, a dam DAM can be provided to prevent the liquid second encapsulation layer 182 from diffusing to the edges of the substrate 101. The dam DAM can be positioned closer to the edges of the substrate 101 than the second encapsulation layer 182. Due to the presence of the dam DAM, the diffusing of the second encapsulation layer 182 to the pad area where conductive pads located on the outermost edge of the substrate 101 are provided can be reduced or prevented.

[0080] The dam DAM is designed to prevent the diffusion of the second encapsulation layer 182. However, when the second encapsulation layer 182 is formed during the process to exceed the height of the dam DAM, the second encapsulation layer 182, as an organic layer, may be exposed to the outside. Therefore, this may allow moisture and other substances to more easily penetrate the light-emitting element. Therefore, as an example, to prevent this limitation, at least ten dam DAMs can be repeatedly formed. The implementation is not limited to this. As an example, fewer than ten dam DAMs can be formed. As another example, one dam DAM can be formed, or even the dam DAM can be omitted.

[0081] Reference Figure 2 The dam DAM can be set on the protective layer 145 of the non-display area NA.

[0082] Furthermore, the dam DAM can be formed simultaneously with at least one of the first intermediate layer 150 and the second intermediate layer 160. The lower layer of the dam DAM can be formed together with the first intermediate layer 150. The upper layer of the dam DAM can be formed together with the second intermediate layer 160. Therefore, the dam DAM can be formed as a double-layered stacked structure. However, the implementation is not limited to this. As an example, the dam DAM can be formed separately from the first intermediate layer 150 and the second intermediate layer 160, and can be formed as a single-layered structure or a stacked structure with more than one layer.

[0083] Therefore, the dam DAM can be made of the same material as the first intermediate layer 150 and the second intermediate layer 160, but is not limited to this.

[0084] Reference Figure 2 The dam DAM can be formed to overlap with the low-potential drive power line VSS. For example, in the non-display area NA, the low-potential drive power line VSS can be formed in a layer below the area where the dam DAM is located.

[0085] The low-potential drive power line VSS and the gate driver 300, configured in the form of a gate-in-panel (GIP), are formed to at least partially surround the exterior of the display panel. The low-potential drive power line VSS may be located further outward than the gate driver 300. Furthermore, the low-potential drive power line VSS may be connected to the anode 171 and apply a common voltage. However, the implementation is not limited to this. As an example, the low-potential drive power line VSS may be located further inward than the gate driver 300. The gate driver 300 is simply shown in the plan and cross-sectional views, but it can be configured by using a thin-film transistor TFT with the same structure as the thin-film transistor TFT of the display area AA.

[0086] Reference Figure 2 The low-potential drive power line VSS is positioned further outward than the gate driver 300. The low-potential drive power line VSS is positioned further outward than the gate driver 300 and at least partially surrounds the display area AA. The low-potential drive power line VSS may be made of the same material as, but is not limited to, the source and drain 140 of the thin-film transistor TFT. For example, the low-potential drive power line VSS may be made of the same material as the gate 125.

[0087] In addition, the low-potential drive power line VSS can be electrically connected to the anode 171. The low-potential drive power line VSS can supply low-potential drive voltage EVSS to multiple pixels in the display area AA.

[0088] Touch layer 190 may optionally be disposed on encapsulation layer 180. Touch buffer layer 191 of touch layer 190 may be located between touch sensor metal and cathode 173 of light-emitting element EL. Touch sensor metal includes touch electrode connection lines 192 and 194 and touch electrodes 195 and 196.

[0089] The touch buffer layer 191 can reduce or prevent chemical solutions (developer or etchant, etc.) used in the manufacturing process of the touch sensor metal disposed on the touch buffer layer 191 or moisture from the outside from penetrating into the light-emitting layer 172 (e.g., the light-emitting layer 172 including organic materials). Therefore, the touch buffer layer 191 can reduce or prevent damage to the light-emitting layer 172, which is susceptible to chemical solutions or moisture.

[0090] The touch buffer layer 191 is formed of a material (e.g., an organic material) that can be formed at a specific temperature (e.g., 100 °C or below) and has a low dielectric constant of 1 to 3 to reduce or prevent damage to the light-emitting layer 172, which includes materials susceptible to high temperatures (e.g., organic materials). For example, the touch buffer layer 191 may be formed of a propylene-based material, an epoxy-based material, or a siloxane-based material. The touch buffer layer 191, formed of an organic insulating material and having planarization properties, can reduce or prevent damage to the encapsulation layer 180 (e.g., due to bending of the organic light-emitting display device) and reduce or prevent damage to the touch sensor metal formed on the touch buffer layer 191.

[0091] According to the mutual capacitance-based touch sensor structure, touch electrodes 195 and 196 can be disposed on the touch buffer layer 191, and touch electrodes 195 and 196 can be arranged to cross each other.

[0092] Touch electrode connecting lines 192 and 194 can electrically connect touch electrodes 195 to each other, or touch electrodes 196 to each other. Touch electrode connecting lines 192 and 194, as well as touch electrodes 195 and 196, can be located in different layers, with a touch insulating layer 193 inserted between them.

[0093] As an example, touch electrode connection lines 192 and 194 can be arranged to overlap with the embankment 165, thereby preventing a reduction in the aperture ratio. However, the implementation is not limited to this. As an example, touch electrode connection lines 192 and 194 can be arranged to overlap with the light-emitting area.

[0094] Meanwhile, in touch electrodes 195 and 196, a portion of touch electrodes 195 and / or 196 or a portion of touch electrode connection line 192 can pass through the top and side surfaces of encapsulation layer 180 and the top and side surfaces of dam DAM, and can be electrically connected to touch drive circuit (not shown) via touch panel 198.

[0095] This portion of touch electrodes 195 and / or 196 or this portion of touch electrode connection line 192 can receive touch drive signals from the touch drive circuit and can send touch drive signals to touch electrodes 195 and / or 196, and can transmit touch sensing signals from touch electrodes 195 and 196 to the touch drive circuit.

[0096] A touch protection layer 197 may be disposed on touch electrodes 195 and 196. In the figure, the touch protection layer 197 is shown as being disposed only on touch electrodes 195 and 196, but is not limited thereto. The touch protection layer 197 may extend to the front and rear surfaces of the dam DAM and is disposed on the touch electrode connection line 192.

[0097] In addition, a color filter (not shown) may optionally be disposed on the encapsulation layer 180. The color filter may be disposed on the touch layer 190 or between the encapsulation layer 180 and the touch layer 190.

[0098] Figure 3 This is a view illustrating the configuration of a gate driver in a display device according to an exemplary embodiment of the present disclosure.

[0099] Reference Figure 3 The gate driver 300 includes a light emission control signal driver 310 and a scan driver 320. The scan driver 320 may include a first scan driver 321, a second scan driver 322, a third scan driver 323, and a fourth scan driver 324. In addition, the second scan driver 322 may include a second odd-numbered scan driver 322_O and a second even-numbered scan driver 322_E.

[0100] In the gate driver 300, shift registers can be symmetrically arranged on both sides of the display area AA. Furthermore, in the gate driver 300, the shift registers on one side of the display area AA can respectively include second scan drivers 322_O and 322_E, a fourth scan driver 324, and a light emission control signal driver 310. The shift registers on the other side of the display area AA can respectively include a first scan driver 321, second scan drivers 322_O and 322_E, and a third scan driver 323. However, this is not a limitation. According to this embodiment, the light emission control signal driver 310 and the first scan driver 321, second scan driver 322, third scan driver 333, and fourth scan driver 334 can be configured differently.

[0101] Each of the multiple stages STG1 to STGn of the shift register may include first scan signal generators SC1(1) to SC1(n), second scan signal generators SC2_O(1) to SC2_O(n) and SC2_E(1) to SC2_E(n), third scan signal generators SC3(1) to SC3(n), fourth scan signal generators SC4(1) to SC4(n), and light emission control signal generators EM(1) to EM(n).

[0102] The first scan signal generators SC1(1) to SC1(n) output first scan signals SC1(1) to SC1(n) through the first scan line SCL1 of the display panel 100. The second scan signal generators SC2_O(1) to SC2_O(n) and SC2_E(1) to SC2_E(n) output second scan signals SC2(1) to SC2(n) through the second scan line SCL2 of the display panel 100. The third scan signal generators SC3(1) to SC3(n) output third scan signals SC3(1) to SC3(n) through the third scan line SCL3 of the display panel 100. The fourth scan signal generators SC4(1) to SC4(n) output fourth scan signals SC4(1) to SC4(n) through the fourth scan line SCL4 of the display panel 100. The light emission control signal generators EM(1) to EM(n) output light emission control signals EM(1) to EM(n) through the light emission control line EML of the display panel 100, but the embodiments of this disclosure are not limited thereto.

[0103] The first scan signals SC1(1) to SC1(n) can be used as signals to drive the A-th transistor (e.g., a compensation transistor, etc.) included in the pixel circuit. The second scan signals SC2_O(1) to SC2_O(n) and SC2_E(1) to SC2_E(n) can be used as signals to drive the B-th transistor (e.g., a data supply transistor, etc.) included in the pixel circuit. The third scan signals SC3(1) to SC3(n) can be used as signals to drive the C-th transistor (e.g., a bias transistor, etc.) included in the pixel circuit. The fourth scan signals SC4(1) to SC4(n) can be used as signals to drive the D-th transistor (e.g., an initialization transistor, etc.) included in the pixel circuit. The light emission control signals EM(1) to EM(n) can be used as signals to drive the E-th transistor (e.g., a light emission control transistor, etc.) included in the pixel circuit. For example, when the light emission control transistor of the pixel is controlled by using the light emission control signals EM(1) to EM(n), the light emission time of the light-emitting element can be changed.

[0104] Reference Figure 3The bias voltage bus VobsL, the first initialization voltage bus VarL, and the second initialization voltage bus ViniL can be disposed between the gate driver 300 and the display area AA. Furthermore, although the bias voltage bus VobsL and the second initialization voltage bus ViniL are shown as being located on the left side of the display area AA, and the first initialization voltage bus VarL is shown as being located on the right side of the display area AA, embodiments of this disclosure are not limited thereto. Alternatively, the bias voltage bus VobsL, the first initialization voltage bus VarL, and the second initialization voltage bus ViniL can all be disposed on one side of the display area AA.

[0105] The bias voltage bus VobsL, the first initialization voltage bus VarL, and the second initialization voltage bus ViniL can respectively provide bias voltage Vobs, first initialization voltage Var, and second initialization voltage Vini to the pixel circuit from power supply 500.

[0106] In the accompanying drawings, the bias voltage bus VobsL, the first initialization voltage bus VarL, and the second initialization voltage bus ViniL are each shown located on the left or right side of the display area AA. However, embodiments of this disclosure are not limited to this arrangement, as the aforementioned buses can also be located on both sides. Furthermore, even if the aforementioned buses are located on one side, there is no limitation on whether they are located on the left or right side.

[0107] Reference Figure 3 One or more optical regions OA1 and OA2 can be set in the display area AA.

[0108] One or more optical regions OA1 and OA2 may be configured to overlap with one or more optoelectronic devices. Optoelectronic devices may include imaging devices such as cameras (image sensors), camera flashes, etc., and sensors such as proximity sensors, illuminance sensors, etc. One or more optical regions OA1 and OA2 may be omitted if necessary.

[0109] For the operation of optical electronic devices, one or more optical regions OA1 and OA2 may have a light-transmitting structure and a transmittance greater than a certain value. As an example, the number of pixels P per unit area in one or more optical regions OA1 and OA2 may be less than the number of pixels P per unit area in the general area of ​​the display area AA excluding optical regions OA1 and OA2. As an example, the resolution of one or more optical regions OA1 and OA2 may be lower than the resolution of the general area of ​​the display area AA.

[0110] The light-transmitting structure in one or more optical regions OA1 and OA2 can be formed by patterning the cathode in the portion where the pixel P is not arranged. Here, the patterned cathode can be removed, for example, by using a laser, or the cathode can be selectively formed and patterned by using a material or masking process such as a cathode deposition prevention layer.

[0111] Furthermore, light-transmitting structures in one or more optical regions OA1 and OA2 can be formed by separating the light-emitting element EL and the pixel circuit in pixel P. As an example, the light-emitting element EL of pixel P is located on optical regions OA1 and OA2, and multiple transistor TFTs constituting the pixel circuit are disposed outside (e.g., around) the optical regions OA1 and OA2, such that the light-emitting element EL and the pixel circuit can be electrically connected through a conductive layer such as a transparent metal layer.

[0112] Figure 4 This is a view showing pixel circuitry in a display device according to an exemplary embodiment of the present disclosure.

[0113] For descriptive purposes, Figure 4 The pixel circuit is shown only as an example, and any structure capable of controlling the emission of the light-emitting element EL by applying an emission control signal EM(n) can be used. For example, the pixel circuit may include an additional scan signal, a switching thin-film transistor connected to the scan signal, and a switching thin-film transistor to which an additional initialization voltage is applied. The connections between the switching elements or the connection locations of the capacitors can be formed in various ways. In the following description, for ease of description, a structure with... Figure 4 The display device shown has a pixel circuit structure.

[0114] Reference Figure 4 Each of the plurality of pixels P may include a pixel circuit having a driving transistor DT, and includes a light-emitting element EL connected to the pixel circuit.

[0115] The pixel circuit can drive the light-emitting element EL by controlling the drive current flowing through it. The pixel circuit may include a driving transistor DT, first transistors T1 through T7, and a capacitor Cst. Each of transistors DT and T1 through T7 may include a first electrode, a second electrode, and a gate. One of the first and second electrodes may be a source, and the other may be a drain.

[0116] Transistor DT and each of T1 through T7 can be a P-type thin-film transistor or an N-type thin-film transistor. Figure 3In this embodiment, the first transistor T1 and the seventh transistor T7 are N-type thin-film transistors, and the other transistors DT and T2 to T6 are P-type thin-film transistors. However, the transistors are not limited to this. According to this embodiment, transistors DT and all or some of the transistors T1 to T7 can be P-type thin-film transistors or N-type thin-film transistors. Furthermore, the N-type thin-film transistor can be an oxide thin-film transistor, and the P-type thin-film transistor can be a polycrystalline silicon thin-film transistor. However, the embodiment is not limited to this. As an example, either the N-type thin-film transistor or the P-type thin-film transistor can be an oxide thin-film transistor, a polycrystalline silicon thin-film transistor, or any other type of thin-film transistor.

[0117] An example is shown below, in which the first transistor T1 and the seventh transistor T7 are N-type thin-film transistors, while the other transistors DT and T2 through T6 are P-type thin-film transistors. Therefore, the first transistor T1 and the seventh transistor T7 are turned on by applying a high voltage, and the other transistors DT and T2 through T6 are turned on by applying a low voltage.

[0118] According to this embodiment, the first transistor T1 constituting the pixel circuit can be used as a compensation transistor, the second transistor T2 can be used as a data supply transistor, the third transistor T3 and the fourth transistor T4 can be used as light-emitting control transistors, the fifth transistor T5 can be used as a bias transistor, and the sixth transistor T6 and the seventh transistor T7 can be used as initialization transistors.

[0119] The light-emitting element EL may include an anode and a cathode. The anode of the light-emitting element EL may be connected to the fifth node N5, and the cathode may be connected to the low-potential drive voltage EVSS.

[0120] The driving transistor DT may include a first electrode connected to the second node N2, a second electrode connected to the third node N3, and a gate connected to the first node N1. The driving transistor DT may provide a driving current Id to the light-emitting element EL based on the voltage of the first node N1 (or the data voltage stored in the capacitor Cst, as described later).

[0121] The first transistor T1 includes a first electrode connected to a first node N1, a second electrode connected to a third node N3, and a gate for receiving a first scan signal SC1(n). The first transistor T1 is turned on in response to the first scan signal SC1(n), and allows a driving transistor DT to be connected in a diode manner between the first node N1 and the third node N3, thereby enabling sampling of the threshold voltage Vth of the driving transistor DT. The first transistor T1 may be a compensation transistor.

[0122] A capacitor Cst can be connected or formed between the first node N1 and the fourth node N4. The capacitor Cst can store or retain the supplied high-potential drive voltage EVDD.

[0123] The second transistor T2 may include a first electrode connected to the data line DL (or receiving the data voltage Vdata), a second electrode connected to the second node N2, and a gate for receiving the second scan signal SC2(n). The second transistor T2 is turned on in response to the second scan signal SC2(n) and transmits the data voltage Vdata to the second node N2. The second transistor T2 may be a data supply transistor.

[0124] The third transistor T3 and the fourth transistor T4 (or the first and second light-emitting control transistors) can be connected between the high-potential driving voltage EVDD and the light-emitting element EL, and can form the current movement path through which the driving current Id generated by the driving transistor DT moves.

[0125] The third transistor T3 includes a first electrode connected to the fourth node N4 and receiving a high-potential drive voltage EVDD, a second electrode connected to the second node N2, and a gate that receives a light-emitting control signal EM(n).

[0126] The fourth transistor T4 includes a first electrode connected to the third node N3, a second electrode connected to the fifth node N5 (or the anode of the light-emitting element EL), and a gate that receives the light-emitting control signal EM(n).

[0127] The third transistor T3 and the fourth transistor T4 are turned on in response to the light emission control signal EM(n). In this case, the drive current Id is supplied to the light-emitting element EL, and the light-emitting element EL can emit light with a brightness corresponding to the drive current Id.

[0128] The fifth transistor T5 includes a first electrode that receives the bias voltage Vobs, a second electrode connected to the second node N2, and a gate that receives the third scan signal SC3(n). The fifth transistor T5 can be a bias transistor.

[0129] The sixth transistor T6 may include a first electrode that receives a first initialization voltage Var, a second electrode connected to the fifth node N5, and a gate that receives a third scan signal SC3(n).

[0130] The sixth transistor T6 can be turned on in response to the third scan signal SC3(n) before (or after) the light-emitting element EL emits light, and the anode (or pixel electrode) of the light-emitting element EL can be initialized using a first initialization voltage Var. The light-emitting element EL may have a parasitic capacitor formed between the anode and cathode. Furthermore, while the light-emitting element EL emits light, the parasitic capacitor is charged, allowing the anode of the light-emitting element EL to have a specific voltage. Therefore, by applying the first initialization voltage Var to the anode of the light-emitting element EL through the sixth transistor T6, the accumulated charge in the light-emitting element EL can be initialized.

[0131] In this disclosure, the gates of the fifth transistor T5 and the sixth transistor T6 are configured to jointly receive the third scan signal SC3(n), but are not necessarily limited thereto. The gates of the fifth transistor T5 and the sixth transistor T6 can be configured to be independently controlled by receiving separate scan signals.

[0132] The seventh transistor T7 may include a first electrode that receives the second initialization voltage Vini, a second electrode connected to the first node N1, and a gate that receives the fourth scan signal SC4(n).

[0133] The seventh transistor T7 can be turned on in response to the fourth scan signal SC4(n), and the gate of the driving transistor DT can be initialized using the second initialization voltage Vini. Due to the high-potential driving voltage EVDD stored in the capacitor Cst, unwanted charge may remain on the gate of the driving transistor DT. Therefore, the remaining charge can be initialized by applying the second initialization voltage Vini to the gate of the driving transistor DT through the seventh transistor T7. Although in Figure 4 The diagram illustrates an 8T1C structure; however, embodiments of this disclosure are not limited to this. The structure of the sub-pixel SP can be selected from 3T1C, 4T1C, 5T1C, 6T1C, 3T2C, 4T2C, 5T2C, 6T2C, 7T2C, 8T2C, etc. Furthermore, it can include more or fewer transistors and capacitors.

[0134] Figures 5A to 5C It is used to describe in Figure 4 A view showing the operation of the scan signal and the light emission control signal during the refresh cycle and hold cycle in the pixel circuit.

[0135] The display device according to the exemplary embodiments of this disclosure can operate as a variable refresh rate (VRR) mode display device. While driving the display device at a constant frequency, the VRR mode can drive the display device by increasing the refresh rate at which the data voltage Vdata is updated when high-speed driving is required, or by reducing the refresh rate at times when power consumption must be reduced or low-speed driving is required.

[0136] Each pixel in a plurality of pixels P can be driven within one second by a combination of refresh frames and hold frames. In this disclosure, a set is defined as a combination of refresh cycles (where the data voltage Vdata is updated) and hold cycles (where the data voltage Vdata is not updated) that repeat within one second. Furthermore, a set cycle is a loop in which the combination of refresh cycles and hold cycles is repeated.

[0137] When the refresh rate is 120 Hz, the cycle used to drive a pixel can consist of only the refresh cycle. That is, the refresh cycle can be repeated 120 times per second. One refresh cycle is 1 / 120 = 8.33 ms, and one set cycle is also 8.33 ms.

[0138] When the refresh rate is 60 Hz, the period used to drive the pixels can be composed of alternating refresh and hold periods. That is, the refresh and hold periods can be alternated 60 times per second. One refresh period and one hold period are 0.5 / 60 = 8.33 ms each, and one set period is 16.66 ms.

[0139] When a pixel is driven at a refresh rate of 1 Hz, a frame can consist of one refresh cycle and 119 hold cycles following that refresh cycle. Furthermore, when a pixel is driven at a refresh rate of 1 Hz, a frame can consist of multiple refresh cycles and multiple hold cycles. Here, one refresh cycle and one hold cycle are each 1 / 120 = 8.33 ms, and one set cycle is 1 s. The implementation is not limited to this. As an example, pixels can also be driven at any refresh rate other than 1 Hz, below 60 Hz or 50 Hz.

[0140] During the refresh cycle, a new data voltage Vdata is charged and applied to the drive transistor DT. During the hold cycle, the data voltage Vdata from the previous frame is held and used. The hold cycle is also known as the skip cycle, in which the process of applying the new data voltage Vdata to the drive transistor DT is omitted.

[0141] Each of the multiple pixels P can initialize the voltage charged or retained in the pixel circuitry during the refresh cycle. Specifically, each of the multiple pixels P can eliminate the effects of the high-potential drive voltage EVDD and data voltage Vdata stored in the previous frame during the refresh cycle. Therefore, each of the multiple pixels P can display an image corresponding to the new data voltage Vdata during the hold period.

[0142] Each of the multiple pixels P can display an image by supplying a drive current corresponding to the data voltage Vdata to the light-emitting element EL during the hold period, and the light-emitting element EL can be kept in the on state.

[0143] First, the description will be in Figure 5A The refresh cycle refers to the driving of the pixel circuitry and the light-emitting elements. The refresh cycle may include at least one of the bias segments Tobs1 and Tobs2, the initialization cycle Ti, the sampling cycle Ts, and the emission cycle Te. However, this is merely an example and is not necessarily limited to this order.

[0144] Reference Figure 5A During the refresh cycle, the pixel circuit can operate in at least one of the bias segments Tobs1 and Tobs2.

[0145] In at least one of the bias sections Tobs1 and Tobs2, a conduction bias stress OBS operation with applied bias voltage Vobs is performed. Furthermore, the light emission control signal EM(n) is at a high voltage, and the third transistor T3 and the fourth transistor T4 are in cutoff operation. The first scan signal SC1(n) and the fourth scan signal SC4(n) are at a low voltage, and the first transistor T1 and the seventh transistor T7 are in cutoff operation. The second scan signal SC2 is at a high voltage, and the second transistor T2 is in cutoff operation.

[0146] A third scan signal SC3(n) with a low voltage is input, and the fifth transistor T5 and the sixth transistor T6 are turned on. As the fifth transistor T5 is turned on, a bias voltage Vobs is applied to the first electrode of the drive transistor DT connected to the second node N2.

[0147] Here, the bias voltage Vobs is supplied to the third node N3, which serves as the drain of the driving transistor DT, thereby reducing the voltage charging time or charging delay of the fifth node N5, which serves as the anode of the light-emitting element EL, during the light-emitting cycle. The driving transistor DT maintains strong saturation.

[0148] For example, as the bias voltage Vobs increases, the voltage at the third node N3, which serves as the drain of the driving transistor DT, can increase, and the gate-source voltage or drain-source voltage of the driving transistor DT can decrease. Therefore, it is preferable that the bias voltage Vobs is at least higher than the data voltage Vdata.

[0149] Here, the magnitude of the source-drain current Id through the driving transistor DT can be reduced, and the stress on the driving transistor DT can be reduced under positive bias stress conditions, thereby eliminating the charging delay of the voltage at the third node N3. In other words, by performing the on-bias stress OBS operation before sampling the threshold voltage Vth of the driving transistor DT, the hysteresis of the driving transistor DT can be reduced.

[0150] Therefore, the conduction bias stress OBS operation in at least one of the bias segments Tobs1 and Tobs2 can be defined as the operation of directly applying an appropriate bias voltage to the driving transistor DT during the non-light emission period.

[0151] Furthermore, as the sixth transistor T6 is turned on in at least one of the bias segments Tobs1 and Tobs2, the anode (or pixel electrode) of the light-emitting element EL connected to the fifth node N5 is initialized to the first initialization voltage Var.

[0152] However, the gates of the fifth transistor T5 and the sixth transistor T6 can receive separate scan signals and be controlled independently. That is, it is not required to apply bias voltages simultaneously to the first electrode of the driving transistor DT and the anode of the light-emitting element EL in the bias section.

[0153] Reference Figure 5A During the refresh cycle, the pixel circuit can operate within the initialization cycle Ti. The gate voltage of the driving transistor DT is initialized within the initialization cycle Ti.

[0154] The first scan signal SC1(n) through the fourth scan signal SC4(n) and the light emission control signal EM(n) are at high voltage, and the first transistor T1 and the seventh transistor T7 are turned on. The second transistor through the sixth transistors T2, T3, T4, T5 and T6 are turned off. With the first transistor T1 and the seventh transistor T7 turned on, the second electrode and gate of the driving transistor DT connected to the first node N1 are initialized to the second initialization voltage Vini.

[0155] Reference Figure 5A During the refresh cycle, the pixel circuit can operate within the sampling period Ts. The threshold voltage Vth of the driving transistor DT is sampled within the sampling period.

[0156] The first scan signal SC1(n), the third scan signal SC3(n), and the light emission control signal EM(n) are at high voltage, while the second scan signal SC2(n) and the fourth scan signal SC4(n) are at low voltage. Therefore, transistors T3, T4, T5, T6, and T7 are off, the first transistor T1 remains on, and the second transistor T2 is on. That is, with the second transistor T2 on, the data voltage Vdata is applied to the driving transistor DT, and the first transistor T1 connects the driving transistor DT between the first node N1 and the third node N3 in a diode configuration, allowing the threshold voltage Vth of the driving transistor DT to be sampled.

[0157] Reference Figure 5A During the refresh cycle, the pixel circuit can operate within the emission cycle Te. Within the emission cycle Te, the sampled threshold voltage Vth shifts, and the light-emitting element EL emits light with a drive current corresponding to the sampled data voltage.

[0158] The light emission control signal EM(n) is at a low voltage, and the third transistor T3 and the fourth transistor T4 are turned on.

[0159] With the third transistor T3 turned on, the high-potential drive voltage EVDD connected to the fourth node N4 is applied through the third transistor T3 to the first electrode of the drive transistor DT connected to the second node N2. The drive current Id supplied from the drive transistor DT to the light-emitting element EL via the fourth transistor T4 becomes independent of the threshold voltage Vth of the drive transistor DT, thereby compensating for the threshold voltage Vth of the drive transistor DT and driving the transistor to operate.

[0160] Next, refer to Figure 5B This will describe the driving of the pixel circuitry and light-emitting elements during the holding period.

[0161] The holding period may include at least one of the bias segments Tobs3 and Tobs4 and the emission period Te'. Descriptions of the pixel circuitry operations identical to those of the refresh period will be omitted.

[0162] As described above, during the refresh cycle, a new data voltage Vdata is charged and applied to the gate of the driving transistor DT. However, the hold cycle differs from the refresh cycle in that it holds and utilizes the data voltage Vdata from the refresh cycle. Therefore, unlike the refresh cycle, the hold cycle does not require an initialization cycle Ti and a sampling period Ts.

[0163] During the hold period, performing only one On-Bias Stress OBS operation is sufficient. However, in this embodiment, for the convenience of the drive circuit, the third scan signal SC3(n) during the hold period is driven in the same manner as the third scan signal SC3(n) during the refresh period. This results in the ability to perform two On-Bias Stress OBS operations, just as during the refresh period.

[0164] Reference Figure 5A The drive signals described during the refresh cycle and Figure 5B The difference between the drive signals during the hold period is generated by the second scan signal SC2(n) and the fourth scan signal SC4(n). The hold period does not require an initialization period Ti and a sampling period Ts. Therefore, unlike the refresh period, the second scan signal SC2(n) is always at a high voltage, and the fourth scan signal SC4(n) is always at a low voltage. That is, the second transistor T2 and the seventh transistor T7 are always off.

[0165] Figure 5C It shows in Figure 5B The driving of light-emitting devices and pixel circuits that do not perform conduction bias stress OBS operation during the holding period.

[0166] Reference Figure 5C During the hold period, the pixel circuit can operate only within the light emission period Te''. In other words, in the pixel circuit, the on-bias stress OBS operation is not performed during the hold period; the second scan signal SC2(n) and the third scan signal SC3(n) are always at a high voltage, and the fourth scan signal SC4(n) is always at a low voltage. That is, the second transistor T2, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 are always off.

[0167] Reference Figures 7 to 10 This document describes in detail an implementation method in which the conduction bias stress OBS operation is not performed during the holding period.

[0168] Figure 6 This is a view used to describe a multi-refresh drive when a low-frequency drive is executed in VRR mode according to an embodiment of the present disclosure. Although the refresh rate in the low-frequency drive is shown as 1Hz, other frequencies such as 2Hz, 5Hz, 10Hz, or 20Hz, which are below 50Hz or 60Hz, are also possible.

[0169] Reference Figure 6 The refresh cycle with the same image data is repeated within a frame, which reduces the time required for the display brightness to reach the target level during low-frequency driving and reduces or minimizes anomalies such as flicker.

[0170] Because the cycle time of the pixel circuit increases when driven at low refresh rates such as 1 Hz, some transistors are implemented using oxide transistors with good cutoff current characteristics to reduce or minimize leakage current. Oxide transistors effectively reduce leakage current due to low cutoff current, but have a relatively slow response speed due to their lower electron mobility compared to polysilicon transistors.

[0171] That is, such as Figure 6 As shown in (a), when a frame consists of one refresh cycle and 119 hold cycles, there may be a delay in the display brightness reaching the target level when the grayscale of the image changes or the scene changes.

[0172] Therefore, after the grayscale of the image is changed, such as Figure 6 As shown in (b), multiple refresh cycles are included in the first frame, which shortens the time required for the display brightness to reach the target level. For example, after a grayscale change in the image, the first frame may include five refresh cycles and 115 hold cycles with the same image data. However, the number of refresh cycles and hold cycles in a frame is not limited to this. Thus, having multiple refresh cycles during low-frequency driving can be referred to as multi-refresh driving.

[0173] Figures 7 to 10 This is a view used to describe a brightness deviation compensation driving method in a display device according to an embodiment of the present disclosure.

[0174] During low-frequency driving at a refresh rate of 1 Hz, the bias voltage Vobs, applied during the hold period to compensate for the threshold voltage Vth of the drive transistor DT, accumulates as the stress voltage of the drive transistor DT. As the number of times the bias voltage Vobs is applied to the drive transistor DT increases, the charge on the drive transistor DT increases and the drive transistor saturates. That is, in a frame, by initializing the drive transistor DT by including an initialization period Ti only in one refresh cycle, the conduction bias stress accumulates over the remaining 119 hold periods.

[0175] Since the accumulation of on-bias stress is caused by the bias voltage Vobs during the hold period, it also occurs in multi-refresh drives with multiple refresh cycles. Therefore, the accumulation of on-bias stress alters the characteristics of the drive transistor DT, thereby reducing the amplitude of the drive current Id and decreasing brightness.

[0176] Furthermore, during scene changes, the threshold voltage Vth driving the transistor DT can temporarily change and then return to its original state. As an example, the threshold voltage Vth changes in the first frame after a scene change (such as a change in the grayscale of an image), so the brightness of the light-emitting element EL may decrease. This is perceived by the user as flickering at the point in time when the image's grayscale changes.

[0177] As described above, during low-frequency driving with a refresh rate of 1 Hz, in order to mitigate the brightness reduction caused by changes in the characteristics of the driving transistor DT due to changes in the threshold voltage Vth of the driving transistor and the accumulation of the bias voltage Vobs used to compensate for the threshold voltage Vth, the on-bias stress OBS operation may not be performed during the hold period of the first frame after the image grayscale change. Figures 7 to 10 In the various embodiments shown, the conduction bias stress (OBS) operation may not be performed.

[0178] Reference Figure 7 The display device can be driven by changing the bias voltage Vobs in stages during the hold period of multiple frames after a scene change, and simultaneously by changing the refresh rate.

[0179] As an example, after a grayscale change in an image in a display device 10 driven at a first refresh rate, the power supply 500 can apply a bias voltage Vobs below a specific level during the hold period of the first frame. Then, it can be operated such that the bias voltage Vobs during the hold period changes in stages to increase to the level of the bias voltage Vobs during the refresh period. Furthermore, while the bias voltage Vobs changes in stages to increase, the display device 10 can operate as the refresh rate changes to a second refresh rate.

[0180] Here, the bias voltage Vobs applied during the refresh cycle can be at a first level, and the bias voltage Vobs applied during the hold period of the first frame after the image grayscale change can be at a second level lower than the first level. Furthermore, the second refresh rate can be higher than the first refresh rate.

[0181] Reference Figure 7 In a low-frequency drive with a first refresh rate, when a set S is defined in units of frames, the first frame after a grayscale change of the image can be the first set S(1), the second frame can be the second set S(2), and the nth frame can be the nth set S(n). Furthermore, the first set S(1) can include multiple subsets SS(1) to SS(n) with a second refresh rate. Each subset SS(1) to SS(n) can include at least one refresh cycle and multiple hold cycles.

[0182] Furthermore, during the hold periods of the multiple subsets SS(1) to SS(n), a bias voltage Vobs is applied that increases in stages from a second level to a first level. The bias voltage Vobs can have the same voltage level during the multiple hold periods of each subset SS.

[0183] For example, the first refresh rate can be 1 Hz, and the second refresh rate can be 10 Hz. Since the display device is driven at 10 Hz in multiple subsets SS (1) to SS (n) included in the first set S (1), the display device can operate at a refresh rate of 10 Hz in six subsets SS (1) to SS (6) during the first set S (1) of 1 Hz. Different voltage levels of bias voltage Vobs can be applied to each of the six subsets SS (1) to SS (6). As an example, the different voltage levels of bias voltage Vobs applied to each of the six subsets SS (1) to SS (6) can be increased sequentially.

[0184] In other words, such as Figure 7 As shown, after the grayscale of the image is changed, the first set S(1) with the first refresh rate includes multiple subsets SS(1) to SS(n) with the second refresh rate, which reduces the accumulation of conduction bias stress and the change of threshold voltage Vth of the driving transistor DT, thereby reducing flicker.

[0185] Reference Figure 8 The display device can operate at a different refresh rate in each of the multiple subsets SS(1) to SS(n).

[0186] As an example, in the first set S(1) after a grayscale change of an image in the display device 10 driven by a first refresh rate, the bias voltage Vobs can be increased from a second level to a first level in stages during the holding period of multiple subsets SS(1) to SS(n), and the display device can operate at a different refresh rate in each of the multiple subsets SS(1) to SS(n). As an example, the different refresh rates in each of the multiple subsets SS(1) to SS(n) can be decreased sequentially.

[0187] For example, the display device may be driven at a first refresh rate of 1 Hz in the first set S(1), at a refresh rate of 10 Hz in the first subset SS(1), at a refresh rate of 7 Hz in the second subset SS(2), and at a refresh rate of 3 Hz in the nth subset SS(n).

[0188] In other words, such as Figure 8As shown, after the grayscale of the image is changed, the first set S(1) with the first refresh rate includes multiple subsets SS(1) to SS(n) with variable refresh rates, which reduces the accumulation of conduction bias stress and the change of threshold voltage Vth of the driving transistor DT, thereby reducing flicker.

[0189] In addition, such as Figure 7 and Figure 8 As shown, multiple subsets of SS in which the bias voltage Vobs level changes can be selectively altered until the next frame appears or a grayscale change occurs in the next image. Furthermore, within each refresh cycle of the multiple subsets of SS, the bias voltage Vobs can be kept constant at a first level without change.

[0190] Reference Figure 9 The display device can be driven by changing the bias voltage Vobs in stages during the hold period of multiple frames after a scene change, and optionally by changing the refresh rate at the same time.

[0191] Here, the plurality of sets S(1) to S(m) driving the display device at a first refresh rate may include a plurality of subsets SS1(1) to SS1(n), SS2(1) to SS2(n) and SSm(1) to SSm(n) driving the display device at a second refresh rate, respectively. Each subset of the plurality of subsets SS1(1) to SS1(n), SS2(1) to SS2(n) and SSm(1) to SSm(n) may include at least one refresh cycle and a plurality of hold cycles.

[0192] Furthermore, during the holding period of the multiple sets S(1) to S(m), a bias voltage Vobs is applied that increases in stages from the second level to the first level. In each of the multiple subsets SS1(1) to SS1(n), SS2(1) to SS2(n), or SSm(1) to SSm(n) included in the multiple sets S(1) to S(m), the bias voltage Vobs applied during the holding period may have the same voltage level.

[0193] For example, the first refresh rate can be 1 Hz, and the second refresh rate can be 10 Hz. Since the display device is driven at 10 Hz in multiple subsets SS1(1) to SS1(n), SS2(1) to SS2(n) and SSm(1) to SSm(n) respectively included in multiple sets S(1) to S(m), the display device can operate at a refresh rate of 10 Hz in six subsets SSm(1) to SSm(6) during a set S of 1 Hz. Different voltage levels of bias voltage Vobs can be applied to each of the multiple sets S(1) to S(m). Alternatively, different voltage levels of bias voltage Vobs are applied to each of the multiple subsets SS1(1) to SS1(n), each of the multiple subsets SS2(1) to SS2(n), or each of the multiple subsets SSm(1) to SSm(n).

[0194] Furthermore, the display device can be operated such that bias voltages Vobs of different voltage levels are applied to multiple subsets SS1(1) to SS1(6) of the first set S(1) to multiple subsets SSm(1) to SSm(n) of the m-th set S(m), and the bias voltage Vobs is changed to increase from the second level to the first level in stages.

[0195] In other words, such as Figure 9 As shown, after the grayscale of the image is changed, multiple sets S(1) to S(m) with a first refresh rate include multiple subsets SS1(1) to SS1(n), ..., SSm(1) to SSm(n) with a second refresh rate. The driving power supply 500 causes the bias voltage Vobs to change across the multiple sets S(1) to S(m). This reduces the accumulation of conduction bias stress and the change in the threshold voltage Vth of the driving transistor DT, thereby reducing flicker.

[0196] Reference Figure 10 The display device can operate at a different refresh rate in each of the multiple sets S(1) to S(m).

[0197] As an example, after the grayscale of the image is changed, the multiple sets S(1) to S(m) in which the display device operates at a first refresh rate may respectively include multiple subsets SS1(1) to SS1(n), SS2(1) to SS2(n) and SSm(1) to SSm(n) with different refresh rates.

[0198] For example, when the display device is driven at a first refresh rate of 1 Hz in each of the multiple sets S(1) to S(m), the display device can operate at a first refresh rate of 10 Hz in the multiple subsets SS1(1) to SS1(n) of the first set S(1), at a first refresh rate of 7 Hz in the multiple subsets SS2(1) to SS2(n) of the second set S(2), and at a first refresh rate of 3 Hz in the multiple subsets SSm(1) to SSm(n) of the m-th set S(m).

[0199] In other words, such as Figure 10 As shown, after the grayscale of the image is changed, multiple sets S(1) to S(m) with a first refresh rate include multiple subsets SS1(1) to SS1(n), SS2(1) to SS2(n), and SSm(1) to SSm(n) with different refresh rates. The driving power supply 500 causes the bias voltage Vobs to change across the multiple sets S(1) to S(m). As a result, the accumulation of conduction bias stress and the change in the threshold voltage Vth of the driving transistor DT are reduced, thereby reducing flicker.

[0200] In addition, such as Figure 9 and Figure 10 As shown, multiple sets S in which the level of the bias voltage Vobs can be selectively changed until a subsequent frame appears or a grayscale change occurs in the next image. Furthermore, within each refresh cycle of the multiple sets S and subsets SS, the bias voltage Vobs can be kept constant at a first level without change.

[0201] In addition, refer to Figures 7 to 10 When the bias voltage Vobs during the hold period is set to be approximately 2 V lower than the bias voltage Vobs during the refresh period, the same effect as when the on-bias stress OBS operation is turned off can be achieved. For example, if the bias voltage Vobs for the first level during the refresh period is 7 V, then the bias voltage Vobs for the second to fourth levels during the hold period can be approximately 5 V, and the bias voltage can be varied to increase in stages between 5 V and 7 V until the next frame appears or a grayscale change occurs for the next image. However, the implementation is not limited to this. As an example, the bias voltage Vobs during the hold period can be any voltage less than or more than 2 V lower than the bias voltage Vobs during the refresh period. Furthermore, the refresh rates described above or shown in the figures are illustrative, and refresh rates other than 1 Hz, 10 Hz, 7 Hz, and 3 Hz can be used, as long as the refresh rate is below 60 Hz.

[0202] Figure 11 This is a view illustrating the effect of applying a brightness deviation compensation drive according to an exemplary embodiment of the present disclosure.

[0203] Figure 11 (a) shows the total change in brightness ΔL at time point t1 when the grayscale of the image changes. Figure 11 (b) illustrates the application of a luminance deviation compensation drive according to an embodiment of this disclosure. From Figure 11 As can be seen from the data, when the brightness deviation compensation drive is executed, even if the grayscale of the image changes, the brightness change ΔL is not large, which can reduce flicker caused by brightness deviation.

[0204] The display device according to embodiments of the present disclosure can be described as follows.

[0205] A display device according to an embodiment of the present disclosure includes: a display panel including a display area having a plurality of pixels and a non-display area surrounding the display area; a gate driver providing a scan signal and a light emission control signal to the display panel; and a controller driving the display panel according to a refresh rate. The plurality of pixels includes light-emitting elements and pixel circuitry for driving the light-emitting elements. In low-frequency driving, the pixel circuitry is driven in a set including at least one refresh cycle and at least one hold cycle. When the grayscale of the image changes, the controller dynamically controls the refresh rate during at least one set of cycles, while simultaneously changing and supplying a bias voltage during at least one hold cycle.

[0206] In a controller during at least one set of events, the display panel is driven at a first refresh rate in low-frequency driving and at a second refresh rate when the grayscale of the image changes.

[0207] The second refresh rate can be higher than the first refresh rate.

[0208] A set can include multiple subsets.

[0209] The display device can be driven at a first refresh rate in the set, and at a second refresh rate in multiple subsets.

[0210] The sum of the second refresh rates can be the first refresh rate.

[0211] The bias voltage can have different voltage levels during multiple subsets.

[0212] Different refresh rates can be provided during multiple subsets.

[0213] The bias voltage can have the same voltage level during multiple subsets.

[0214] The first frame after an image's grayscale change can include multiple refresh cycles.

[0215] The pixel circuit may further include: a driving transistor having a first electrode configured to receive a data voltage and a bias voltage, and a second electrode connected to a light-emitting element; a switching transistor connected between the driving transistor and a data line, and applying a data voltage to the driving transistor in response to a first scan signal; and a bias transistor applying a bias voltage to the driving transistor in response to a second scan signal.

[0216] The gate driver may include a first scan driver to a fourth scan driver that applies a first scan signal to a fourth scan signal to the pixel circuit, and a light emission control signal driver that applies a light emission control signal. The second scan driver may include a second odd-numbered scan driver and a second even-numbered scan driver.

[0217] The display panel may include: a bias voltage bus that applies a bias voltage to the pixel circuitry; and an initialization voltage bus that applies an initialization voltage to the pixel circuitry. The bias voltage bus and the initialization voltage bus may be located between the gate driver and the display area.

[0218] The display area may include one or more optical areas having light-transmitting structures formed therein, as well as a general area other than one or more optical areas.

[0219] One or more optical regions may overlap with optical electronic devices.

[0220] The resolution of one or more optical zones can be lower than that of a general zone.

[0221] A display device according to an embodiment of the present disclosure may include: a display panel including a plurality of pixels; and a controller that controls the driving of the display panel according to a refresh rate. The display panel can be driven in a set including at least one refresh cycle and at least one hold cycle during low-frequency driving. In a first set following a grayscale change in an image, the controller can drive the display panel, thereby including a plurality of refresh cycles.

[0222] The above description and accompanying drawings are merely illustrative of the spirit of this disclosure. Those skilled in the art to which this disclosure pertains may make various modifications and alterations (e.g., combinations, separations, substitutions, changes, etc.) without departing from the essential characteristics of this disclosure. Therefore, the embodiments disclosed herein are for description and not for limiting the spirit of this disclosure, and the scope of the spirit of this disclosure is not limited by these embodiments. The scope of protection of this disclosure should be interpreted through the following claims, and all technical spirit within the scope of its equivalents should be interpreted as included within the scope of this disclosure.

[0223] Beneficial effects

[0224] The display device according to the embodiments of the present disclosure reduces the deviation of the bias stress of the driving transistor at the time point of screen switching of the image (such as grayscale change) by using the first to fourth methods of brightness deviation compensation driving, thereby reducing the occurrence of brightness differences and reducing flicker.

[0225] It will be apparent to those skilled in the art that various modifications and alterations can be made to the display device of this disclosure without departing from the technical spirit or scope thereof. Therefore, this disclosure is intended to cover any modifications and alterations to this disclosure that fall within the scope of the appended claims and their equivalents.

[0226] Cross-references to related applications

[0227] This application claims priority to Korean Patent Application No. 10-2022-0093956, filed on July 28, 2022, the entire contents of which are incorporated herein by reference for various purposes.

Claims

1. A display device, the display device comprising: The display panel includes a display area with a plurality of pixels; as well as The controller drives the display panel according to the refresh rate. The plurality of pixels includes a light-emitting element and a pixel circuit for driving the light-emitting element. The pixel circuit is driven in a set including at least one refresh cycle and at least one hold cycle, and Wherein, when the grayscale of the image changes, the controller changes the bias voltage during at least one hold period in at least one set. Wherein, the at least one set includes multiple subsets, and the multiple subsets include a first subset and a second subset. Each of the plurality of subsets includes at least one refresh cycle and at least one hold cycle. The bias voltage is at a first voltage level during the first hold period of the first subset. Wherein, the bias voltage is at a second voltage level during the second hold period of the second subset, and The second voltage level is different from the first voltage level.

2. The display device according to claim 1, wherein, The controller dynamically controls the refresh rate simultaneously during the at least one set.

3. The display device according to claim 2, wherein, The display panel is driven at a first refresh rate before the at least one set, and at a second refresh rate during the at least one set when the grayscale of the image changes.

4. The display device according to claim 3, wherein, The first refresh rate is less than 50 Hz.

5. The display device according to claim 3, wherein, The second refresh rate is higher than the first refresh rate but lower than 50 Hz.

6. The display device according to claim 1, wherein, The display panel is driven at a first refresh rate in the at least one set and at one or more second refresh rates in the plurality of subsets.

7. The display device according to claim 6, wherein, The combination of one or more second refresh rates of the plurality of subsets is the first refresh rate.

8. The display device according to claim 1, wherein, The bias voltage has different voltage levels during the hold period of the plurality of subsets.

9. The display device according to claim 8, wherein, The different voltage levels of the bias voltage during the hold period of the plurality of subsets are increased in stages to the voltage level of the bias voltage during the refresh period of the plurality of subsets.

10. The display device according to claim 8, wherein, The bias voltage has the same voltage level during the refresh cycle of the plurality of subsets.

11. The display device according to claim 8, wherein, The display panels are driven at different refresh rates in the multiple subsets.

12. The display device according to claim 11, wherein, The different refresh rates decrease sequentially across the subsets.

13. The display device according to claim 1, wherein, The bias voltage has the same voltage level during the plurality of subsets.

14. The display device according to claim 13, wherein, The display panels are driven at different refresh rates in the multiple subsets.

15. The display device according to claim 1, wherein, The first frame after the grayscale change of the image includes multiple refresh cycles.

16. The display device according to claim 1, wherein, The pixel circuit includes: A driving transistor, wherein a first electrode of the driving transistor is configured to receive a data voltage and the bias voltage, and a second electrode of the driving transistor is connected to the light-emitting element; A switching transistor, connected between the driving transistor and the data line, and applying the data voltage to the driving transistor in response to a first scan signal; and A bias transistor that applies the bias voltage to the drive transistor in response to a second scan signal.

17. The display device of claim 1, further comprising a gate driver for providing a scan signal to the display panel. in, The gate driver includes a first scan driver, a second scan driver, a third scan driver, and a fourth scan driver that apply first to fourth scan signals to the pixel circuit, and a light emission control signal driver that applies light emission control signals. The second scan driver includes a second odd-numbered scan driver and a second even-numbered scan driver.

18. The display device according to claim 1, further comprising a gate driver for providing scan signals and light emission control signals to the display panel. in, The display panel also includes: A bias voltage bus that applies the bias voltage to the pixel circuit; and An initialization voltage bus is used to apply an initialization voltage to the pixel circuit, and The bias voltage bus and the initialization voltage bus are disposed between the gate driver and the display area.

19. The display device according to claim 1, wherein, The display area includes one or more optical areas in which a light-transmitting structure is formed, and a general area other than the one or more optical areas.

20. The display device according to claim 19, wherein, The one or more optical regions overlap with optical electronic devices.

21. The display device according to claim 19, wherein, The resolution of one or more optical regions is lower than the resolution of the general region.

22. The display device according to claim 1, wherein, The bias voltage is increased in stages during multiple sets of hold periods immediately following a grayscale change in the image.

23. The display device according to claim 22, wherein, In each of the plurality of sets, the bias voltage has the same voltage level in each of the plurality of subsets.

24. The display device according to claim 22, wherein, The refresh rates in the plurality of sets decrease sequentially.

25. The display device according to claim 1, wherein, The pixel circuit includes a driving transistor, a first electrode of which is configured to receive a data voltage and a bias voltage, and a second electrode of which is connected to the light-emitting element. Specifically, the bias voltage is applied to the first electrode of the driving transistor before the sampling period in which the threshold voltage of the driving transistor is sampled during the refresh period, and the bias voltage is applied to the first electrode of the driving transistor before the light emission period in the at least one hold period.

26. The display device according to claim 25, wherein, The bias voltage is higher than the data voltage.

27. The display device according to claim 1, wherein, During the at least one set, the bias voltage of the at least one hold cycle is set to be 2V lower than the bias voltage of the at least one refresh cycle.

28. A display device, the display device comprising: The display panel includes a plurality of pixels; as well as The controller controls the driving of the display panel according to the refresh rate. The display panel is driven in a set including at least one refresh cycle and at least one hold cycle, and Wherein, after the grayscale of the image is changed, at least one set in the set includes multiple subsets, the multiple subsets including a first subset and a second subset. The display device is driven at a first subset refresh rate in the first subset. Wherein, the display device is driven at a second subset refresh rate in the second subset, and The refresh rate of the second subset differs from that of the first subset. Each of the plurality of subsets includes at least one refresh cycle and at least one hold cycle.

29. The display device according to claim 28, in, In the first set following the grayscale change of the image, the controller drives the display panel, including multiple refresh cycles, and The controller dynamically controls the refresh rate during at least one set of the first set after the grayscale of the image has changed, and simultaneously changes and supplies a bias voltage during at least one hold period in the at least one set.

30. The display device according to claim 29, in, The display device is driven at a first refresh rate in the at least one set, and at one or more second refresh rates higher than the first refresh rate in the plurality of subsets. Wherein, the combination of one or more second refresh rates is the first refresh rate.

Images