Pixel driving circuit and display panel

Abstract

The application discloses a pixel driving circuit and a display panel. The pixel driving circuit comprises a first light-emitting control module, a driving transistor, a second light-emitting control module, a data writing module and a first initialization module. The driving timing of the pixel driving circuit comprises a writing frame and a holding frame. The writing frame comprises a first reset stage and a data writing stage in sequence. In the first reset stage, the first light-emitting control module is used for writing the first power signal into the first electrode and the second electrode of the driving transistor, or the first initialization module and the second light-emitting control module are used for writing the first initialization signal into the first electrode and the second electrode of the driving transistor. The application can reduce the characteristic reset effect difference of the driving transistor in the writing frame and the holding frame, and improve the flicker caused by the brightness difference between the writing frame and the holding frame.

Description

Technical Field

[0001] This application relates to the field of display technology, specifically to a pixel driving circuit and a display panel. Background Technology

[0002] With the continuous development of AMOLED (Active-Matrix Organic Light-Emitting Diode) products in the consumer market, people have increasingly higher requirements for the optical performance of mobile phone products. Flicker, as an important indicator for evaluating the optical performance of mobile phones, is also facing increasingly stringent specifications. At the same time, the introduction of low-frequency displays has also led to flicker becoming increasingly severe.

[0003] In low-frequency displays, a single frame typically includes a write frame and a hold frame, with the hold frame comprising at least one subframe. Because the characteristics of the driving transistors differ between the first subframe of the write frame and the first subframe of the hold frame, a brightness difference exists between the write frame and the first subframe of the hold frame, resulting in screen flickering. Summary of the Invention

[0004] This application provides a pixel driving circuit and a display panel to solve the technical problem in the prior art where the brightness difference between the first sub-frame of the written frame and the held frame causes screen flickering.

[0005] In a first aspect, this application provides a pixel driving circuit, comprising:

[0006] Drive transistors;

[0007] The first light-emitting control module has a control terminal connected to a first enable signal, an input terminal connected to a first power signal, and an output terminal electrically connected to the first electrode of the driving transistor.

[0008] The second light-emitting control module has a control terminal connected to a second enable signal, and its output terminal is electrically connected to the second electrode of the driving transistor.

[0009] A data writing module, wherein a first control terminal of the data writing module is connected to a first control signal, a second control terminal of the data writing module is connected to a second control signal, an input terminal of the data writing module is connected to a data signal, and the data writing module is also electrically connected to the gate, first electrode, and second electrode of the driving transistor; and

[0010] The first initialization module has a control terminal connected to a third control signal, an input terminal connected to a first initialization signal, and an output terminal electrically connected to the input terminal of the second light-emitting control module.

[0011] The driving timing of the pixel driving circuit includes a write frame and a hold frame. The write frame includes a first reset phase and a data write phase performed sequentially. In the first reset phase, the first light emission control module is used to write the first power signal to the first and second terminals of the driving transistor, or the first initialization module and the second light emission control module are used to write the first initialization signal to the first and second terminals of the driving transistor.

[0012] Optionally, in some embodiments of this application, the holding frame includes at least one subframe. If the brightness of the written frame is less than the brightness of the first subframe of the holding frame, then in the first reset phase, the first light emission control module responds to the first enable signal and writes the first power signal to the first and second terminals of the driving transistor.

[0013] Optionally, in some embodiments of this application, the first control signal and the third control signal are the same signal.

[0014] Optionally, in some embodiments of this application, the pixel driving circuit further includes a second initialization module, wherein the control terminal of the second initialization module is connected to a fourth control signal, the input terminal of the second initialization module is connected to a second initialization signal, and the output terminal of the second initialization module is electrically connected to the gate of the driving transistor;

[0015] During the first reset phase, the second initialization module responds to the fourth control signal by writing the second initialization signal to the gate of the driving transistor.

[0016] Optionally, in some embodiments of this application, the holding frame includes at least one subframe. If the brightness of the written frame is greater than the brightness of the first subframe of the holding frame, then in the first reset phase, the first initialization module responds to the third control signal and writes the first initialization signal to the fourth node; the second light emission control module responds to the second enable signal and writes the first initialization signal to the first and second terminals of the driving transistor.

[0017] Optionally, in some embodiments of this application, the pixel driving circuit further includes a second initialization module, wherein the control terminal of the second initialization module is connected to a fourth control signal, the input terminal of the second initialization module is connected to a second initialization signal, and the output terminal of the second initialization module is electrically connected to the gate of the driving transistor;

[0018] The write frame further includes a second reset phase, which is located between the first reset phase and the data write phase;

[0019] During the second reset phase, the second initialization module responds to the fourth control signal by writing the second initialization signal to the gate of the driving transistor.

[0020] Optionally, in some embodiments of this application, the first control signal and the third control signal are different signals.

[0021] Optionally, in some embodiments of this application, the driving timing of the pixel driving circuit further includes a third reset stage and a light emission stage after the data writing stage;

[0022] During the data writing phase, the data writing module transmits the compensated data signal to the gate of the driving transistor in response to the first control signal and the second control signal.

[0023] In the third reset phase, the first light-emitting control module responds to the first enable signal and writes the first power signal to the first and second terminals of the driving transistor.

[0024] During the light-emitting phase, the first light-emitting control module responds to the first enable signal and the second light-emitting control module responds to the second enable signal to control the light-emitting device to emit light.

[0025] Optionally, in some embodiments of this application, during the holding frame, the data writing module is further configured to write the data signal to the first and second poles of the driving transistor at least once.

[0026] Secondly, this application also provides a display panel, the display panel including a plurality of pixel units arranged in an array, each of the pixel units including a pixel driving circuit as described in any of the preceding claims.

[0027] This application provides a pixel driving circuit and a display panel. The pixel driving circuit includes a first light-emitting control module, a driving transistor, a second light-emitting control module, a data writing module, and a first initialization module. Before the data writing stage, this application resets the potentials of the first and second terminals of the driving transistor by either writing a first power signal to the first and second terminals of the driving transistor through the first light-emitting control module, or writing a first initialization signal to the first and second terminals of the driving transistor through the first and second initialization modules. This changes the gate-source voltage of the driving transistor, adjusts the reset effect of the driving transistor in the write frame, reduces the difference in the characteristic reset effect of the driving transistor between the write frame and the hold frame, thereby reducing the brightness difference between the write frame and the hold frame and improving screen flicker. Attached Figure Description

[0028] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0029] Figure 1 This is a schematic diagram of the first circuit structure of the pixel driving circuit provided in this application;

[0030] Figure 2 yes Figure 1 The signal timing diagram of the pixel driving circuit for writing frames is shown.

[0031] Figure 3 This is a schematic diagram of the second circuit structure of the pixel driving circuit provided in this application;

[0032] Figure 4 yes Figure 3 The signal timing diagram of the pixel driving circuit for writing frames is shown.

[0033] Figure 5 yes Figure 1 The signal timing diagram of the write frame and hold frame of the pixel driving circuit is shown.

[0034] Figure 6 This is a schematic diagram of a display panel provided in this application. Detailed Implementation

[0035] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0036] In the description of this application, it should be understood that the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Therefore, features defined with "first" and "second," etc., may explicitly or implicitly include one or more of the stated features, and thus should not be construed as limiting this application. Furthermore, it should be noted that unless otherwise explicitly specified and limited, the terms "connected" and "linked" should be interpreted broadly, for example, they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal connection of two elements. Those skilled in the art can understand the specific meaning of the above terms in this invention based on the specific circumstances.

[0037] This application provides a pixel driving circuit and a display panel, which will be described in detail below. It should be noted that the order of description of the following embodiments is not intended to limit the preferred order of the embodiments of this application.

[0038] Please see Figures 1-3 , Figure 1 This is a schematic diagram of the first circuit structure of the pixel driving circuit provided in this application. Figure 2 yes Figure 1 The signal timing diagram of the pixel driving circuit for writing frames is shown below. Figure 3 This is a schematic diagram of the second circuit structure of the pixel driving circuit provided in this application. In the embodiments of this application, the pixel driving circuit 100 includes a first light emission control module 101, a driving transistor TD, a second light emission control module 102, a data writing module 103, and a first initialization module 105.

[0039] The control terminal of the first light-emitting control module 101 is connected to the first enable signal EM_L. The input terminal of the first light-emitting control module 101 is connected to the first power signal ELVDD. The output terminal of the first light-emitting control module 101 is electrically connected to the first node A.

[0040] The first light-emitting control module 101 includes, but is not limited to, a first transistor T1. The gate of the first transistor T1 is connected to a first enable signal EM_L. One of the source and drain of the first transistor T1 is connected to a first power supply signal ELVDD. The other of the source and drain of the first transistor T1 is electrically connected to a first node A.

[0041] The first terminal of the driving transistor TD is electrically connected to the first node A. The second terminal of the driving transistor TD is electrically connected to the second node B. The gate of the driving transistor TD is electrically connected to the third node Q.

[0042] The first electrode is either the source or the drain of the driving transistor TD, and the second electrode is either the source or the drain of the driving transistor TD.

[0043] The control terminal of the second light-emitting control module 102 is connected to the second enable signal EM_R. The input terminal of the second light-emitting control module 102 is electrically connected to the second node B. The output terminal of the second light-emitting control module 102 is electrically connected to the fourth node C, that is, electrically connected to the output terminal of the first initialization module 105.

[0044] The second light-emitting control module 102 includes, but is not limited to, a second transistor T2. The gate of the second transistor T2 is connected to a second enable signal EM_R. One of the source and drain of the second transistor T2 is electrically connected to the second node B. The other of the source and drain of the second transistor T2 is electrically connected to the fourth node C.

[0045] The first control terminal of the data writing module 103 is connected to the first control signal PScan(n). The second control terminal of the data writing module 103 is connected to the second control signal NScan(n+10). The input terminal of the data writing module 103 is connected to the data signal Data. The data writing module 103 is also electrically connected to the first node A, the second node B, and the third node Q.

[0046] The data writing module 103 includes, but is not limited to, a third transistor T3 and a fourth transistor T4. The gate of the third transistor T3 is connected to a first control signal PScan(n). One of the source and drain of the third transistor T3 is connected to a data signal Data. The other of the source and drain of the third transistor T3 is electrically connected to a first node A. The gate of the fourth transistor T4 is connected to a second control signal NScan(n+10). One of the source and drain of the fourth transistor T4 is electrically connected to a second node B. The other of the source and drain of the fourth transistor T4 is electrically connected to a third node Q.

[0047] The control terminal of the first initialization module 105 is connected to the third control signal PScan(n) / PScan(n-1). The input terminal of the first initialization module 105 is connected to the first initialization signal Vi1.

[0048] The first initialization module 105 includes, but is not limited to, the sixth transistor T6. The gate of the sixth transistor T6 is connected to the third control signal PScan(n) / PScan(n-1). One of the source and drain of the sixth transistor T6 is connected to the first initialization signal Vi1. The other of the source and drain of the sixth transistor T6 is electrically connected to the fourth node C.

[0049] In this embodiment, the driving timing of the pixel driving circuit 100 includes a write frame and a hold frame. The write frame includes a first reset phase M1 and a data write phase M2 performed sequentially. In the first reset phase M1, the first and second terminals of the driving transistor TD are written with a first power supply signal ELVDD or a first initialization signal Vi1.

[0050] The write frame includes one subframe, and the hold frame includes at least one subframe. It is understood that the display panel can include multiple display frequencies, such as 30Hz, 60Hz, and 120Hz. For example, using 120Hz as a reference, when the display panel is displaying at 120Hz, the driving timing of the pixel driving circuit 100 only includes the write frame, which includes one subframe. When the display panel is displaying at 30Hz, the driving timing of the pixel driving circuit 100 includes both write and hold frames. The write frame includes one subframe, and the hold frames include three subframes. That is, when the display panel is displaying at 120Hz, one display frame includes one subframe. When the display panel is displaying at 30Hz (a low-frequency display), one display frame includes three subframes. The pixel driving circuit 100 only writes the compensated data signal Data to the gate of the driving transistor TD during the write frame.

[0051] In this embodiment, before the data writing stage M2, the first power signal ELVDD is written to the first and second terminals of the driving transistor DT by the first light-emitting control module 101, or the first initialization signal Vi1 is written to the first and second terminals of the driving transistor TD by the first initialization module 105 and the second light-emitting control module 102, thereby resetting the potential of the first and second terminals of the driving transistor TD. By changing the gate-source voltage Vgs of the driving transistor TD, the reset effect of the driving transistor TD in the writing frame is adjusted, reducing the difference in the characteristic reset effect of the driving transistor TD in the first sub-frame of the writing frame and the holding frame, thereby reducing the brightness difference between the first sub-frame of the writing frame and the holding frame and improving screen flicker.

[0052] In some embodiments of this application, the pixel driving circuit 100 further includes a first initialization module 104, a first capacitor Cst, and a light-emitting device D.

[0053] The control terminal of the first initialization module 104 is connected to the fourth control signal PScan(n) / PScan(n-1). The input terminal of the first initialization module 104 is connected to the second initialization signal Vi2. The output terminal of the first initialization module 104 is connected to the fourth node C.

[0054] The first initialization module 104 includes, but is not limited to, the sixth transistor T6. The gate of the sixth transistor T6 is connected to the fourth control signal PScan(n) / PScan(n-1). One of the source and drain of the sixth transistor T6 is connected to the second initialization signal Vi2. The other of the source and drain of the sixth transistor T6 is connected to the fourth node C.

[0055] One plate of the first capacitor Cst is connected to the third node Q. The other plate of the first capacitor Cst is connected to the first power supply signal ELVDD.

[0056] One end of the light-emitting device D is connected to the fourth node C. The other end of the light-emitting device D is connected to the second power supply signal VSS.

[0057] In this application, the voltage of the first power signal ELVDD is greater than the voltage of the second power signal VSS. The light-emitting device D can be a miniature LED, a micro LED, or an organic LED; this application does not specifically limit its application in this regard.

[0058] It should be noted that the transistors used in all embodiments of this application can be thin-film transistors, field-effect transistors, or other devices with the same characteristics. Since the source and drain of the transistors used here are symmetrical, their source and drain are interchangeable. In the embodiments of this application, to distinguish the two terminals of the transistor other than the gate, one terminal is called the source and the other terminal is called the drain. According to the configuration in the accompanying drawings, the middle terminal of the switching transistor is the gate, the signal input terminal is the drain, and the output terminal is the source. In addition, the transistors used in the embodiments of this application can include both P-type transistors and / or N-type transistors. The P-type transistor is turned on when the gate is low and turned off when the gate is high, while the N-type transistor is turned on when the gate is high and turned off when the gate is low.

[0059] Furthermore, to improve the performance of the pixel driving circuit 100, the transistors used in this embodiment are low-temperature polycrystalline silicon thin-film transistors (LTPS) and oxide semiconductor thin-film transistors (OSTs). The OSTs can be, for example, indium gallium zinc oxide (IGaZ) thin-film transistors. In this embodiment, both types of thin-film transistors are used in the same pixel driving circuit 100, making the OSTs the device at locations with high leakage current in the pixel driving circuit 100. This effectively prevents charge leakage at the gate of the corresponding driving transistor TD during low-frequency driving, further preventing screen flickering.

[0060] Specifically, the following embodiments of this application use P-type low-temperature polysilicon transistors as examples, and N-type oxide transistors as examples, for the first transistor T1, driving transistor TD, second transistor T2, third transistor T3 and sixth transistor T6 in the pixel driving circuit 100. However, this should not be construed as a limitation of this application.

[0061] Please continue reading. Figure 1 and Figure 2 In some embodiments of this application, the holding frame includes at least one subframe. If the brightness of the written frame is less than the brightness of the first subframe of the holding frame, then in the first reset phase M1, the first light emission control module 101 responds to the first enable signal EM_L and writes the first power signal ELVDD to the first and second terminals of the driving transistor TD.

[0062] Specifically, during the first reset phase M1, the first enable signal EM_L is low, and the first transistor T1 is turned on. The first power supply signal ELVDD is written to the first and second terminals of the driving transistor TD via the first transistor T1 and the driving transistor TD.

[0063] Furthermore, in the first reset phase M1, the second initialization module 104 responds to the fourth control signal NScan(n) and writes the second initialization signal Vi2 to the gate of the driving transistor TD.

[0064] Specifically, during the first reset phase M1, the fourth control signal NScan(n) is high, and the fifth transistor T5 is turned on. The second initialization signal Vi2 is written to the gate of the driving transistor TD via the fifth transistor T5.

[0065] That is, in the embodiments of this application, both the first light-emitting control module 101 and the second initialization module 104 operate in the first reset phase M1. Of course, by controlling the timing of the fourth control signal NScan(n) and the first enable signal EM_L, the first light-emitting control module 101 and the second initialization module 104 can also be controlled to operate in stages, and this application does not make specific limitations in this regard.

[0066] It is understandable that writing the first power supply signal ELVDD to the first and second terminals of the driving transistor TD can keep the gate-source voltage Vgs of the driving transistor TD at a fixed value, i.e., Vgs = Vgd = Vi² - ELVDD. Since the voltage value of the first power supply signal ELVDD is relatively large, it increases the voltage difference between Vgs and Vgd, which increases the characteristic reset effect of the driving transistor Td. This can effectively improve the brightness of the written frame and reduce flickering caused by low brightness of the written frame.

[0067] In this embodiment of the application, during the data writing stage M2, the data writing module 103, in response to the first control signal PScan(n) and the second control signal NScan(n+10), transmits the compensated data signal Data to the third node Q, that is, writes the compensated data signal to the gate of the driving transistor TD.

[0068] Specifically, in the data writing phase M2, the first control signal PScan(n) is low, the second control signal NScan(n+10) is high, and both the third transistor T3 and the fourth transistor T4 are turned on. The data writing phase M2 includes compensation for the threshold voltage of the driving transistor TD. Therefore, the data written to the third node Q is the compensated data signal, specifically Vdata + Vth, where Vth is the threshold voltage of the driving transistor.

[0069] In this embodiment, the first control signal PScan(n) and the third control signal PScan(n) are the same signal. Therefore, during the data writing stage M2, the first initialization module 105 and the data writing module 103 operate simultaneously. The first initialization module 105, in response to the third control signal PScan(n), writes the first initialization signal Vi1 to the fourth node C, thereby resetting the anode of the light-emitting device D and improving display uniformity.

[0070] Specifically, during the data writing phase M2, the third control signal PScan(n) is low, and the sixth transistor T6 is turned on. The first initialization signal Vi1 is written to the fourth node C via the sixth transistor T6.

[0071] In this embodiment, the driving timing of the pixel driving circuit 100 further includes a third reset stage M3 and an emissive stage M4 after the data writing stage M2.

[0072] In the third reset phase M3, the first light-emitting control module 101 responds to the first enable signal EM_L and writes the first power signal ELVDD to the first and second terminals of the driving transistor TD.

[0073] Specifically, in the third reset phase M3, the first enable signal EM_L is low, and the first transistor T1 is turned on. The first power supply signal ELVDD is written to the first and second terminals of the driving transistor TD via the first transistor T1 and the driving transistor TD.

[0074] Understandably, in the third reset phase M3, the first light-emitting control module 101 transmits the first power signal ELVDD to the first and second terminals of the driving transistor TD. This ensures that under different data signals Data, the pixel driving circuit 100 can reset the potentials of the first and second terminals of the driving transistor TD to the same value, reducing the impact on the characteristics of the driving transistor DT.

[0075] During the light-emitting stage M4, the first light-emitting control module 101 responds to the first enable signal EM_L and the second light-emitting control module 102 responds to the second enable signal EM_R to control the light-emitting device D to emit light.

[0076] Specifically, during the light-emitting stage M4, both the first enable signal EM_L and the second enable signal EM_R are at a low level, and both the first transistor T1 and the second transistor T2 are turned on. Current flows through the first transistor T1, the driving transistor TD, and the second transistor T2 to the light-emitting device D, thereby enabling the light-emitting device D to emit light normally.

[0077] In some embodiments of this application, the pixel driving circuit 100 further includes a second capacitor Cboost. One plate of the second capacitor Cboost is electrically connected to the third node Q. The other plate of the second capacitor Cboost is connected to the first control signal PScan(n).

[0078] The function of the second capacitor, Cboost, is to adjust the potential of the third node, Q, which in turn adjusts the gate potential of the driving transistor TD. This changes the variation range of different data signals Data, mitigating the flickering issue caused by excessive leakage current in the display panel.

[0079] Please see Figure 3 and Figure 4 , Figure 4 yes Figure 3 The signal timing diagram of the pixel driving circuit for writing frames is shown. Figure 3 The pixel driving circuit 100 shown is Figure 1 The difference in the pixel driving circuit 100 shown is that, in this embodiment, the holding frame includes at least one subframe. If the brightness of the written frame is greater than the brightness of the first subframe of the holding frame, then in the first reset phase M1, the first initialization module 105, in response to the third control signal PScan(n-1), writes the first initialization signal Vi1 to the fourth node C. The second light emission control module 102, in response to the second enable signal EM_R, writes the first initialization signal Vi1 to the first and second terminals of the driving transistor TD.

[0080] Specifically, in the first reset phase M1, the third control signal PScan(n-1) and the second enable signal EM_R are both at low potentials, the sixth transistor T6 and the second transistor T2 are turned on, and the first initialization signal Vi1 is written to the first and second terminals of the driving transistor TD through the sixth transistor T6 and the second transistor T2.

[0081] In this embodiment of the application, the write frame further includes a second reset phase M5, which is located between the first reset phase M1 and the data write phase M2.

[0082] In the second reset phase M5, the second initialization module 104 responds to the fourth control signal NScan(n) and writes the second initialization signal Vi2 to the gate of the driving transistor TD, thus completing the initialization of the gate of the driving transistor TD.

[0083] Specifically, during the second reset phase M5, the fourth control signal NScan(n) is high, and the fifth transistor T5 is turned on. The second initialization signal Vi2 is written to the gate of the driving transistor TD via the fifth transistor T5.

[0084] It is understandable that writing the first initialization signal Vi1 to the first and second terminals of the driving transistor TD can make the gate-source voltage Vgs of the driving transistor TD a fixed value Vgs = Vgd = Vi2 - Vi1. Since the voltage value of the first initialization signal Vi1 is small, the voltage difference Vgs / Vgd is reduced, which reduces the characteristic reset effect of the driving transistor Td. This can effectively reduce the brightness of the written frame and improve the flickering caused by the high brightness of the written frame.

[0085] In the embodiments of this application, the first control signal PScan(n) and the third control signal PScan(n-1) are different signals.

[0086] It is understandable that when the first initialization signal Vi1 is written to the first and second terminals of the driving transistor TD during the first reset phase M1, the first initialization module 105 and the second light emission control module 102 need to operate simultaneously. The data writing phase M2 occurs after the first reset phase M1. Therefore, the first control signal PScan(n) and the third control signal PScan(n-1) are different signals, thus ensuring the normal operation of the pixel driving circuit 100.

[0087] In this embodiment, the driving timing of the pixel driving circuit 100 includes a third reset stage M3 and a light emission stage M4 after the data writing stage M2. For details, please refer to the above embodiments, which will not be repeated here.

[0088] In this embodiment of the application, during the holding frame, the data writing module 103 is also used to write the data signal Data to the first and second poles of the driving transistor TD at least once.

[0089] For details, please refer to Figure 3 and Figure 5 , Figure 5 yes Figure 3 The diagram shows the signal timing of the write frame and hold frame of the pixel driving circuit. This embodiment uses an example where the hold frame includes two subframes: a first subframe and a second subframe.

[0090] The signal timing of the first and second subframes is the same. The difference from the write frame is that, within the first or second subframe, the driving timing of the pixel driving circuit 100 does not include the first reset phase M1. Furthermore, during the data write phase M2, the fourth control signal NScan(n) remains low, and the fourth transistor T4 and the fifth transistor T5 remain off. When the first control signal PScan(n) is low, the third transistor T3 turns on, and the data write module 103 writes the data signal Data to the first and second terminals of the driving transistor TD, thus resetting the first and second terminals of the driving transistor TD. Therefore, the first and second terminals of the driving transistor TD are reset within each subframe of the hold frame.

[0091] Within the first or second subframe, the gate of the driving transistor TD is held by the data signal Data written in the write frame. It should be noted that the data signal Data written in the write frame is different from the data signal Data written in the hold frame.

[0092] Please see Figure 6 , Figure 6 This is a schematic diagram of a display panel provided in an embodiment of this application. This application also provides a display panel 1000, including a plurality of pixel units 110 arranged in an array. Each pixel unit 110 includes the pixel driving circuit 100 described in any of the above embodiments; details can be found above, and will not be repeated here.

[0093] In this embodiment, the display panel 1000 may be an OLED (Organic Light-Emitting Diode) display panel, a Mini LED (Mini Light-Emitting Diode) display panel, a Micro LED (Micro Light-Emitting Diode) display panel, etc.

[0094] In the display panel 1000 provided in this application embodiment, the pixel driving circuit 100 includes a first light-emitting control module, a driving transistor, a second light-emitting control module, a data writing module, a second initialization module, a first initialization module, a first capacitor, and a light-emitting device. This application embodiment, by writing a first power signal or a first initialization signal to the first and second terminals of the driving transistor during the first reset phase before the data writing phase, can adjust the reset effect of the driving transistor in the write frame by changing the gate-source voltage of the driving transistor. This reduces the difference in the characteristic reset effect of the driving transistor between the write frame and the hold frame, thereby reducing the brightness difference between the write frame and the hold frame and improving screen flicker.

[0095] The pixel driving circuit and display panel provided in the embodiments of this application have been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of this application. The description of the above embodiments is only for the purpose of helping to understand the method and core ideas of this application. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of this application. Therefore, the content of this specification should not be construed as a limitation of this application.

Claims

1. A pixel driving circuit, characterized in that, include: Drive transistors; The first light-emitting control module has a control terminal connected to a first enable signal, an input terminal connected to a first power signal, and an output terminal electrically connected to the first electrode of the driving transistor. The second light-emitting control module has a control terminal connected to a second enable signal, and its output terminal is electrically connected to the second electrode of the driving transistor. The data writing module has a first control terminal connected to a first control signal, a second control terminal connected to a second control signal, an input terminal connected to a data signal, and is also electrically connected to the gate, first electrode, and second electrode of the driving transistor. as well as The first initialization module has a control terminal connected to a third control signal, an input terminal connected to a first initialization signal, and an output terminal electrically connected to the input terminal of the second light-emitting control module. The second initialization module has a control terminal connected to a fourth control signal, an input terminal connected to a second initialization signal, and an output terminal electrically connected to the gate of the driving transistor. The driving timing of the pixel driving circuit includes a write frame and a hold frame, wherein the hold frame includes at least one subframe; and the write frame includes a first reset phase and a data write phase performed sequentially. During the first reset phase, if the brightness of the write frame is less than the brightness of the first subframe of the hold frame, the first light emission control module is used to write the first power signal to the first and second terminals of the driving transistor to increase the brightness of the write frame; or if the brightness of the write frame is greater than the brightness of the first subframe of the hold frame, the first initialization module and the second light emission control module are used to write the first initialization signal to the first and second terminals of the driving transistor to decrease the brightness of the write frame.

2. The pixel driving circuit according to claim 1, characterized in that, If the brightness of the written frame is less than the brightness of the first subframe of the held frame, then during the first reset phase, the first light emission control module responds to the first enable signal and writes the first power signal to the first and second terminals of the driving transistor.

3. The pixel driving circuit according to claim 2, characterized in that, The first control signal and the third control signal are the same signal.

4. The pixel driving circuit according to claim 2, characterized in that, During the first reset phase, the second initialization module responds to the fourth control signal by writing the second initialization signal to the gate of the driving transistor.

5. The pixel driving circuit according to claim 1, characterized in that, If the brightness of the written frame is greater than the brightness of the first subframe of the held frame, then during the first reset phase, the first initialization module responds to the third control signal, and the second light emission control module responds to the second enable signal, and writes the first initialization signal to the first and second terminals of the driving transistor.

6. The pixel driving circuit according to claim 5, characterized in that, The write frame further includes a second reset phase, which is located between the first reset phase and the data write phase; During the second reset phase, the second initialization module responds to the fourth control signal by writing the second initialization signal to the gate of the driving transistor.

7. The pixel driving circuit according to claim 5, characterized in that, The first control signal and the third control signal are different signals.

8. The pixel driving circuit according to any one of claims 1 to 7, characterized in that, The driving timing of the pixel driving circuit includes a third reset stage and a light emission stage after the data writing stage; During the data writing phase, the data writing module transmits the compensated data signal to the gate of the driving transistor in response to the first control signal and the second control signal. In the third reset phase, the first light-emitting control module responds to the first enable signal and writes the first power signal to the first and second terminals of the driving transistor. During the light-emitting phase, the first light-emitting control module responds to the first enable signal and the second light-emitting control module responds to the second enable signal to control the light-emitting device to emit light.

9. The pixel driving circuit according to any one of claims 1 to 7, characterized in that, During the holding frame, the data writing module is also used to write the data signal to the first and second poles of the driving transistor at least once.

10. A display panel, characterized in that, The display panel includes a plurality of pixel units arranged in an array, and each pixel unit includes a pixel driving circuit as described in any one of claims 1-9.

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