A pixel circuit

Abstract

The application discloses a pixel circuit, including: the working stage of the pixel circuit includes a write stage and a holding stage, the pixel circuit includes: a driving transistor connected between a first power supply line and a second power supply line; one of the source and the drain of a compensation transistor is connected to the gate of the driving transistor, and the other of the source and the drain of the compensation transistor is connected to one of the source and the drain of the driving transistor; a first reset transistor is connected between a reset signal line and the gate of the driving transistor, the first reset transistor includes a first sub-transistor and a second sub-transistor connected in series, and the first sub-transistor and the second sub-transistor have a first node therebetween; a boosting capacitor and a storage capacitor connected in parallel, one end of the boosting capacitor and one end of the storage capacitor are connected between the gate of the driving transistor and one of the source and the drain of the first reset transistor. The application improves the uniformity of brightness in a frame.

Description

Technical Field

[0001] This application relates to the field of display panel driving technology, and more specifically to a pixel circuit. Background Technology

[0002] Organic light-emitting diodes (OLEDs) have advantages such as simple fabrication process, low cost, high luminous efficiency, easy formation of flexible structures, low power consumption, high color saturation, and wide viewing angle. OLED display technology has become an important display technology.

[0003] OLEDs are current-driven light-emitting devices, primarily consisting of an anode, a cathode, and an organic material functional layer. The main working principle of an OLED is that the organic material functional layer emits light through carrier injection and recombination under the influence of the electric field formed by the anode and cathode. However, as users' demands for display screen power consumption increase, some technologies employ low-temperature poly-oxide (LTPO) substrate processes with low-frequency driving to reduce the display panel's power consumption and extend standby time. However, low-frequency driving can result in some black areas not being completely black, leading to issues like bright spots. Summary of the Invention

[0004] This application provides a pixel circuit that can improve the display effect by reducing bright spots.

[0005] This application provides a pixel circuit, the pixel circuit's operating phases including a write phase and a hold phase, the pixel circuit comprising:

[0006] A driving transistor, wherein the driving transistor is connected in series between the first power line and the second power line;

[0007] A compensation transistor, wherein one of the source and drain of the compensation transistor is connected to the gate of the driving transistor, and the other of the source and drain of the compensation transistor is connected to one of the source and drain of the driving transistor.

[0008] A first reset transistor is connected between a reset signal line and the gate of the driving transistor. The first reset transistor includes a first sub-transistor and a second sub-transistor connected in series, with a first node between the first sub-transistor and the second sub-transistor.

[0009] A boost capacitor and a storage capacitor are connected in parallel, with one end of the boost capacitor and one end of the storage capacitor connected between the gate of the driving transistor and one of the source and drain of the first reset transistor.

[0010] The channel type of the compensation transistor is the same as that of the first reset transistor, while the channel type of the driving transistor is different from that of the compensation transistor.

[0011] This application provides a pixel circuit. The pixel circuit and display panel provided by this application can reduce the gate leakage current of the driving transistor by reducing the voltage difference between the gate of the driving transistor and the first node, so that the light emission current flowing through the driving transistor is more constant, thereby improving the uniformity of brightness within the frame. Attached Figure Description

[0012] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0013] Figure 1 This is a schematic diagram of a pixel circuit provided in an embodiment of this application;

[0014] Figure 2 This is another circuit diagram of the pixel circuit provided in the embodiments of this application;

[0015] Figure 3 This is another circuit diagram of the pixel circuit provided in the embodiments of this application;

[0016] Figure 4 This is another circuit diagram of the pixel circuit provided in the embodiments of this application;

[0017] Figure 5 This is a timing diagram provided in an embodiment of this application;

[0018] Figure 6 This is another timing diagram provided in an embodiment of this application;

[0019] Figure 7 This is another timing diagram provided in an embodiment of this application;

[0020] Figure 8 This is another timing diagram provided in an embodiment of this application;

[0021] Figure 9 This is another timing diagram provided in an embodiment of this application;

[0022] Figure 10 This is another timing diagram provided in the embodiments of this application. Detailed Implementation

[0023] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0024] In the description of this application, it should be understood that the terms "one end," "the other end," etc., indicating the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the stated features. In the description of this application, "a plurality of" means two or more, unless otherwise explicitly specified.

[0025] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "connected" and "linked" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection, a link, or a connection that allows for communication; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.

[0026] The following disclosure provides many different implementations or examples for carrying out different structures of this application. To simplify the disclosure, specific examples of components and arrangements are described below. Of course, these are merely examples and are not intended to limit the scope of this application. Furthermore, reference numerals and / or letters may be repeated in different examples; such repetition is for simplification and clarity and does not in itself indicate a relationship between the various implementations and / or arrangements discussed. In the above embodiments, the descriptions of each embodiment have their own emphasis; parts not described in detail in a certain embodiment can be referred to in the relevant descriptions of other embodiments.

[0027] The display panel in this application embodiment can be used in mobile phones, tablets, desktop computers, laptops, e-readers, handheld computers, electronic display screens, laptops, ultra-mobile personal computers (UMPCs), netbooks, as well as cellular phones, personal digital assistants (PDAs), augmented reality (AR) / virtual reality (VR) devices, media players, wearable devices, digital cameras, car navigation systems, etc.

[0028] In the circuit structure provided by the embodiments of this application, nodes such as the first node and the second node do not represent actual existing components, but rather represent the junction points of related couplings in the circuit diagram. In other words, these nodes are equivalent to the junction points of related couplings in the circuit diagram.

[0029] This application provides a pixel circuit whose operating phases include a write phase and a hold phase, such as... Figures 1 to 4 As shown, the pixel circuit includes:

[0030] A driving transistor T1 is connected in series between the first power line VDD and the second power line VSS.

[0031] A compensation transistor T3, one of the source and drain of the compensation transistor T3 is connected to the gate of the driving transistor T1, and the other of the source and drain of the compensation transistor T3 is connected to one of the source and drain of the driving transistor T1.

[0032] The first reset transistor T4 is connected between the reset signal line Vi-Gate and the gate of the driving transistor T1. The first reset transistor T4 includes a first sub-transistor T41 and a second sub-transistor T42 connected in series, with a first node N1 between the first sub-transistor T41 and the second sub-transistor T42.

[0033] A boost capacitor Cboost and a storage capacitor Cst are connected in parallel, with one end of the boost capacitor Cboost and one end of the storage capacitor Cst connected between the gate of the driving transistor T1 and one of the source and drain of the first reset transistor T4.

[0034] The channel type of the compensation transistor T3 is the same as that of the first reset transistor T4, while the channel type of the driving transistor T1 is different from that of the compensation transistor T3.

[0035] Specifically, one of the source and drain of the compensation transistor T3 is connected to one of the source and drain of the driving transistor T1, and the gate of the compensation transistor T3 is connected to the first scan line. A first reset transistor T4 has one of its source and drain connected to one of the source and drain of the compensation transistor T3 and the gate of the driving transistor T1, respectively. The other of the source and drain of the first reset transistor T4 is connected to the reset signal line Vi-Gate, and the gate of the first reset transistor T4 is connected to the second scan line.

[0036] The display panel includes multiple pixels arranged in an array, with each pixel connected to a corresponding pixel circuit. The leakage current of a dual-gate thin-film transistor is smaller than that of a single-gate thin-film transistor. In this application, both the compensation transistor T3 and the first reset transistor T4 can be configured as dual-gate thin-film transistors, or simply dual-gate transistors. A dual-gate transistor includes two transistors of the same channel type. One of the source and drain of the first transistor is connected to the other of the source and drain of the second transistor, and these two transistors of the same channel type share a common gate.

[0037] The first reset transistor T4 includes a first sub-transistor T41 and a second sub-transistor T42 with the same channel type. The other of the source and drain of the first sub-transistor T41 is connected to the reset signal line Vi-Gate. The other of the source and drain of the first sub-transistor T41 is connected to the other of the source and drain of the second sub-transistor T42. The other of the source and drain of the second sub-transistor T42 is connected to the gate of the driving transistor T1. The first node N1 is any node on the connection line between the source and drain of the first sub-transistor T41 and the other of the source and drain of the second sub-transistor T42.

[0038] It should be noted that the first power line VDD is used to transmit the first power signal VDD, and the second power line VSS is used to transmit the second power signal VSS. The potential of the first power signal VDD is higher than that of the second power signal VSS. The reset signal line Vi-Gate is used to transmit the first potential signal Vi-G. The first scan line is used to transmit the first scan signal Nscan(n), and the second scan line is used to transmit the second scan signal Nscan(n-7).

[0039] It is understood that in this embodiment, the channel type of the compensation transistor T3 is the same as that of the first reset transistor T4, while the channel type of the driving transistor T1 is different from that of the compensation transistor T3. For example, in this embodiment, both the compensation transistor T3 and the first reset transistor T4 are P-channel thin-film transistors, and the driving transistor T1 is an N-channel thin-film transistor; or both the compensation transistor T3 and the first reset transistor T4 are N-channel thin-film transistors, and the driving transistor T1 is a P-channel thin-film transistor.

[0040] In some embodiments, when the pixel circuit switches from a first frequency to a second frequency lower than the first frequency, the potential difference between the first node N1 and the gate of the driving transistor T1 during the holding phase is less than the voltage signal connected to the reset signal line Vi-Gate during the writing phase.

[0041] During the holding phase, the potential difference between the first node N1 and the gate of the driving transistor T1 is reduced so that the voltage signal connected to the reset signal line Vi-Gate during the holding phase is less than the voltage signal connected to the reset signal line Vi-Gate during the writing phase.

[0042] Specifically, it can be understood that in this embodiment, when the pixel circuit switches from a first frequency to a second frequency lower than the first frequency, that is, when the driving signal received by the first scan line or the second scan line of the pixel circuit switches from a high frequency to a low frequency, for example, from 120Hz to 30Hz, or from 120Hz to 10Hz, the pixel circuit, during the holding phase, can timely change the potential of the other of the source and drain of the compensation transistor T3 and the potential of one of the source and drain of the first reset transistor T4 through the reset signal line Vi-Gate connected to the other of the source and drain of the first reset transistor T4, so as to reduce the voltage difference between the gate of the driving transistor T1 and one of the source and drain of the compensation transistor T3, and between the gate of the driving transistor T1 and one of the source and drain of the first reset transistor T4, thereby reducing the gate leakage current of the driving transistor T1, making the light-emitting current flowing through the driving transistor T1 more stable, and thus improving the uniformity of brightness within the display cycle of the display panel.

[0043] In some embodiments, such as Figures 1 to 4As shown, the channel type of the compensation transistor T3 is the same as that of the first reset transistor T4. The first reset transistor T4 is a dual-gate transistor, and it includes a first sub-transistor T41 and a second sub-transistor T42. The channel types of the first sub-transistor T41 and the second sub-transistor T42 are the same as those of the first reset transistor T4. That is, the channel types of the first sub-transistor T41, the second sub-transistor T42, the compensation transistor T3, and the first reset transistor T4 are the same. The channel type of the driving transistor T1 is different from that of the compensation transistor T3. For example, the first sub-transistor T41, the second sub-transistor T42, the compensation transistor T3, and the first reset transistor T4 are all N-type MOS transistors, and the driving transistor T1 is a P-type MOS transistor.

[0044] Specifically, such as Figure 1 and Figure 5 As shown, the reset signal line Vi-Gate is used to transmit the first potential signal Vi-G. The operation phase of the pixel circuit includes a write phase and a hold phase. During the hold phase, the voltage signal connected to the reset signal line is increased, that is, the potential of the first potential signal Vi-G in the write phase is lower than the potential in the hold phase.

[0045] For example, when the first reset transistor T4 is an NMOS transistor, in the case of... Figure 1 In the pixel circuit with the 7T2C (T represents transistor, C represents capacitor) structure shown, when the pixel circuit switches from receiving a high-frequency scanning signal to receiving a low-frequency scanning signal, the magnitude of the first potential signal Vi-G during the holding phase is changed by timing control, so that the potential of the first potential signal Vi-G during the holding phase is greater than the potential of the first potential signal Vi-G during the writing phase. In this way, the gate potential of the driving transistor T1 remains stable, thereby reducing the risk of bright spots and improving the uniformity of brightness within the frame.

[0046] It should be noted that, such as Figure 5 As shown, the first potential signal Vi-G has a lower potential during the write phase than during the hold phase. This not only helps reduce the gate leakage current of the driving transistor T1 but also helps change the potential of the third node B and the second node A, thereby reducing the unidirectional drift range of the threshold voltage of the driving transistor T1 in a single operating state. Specifically, the potential of the third node B can be linked to the potential of the second node A through the driving transistor T1; that is, when the potential of either the second node A or the third node B changes, the potential of the other node also changes accordingly.

[0047] In some embodiments, such as Figure 2As shown, the first node N is connected to the gate of the driving transistor T1 and one of the source and drain of the compensation transistor T3.

[0048] Specifically, such as Figure 2 As shown, since the first reset transistor T4 is a dual-gate transistor, the first node N is connected to the gate of the driving transistor T1 and one of the source and drain of the compensation transistor T3. During the holding phase, the pixel circuit raises the first potential signal Vi-G connected to the reset signal line, meaning that the potential of the first potential signal Vi-G during the writing phase is lower than its potential during the holding phase. By connecting the first node N to one of the source and drain of the compensation transistor T3 and the gate of the driving transistor T1, the potential of one of the source and drain of the compensation transistor T3 and the potential of one of the source and drain of the first reset transistor T4 can be changed in a timely manner. This reduces the voltage difference between the gate of the driving transistor T1 and one of the source and drain of the compensation transistor T3, and between the gate of the driving transistor T1 and one of the source and drain of the first reset transistor T4, thereby reducing the gate leakage current of the driving transistor T1. This makes the light-emitting current flowing through the driving transistor T1 more stable, thereby improving the uniformity of brightness within the display cycle of the display panel.

[0049] In some embodiments, such as Figure 3 and Figure 10 ,as well as Figure 4 and Figure 10 As shown, the pixel circuit further includes:

[0050] A first capacitor C1, one end of which is connected to the first node;

[0051] The first control transistor T8 has one of its source and drain connected to the second potential line Vi3 or the first power supply line VDD, the gate of the first control transistor T8 is connected to the third scan line Pscan(n), and the other of its source and drain is connected to the other end of the first capacitor C1.

[0052] During the holding phase, the voltage signal connected to the second potential line Vi3 or the first power line VDD is greater than the voltage signal connected to the second potential line Vi3 or the first power line VDD during the writing phase.

[0053] Specifically, the second potential line is used to transmit the second potential signal Vi3, and the third scan line is used to transmit the third scan signal Pscan(n). In some embodiments, the channel type of the first control transistor T8 is the same as the channel type of the compensation transistor T3. For example, both the first control transistor T8 and the compensation transistor T3 are NMOS transistors.

[0054] Specifically, such as Figure 3 As shown, a first capacitor C1 is connected at one end to the first node N; a first control transistor T8 is connected to a second potential line Vi3, the gate of the first control transistor T8 is connected to a third scan line Pscan(n), and one of the source and drain of the first control transistor T8 is connected to the other end of the first capacitor C1; the pixel circuit is configured to, during the holding phase, increase the voltage signal connected to the second potential line Vi3, so that the voltage signal connected to the second potential line Vi3 charges the first capacitor C1. Figure 10 As shown, during the holding phase, the control transistor T8 increases the voltage signal connected to the second potential line Vi3, which is the other of the source and drain of the first control transistor T8. This allows the voltage signal connected to the second potential line Vi3 to charge one side of the first capacitor C1. Due to the coupling effect between the first capacitor C1 and the first node N, the potential at the first node N1 increases, thereby reducing the difference between the potential of the first node N1 and the potential of the gate of the driving transistor T1.

[0055] Specifically, such as Figure 4 As shown, a first capacitor C1 is connected at one end to the first node N; a first control transistor T8 is connected to the first power supply line VDD, its gate is connected to the third scan line Pscan(n), and its source and drain are connected to the other end of the first capacitor C1; the pixel circuit is configured to, during the holding phase, increase the voltage signal connected to the first power supply line VDD, so that the voltage signal connected to the first power supply line VDD charges the first capacitor C1. Figure 10 As shown, during the holding phase, the control transistor T8 increases the voltage signal connected to the first power line VDD via the source and drain of the first control transistor T8, thereby charging the voltage signal connected to the first power line VDD to one side of the first capacitor C1. Due to the coupling effect generated by the connection between the first capacitor C1 and the first node N, the potential at the first node N1 increases, thereby reducing the difference between the potential of the first node N1 and the potential of the gate of the driving transistor T1.

[0056] In some embodiments, during the holding phase, the gate-on voltage VGH of the first reset transistor T4 is lower than during the writing phase.

[0057] Specifically, the pixel circuit is configured to lower the gate-on voltage VGH of the first reset transistor T4 during the holding phase. For example... Figure 7 As shown, it can be analyzed that by reducing the gate g connection of the driving transistor T1, as shown... Figure 6 The enable signal V_vgh shown increases the source-gate voltage Vsg of the driving transistor T1, which is equivalent to increasing the source-drain voltage Vsd of the driving transistor T1, thereby reducing the leakage current of the driving transistor T1. Therefore, as Figure 8 As shown, in this embodiment of the application, while ensuring the high-frequency display effect, the potential of the turn-on voltage VGH of the first reset transistor T4 is reduced to suppress the gate potential difference between the first node N1 and the driving transistor T1, thereby reducing the risk of bright spots.

[0058] In some embodiments, during the holding phase, the gate turn-off voltage VGL of the first reset transistor T4 is greater than the gate turn-off voltage VGL of the first reset transistor T4 during the writing phase.

[0059] Specifically, the pixel circuit is configured to increase the gate turn-off voltage VGL of the first reset transistor T4 during the holding phase. For example... Figure 9 As shown, it can be analyzed that by reducing the gate g connection of the driving transistor T1, as shown... Figure 6 The enable signal V_vgh shown increases the source-gate voltage Vsg of the driving transistor T1, which is equivalent to increasing the source-drain voltage Vsd of the driving transistor T1, thereby reducing the leakage current of the driving transistor T1. Therefore, as Figure 9 As shown, in this embodiment of the application, while ensuring the high-frequency display effect, the potential of the gate turn-off voltage of the first reset transistor T4 is increased to suppress the gate potential difference between the first node N1 and the driving transistor T1, thereby reducing the risk of bright spots.

[0060] In some embodiments, the pixel circuit further includes:

[0061] A first light-emitting control transistor T6, one of the source and drain of the first light-emitting control transistor T6 is connected to the source and drain of the driving transistor T1, and the gate of the first light-emitting control transistor T6 is connected to the light-emitting control line EM.

[0062] The light-emitting device D1 has its anode connected to one of the source and drain of the first light-emitting control transistor T6, and its cathode connected to the second power line VSS.

[0063] The second control transistor T7 has one of its source and drain connected to the initialization line Vi-Ano, the other of its source and drain connected to the anode of the light-emitting device, and its gate connected to the fourth scan line Pscan(n-1).

[0064] During the holding phase, the voltage signal connected to the initialization line Vi-Ano is greater than the voltage signal connected to the initialization line Vi-Ano during the writing phase.

[0065] Specifically, the pixel circuit is configured to increase the voltage signal connected to the data line Vi-Ano during the hold phase. The data line Vi-Ano is used to transmit the third potential signal Vi-Ano. The pixel circuit's operating phases include a write phase and a hold phase. During the hold phase, the voltage signal connected to the data line is increased, meaning the potential of the third potential signal Vi-Ano during the write phase is lower than its potential during the hold phase. For example, when the first reset transistor T4 is an NMOS transistor, in such cases... Figure 1 In the pixel circuit with the 7T2C (T represents transistor, C represents capacitor) structure shown, when the pixel circuit switches from receiving a high-frequency scanning signal to receiving a low-frequency scanning signal, the magnitude of the third potential signal Vi-Ano during the holding phase is changed by timing control. This ensures that the potential of the third potential signal Vi-Ano during the holding phase is greater than that during the writing phase. In this way, the gate potential of the driving transistor T1 remains stable, thereby reducing the risk of bright spots and improving the uniformity of brightness within the frame.

[0066] It should be noted that, such as Figure 5 As shown, the third potential signal Vi-Ano has a lower potential during the write phase than during the hold phase. This not only helps reduce the gate leakage current of the driving transistor T1, but also helps change the potentials of the fourth node C and the third node B, thereby reducing the unidirectional drift range of the threshold voltage of the driving transistor T1 in a single operating state. Specifically, the potential of the third node B can be linked to the potential of the fourth node C through the driving transistor T1; that is, when the potential of either the third node B or the fourth node C changes, the potential of the other node also changes accordingly.

[0067] In some embodiments, under the control of the fourth scan line Pscan(n-1) connected to the gate of the second control transistor T7, the second control transistor T7 can be turned on multiple times in different stages of a frame to adjust or reset the anode potential of the light-emitting device D1 multiple times. This can improve the light emission brightness of the light-emitting device D1, and further improve the brightness difference within the frame.

[0068] Among them, the light-emitting device D1 can be one of organic light-emitting diode, quantum dot light-emitting diode, micro light-emitting diode or mini light-emitting diode.

[0069] It should be noted that the voltage signal connected to the data line is increased, that is, the potential of the third potential signal Vi-Ano in the writing stage is lower than the potential in the holding stage, which is beneficial to adjust or reset the anode potential of the light-emitting device D1, so as to further improve the brightness difference within the frame.

[0070] In some embodiments, the pixel circuit further includes:

[0071] The second light-emitting control transistor T5 has one of its source and drain connected to the first power line VDD, the other of its source and drain connected to the other of its source and drain connected to the driving transistor T1, and its gate connected to the gate of the first light-emitting control transistor T6.

[0072] The third control transistor T2, the other of the source and drain of the third control transistor T2 is connected to the data line Data, the gate of the third control transistor T2 is connected to the third scan line Pscan(n), and the other of the source and drain of the third control transistor T2 is connected to the other of the source and drain of the driving transistor T1.

[0073] During the holding phase, the voltage signal connected to the data line is greater than the voltage signal connected to the data line during the writing phase.

[0074] Specifically, the pixel circuit is configured to increase the voltage signal connected to the data line during the hold phase. The data line is used to transmit the data signal Data. The pixel circuit operates in two phases: a write phase and a hold phase. During the hold phase, the voltage signal connected to the data line is increased, meaning the potential of the data signal Data during the write phase is lower than its potential during the hold phase. For example, when the first reset transistor T4 is an NMOS transistor, in such cases… Figure 1 In the pixel circuit with the 7T2C (T represents transistor, C represents capacitor) structure shown, when the pixel circuit switches from receiving a high-frequency scanning signal to receiving a low-frequency scanning signal, the magnitude of the data signal Data during the holding phase is changed by timing control, so that the potential of the data signal Data during the holding phase is greater than the potential of the data signal Data during the writing phase. In this way, the gate potential of the driving transistor T1 remains stable, thereby reducing the risk of bright spots and improving the uniformity of brightness within the frame.

[0075] It should be noted that, such as Figure 5 As shown, the potential of the data signal Data during the write phase is lower than its potential during the hold phase. This not only helps reduce the gate leakage current of the driving transistor T1, but also helps to change the potentials of the second node A and the third node B, thereby reducing the unidirectional drift range of the threshold voltage of the driving transistor T1 in a single operating state. Specifically, the potential of the third node B can be linked to the potential of the second node A through the driving transistor T1; that is, when the potential of either the third node B or the second node A changes, the potential of the other node also changes accordingly.

[0076] It should be noted that the channel material of these transistors is low-temperature polycrystalline silicon, which not only improves the dynamic performance of the pixel circuit but also simplifies the fabrication process, structure, and cost. While low-temperature polycrystalline silicon thin-film transistors are a preferred option, they are not the only option. At least one of the aforementioned transistors may also be an indium gallium zinc oxide thin-film transistor.

[0077] The pixel circuit provided in the embodiments of this application has been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of this application. The description of the above embodiments is only for the purpose of helping to understand the technical solutions and core ideas of this application. Those skilled in the art should understand that they can still modify the technical solutions described in the foregoing embodiments or make equivalent substitutions for some of the technical features. These modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A pixel circuit, characterized in that, The operation phases of the pixel circuit include a write phase and a hold phase. The pixel circuit includes: A driving transistor, wherein the driving transistor is connected in series between the first power line and the second power line; A compensation transistor, wherein one of the source and drain of the compensation transistor is connected to the gate of the driving transistor, and the other of the source and drain of the compensation transistor is connected to one of the source and drain of the driving transistor. A first reset transistor is connected between a reset signal line and the gate of the driving transistor. The first reset transistor includes a first sub-transistor and a second sub-transistor connected in series, with a first node between the first sub-transistor and the second sub-transistor. A boost capacitor and a storage capacitor are connected in parallel, with one end of the boost capacitor and one end of the storage capacitor connected between the gate of the driving transistor and one of the source and drain of the first reset transistor. The channel type of the compensation transistor is the same as that of the first reset transistor, while the channel type of the driving transistor is different from that of the compensation transistor. The first node is connected to the gate of the driving transistor and one of the source and drain of the compensation transistor.

2. The pixel circuit according to claim 1, characterized in that, If the pixel circuit switches from a first frequency to a second frequency lower than the first frequency, the potential difference between the first node and the gate of the driving transistor during the holding phase is less than the voltage signal connected to the reset signal line during the writing phase.

3. The pixel circuit according to claim 2, characterized in that, During the holding phase, the voltage signal connected to the reset signal line is less than the voltage signal connected to the reset signal line during the writing phase.

4. The pixel circuit according to claim 1, characterized in that, The pixel circuit also includes: A first capacitor, one end of which is connected to the first node; A first control transistor, one of the source and drain of the first control transistor is connected to a second potential line or the first power supply line, the gate of the first control transistor is connected to a third scan line, and the other of the source and drain of the first control transistor is connected to the other end of the first capacitor. During the holding phase, the voltage signal connected to the second potential line or the first power line is greater than the voltage signal connected to the second potential line or the first power line during the writing phase.

5. The pixel circuit according to claim 4, characterized in that, The channel type of the first control transistor is the same as that of the compensation transistor.

6. The pixel circuit according to claim 5, characterized in that, During the holding phase, the gate turn-on voltage of the first reset transistor is lower than that during the writing phase.

7. The pixel circuit according to claim 5, characterized in that, During the holding phase, the gate turn-off voltage of the first reset transistor is greater than the gate turn-off voltage of the first reset transistor during the writing phase.

8. The pixel circuit according to any one of claims 1 to 7, characterized in that, The pixel circuit also includes: A first light-emitting control transistor, wherein one of the source and drain of the first light-emitting control transistor is connected to one of the source and drain of the driving transistor, and the gate of the first light-emitting control transistor is connected to a light-emitting control line. A light-emitting device, wherein the anode of the light-emitting device is connected to one of the source and drain of the first light-emitting control transistor, and the cathode of the light-emitting device is connected to the second power line; The second control transistor has one of its source and drain connected to the initialization line, the other of its source and drain connected to the anode of the light-emitting device, and its gate connected to the fourth scan line. During the holding phase, the voltage signal connected to the initialization line is greater than the voltage signal connected to the initialization line during the writing phase.

9. The pixel circuit according to claim 8, characterized in that, The pixel circuit also includes: The second light-emitting control transistor has one of its source and drain connected to the first power line, the other of its source and drain connected to the other of the driving transistor, and its gate connected to the gate of the first light-emitting control transistor. A third control transistor, one of its source and drain is connected to a data line, its gate is connected to a third scan line, and the other of its source and drain is connected to the other of the source and drain of the driving transistor; the voltage signal applied to the data line during the holding phase is greater than the voltage signal applied to the data line during the writing phase.

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