Gate driving circuit, display panel and display device

Abstract

A gate driving circuit, a display panel, and a display device are provided. The gate driving circuit includes a first mode controller configured to output, in response to reception of a first mode signal, a first emission signal based on at least one of a potential of a first node and a potential of a second node to a first output line, a second mode controller configured to output, in response to reception of a second mode signal, a second emission signal based on at least one of the potential of the first node and the potential of the second node to a second output line, and a node controller configured to control the potential of the first node and the potential of the second node by using at least one of a start signal, a first clock signal, and a second clock signal.

Description

[0001] Cross-reference to related applications

[0002] This application claims the benefit of Korean Patent Application No. 10-2022-0093903, filed on July 28, 2022, the entire contents of which are expressly incorporated herein by reference. Technical Field

[0003] The present invention relates to a gate driving circuit and a display panel and display device including the gate driving circuit, wherein the gate driving circuit provides signals for controlling a pixel circuit including a plurality of light-emitting elements. Background Technology

[0004] With the advancement of technology in modern society, display devices are used in various forms to provide information to users. In addition to electronic display panels that simply transmit visual information in one direction, display devices also include various electronic devices used to check user input and require more advanced technology to provide information in response to the checked input.

[0005] For example, display devices may be included in a vehicle to provide various information to the driver and passengers. However, the vehicle's display devices need to display content correctly so as not to interfere with driving. For instance, the display devices need to limit the display of content that could impair driver attention while driving. Summary of the Invention

[0006] Therefore, embodiments of the present invention aim to provide a gate driving circuit and a display panel and display device including the gate driving circuit, wherein the gate driving circuit provides signals for controlling a pixel circuit including a plurality of light-emitting elements.

[0007] One aspect of the present invention is to provide a gate driving circuit and a display panel and display device including the gate driving circuit, wherein the gate driving circuit provides signals to a pixel circuit for controlling the viewing angle of the display device according to a mode by using a plurality of light-emitting elements.

[0008] Additional features and aspects will be set forth in the following description, some of which will be obvious from the description or may be learned by practice of the inventive concept provided herein. Other features and aspects of the inventive concept may be realized and obtained by means of the structures specifically pointed out in the written description or its derivatives, as well as in the claims and drawings.

[0009] To achieve these and other aspects of the inventive concept, as embodied and broadly described herein, a gate driving circuit may include: a first mode controller configured to output a first light emission signal based on at least one of the potentials of a first node and a second node to a first output line in response to the reception of a first mode signal; a second mode controller configured to output a second light emission signal based on at least one of the potentials of the first node and the second node to a second output line in response to the reception of a second mode signal; and a node controller configured to control the potentials of the first node and the second node by using at least one of a start signal, a first clock signal, and a second clock signal.

[0010] According to another aspect of the present invention, a display panel may include: a plurality of pixel circuits; and a gate driving circuit configured to control the driving of the plurality of pixel circuits based on the provision of a first light-emitting signal and a second light-emitting signal to each of the plurality of pixel circuits, wherein the gate driving circuit includes: a first mode controller configured to output a first light-emitting signal based on at least one of the potential of a first node and the potential of a second node to a first output line in response to the reception of a first mode signal; a second mode controller configured to output a second light-emitting signal based on at least one of the potential of the first node and the potential of the second node to a second output line in response to the reception of a second mode signal; and a controller configured to control the potential of the first node and the potential of the second node by using at least one of a start signal, a first clock signal, and a second clock signal.

[0011] According to another aspect of the present invention, a display device may be disposed in at least a portion of a transport means to provide at least one type of content, and the display device may include: a plurality of pixel circuits; and a gate driving circuit configured to control the driving of the plurality of pixel circuits based on the provision of a first light-emitting signal and a second light-emitting signal to each of the plurality of pixel circuits, wherein the gate driving circuit includes: a first mode controller configured to output a first light-emitting signal based on at least one of the potentials of a first node and a second node to a first output line in response to the reception of a first mode signal; a second mode controller configured to output a second light-emitting signal based on at least one of the potentials of the first node and the second node to a second output line in response to the reception of a second mode signal; and a controller configured to control the potentials of the first node and the second node by using at least one of a start signal, a first clock signal, and a second clock signal.

[0012] It should be understood that the preceding general description and the following detailed description are illustrative and explanatory, intended to provide further explanation of the claimed inventive concept. Attached Figure Description

[0013] The accompanying drawings, which provide a further understanding of the invention and are incorporated in and form a part of this application, illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.

[0014] In the attached diagram:

[0015] Figure 1 This is a view illustrating an example of a display device according to an embodiment of the present invention;

[0016] Figure 2 This is a functional block diagram illustrating a display device according to an embodiment of the present invention;

[0017] Figure 3 This is a view illustrating an example of the pixel circuit of a display device according to an embodiment of the present invention;

[0018] Figure 4 This is a view illustrating an example of a pixel array (wherein a gate driving circuit is connected to a pixel circuit) of a display device according to an embodiment of the present invention;

[0019] Figure 5 and 6 This is a view illustrating an example of the pixel circuit of a display device according to an embodiment of the present invention;

[0020] Figure 7This is a view illustrating an example of a lens arrangement included in a display device according to an embodiment of the present invention;

[0021] Figure 8 It is along Figure 7 A sectional view taken by line I-I';

[0022] Figure 9 It is along Figure 7 A sectional view taken from line II-II';

[0023] Figure 10 and 11 This is a conceptual diagram illustrating the gate driving circuit of a display device according to an embodiment of the present invention;

[0024] Figures 12 to 16 This is a view illustrating an example of a gate driving circuit of a display device according to an embodiment of the present invention;

[0025] Figure 17 This is a view illustrating an example of the signal flow of a display device according to an embodiment of the present invention. Detailed Implementation

[0026] Considering the functionality of this invention, the terms used in the embodiments have been selected from currently widely used general terminology; however, they may be varied according to the intent of a person skilled in the art, promotion, the emergence of new technologies, etc. If necessary, the applicant may choose any specific term. In such cases, the meaning of the term will be described in detail in the corresponding specification. Therefore, the terminology used in this invention should be defined based on its content and meaning throughout the invention, rather than simply its name.

[0027] When a part of an invention includes a certain element, it means that other components are not excluded, but may be further included unless otherwise specified.

[0028] The expression "at least one of A, B, and C" described throughout the invention may include "A alone," "B alone," "C alone," "A and B," "A and C," "B and C," or "all of A, B, and C." The advantages and features of the invention, as well as its implementation methods, will become apparent from the following detailed description of embodiments taken in conjunction with the accompanying drawings.

[0029] The shapes, dimensions, proportions, angles, and quantities disclosed in the accompanying drawings to describe various embodiments of the invention are merely examples, and the invention is therefore not limited to the details shown. Similar reference numerals refer to similar elements throughout. In the following description, detailed descriptions of related known functions or constructions will be omitted or may be briefly discussed when it is determined that such detailed descriptions would unnecessarily obscure the focus of the invention.

[0030] Where the terms "including," "having," and "comprise" are used in this specification, other parts may also exist, unless "only" is used. Singular terms may include plural forms unless otherwise specified. When interpreting an element, although not explicitly stated, the element should be interpreted as including the error region.

[0031] When describing positional relationships, such as when the positional order is described as "above," "over," "below," "below," "after," etc., situations where they do not touch may be included, unless the word "directly" is used. For example, if it is mentioned that the first element is "above" the second element, it does not mean that the first element must be or is directly above the second element in the drawing.

[0032] It will be understood that although the terms "first," "second," etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are merely used to distinguish one element from another and do not limit any order or sequence. For example, without departing from the scope of the invention, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element.

[0033] For ease of illustration, the area, length, or thickness of each element described in this specification is illustrated; however, the invention is not necessarily limited to the area and thickness of the illustrated construction.

[0034] The features of the various embodiments of the present invention can be combined or integrated with each other, either partially or entirely, and can be interoperable and driven in various ways, as will be fully understood by those skilled in the art. The various embodiments of the present invention can be implemented independently of each other, or can be implemented together in an interdependent relationship.

[0035] The terms used in this invention are selected from those generally known and adopted, which will be described later, but may be modified according to the intentions, practices, etc. of the user or operator. Therefore, the terminology used herein should be defined by the specification disclosed herein.

[0036] The transistors constituting the pixel circuits in this invention may include at least one of oxide thin-film transistors (TFTs), amorphous silicon TFTs (a-Si TFTs), and low-temperature polycrystalline silicon (LTPS) TFTs.

[0037] The embodiments described below will be based on organic light-emitting display devices. However, the embodiments of the present invention are not limited to organic light-emitting display devices, but can be applied to inorganic light-emitting display devices that include inorganic light-emitting materials. For example, the embodiments of the present invention can be applied to quantum dot display devices.

[0038] It will be understood that terms such as “first,” “second,” and “third” are used only to distinguish one element from another in each implementation, and the implementation is not limited by these terms. Therefore, the same term may refer to different elements based on the implementation.

[0039] In the following description, embodiments of the present invention will be described with reference to the accompanying drawings.

[0040] Figure 1 This is a view illustrating an example of a display device according to an embodiment of the present invention.

[0041] Display device 100 may be disposed in at least a portion of a vehicle to provide at least one type of content. For example, display device 100 may be disposed on at least a portion of a vehicle dashboard. The vehicle dashboard includes components disposed on the front surface of the vehicle's front seats (e.g., driver's seat and passenger seat). For example, input components for controlling various functions within the vehicle (e.g., air conditioning, audio system, and navigation system) may be disposed on the vehicle dashboard.

[0042] In one embodiment, the display device 100 may be mounted on the vehicle dashboard and may be used as an input unit for at least some of the various functions of the vehicle. The display device 100 may provide various vehicle-related information, such as driving information (e.g., the vehicle's current speed, remaining fuel, and driving distance) and information about vehicle components (e.g., tire damage).

[0043] In one embodiment, the display device 100 may be positioned across the driver's seat and passenger seat located in the front seats of the vehicle. Users of the display device 100 may include the vehicle driver and passengers in the vehicle's passenger seats. That is, both the vehicle's driver and passengers can use the display device 100.

[0044] In the implementation method, Figure 1 Only a portion of the display device 100 may be shown in the image. Figure 1 The display device 100 shown may correspond to a display panel among the various components included in the display device 100. As a specific example, Figure 1 The display device 100 shown can display at least a portion of the display area or non-display area of ​​a display panel. Among the components of the display device 100, besides... Figure 1 Components other than those shown may be encapsulated inside (or at least part of) the vehicle.

[0045] Figure 2 This is a functional block diagram illustrating a display device according to an embodiment of the present invention.

[0046] The display device according to one embodiment of the present invention may be an electroluminescent display device. The electroluminescent display device may be an organic light-emitting diode (OLED) display device, a quantum dot OLED display device, or an inorganic light-emitting diode (LED) display device.

[0047] Reference Figure 2 The display device may include a display panel DP, a data driver DD, a gate driver GD, a timing controller TC, and a power supply unit PU.

[0048] In this implementation, the display panel DP can generate an image to be provided to the user. For example, the display panel DP can generate and display the image to be provided to the user via a pixel area PA provided with pixel circuitry.

[0049] The data driver DD, gate driver GD, timing controller TC, and power supply unit PU can be supplied with signals for operating each pixel area PA via signal lines. These signal lines may include, for example, data lines DL, gate lines GL, and power supply lines PL, such as... Figure 3 As shown.

[0050] For example, the data driver DD can apply a data signal to each pixel area PA via the data line DL, the gate driver GD can apply a gate signal to each pixel area PA via the gate line GL, and the power supply unit PU can provide a power supply voltage to each pixel area PA via the power supply voltage supply line PL.

[0051] The timing controller TC controls the data driver DD and the gate driver GD. For example, the timing controller TC rearranges the digital video data input from the outside according to the resolution of the display panel DP, and provides the rearranged digital video data to the data driver DD.

[0052] The data driver DD can convert digital video data input from the timing controller TC into analog data voltage based on data control signals, and provide the analog data voltage to multiple data lines.

[0053] The gate driver (GD) can generate scan signals and light emission signals (or light emission control signals) based on gate control signals. The gate driver (GD) may include a scan driver and a light emission signal driver. The scan driver or scan output unit can generate scan signals in a row-sequential manner to drive at least one scan line connected to each pixel row and provide the scan signals to the scan lines. The light emission signal driver can generate light emission signals in a row-sequential manner to drive at least one light emission signal line connected to each pixel row and provide the light emission signal to the light emission signal line.

[0054] According to an embodiment, the gate driver GD can be disposed on the display panel DP using an in-panel gate driver (GIP) method. For example, the gate driver GD can be divided into multiple gate drive circuits GD, which are then disposed on at least two sides of the display panel DP.

[0055] The display area AA of the display panel DP may include multiple pixel areas PA (or pixels or pixel circuits). Multiple data lines (e.g.) Figure 3 The data line DL is connected to multiple gate lines (e.g., in the pixel area PA) in the pixel area PA. Figure 3 The gate lines (GL) intersect, and sub-pixels disposed in each intersection region may be included in a pixel region PA. The corresponding sub-pixels included in a pixel region PA may emit light of a corresponding color that is different from each other. For example, a pixel region PA may achieve blue, red, and green by using three sub-pixels, but is not limited thereto. Depending on the specific case, the pixel region PA may further include sub-pixels for further implementing a specific color (e.g., white).

[0056] In pixel region PA, the area that realizes blue can be called the blue sub-pixel region, the area that realizes red can be called the red sub-pixel region, and the area that realizes green can be called the green sub-pixel region.

[0057] In an implementation, the pixel region PA may include a plurality of sub-pixels. Each of the plurality of sub-pixels may be divided into a first lens region and a second lens region that provide corresponding viewing angles different from each other. For example, the pixel region PA may include a first lens region that provides light to a first range to form a first viewing angle and a second lens region that provides light to a second range to form a second viewing angle. The first range may correspond to a range wider than the second range.

[0058] The non-display area BZ can be disposed along the periphery of the display area. Components for driving the pixel circuitry disposed in the pixel area PA can be disposed in the non-display area BZ. For example, at least a portion of the gate driver GD can be disposed in the non-display area BZ. The non-display area BZ can be referred to as the border area.

[0059] Figure 3 An example of a pixel circuit of a display device according to an embodiment of the present invention is shown. The pixel area PA may include a plurality of sub-pixels that present different colors and a pixel circuit corresponding to each of the plurality of sub-pixels. Figure 3 An example of a pixel circuit corresponding to a sub-pixel set in pixel region PA is shown.

[0060] Reference Figure 3 The pixel circuit may include: multiple transistors DT, ST, ET1 and ET2; capacitor Cst; and multiple light-emitting elements 310 and 320.

[0061] The driving transistor DT and capacitor Cst can be connected to the switching transistor ST. The first electrode of the driving transistor DT can be connected to the power supply voltage line PL.

[0062] A switching transistor ST can be connected to the gate line GL to receive a gate signal. The switching transistor ST can be turned on or off by the gate signal. The first electrode of the switching transistor ST can be connected to the data line DL. In this case, a data signal can be provided to the gate of the drive transistor DT via the switching transistor ST in response to the switching transistor ST being turned on.

[0063] A capacitor Cst can be placed between the gate and the second electrode of the driving transistor DT. The capacitor Cst can hold the signal applied to the gate of the driving transistor DT, such as a data signal, for one frame.

[0064] According to the embodiments, the driving transistor DT, the switching transistor ST, and the capacitor Cst can be components used to drive light-emitting elements (e.g., the first light-emitting diode 310 and the second light-emitting diode 320), and can be referred to as a driving section, but are not limited to these terms.

[0065] A first light-emitting diode (or first light-emitting element) 310 can be connected to a first transistor ET1 that is turned on or off by a first light-emitting signal EM1. A second light-emitting diode 320 (or second light-emitting element) can be connected to a second transistor ET2 that is turned on or off by a second light-emitting signal EM2. The first transistor ET1 can be referred to as the first light-emitting control transistor. The second transistor ET2 can be referred to as the second light-emitting control transistor.

[0066] In this scenario, the first light-emitting element 310 or the second light-emitting element 320 can be connected to other elements of the pixel circuit, such as a driving transistor DT, depending on the mode. The mode can be specified by user input or determined when predetermined conditions are met. For example, when a predetermined first condition is met, the first light-emitting element 310 can emit light based on the provision of a first light-emitting signal EM1. When a predetermined second condition is met, the second light-emitting element 320 can emit light based on the provision of a second light-emitting signal EM2. The first condition may include predetermined conditions for driving a first mode. The second condition may include predetermined conditions for driving a second mode.

[0067] Figure 3 The multiple transistors DT, ST, ET1, and ET2 may comprise at least one of amorphous silicon, polycrystalline silicon, and oxide semiconductors such as IGZO. The first or second electrode of the transistor may be a source or a drain. For example, the first electrode may be a source, and the second electrode may be a drain. As another example, the first electrode may be a drain, and the second electrode may be a source.

[0068] Figure 4This is a view illustrating an example of a pixel array in a display device according to an embodiment of the present invention.

[0069] Reference Figure 4 Multiple horizontal pixel lines L1, L2, L3, and L4 can be set on the display panel (e.g., Figure 2 In the pixel array of the display panel (DP), multiple pixels PXL, which are horizontally adjacent to each other and jointly connected to gate lines (e.g., scan line 410, first light-emitting signal line 420 and second light-emitting signal line 425), can be arranged in each of multiple horizontal pixel lines L1, L2, L3 and L4.

[0070] In this scenario, each of the multiple horizontal pixel lines L1, L2, L3, and L4 can refer to multiple pixels PXL arranged on a line implemented by horizontally adjacent pixels PXL. The pixel array may include a first power line 430 for providing a high-potential power supply voltage ELVDD to the pixels PXL and a second power line 440 for providing a reference voltage Vref to the pixels PXL. Furthermore, the pixels PXL may be connected to a low-potential power supply voltage ELVSS (see...). Figure 5 ).

[0071] In an embodiment, the gate line may include a scan line 410 provided with a scan signal Scan, a common light emission signal line 415 provided with a common light emission signal EM0, a first light emission signal line 420 provided with a first light emission signal EM1, and a second light emission signal line 425 provided with a second light emission signal EM2.

[0072] Pixel PXL can emit light of at least one color. For example, pixel PXL can emit any one of red, green, blue, and white light. Pixels PXL can constitute a unit pixel, and the color realized in the unit pixel can be determined according to the emission ratio of red, green, blue, and white. Data line 450, scan line 410, common emission signal line 415, first emission signal line 420, second emission signal line 425, first power line 430, and second power line 440 can be connected to each pixel PXL.

[0073] Figure 5 and 6 This is a view illustrating an example of the pixel circuitry of a display device according to an embodiment of the present invention. Specifically, Figure 5 and 6 An example of a pixel circuit including a unit pixel PXL in a pixel array is shown.

[0074] Reference Figure 5The pixel circuit 500 may include twelve (12) transistors and a capacitor. At least a portion of the twelve transistors included in the pixel circuit 500 may be n-type transistors or p-type transistors. In the case of p-type transistors, the low-level voltage of each drive signal refers to the voltage used to turn on the TFT, and the high-level voltage of each drive signal may refer to the voltage used to turn off the TFT.

[0075] A low-level voltage may correspond to a predetermined voltage lower than a high-level voltage. For example, a low-level voltage may include a voltage corresponding to the range of -8V to -12V. A high-level voltage may correspond to a predetermined voltage higher than a low-level voltage. For example, a high-level voltage may include a voltage corresponding to the range of 6V to 8V. According to one embodiment, a low-level voltage may refer to a first voltage, and a high-level voltage may be referred to as a second voltage. In this case, the first voltage may be a value lower than the second voltage.

[0076] The first electrode or second electrode of the transistor described below may refer to either the source or the drain. However, using terms such as first electrode and second electrode to distinguish each electrode does not limit which electrode corresponds to which electrode. Furthermore, the first electrode may not refer to the same electrode for every electrode. For example, the first electrode of the first transistor T1 may refer to the source of the first transistor T1, and the first electrode of the sixth transistor T6 may refer to the drain of the sixth transistor T6.

[0077] The driving transistor DT can be connected to a first transistor T1 connected to a first light-emitting element ED1 and a second transistor T2 connected to a second light-emitting element ED2. For example, the first electrode of the driving transistor DT can be connected to the first transistor T1 and the second transistor T2. Depending on the connection between the gate of the first transistor T1 and the first light-emitting signal line 420, the first transistor T1 can be turned on or off by the first light-emitting signal EM1. Depending on the connection between the gate of the second transistor T2 and the second light-emitting signal line 425, the second transistor T2 can be turned on or off by the second light-emitting signal EM2. The first light-emitting signal line 420 can correspond to the gate line used to provide the first light-emitting signal EM1. The second light-emitting signal line 425 can correspond to the gate line used to provide the second light-emitting signal EM2.

[0078] Figure 5 The first light-emitting signal EM1 may correspond to the nth first light-emitting signal EM1(n) provided to the nth row in response to the pixel circuit 500 being positioned in the nth pixel row. The second light-emitting signal EM2 may correspond to the nth second light-emitting signal EM2(n) provided to the nth row in response to the pixel circuit 500 being positioned in the nth pixel row.

[0079] The driving transistor DT can be connected to at least one of the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the sixth transistor T6, the seventh transistor T7, and the capacitor C1. For example, the first electrode of the driving transistor DT can be connected to the first transistor T1, the second transistor T2, the third transistor T3, and the capacitor C1. The second electrode of the driving transistor DT can be connected to the sixth transistor T6 and the seventh transistor T7.

[0080] The first transistor T1 can be connected to at least one of the first light-emitting element ED1, the second transistor T2, the third transistor T3, the (5-1)th transistor T51, and the driving transistor DT. For example, the first electrode of the first transistor T1 can be connected to the driving transistor DT and the third transistor T3. The second electrode of the first transistor T1 can be connected to the (5-1)th transistor T51 and the first light-emitting element ED1. The gate of the first transistor T1 can be connected to the first light-emitting signal line 420 for providing the first light-emitting signal EM1. Therefore, the first transistor T1 can be turned on or off by providing the first light-emitting signal EM1. When the first transistor T1 is turned on, the voltage of the driving transistor DT can be applied to the first light-emitting element ED1 (e.g., the anode of the first light-emitting element ED1).

[0081] The second transistor T2 can be connected to at least one of the second light-emitting element ED2, the first transistor T1, the third transistor T3, the (5-2)th transistor T52, and the driving transistor DT. The first electrode of the second transistor T2 can be connected to the driving transistor DT and the third transistor T3. The second electrode of the second transistor T2 can be connected to the second light-emitting element ED2 and the (5-2)th transistor T52. The gate of the second transistor T2 can be connected to the second light-emitting signal line 425 for providing the second light-emitting signal EM2. Therefore, the second transistor T2 can be turned on or off based on the provision of the second light-emitting signal EM2. When the second transistor T2 is turned on, the voltage of the driving transistor DT can be applied to the second light-emitting element ED2 (e.g., the anode of the second light-emitting element ED2).

[0082] A first lens may be disposed on a first light-emitting element ED1. In this case, the viewing angle of the area where the first light-emitting element ED1 is disposed may have a first value or a greater value. A second lens may be disposed on a second light-emitting element ED2. In this case, the viewing angle of the area where the second light-emitting element ED2 is disposed may have a value less than the first value. The viewing angle of the area where the first light-emitting element ED1 is disposed may be wider than the viewing angle of the area where the second light-emitting element ED2 is disposed. For example, the area where the first light-emitting element ED1 is disposed may provide light to the area corresponding to the driver's seat and the passenger seat. The area where the second light-emitting element ED2 is disposed may provide light to the area corresponding to the passenger seat, excluding the driver's seat.

[0083] The third transistor T3 may be connected to at least one of the driving transistor DT, the first transistor T1, the second transistor T2, the fourth transistor T4, and the capacitor C1. For example, the first electrode of the third transistor T3 may be connected to the fourth transistor T4, the capacitor C1, and the driving transistor DT. The second electrode of the third transistor T3 may be connected to the first transistor T1, the second transistor T2, and the driving transistor DT. The gate of the third transistor T3 may be connected to a capacitor C1 for use in a configuration where... Figure 5 In the row of the pixel circuit, that is, in the nth row, the nth scan line provides the scan signal Scan. Therefore, the third transistor T3 can be provided with the nth scan signal Scan(n), and can be turned on or off by the nth scan signal Scan(n).

[0084] The fourth transistor T4 may be connected to at least one of the driving transistor DT, the third transistor T3, the (5-1)th transistor T51, the (5-2)th transistor T52, and the capacitor C1. For example, the first electrode of the fourth transistor T4 may be connected to the third transistor T3, the capacitor C1, and the driving transistor DT. The second electrode of the fourth transistor T4 may be connected to the (5-1)th transistor T51, the (5-2)th transistor T52, and the initialization voltage line 512 for providing the initialization voltage Vini. The gate of the fourth transistor T4 may be connected to the (n-1)th scan line that provides the scan signal Scan in the (n-1)th row. The fourth transistor T4 may be provided with the (n-1)th scan signal Scan(n-1) and may be turned on or off by the (n-1)th scan signal Scan(n-1).

[0085] Transistor T51 (5-1) can be connected to at least one of the first transistor T1, the fourth transistor T4, and the first light-emitting element ED1. For example, the first electrode of transistor T51 (5-1) can be connected to the fourth transistor T4. The second electrode of transistor T51 (5-1) can be connected to the first transistor T1 and the first light-emitting element ED1. The gate of transistor T51 (5-1) can be connected to the nth scan line. Therefore, transistor T51 (5-1) can be provided with the nth scan signal Scan(n) and can be turned on or off by the nth scan signal Scan(n).

[0086] Transistor T52 (5-2) can be connected to at least one of the second transistor T2, the fourth transistor T4, and the second light-emitting element ED2. For example, the first electrode of transistor T52 (5-2) can be connected to the fourth transistor T4. The second electrode of transistor T52 (5-2) can be connected to the second transistor T2 and the second light-emitting element ED2. The gate of transistor T52 (5-2) can be connected to the nth scan line. Therefore, transistor T52 (5-2) can be provided with the nth scan signal Scan(n) and can be turned on or off by the nth scan signal Scan(n).

[0087] The sixth transistor T6 can be connected to at least one of the seventh transistor T7, the eighth transistor T8, and the driving transistor DT. For example, the first electrode of the sixth transistor T6 can be connected to the seventh transistor T7 and the driving transistor DT. The second electrode of the sixth transistor T6 can be connected to the eighth transistor T8. Furthermore, the second electrode of the sixth transistor T6 can be connected to the high-potential voltage line 517 for providing the high-potential voltage ELVDD. The gate of the sixth transistor T6 can be connected to the common light-emitting signal line 415. In this case, the sixth transistor T6 can be provided with a common light-emitting signal EM0 and can be turned on or off by the common light-emitting signal EM0. Figure 5 The common light emission signal EM0 can correspond to the nth common light emission signal EM0(n) provided to the nth row in response to the case where the pixel circuit 500 is set in the nth pixel row.

[0088] In an embodiment where the sixth transistor T6 is turned on based on the provision of the nth common light-emitting signal EM0(n), a high potential voltage ELVDD can be applied to the second electrode of the driving transistor DT.

[0089] The seventh transistor T7 may be connected to at least one of the sixth transistor T6 and the drive transistor DT. For example, the first electrode of the seventh transistor T7 may be connected to the sixth transistor T6 and the drive transistor DT. The second electrode of the seventh transistor T7 may be connected to the data line 515 (e.g., for providing the data voltage Vdata). Figure 3 The data line DL). The gate of the seventh transistor T7 can be connected to the nth scan line. Therefore, the seventh transistor T7 can be provided with the nth scan signal Scan(n) and can be turned on or off by the nth scan signal Scan(n).

[0090] In the implementation, when the seventh transistor T7 is turned on based on the nth scan signal Scan(n), the data voltage Vdata can be applied to the second electrode of the driving transistor DT.

[0091] In this implementation, the eighth transistor T8 may be connected to at least one of the capacitor C1, the sixth transistor T6, the ninth transistor T9, and the tenth transistor T10. For example, the first electrode of the eighth transistor T8 may be connected to the sixth transistor T6 and the high-potential voltage line 517 for providing the high-potential voltage ELVDD. The second electrode of the eighth transistor T8 may be connected to the capacitor C1, the ninth transistor T9, and the tenth transistor T10. The gate of the eighth transistor T8 may be connected to the common light-emitting signal line 415. In this case, the eighth transistor T8 may be provided with a common light-emitting signal EM0 and may be turned on or off by the common light-emitting signal EM0.

[0092] In one embodiment, the ninth transistor T9 may be connected to at least one of the eighth transistor T8, the tenth transistor T10, and the capacitor C1. For example, the first electrode of the ninth transistor T9 may be connected to the tenth transistor T10. The first electrode of the ninth transistor T9 may be further connected to a reference voltage line 511 for providing a reference voltage Vref. The second electrode of the ninth transistor T9 may be connected to the capacitor C1, the eighth transistor T8, and the tenth transistor T10. The gate of the ninth transistor T9 may be connected to the nth scan line. Therefore, the ninth transistor T9 may be provided with the nth scan signal Scan(n) and may be turned on or off by the nth scan signal Scan(n).

[0093] In this implementation, the tenth transistor T10 may be connected to at least one of the eighth transistor T8, the ninth transistor T9, and the capacitor C1. For example, the first electrode of the tenth transistor T10 may be connected to the ninth transistor T9. The first electrode of the tenth transistor T10 may be further connected to a reference voltage line 511 for providing a reference voltage Vref. The second electrode of the tenth transistor T10 may be connected to the capacitor C1, the eighth transistor T8, and the ninth transistor T9. The tenth transistor T10 may be connected in parallel to the ninth transistor T9. The gate of the tenth transistor T10 may be connected to the (n-1)th scan line. Therefore, the tenth transistor T10 may be provided with the (n-1)th scan signal Scan(n-1) and may be turned on or off by the (n-1)th scan signal Scan(n-1).

[0094] Figure 6 It shows the basis with Figure 5 A different implementation of the pixel circuit 600. Hereinafter, it is compared with reference to... Figure 5 Repeated descriptions can be omitted. Figure 6 The pixel circuit 600 may include eight transistors and a capacitor. At least some of the eight transistors included in the pixel circuit 600 may be n-type transistors or p-type transistors.

[0095] The driving transistor DT can be connected to at least one of the first transistor T1, the second transistor T2, the third transistor T3, and the capacitor C1. The driving transistor DT can be further connected to a high-potential voltage line 517. For example, the first electrode of the driving transistor DT can be connected to the high-potential voltage line 517. The second electrode of the driving transistor DT can be connected to the first transistor T1, the second transistor T2, and the third transistor T3. The gate of the driving transistor DT can be connected to the capacitor C1.

[0096] The first transistor T1 can be connected to at least one of the second transistor T2, the third transistor T3, the (4-1)th transistor T41, the first light-emitting element ED1, and the driving transistor DT. For example, the first electrode of the first transistor T1 can be connected to the second transistor T2, the third transistor T3, and the driving transistor DT. The second electrode of the first transistor T1 can be connected to the (4-1)th transistor T41 and the first light-emitting element ED1. The gate of the first transistor T1 can be connected to the first light-emitting signal line 420, and the first transistor T1 can be turned on or off by the first light-emitting signal EM1 based on its connection to the first light-emitting signal line 420.

[0097] The second transistor T2 can be connected to at least one of the first transistor T1, the third transistor T3, the (4-2)th transistor T42, the second light-emitting element ED2, and the driving transistor DT. For example, the first electrode of the second transistor T2 can be connected to the first transistor T1, the third transistor T3, and the driving transistor DT. The second electrode of the second transistor T2 can be connected to the (4-2)th transistor T42 and the second light-emitting element ED2. The gate of the second transistor T2 can be connected to the second light-emitting signal line 425, and the second transistor T2 can be turned on or off by the second light-emitting signal EM2 based on its connection to the second light-emitting signal line 425.

[0098] The third transistor T3 may be connected to at least one of the capacitor C1, the driving transistor DT, the first transistor T1, the second transistor T2, the (4-1)th transistor T41, and the (4-2)th transistor T42. For example, the first electrode of the third transistor T3 may be connected to the capacitor C1 and the driving transistor DT. The second electrode of the third transistor T3 may be connected to the driving transistor DT, the first transistor T1, and the second transistor T2. The gate of the third transistor T3 may be connected to the (n-1)th scan line for providing a scan signal in the (n-1)th row. Therefore, the third transistor T3 may be provided with the (n-1)th scan signal Scan(n-1), and the third transistor T3 may be turned on or off by the (n-1)th scan signal Scan(n-1).

[0099] The (4-1) transistor T41 can be connected to at least one of the first transistor T1, the fifth transistor T5, and the first light-emitting element ED1. For example, the first electrode of the (4-1) transistor T41 can be connected to the fifth transistor T5. The second electrode of the (4-1) transistor T41 can be connected to the first transistor T1 and the first light-emitting element ED1. The gate of the (4-1) transistor T41 can be connected to the (n-1)th scan line. Therefore, the (4-1) transistor T41 can be provided with the (n-1)th scan signal Scan(n-1) and can be turned on or off by the (n-1)th scan signal Scan(n-1).

[0100] Transistor T42 (4-2) can be connected to at least one of the second transistor T2, the fifth transistor T5, and the second light-emitting element ED2. For example, the first electrode of transistor T42 (4-2) can be connected to the fifth transistor T5. The second electrode of transistor T42 (4-2) can be connected to the second transistor T2 and the second light-emitting element ED2. The gate of transistor T42 (4-2) can be connected to the (n-1)th scan line. Therefore, transistor T42 (4-2) can be provided with the (n-1)th scan signal Scan(n-1) and can be turned on or off by the (n-1)th scan signal Scan(n-1).

[0101] The fifth transistor T5 can be connected to at least one of the (4-1) transistor T41, the (4-2) transistor T42, the sixth transistor T6, and the capacitor C1. For example, the first electrode of the fifth transistor T5 can be connected to the sixth transistor T6 and the capacitor C1. The second electrode of the fifth transistor T5 can be connected to the (4-1) transistor T41 and the (4-2) transistor T42. The second electrode of the fifth transistor T5 can be further connected to the reference voltage line 511 for providing the reference voltage Vref. The gate of the fifth transistor T5 can be connected to the common light-emitting signal line 415 for providing the common light-emitting signal EM0. Therefore, the fifth transistor T5 can be provided with the common light-emitting signal EM0 and can be turned on or off by the common light-emitting signal EM0.

[0102] The sixth transistor T6 may be connected to at least one of the fifth transistor T5 and capacitor C1. For example, the first electrode of the sixth transistor T6 may be connected to the fifth transistor T5 and capacitor C1. The second electrode of the sixth transistor T6 may be connected to data line 515 (e.g., for providing data voltage Vdata). Figure 3 The data line DL). The gate of the sixth transistor T6 can be connected to the nth scan line that provides the scan signal Scan in the nth row. Therefore, the sixth transistor T62 can be provided with the nth scan signal Scan(n), and the sixth transistor T6 can be turned on or off by the nth scan signal Scan(n).

[0103] Figure 5 and 6 An example of a transistor being implemented as p-type is shown, but the invention is not limited thereto. According to an embodiment, in Figure 5 and / or Figure 6 At least some of the transistors included can be implemented as n-type.

[0104] Figure 7 A plane of a portion of a display device according to an embodiment of the present invention is shown. Figure 7 The plane of pixel region PA is shown when three sub-pixels are set in pixel region PA. Figure 8 It is along Figure 7 A sectional view taken by line I-I'; Figure 9 It is along Figure 7 The sectional view taken from line II-II'. (Refer to...) Figures 7 to 9 The following description is provided.

[0105] exist Figure 7 In this design, the pixel area PA may include a blue sub-pixel area BPA for achieving blue, a red sub-pixel area RPA for achieving red, and a green sub-pixel area GPA for achieving green. According to an implementation, the blue sub-pixel area BPA may correspond to a first sub-pixel, the red sub-pixel area RPA may correspond to a second sub-pixel, and the green sub-pixel area GPA may correspond to a third sub-pixel. Pixel circuits may correspond to each sub-pixel. A corresponding pixel circuit may be provided for each sub-pixel.

[0106] Pixel region PA may include first lens regions BWE, RWE, GWE and second lens regions BNE, RNE, GNE that provide different viewing angles. The second lens regions BNE, RNE, GNE of each pixel region PA can operate independently of the corresponding first lens regions BWE, RWE, GWE. For example, each pixel region PA may include a first light-emitting element 310 (e.g., ...) located on the first lens region (e.g., BWE, RWE, GWE) of the corresponding pixel region PA. Figure 3 The first light-emitting element 310) and the second light-emitting element 320 located on the second lens areas BNE, RNE, GNE of the corresponding pixel area PA (e.g. Figure 3 (the second light-emitting element 320).

[0107] The first light-emitting element 310 can emit light of a specific color. For example, the first light-emitting element 310 may include a first lower electrode 311, a first light-emitting layer 312, and a first upper electrode 313 sequentially stacked on the substrate 10. The substrate 10 may include an insulating material. The substrate 10 may include a transparent material. For example, the substrate 10 may include glass or plastic.

[0108] The first lower electrode 311 may include a conductive material. The first lower electrode 311 may include a material with high reflectivity. For example, the first lower electrode 311 may include metals such as aluminum (Al) and silver (Ag). The first lower electrode 311 may have a multilayer structure. For example, the first lower electrode 311 may have a structure in which a reflective electrode made of metal is located between transparent electrodes made of transparent conductive materials such as ITO and IZO.

[0109] The first light-emitting layer 312 can generate light with a brightness corresponding to the voltage difference between the first lower electrode 311 and the first upper electrode 313. For example, the first light-emitting layer 312 may include a light-emitting material layer (EML) having a light-emitting material. The light-emitting material may include organic materials, inorganic materials, or mixed materials.

[0110] The first light-emitting layer 312 may have a multilayer structure. For example, the first light-emitting layer 312 may further include at least one of a hole injection layer HIL, a hole transport layer HTL, an electron transport layer ETL, and an electron injection layer EIL.

[0111] The first upper electrode 313 may include a conductive material. The first upper electrode 313 may include a material different from that of the first lower electrode 311. The transmittance of the first upper electrode 313 may be higher than that of the first lower electrode 311. For example, the first upper electrode 313 may be a transparent electrode made of a transparent conductive material such as indium tin oxide (ITO) and indium zinc oxide (IZO). Therefore, in a display device according to an embodiment of the present invention, light generated by the first light-emitting layer 312 can pass through the first upper electrode 313 and be emitted.

[0112] The second light-emitting element 320 can achieve the same color as the first light-emitting element 310. The second light-emitting element 320 can have the same structure as the first light-emitting element 310. For example, the second light-emitting element 320 may include a second lower electrode 321, a second light-emitting layer 322, and a second upper electrode 323 stacked sequentially on the substrate 10.

[0113] The second lower electrode 321 may correspond to the first lower electrode 311, the second light-emitting layer 322 may correspond to the first light-emitting layer 312, and the second upper electrode 323 may correspond to the first upper electrode 313. For example, the second lower electrode 321 with respect to the second light-emitting element 320 may be formed with the same structure as the first lower electrode 311, and this may be equally applied to the second light-emitting layer 322 and the second upper electrode 323. That is, the first light-emitting element 310 and the second light-emitting element 320 may be formed with the same structure, but the present invention is not limited thereto. Depending on the specific circumstances, at least some elements of the first light-emitting element 310 and the second light-emitting element 320 may be configured differently from each other.

[0114] In one embodiment, the second light-emitting layer 322 may be separated from the first light-emitting layer 312. Therefore, in the display device according to an embodiment of the present invention, light emission due to leakage current can be avoided. Furthermore, in a display device according to one embodiment of the present invention, light can be generated only in one of the first light-emitting layer 312 and the second light-emitting layer 322, depending on user selection or predetermined conditions.

[0115] In the implementation, the first light-emitting element 310 and the second light-emitting element 320 of the pixel area PA may be located in the driving part of the corresponding pixel area PA (e.g., Figure 3 The first light-emitting element 310 and the second light-emitting element 320 of each pixel region PA are disposed on the driving unit 205 of the corresponding pixel region PA. For example, at least one insulating film (e.g., element buffer film 110, gate insulating film 120, interlayer insulating film 130, lower passivation film 140 and coating layer 150) is located on the substrate 10, and the first light-emitting element 310 and the second light-emitting element 320 of each pixel region PA can be disposed on one of the insulating films. Therefore, in a display device according to an embodiment of the present invention, the first light-emitting element 310 and the second light-emitting element 320 of each pixel region PA can be prevented from being unnecessarily connected to the driving unit 205 of the corresponding pixel region PA.

[0116] In this embodiment, the element buffer film 110, the gate insulating film 120, the interlayer insulating film 130, the lower passivation film 140, and the coating layer 150 may be stacked on the substrate 10. The element buffer film 110 may include an insulating material. For example, the element buffer film 110 may include an inorganic insulating material such as silicon oxide (SiO) or silicon nitride (SiN). The element buffer film 110 may have a multilayer structure. For example, the element buffer film 110 may have a stacked structure of a film made of silicon nitride (SiN) and a film made of silicon oxide (SiO).

[0117] In one embodiment, the component buffer film 110 may be located between the substrate 10 and the driving portion 205 of each pixel region PA. The component buffer film 110 prevents the substrate 10 from being contaminated during the process of forming the driving portion 205. For example, the upper surface of the substrate 10 facing the driving portion 205 of each pixel region PA may be covered by the component buffer film 110. The driving portion 205 of each pixel region PA may be located on the component buffer film 110.

[0118] In some embodiments, the gate insulating film 120 may include an insulating material. For example, the gate insulating film 120 may include an inorganic insulating material such as silicon oxide (SiO) or silicon nitride (SiN). The gate insulating film 120 may include a material having a high dielectric constant. For example, the gate insulating film 120 may include a high-k material such as hafnium oxide (HfO). The gate insulating film 120 may have a multilayer structure.

[0119] The gate insulating film 120 may be located on the element buffer film 110. The gate insulating film 120 may extend between the semiconductor pattern and the gate of the transistor. For example, the gates of the driving transistor DT and the switching transistor ST may be insulated from the semiconductor patterns of the driving transistor DT and the switching transistor ST via the gate insulating film 120. The gate insulating film 120 may cover the first semiconductor pattern and the second semiconductor pattern of each pixel region PA. The gates of the driving transistor DT and the switching transistor ST may be disposed on the gate insulating film 120.

[0120] Interlayer insulating film 130 may include an insulating material. For example, interlayer insulating film 130 may include an inorganic insulating material such as silicon oxide (SiO) or silicon nitride (SiN). Interlayer insulating film 130 may be located on gate insulating film 120. Interlayer insulating film 130 may extend between the gate and source of each of the driving transistor DT and the switching transistor ST, and between the gate and drain. For example, the source and drain of each of the driving transistor DT and the switching transistor ST may be insulated from the gate by interlayer insulating film 130. Interlayer insulating film 130 may cover the gate of each of the driving transistor DT and the switching transistor ST. The source and drain of each pixel region PA may be disposed on interlayer insulating film 130. Gate insulating film 120 and interlayer insulating film 130 may expose the source and drain regions of each semiconductor pattern located in each pixel region PA.

[0121] In this embodiment, the lower passivation film 140 may include an insulating material. For example, the lower passivation film 140 may include inorganic insulating materials such as silicon oxide (SiO) and silicon nitride (SiN). The lower passivation film 140 may be located on the interlayer insulating film 130. The lower passivation film 140 prevents the driving portion 205 from being damaged by external moisture and impact. The lower passivation film 140 may extend along the surfaces of the driving transistor DT and the switching transistor ST that are opposite to the substrate 10. The lower passivation film 140 may be in contact with the interlayer insulating film 130 on the outside of the driving portion 205 located in each pixel region PA.

[0122] The coating layer 150 may include an insulating material. The coating layer 150 may include a material different from the material of the lower passivation film 140. For example, the coating layer 150 may include an organic insulating material. The coating layer 150 may be located on the lower passivation film 140. The coating layer 159 may eliminate step differences caused by the driving portion 205 of each pixel region PA. For example, the upper surface of the coating layer 150 facing the substrate 10 may be a flat surface.

[0123] In one embodiment, the first transistor ET1 is electrically connected between the drain of the driving transistor DT and the first lower electrode 311 of the first light-emitting element 310. The second transistor ET2 is electrically connected between the drain of the driving transistor DT and the second lower electrode 321 of the second light-emitting element 320.

[0124] The first transistor ET1 may include a first light-emitting semiconductor pattern 211, a first light-emitting gate 213, a first light-emitting source 215, and a first light-emitting drain 217. The first transistor ET1 may have the same structure as the switching transistor ST and the driving transistor DT. For example, the first light-emitting semiconductor pattern 211 may be located between the element buffer film 110 and the gate insulating film 120, and the first light-emitting gate 213 may be located between the gate insulating film 120 and the interlayer insulating film 130. The first light-emitting source 215 and the first light-emitting drain 217 may be located between the interlayer insulating film 130 and the lower passivation film 140. The first light-emitting gate 213 may overlap with the channel region of the first light-emitting semiconductor pattern 211. The first light-emitting source 215 may be electrically connected to the source region of the first light-emitting semiconductor pattern 211. The first light-emitting drain 217 may be electrically connected to the drain region of the first light-emitting semiconductor pattern 211.

[0125] In an embodiment, the second transistor ET2 may include a second light-emitting semiconductor pattern 221, a second light-emitting gate 223, a second light-emitting source 225, and a second light-emitting drain 227. For example, the second light-emitting semiconductor pattern 221 may be located on the same layer as the first light-emitting semiconductor pattern 211, the second light-emitting gate 223 may be located on the same layer as the first light-emitting gate 213, and the second light-emitting source 225 and the second light-emitting drain 227 may be located on the same layer as the first light-emitting element 215 and the first light-emitting drain 217.

[0126] In one implementation, the first transistor ET1 may be formed simultaneously with the switching transistor ST and the driving transistor DT. The first transistor ET1 may also be formed simultaneously with the second transistor ET2.

[0127] The first light-emitting element 310 and the second light-emitting element 320 of each pixel region PA can be located on the coating layer 150 of the corresponding pixel region PA. For example, the first lower electrode 311 of the first light-emitting element 310 can be electrically connected to the first light-emitting drain 217 of the first transistor ET1 through the lower passivation film 140 and the coating layer 150, and the second lower electrode 321 of the second light-emitting element 320 can be electrically connected to the second light-emitting drain 227 of the second transistor ET2 through the lower passivation film 140 and the coating layer 150.

[0128] The second lower electrode 321 of each pixel region PA may be separated from the first lower electrode 311 of the corresponding pixel region PA. For example, a dam insulating film 160 may be disposed between the first lower electrode 311 and the second lower electrode 321 of each pixel region PA. The dam insulating film 160 may include an insulating material. For example, the dam insulating film 160 may include an organic insulating material. The dam insulating film 160 may include a material different from the material of the coating layer 150.

[0129] The second lower electrode 321 of each pixel region PA can be insulated from the first lower electrode 311 of the corresponding pixel region PA through the dam insulating film 160. For example, the dam insulating film 160 can cover the edges of the first lower electrode 311 and the second lower electrode 321 located in each pixel region PA. Therefore, in the display device, an image can be provided to the user through the first lens areas BWE, RWE, GWE of each pixel region PA provided with the first light-emitting element 310, or through the second lens areas BNE, RNE, GNE of each pixel region PA provided with the second light-emitting element 320.

[0130] The first light-emitting layer 312 and the first upper electrode 313 of the first light-emitting element 310 located in each pixel region PA can be stacked on a portion of the corresponding first lower electrode 311 exposed by the dam insulating film 160. The second light-emitting layer 322 and the second upper electrode 323 of the second light-emitting element 320 located in each pixel region PA can be stacked on a portion of the corresponding second lower electrode 321 exposed by the dam insulating film 160. For example, the dam insulating film 160 can distinguish the first light-emitting regions BE1, RE1, GE1 that emit light through the first light-emitting element 310 and the second light-emitting regions BE2, RE2, GE2 that emit light through the second light-emitting element 320 in each pixel region PA. The size of the second light-emitting regions BE2, RE2, GE2 that are distinguished in each pixel region PA can be smaller than the size of the first light-emitting regions BE1, RE1, GE1.

[0131] The second upper electrode 323 of each pixel region PA can be electrically connected to the first upper electrode 313 of the corresponding pixel region PA. For example, the voltage applied to the second upper electrode 323 of the second light-emitting element 320 located in each pixel region PA can be the same as the voltage applied to the first upper electrode 313 of the first light-emitting element 310 located in the corresponding pixel region PA. The second upper electrode 323 of each pixel region PA can be made of the same material as the first upper electrode 313 of the corresponding pixel region PA. For example, the second upper electrode 323 of each pixel region PA can be formed simultaneously with the first upper electrode 313 of the corresponding pixel region PA. The second upper electrode 323 of each pixel region PA can extend onto the insulating film 160 to directly contact the first upper electrode 313 of the corresponding pixel region PA. The brightness of the first lens regions BWE, RWE, GWE and the second lens regions BNE, RNE, GNE located in each pixel region PA can be controlled by the driving current generated in the corresponding pixel region PA.

[0132] The encapsulation component 800 may be located on the first light-emitting element 310 and the second light-emitting element 320 in each pixel region PA. The encapsulation component 800 can prevent the light-emitting elements 310 and 320 from being damaged by external moisture and impact. The encapsulation component 800 may have a multi-layer structure. For example, the encapsulation component 800 may include a first encapsulation layer 810, a second encapsulation layer 820, and a third encapsulation layer 830 stacked sequentially. The first encapsulation layer 810, the second encapsulation layer 820, and the third encapsulation layer 830 may include insulating materials. The second encapsulation layer 820 may include materials different from those of the first encapsulation layer 810 and the third encapsulation layer 830. For example, the first encapsulation layer 810 and the third encapsulation layer 830 may be inorganic encapsulation layers including inorganic insulating materials, and the second encapsulation layer 820 may be an organic encapsulation layer including organic insulating materials. Therefore, the light-emitting elements 310 and 320 of the display device can be effectively prevented from being damaged by external moisture and impact.

[0133] The first lens 510 and the second lens 520 may be located on the encapsulation member 800 of each pixel area PA.

[0134] The first lens 510 may be located on the first lens areas BWE, RWE, and GWE of each pixel area PA. For example, light generated by the first light-emitting element 310 of each pixel area PA may be emitted via the first lens 510 of the corresponding pixel area PA. The first lens 510 may have a shape in which light is not restricted in at least one direction. For example, the planar shape of the first lens 510 located in each pixel area PA may have a bar shape extending in a first direction.

[0135] In this scenario, the direction of light movement emitted from the first lens areas BWE, RWE, and GWE of the pixel area PA is not limited to the first direction. For example, content or images provided via the first lens areas BWE, RWE, and GWE of the pixel area PA can be shared with a person adjacent to the user in the first direction. The provision of content via the first lens areas BWE, RWE, and GWE is a mode of providing content within a first viewing angle range, which may be referred to as the first mode, wherein the first viewing angle range is wider than the second viewing angle range provided by the second lens areas BNE, RNE, and GNE.

[0136] The second lens 520 may be located on the second lens areas BNE, RNE, and GNE of each pixel area PA. Light generated by the second light-emitting element 320 of each pixel area PA may be emitted via the second lens 520 of the corresponding pixel area PA. The second lens 520 may restrict the direction of movement of light passing through a first direction and / or a second direction. For example, the planar shape of the second lens 520 located in the pixel area PA may be circular. In this case, the direction of movement of light emitted from the second lens areas BNE, RNE, and GNE of the pixel area PA may be limited to the first direction and the second direction. That is, the content provided by the second lens areas BNE, RNE, and GNE of the pixel area PA will not be shared by people adjacent to the user. The provision of content via the second lens areas BNE, RNE, and GNE is a mode of providing content with a second viewing angle range, which may be referred to as the second mode, wherein the second viewing angle range is narrower than the first viewing angle range provided by the first lens areas BWE, RWE, and GWE.

[0137] The first light-emitting areas BE1, RE1, and GE1 included in the first lens areas BWE, RWE, and GWE of each pixel region PA may have shapes corresponding to the first lenses 510 located on the first lens areas BWE, RWE, and GWE of the respective pixel region PA. For example, the planar shape of the first light-emitting areas BE1, RE1, and GE1 defined in the first lens areas BWE, RWE, and GWE of each pixel region PA may have a strip shape extending in a first direction. The first lenses 510 located on the first lens areas BWE, RWE, and GWE of the pixel region PA may have a larger size than the size of the first light-emitting areas BE1, RE1, and GE1 included in the first lens areas BWE, RWE, and GWE of the respective pixel region PA. Therefore, the efficiency of light emitted from the first light-emitting areas BE1, RE1, and GE1 of the pixel region PA can be improved.

[0138] The second light-emitting areas BE2, RE2, and GE2 included in the second lens areas BNE, RNE, and GNE of each pixel region PA can have shapes corresponding to the second lenses 520 located on the corresponding second lens areas BNE, RNE, and GNE of the pixel region PA. For example, the planar shape of the second light-emitting areas BE2, RE2, and GE2 included in the second lens areas BNE, RNE, and GNE of the pixel region PA can be circular. The second lenses 520 located on the second lens areas BNE, RNE, and GNE of the pixel region PA can have a larger size than the size of the second light-emitting areas BE2, RE2, and GE2 included in the corresponding second lens areas BNE, RNE, and GNE of the pixel region PA. For example, the planar shape of the second light-emitting areas BE2, RE2, and GE2 located on the second lens areas BNE, RNE, and GNE of each pixel region PA can be a circle concentric with the planar shape of the second lens 520 located on the corresponding second lens areas BNE, RNE, and GNE of the pixel region PA. In this case, the efficiency of light emitted from the second light-emitting areas BE2, RE2, and GE2 of the pixel region PA can be improved.

[0139] In an embodiment, the first lens region BWE, RWE, or GWE of the pixel region PA may include a first light-emitting region BE1, RE1, or GE1. The second lens region BNE, RNE, or GNE of the pixel region PA may include multiple second light-emitting regions BE2, RE2, or GE2.

[0140] In one embodiment, a first lens 510 may be disposed on the first lens areas BWE, RWE, and GWE of the pixel area PA. A plurality of second lenses 520 may be disposed on the second lens areas BNE, RNE, and GNE of the pixel area PA.

[0141] In one embodiment, the second light-emitting regions BE2, RE2, and GE2 included in the second lens regions BNE, RNE, and GNE of pixel region PA can be driven for each sub-pixel region. The second light-emitting regions included in a sub-pixel region (e.g., the second light-emitting region BE2, the second light-emitting region RE2, or the second light-emitting region GE2) can be driven simultaneously.

[0142] In this embodiment, a second lower electrode 321 may be located on the second lens regions BNE, RNE, and GNE of each pixel region PA. A dam insulating film 160 may be located between the second lower electrode 321 and the second light-emitting layer 322, between the second light-emitting regions BE2, RE2, and GE2. The dam insulating film 160 may be located between the second lower electrode 321 and the second light-emitting layer 322, between the second light-emitting regions BE2, RE2, and / or between the second light-emitting regions GE2. The second light-emitting layer 322 may be separated from the second lower electrode 321 by the dam insulating film 160 located between the second light-emitting regions BE2, RE2, and GE2 of the second lens regions BNE, RNE, and GNE. In this case, the luminous efficiency of the second light-emitting regions BE2, RE2, and GE2 can be improved.

[0143] In the implementation, the size of each of the second light-emitting areas BE2, RE2, and GE2 located in the second lens areas BNE, RNE, and GNE of pixel area PA can be specified as a specific value. For example, the sizes of the second light-emitting areas BE2, RE2, and GE2 located in the second lens areas BNE, RNE, and GNE of pixel area PA can be made to be identical to each other. The second light-emitting areas BE2, RE2, and GE2 located in the second lens areas BNE, RNE, and GNE of pixel area PA can have the same size as the sizes of the second light-emitting areas BE2, RE2, and GE2 included in the second lens areas BNE, RNE, and GNE of adjacent pixel areas PA.

[0144] In this implementation, the number of second light-emitting regions may differ for each of the sub-pixel regions RPA, GPA, and BPA. For example, the number of second light-emitting regions BE2 defined in the second lens region BNE of the blue sub-pixel region BPA may be greater than the number of second light-emitting regions RE2 defined in the second lens region RNE of the red sub-pixel region RPA. Similarly, the number of second light-emitting regions RE2 defined in the second lens region RNE of the red sub-pixel region RPA may be greater than the number of second light-emitting regions GE2 defined in the second lens region GNE of the green sub-pixel region GPA. In this case, by adjusting the number of second light-emitting regions BE2, RE2, and GE2 defined in the second lens regions BNE, RNE, and GNE of each pixel region PA, the efficiency deviation of the second light-emitting elements 320 located in the second lens regions BNE, RNE, and GNE of the pixel region can be compensated.

[0145] In an implementation, the sizes of the first light-emitting areas BE1, RE1, and GE1 may differ for each of the sub-pixel regions RPA, GPA, and BPA. For example, the first light-emitting area BE1 of the blue sub-pixel region BPA may have a different size than the first light-emitting area RE1 of the red sub-pixel region RPA, and may also have a different size than the first light-emitting area GE1 of the green sub-pixel region GPA. The size of the first light-emitting area BE1 of the blue sub-pixel region BPA may be larger than the size of the first light-emitting area RE1 of the red sub-pixel region RPA. The size of the first light-emitting area RE1 of the red sub-pixel region RPA may be larger than the size of the first light-emitting area GE1 of the green sub-pixel region GPA. Therefore, in a display device according to an embodiment of the present invention, the efficiency deviation of the first light-emitting elements 310 located on the first lens regions BWE, RWE, and GWE of each pixel region PA can be compensated by the size of the first light-emitting areas BE1, RE1, and GE1 defined in the first lens regions BWE, RWE, and GWE of each pixel region PA.

[0146] In an embodiment, a lens protective film 600 may be located on the first lens 510 and the second lens 520 of the pixel region PA. The lens protective film 600 may include an insulating material. For example, the lens protective film 600 may include an organic insulating material. The refractive index of the lens protective film 600 may be less than the refractive index of the first lens 510 and the second lens 520 located in each pixel region PA. Therefore, in the display device according to an embodiment of the present invention, due to the difference in refractive index with the lens protective film 600, light passing through the first lens 510 and the second lens 520 of each pixel region PA will not be reflected in the direction toward the substrate 10.

[0147] Figure 10 and 11 This is a conceptual diagram illustrating the gate driving circuit of a display device according to an embodiment of the present invention.

[0148] A gate driving circuit according to one embodiment of the present invention may include a scan driver and a light-emitting driver. The scan driver may generate scan signals (e.g., an nth scan signal Scan(n) and an (n-1)th scan signal Scan(n-1)). The light-emitting driver may generate light-emitting signals (e.g., a common light-emitting signal EM0, a first light-emitting signal EM1, and a second light-emitting signal EM2). The gate driving circuit may control the driving of a plurality of pixel circuits based on the provision of the first light-emitting signal EM1 and the second light-emitting signal EM2 to each of the plurality of pixel circuits.

[0149] Figure 10 A functional block diagram of a light-emitting driver included in a gate driving circuit according to an embodiment of the present invention is shown. (Refer to...) Figure 10The light-emitting driver 1000 can be implemented as a gate shift register including multiple stages (e.g., a first stage ST1, a second stage ST2, a third stage ST3, and a fourth stage ST4). According to an embodiment, the stages can be formed in a gate-in-panel (GIP) manner disposed inside the panel, but it is not limited thereto; the stages can be configured to be distinct from the panel.

[0150] Multiple stages ST1 to ST4 can output light-emitting signals (e.g., a first light-emitting signal EM1, a second light-emitting signal EM2, and a common light-emitting signal EM0) when their operation is activated sequentially. In an embodiment, the first stage ST1 may refer to the stage located on top of the light-emitting driver. After the first stage ST1, the second to fourth stages ST2 to ST4 can be sequentially arranged.

[0151] In this implementation, the operation of the first stage ST1 can be activated based on an external start signal VST, and the second stage ST2 and other stages (e.g., the third stage ST3 and the fourth stage ST4) can be activated based on any one of the emission signals EM1, EM2, and EM0 of the preceding stage. The emission signal of the preceding stage is an internal start signal and becomes a carry signal CRY. In this case, the term "preceding stage" can refer to the stage located above the reference stage that generates an emission signal whose phase is earlier than the phase of the emission signal output from the reference stage.

[0152] Reference Figure 10 In order to output the light emission signal, multiple stages ST1 to ST4 receive an external start signal EVST, a first clock signal ECLK1, and a second clock signal ECLK2 from a level shifter (not shown). The external start signal EVST, the first clock signal ECLK1, and the second clock signal ECLK2 can swing between a gate high voltage VGH and a gate low voltage VGL.

[0153] An external start signal EVST can be input to the first stage ST1, and a first clock signal ECLK1 and a second clock signal ECLK2 can be input to all stages ST1 through ST4. The first clock signal ECLK1 and the second clock signal ECLK2 can have opposite phases. According to an embodiment, for proper operation of stages connected in a cascade manner, the input positions of the first clock signal ECLK1 and the second clock signal ECLK2 can be set to be opposite in odd-numbered stages and even-numbered stages. For example, when the first clock signal ECLK1 is input to the first terminal and the second clock signal ECLK2 is input to the second terminal at an odd-numbered stage, the first clock signal ECLK1 can be input to the second terminal and the second clock signal ECLK2 can be input to the first terminal at an even-numbered stage.

[0154] In this implementation, each of stages ST1 through ST4 can activate the operation of node Q based on a start signal applied to the start terminal in each frame. In this case, node activation means that a low gate voltage VGL or a corresponding voltage is applied to the node. Node inactivation means that a high gate voltage VGH or a corresponding voltage is applied to the node. The low gate voltage VGL can refer to the gate on-state voltage, and the high gate voltage VGH can refer to the gate off-state voltage.

[0155] According to an embodiment, as shown in the figure, each of stages ST1 to ST4 may be provided with a gate high potential voltage VGH and a gate low potential voltage VGL from an external power supply (not shown). The gate high potential voltage VGH may be preset to a value between 20V and 30V, and the gate low potential voltage VGL may be preset to a value between -10V and 0V, but the invention is not limited thereto.

[0156] In one embodiment, the gate low potential voltage VGL can be provided via a first voltage line providing a first value of voltage. According to one embodiment, the first voltage line may be referred to as a low potential line. The gate high potential voltage VGH can be provided via a second voltage line providing a second value of voltage higher than the first value. According to one embodiment, the second voltage line may be referred to as a high potential line.

[0157] Figure 11 This is a simplified circuit diagram illustrating the gate drive circuit according to an embodiment of the present invention. More specifically, Figure 11 This diagram illustrates a stage (e.g., in a light-emitting driver within a gate drive circuit) that is included. Figure 10 The circuit diagram of the first stage ST1).

[0158] Reference Figure 11 The gate drive circuit may include a node controller 1101, a first mode controller 1111, and a second mode controller 1112. The first mode controller 1111 may include a first pull-down transistor PD1, a first pull-up transistor PU1, and mode control transistors M11 and M12. The second mode controller 1112 may include a second pull-down transistor PD2, a second pull-up transistor PU2, and mode control transistors M21 and M22.

[0159] In some implementations, the internal circuitry of node controller 1101 may be configured to include a plurality of transistors. The internal circuitry of node controller 1101 may include Q nodes, QB nodes, and set nodes (or start nodes). In some cases, the internal circuitry of node controller 1101 may further include reset nodes for inputting reset signals, input nodes for inputting various voltages (e.g., drive voltages), etc.

[0160] In one implementation, node controller 1101 may receive a gate start signal VST indicating the start of gate driving for a corresponding gate driver. The node to which the gate start signal VST is applied may be referred to as a set node. In this case, depending on the number of phases of the clock signal, the gate start signal VST may include an external start signal (e.g., Figure 10 The external start signal (EVST) or a signal output from a component of the gate drive circuit (e.g., in the preceding stage) before the current gate line (e.g., a carry signal). Figure 10 The carry signal (CRY).

[0161] In this implementation, the node controller 1101 may receive a first clock signal ECLK1 and a second clock signal ECLK2.

[0162] In one implementation, the Q node of the node controller 1101 may be electrically connected to the gate node of a pull-down transistor (e.g., a first pull-down transistor PD1 and a second pull-down transistor PD2). The QB node of the node controller 1101 may be electrically connected to the gate node of a pull-up transistor (e.g., a first pull-up transistor PU1 and a second pull-up transistor PU2). The Q node and QB node may be repeatedly charged and discharged.

[0163] In one implementation, the (1-1) mode control transistor M11 may be disposed between the Q node and the first pull-down transistor PD1. For example, the first electrode of the (1-1) mode control transistor M11 may be connected to the Q node, and the second electrode of the (1-1) mode control transistor M11 may be connected to the gate of the first pull-down transistor PD1. The gate of the (1-1) mode control transistor M11 may be connected to the first mode signal line 1110, wherein a first mode signal MOD1 that controls the operation to the first mode is provided to the first mode signal line 1110. The (1-1) mode control transistor M11 may be turned on or off based on the provision of the first mode signal MOD1.

[0164] The (2-1) mode control transistor M21 can be disposed between the Q node and the second pull-down transistor PD2. For example, the first electrode of the (2-1) mode control transistor M21 can be connected to the Q node, and the second electrode of the (2-1) mode control transistor M21 can be connected to the gate of the second pull-down transistor PD2. The gate of the (2-1) mode control transistor M21 can be connected to the second mode signal line 1120, wherein a second mode signal MOD2 that controls the operation to the second mode is provided to the second mode signal line 1120. The (2-1) mode control transistor M21 can be turned on or off based on the provision of the second mode signal MOD2.

[0165] The mode control transistor M12 (1-2) can be disposed between the QB node and the first pull-up transistor PU1. For example, the first electrode of the mode control transistor M12 (1-2) can be connected to the QB node, and the second electrode of the mode control transistor M12 (1-2) can be connected to the gate of the first pull-up transistor PU1. The gate of the mode control transistor M12 (1-2) can be connected to the first mode signal line 1110, wherein a first mode signal MOD1 that controls the operation to the first mode is provided to the first mode signal line 1110. The mode control transistor M12 (1-2) can be turned on or off based on the provision of the first mode signal MOD1.

[0166] The (2-2) mode control transistor M22 can be disposed between the QB node and the second pull-up transistor PU2. For example, the first electrode of the (2-2) mode control transistor M22 can be connected to the QB node, and the second electrode of the (2-2) mode control transistor M22 can be connected to the gate of the second pull-up transistor PU2. The gate of the (2-2) mode control transistor M22 can be connected to the second mode signal line 1120, wherein a second mode signal MOD2 that controls the operation to the second mode is provided to the second mode signal line 1120. The (2-2) mode control transistor M22 can be turned on or off based on the provision of the second mode signal MOD2.

[0167] In this case, the first mode may refer to a first light-emitting element (e.g., a light-emitting element that emits light based on the provision of a first light-emitting signal EM1). Figure 5 Or the mode in which the viewing angle of the first light-emitting element ED1 (or 6) is greater than or equal to the first value. (Refer to...) Figure 8 The described first lens 510 may be disposed on a first light-emitting element (which emits light in a first mode) to provide light with a wider viewing angle than the second mode, which will be described later. The second mode may refer to a second light-emitting element (e.g., emitting light based on the provision of the first light-emitting signal EM1) that emits light. Figure 5 Or the second light-emitting element ED2 of 6 has a viewing angle smaller than the first value. (Refer to...) Figure 9 The described second lens 520 may be disposed on the second light-emitting element (which emits light in the second mode) to provide light with a narrower angle of view than the second mode.

[0168] In this implementation, the first pull-down transistor PD1 and the second pull-down transistor PD2 may be connected to a first voltage line (or a low-potential line). For example, the first electrode of each of the first pull-down transistor PD1 and the second pull-down transistor PD2 may be connected to the first voltage line (or a low-potential line). The first pull-up transistor PU1 and the second pull-up transistor PU2 may be connected to a second voltage line (or a high-potential line). For example, the first electrode of each of the first pull-up transistor PU1 and the second pull-up transistor PU2 may be connected to the second voltage line (or a high-potential line).

[0169] According to the embodiment, when the first pull-down transistor PD1 is turned on, a gate low potential voltage VGL can be provided as the first light-emitting signal EM1. When the first pull-up transistor PU1 is turned on, a gate high potential voltage VGH can be provided as the first light-emitting signal EM1. When the second pull-down transistor PD2 is turned on, a gate low potential voltage VGL can be provided as the second light-emitting signal EM2. When the second pull-up transistor PU2 is turned on, a gate high potential voltage VGH can be provided as the second light-emitting signal EM2. In this case, the gate high potential voltage VGH can be a voltage with a higher voltage value than the gate low potential voltage VGL. The values ​​of each of the gate high potential voltage VGH and the gate low potential voltage VGL can be predetermined.

[0170] According to the implementation method, at least one of the mode control transistors M11, M12, M21, and M22 may be omitted. (See reference...) Figure 12 and / or Figure 13 A more detailed example related to this is described below. See also... Figure 14 and / or Figure 15 Description as follows Figure 11 A more detailed example is shown, including mode control transistors M11, M12, M21, and M22.

[0171] In one embodiment, the transistors included in the gate drive circuit may be p-type. In this case, the transistors are turned on when a low-level voltage is applied to each transistor, and are turned off when a high-level voltage is applied to each transistor. Hereinafter, all transistors included in the gate drive circuit described in this invention may be p-type, but the embodiment is not limited thereto, and n-type transistors may also be used depending on design changes.

[0172] Furthermore, the terms "first electrode" and "second electrode" are used to distinguish the electrodes of a transistor included in a gate drive circuit. For each transistor, the first electrode and / or the second electrode may be distinguished to be interpreted as a source or a drain, but the invention is not limited thereto.

[0173] Figures 12 to 16 This is a view illustrating an example of a gate driving circuit of a display device according to an embodiment of the present invention. More specifically, Figures 12 to 16 It shows Figure 11 Various embodiments of the gate drive circuit are described below. Descriptions that are repeated in the preceding descriptions may be omitted.

[0174] Figure 12 This is one embodiment of the gate driving circuit of a display device according to an embodiment of the present invention. (Refer to...) Figure 12 The gate drive circuit may include a node controller 1201 (e.g., Figure 11 Node controller 1101), first mode controller 1211 (e.g. Figure 11 First mode controller 1111), second mode controller 1212 (e.g. Figure 11 At least one of the second mode controller 1112 and the common signal controller 1213.

[0175] In this implementation, node controller 1201 may receive various control signals. For example, node controller 1201 may receive clock signals ECLK1 and ECLK2, a gate start signal VST, and a gate high voltage VGH. Node controller 1201 may control elements connected to node controller 1201 (e.g., first mode controller 1211 and second mode controller 1212) based on the applied control signals. Node controller 1201 may control the potential of Q nodes and QB nodes by using at least one of the gate start signal VST, the first clock signal ECLK1, and the second clock signal ECLK2.

[0176] In one implementation, the first electrode of the first transistor T1 may receive a gate start signal VST. The first transistor T1 may be turned on or off based on the provision of a second clock signal ECLK2.

[0177] The first electrode of the second transistor T2 can be connected to the second electrode of the first transistor T1. The second transistor T2 can receive the gate start signal VST in response to the conduction of the first transistor T1. The second transistor T2 can be turned on or off based on the provision of the first clock signal ECLK1.

[0178] The first electrode of the third transistor T3 can be connected to the second electrode of the second transistor T2. The third transistor T3 can receive the gate start signal VST via the second transistor T2 in response to the second transistor T2 being turned on. The second electrode of the third transistor T3 can be connected to a high-potential line used to provide a gate high-potential voltage VGH.

[0179] The fourth transistor T4 can be turned on or off based on the provision of the second clock signal ECLK2. The first electrode of the fourth transistor T4 can be connected to a low-potential line for providing a low-potential voltage VGL. The second electrode of the fourth transistor T4 can be connected to the gate of the third transistor T3. When the fourth transistor T4 is turned on, the gate low-potential voltage VGL can be provided to the gate of the third transistor T3.

[0180] The gate of the fifth transistor T5 can be connected to the first transistor T1, the second transistor T2, and the tenth transistor T10. The gate of the fifth transistor T5 can be provided with a gate start signal VST in response to the conduction of the first transistor T1. The first electrode of the fifth transistor T5 can be connected to the ninth transistor T9 and the common signal controller 1213. The second electrode of the fifth transistor T5 can be connected to a high-potential line for providing a high-potential voltage VGH.

[0181] The first electrode of the eighth transistor T8 can be connected to the line used to provide the first clock signal ECLK1. The second electrode of the eighth transistor T8 can be connected to the ninth transistor T9 and the node control capacitor CQ'. The gate of the eighth transistor T8 can be connected to the second electrode of the tenth transistor T10. The eighth transistor T8 can receive the second clock signal ECLK2 in response to the conduction of the tenth transistor T10.

[0182] The first electrode of the ninth transistor T9 can be connected to the second electrode of the eighth transistor T8 and the node control capacitor CQ'. The second electrode of the ninth transistor T9 can be connected to the fifth transistor T5 and the common signal controller 1213. The gate of the ninth transistor T9 can be turned on or off based on the provision of the first clock signal ECLK1.

[0183] The first electrode of the tenth transistor T10 may be connected to the line used to provide the second clock signal ECLK2 and the fourth transistor T4. The second electrode of the tenth transistor T10 may be connected to the third transistor T3, the fourth transistor T4, the eighth transistor T8, and the node control capacitor CQ'. According to an embodiment, the tenth transistor T10 may include dual gates, but is not limited thereto.

[0184] In this embodiment, the node connected to the second electrode of the first transistor T1, the first electrode of the second transistor T2, the gate of the fifth transistor T5, and the gate of the tenth transistor T10 can be referred to as a Q node (or the first node). The Q node can be connected to the first mode controller 1211, the second mode controller 1212, and the common signal controller 1213. The node connected to the first electrode of the fifth transistor T5 and the second electrode of the ninth transistor T9 can be referred to as a QB node or the second node. The QB node can be connected to the first mode controller 1211, the second mode controller 1212, and the common signal controller 1213.

[0185] Reference Figure 12 The Q node can be connected to the fourteenth transistor T14 of the first node controller 1211, the twentieth transistor T20 of the second node controller 1212, and the sixth transistor T6 of the common signal controller 1213. In one embodiment, the second capacitor CQ of the common signal controller 1213 can be further connected to the Q node.

[0186] The twelfth transistor T12, the sixteenth transistor T16, and the first-mode pull-up capacitor CQSB of the first-mode controller 1211 can be connected to the QB node. The twenty-second transistor T22, the eighteenth transistor T18, and the second-mode pull-up capacitor CQPB of the second-mode controller 1212 can be connected to the QB node. The seventh transistor T7 and the third capacitor CQB of the common signal controller 1213 can be connected to the QB node.

[0187] In one implementation, the first mode controller 1211 may provide a first mode signal MOD1. In response to receiving the first mode signal MOD1, the first mode controller 1211 may output a first light emission signal EM1, which is at least one of a potential based on the Q node and a potential based on the QB node, to the first output line 1221. The fourteenth transistor T14 may be turned on or off based on the provision of the first mode signal MOD1. The gate of the fourteenth transistor T14 may be connected to the first mode signal line 1210 for providing the first mode signal MOD1. The fourteenth transistor T14 may correspond to... Figure 11 The (1-1) mode control transistor M11. In one embodiment, the first mode signal MOD1 may include a signal that causes the display device to operate in the first mode. In this case, the first mode controller 1211 can control the display device to operate in the first mode.

[0188] In the implementation, the eleventh transistor T11 of the first mode controller 1211 may correspond to Figure 11 The first pull-down transistor PD1. The first electrode of the eleventh transistor T11 can be connected to a low-potential line for providing the gate low-potential voltage VGL. When the eleventh transistor T11 is turned on, the gate low-potential voltage VGL can be provided to the pixel circuit (e.g., as the first light-emitting signal EM1) via the second electrode of the eleventh transistor T11. Figure 5 or Figure 6 (pixel circuit).

[0189] In one embodiment, the first mode controller 1211 can output a first emission signal EM1 to the first output line 1221 based on at least one of the potentials of the Q node and the QB node. The first output line 1221 can be connected to a pixel circuit, therefore, the first emission signal EM1 can be provided to the pixel circuit. According to one embodiment, the transistor in the pixel circuit for receiving the first emission signal EM1 is, for example... Figure 6 The first transistor T1 can be called the first light-emitting control transistor, but is not limited to this.

[0190] For example, the twelfth transistor T12 of the first mode controller 1211 can correspond to Figure 11The first pull-up transistor is PU1. The gate of the twelfth transistor T12 can be connected to the QB node. The twelfth transistor T12 can be turned on or off based on a signal provided via the QB node (e.g., a first clock signal ECLK1). The first electrode of the twelfth transistor T12 can be connected to a high-potential line for providing a gate high-potential voltage VGH. When the twelfth transistor T12 is turned on, the gate high-potential voltage VGH can be provided to the pixel circuit as a first light-emitting signal EM1 via the second electrode of the twelfth transistor T12.

[0191] In one embodiment, the eleventh transistor T11 may be connected between a first voltage line for providing a first value of voltage and a first output line 1221. In this case, the first voltage line may correspond to a low potential line, and the first value may correspond to a gate low potential voltage VGL. The twelfth transistor T12 may be controlled by the potential of the QB node and may be connected between the first output line 1221 and a second voltage line for providing a second value of voltage higher than the first value. The second voltage line may correspond to a high potential line, and the second value may correspond to a gate high potential voltage VGH.

[0192] In one implementation, the gate of the eleventh transistor T11 may be connected to the first-mode pull-up capacitor CQS and the fifteenth transistor T15. The first-mode controller 1211 may include elements related to the circuit's reset. For example, the first-mode controller 1211 may include the thirteenth transistor T13, the fifteenth transistor T15, and the sixteenth transistor T16, which receive the reset signal EQRST. The thirteenth transistor T13, the fifteenth transistor T15, and the sixteenth transistor T16 may be turned on or off based on the reset signal EQRST.

[0193] According to the implementation, the thirteenth transistor T13, which receives the reset signal EQRST, may be referred to as the first reset transistor. The thirteenth transistor T13 may be controlled by the reset signal EQRST. The thirteenth transistor T13 may initialize the first output line 1221 based on the control of the reset signal EQRST. The reset signal EQRST may be implemented as a specific voltage value, and in some cases may be referred to as the reset voltage, but is not limited thereto.

[0194] In one implementation, the second mode controller 1212 may provide a second mode signal MOD2. In response to receiving the second mode signal MOD2, the second mode controller 1212 may output a second light emission signal EM2 based on at least one of the potentials of the Q node and the QB node to the second output line 1222. The twentieth transistor T20 may be turned on or off based on the provision of the second mode signal MOD2. The gate of the twentieth transistor T20 may be connected to the second mode signal line 1220 for providing the second mode signal MOD2. The twentieth transistor T20 may correspond to... Figure 11The (2-1) mode control transistor M21. In one embodiment, the second mode signal MOD2 may include a signal that causes the display device to operate in the second mode. In this case, the second mode controller 1212 can control the display device to operate in the second mode.

[0195] In the implementation, the seventeenth transistor T17 of the second mode controller 1212 may correspond to Figure 11 The second pull-down transistor PD2. The first electrode of the seventeenth transistor T17 can be connected to a low-potential line for providing the gate low-potential voltage VGL. When the seventeenth transistor T17 is turned on, the gate low-potential voltage VGL can be provided to the pixel circuit (e.g., as a second light-emitting signal EM2) via the second electrode of the seventeenth transistor T17. Figure 5 or Figure 6 (pixel circuit).

[0196] In the implementation, the eighteenth transistor T18 of the second mode controller 1212 may correspond to Figure 11 The second pull-up transistor PU2. The gate of the eighteenth transistor T18 can be connected to the QB node. The eighteenth transistor T18 can be turned on or off based on a signal provided via the QB node (e.g., the first clock signal ECLK1). The first electrode of the eighteenth transistor T18 can be connected to a high-potential line for providing a gate high-potential voltage VGH. When the eighteenth transistor T18 is turned on, the gate high-potential voltage VGH can be provided to the pixel circuit as a second light-emitting signal EM2 via the second electrode of the eighteenth transistor T18.

[0197] In one embodiment, the second mode controller 1212 can output a second light emission signal EM2 to the second output line 1222 based on at least one of the potentials of the Q node and the QB node. The second output line 1222 can be connected to a pixel circuit, thus the second light emission signal EM2 can be provided to the pixel circuit. According to one embodiment, the transistor in the pixel circuit for receiving the second light emission signal EM2 is, for example... Figure 6 The second transistor T2 can be called the second light-emitting control transistor, but is not limited to this.

[0198] In one implementation, the gate of the seventeenth transistor T17 may be connected to the second-mode pull-up capacitor CQP and the twenty-first transistor T21. The second-mode controller 1212 may include elements related to the circuit's reset. For example, the second-mode controller 1212 may include the twenty-first transistor T21, the twenty-second transistor T22, and the nineteenth transistor T19, which receive the reset signal EQRST. The twenty-first transistor T21, the twenty-second transistor T22, and the nineteenth transistor T19 may be turned on or off based on the reset signal EQRST.

[0199] According to the implementation method, the nineteenth transistor T19, which receives the reset signal EQRST, can be referred to as the second reset transistor. The nineteenth transistor T19 can be controlled by the reset signal EQRST. The nineteenth transistor T19 can initialize the second output line 1222 based on the control of the reset signal EQRST.

[0200] In this implementation, the common signal controller 1213 may include a sixth transistor T6, a seventh transistor T7, and a reset transistor TRST. The sixth transistor T6 can be used as a pull-down transistor, and the seventh transistor T7 can be used as a pull-up transistor. The reset transistor TRST can be used to reset the common signal controller 1213. The common signal controller 1213 can output a common light emission signal EMO to the third output line 1223 based on the potentials of the Q node and the QB node.

[0201] In one implementation, the first electrode of the sixth transistor T6 may be connected to a low-potential line for providing a gate low-potential voltage VGL. The sixth transistor T6 may be turned on or off based on a signal provided to the Q node. When the sixth transistor T6 is turned on, the gate low-potential voltage VGL may be provided to the pixel circuit as a common light-emitting signal EMO via the second electrode of the sixth transistor T6.

[0202] In this implementation, the first electrode of the seventh transistor T7 may be connected to a high-potential line for providing a gate high-potential voltage VGH. The seventh transistor T7 may be turned on or off based on a signal provided to the QB node. When the seventh transistor T7 is turned on, the gate high-potential voltage VGH may be provided to the pixel circuit as a common light-emitting signal EMO via the second electrode of the seventh transistor T7.

[0203] In this implementation, a common light emission signal EM0 can be provided at a predetermined period. For example, regardless of whether a first mode signal MOD1 or a second mode signal MOD2 is provided, the common light emission signal EM0 can be provided to the pixel circuit at a constant time interval.

[0204] In this implementation, the common light-emitting signal EM0 can be output to the third output line 1223. The third output line 1223 can be connected to the pixel circuit, so the common light-emitting signal EM0 can be provided to the pixel circuit.

[0205] Figure 13 This is another embodiment of the gate driving circuit of the display device according to the present invention. Hereinafter, reference will be made to... Figure 12 The implementation method is described in Figure 13 The text can be omitted, and the description will be given based on the additional settings.

[0206] Reference Figure 13The common signal controller 1313 may include a first common control transistor T30. The first common control transistor T30 may be connected to the gate of a sixth transistor T6. The first electrode of the first common control transistor T30 may be connected to the second electrode of the first transistor T1, the first electrode of the second transistor T2, and the gate of the tenth transistor T10. The second electrode of the first common control transistor T30 may be connected to the second capacitor CQ and the gate of the sixth transistor T6.

[0207] In this implementation, the first common control transistor T30 can control the provision of the common light-emitting signal EMO. For example, the gate of the first common control transistor T30 can receive the common control signal VGL_C. The first common control transistor T30 can be turned on or off based on the receipt of the common control signal VGL_C. For example, the first common control transistor T30 can be turned on when the common control signal VGL_C is low and turned off when the common control signal VGL_C is high. A signal can be provided to the gate of the sixth transistor T6 based on the conduction of the first common control transistor T30, and the sixth transistor T6 can be turned on or off based on the signal provided.

[0208] Figure 14 This is another embodiment of the gate driving circuit of the display device according to the present invention. Hereinafter, reference will be made to... Figure 12 and 13 The implementation method is described in Figure 14 The text can be omitted, and the description will be given based on the additional settings.

[0209] Reference Figure 14 The first mode controller 1411 may further include a twenty-third transistor T23. The twenty-third transistor T23 may be turned on or off based on the availability of the first mode signal MOD1. For example, the twenty-third transistor T23 may be turned off when the first mode signal MOD1 is high and may be turned on when the first mode signal MOD1 is low.

[0210] The on / off state of the twelfth transistor T12 can be controlled based on the operation of the twenty-third transistor T23. For example, a signal applied to the first electrode of the twenty-third transistor T23 can be provided to the gate of the twelfth transistor T12 in response to the on state of the twenty-third transistor T23. Therefore, the on / off state of the twelfth transistor T12 can be controlled.

[0211] In one implementation, the second mode controller 1412 may further include a twenty-fourth transistor T24. The twenty-fourth transistor T24 may be turned on or off based on the availability of the second mode signal MOD2. For example, the twenty-fourth transistor T24 may be turned off when the second mode signal MOD2 is high and may be turned on when the second mode signal MOD2 is low.

[0212] The on / off state of the eighteenth transistor T18 can be controlled based on the operation of the twenty-fourth transistor T24. For example, a signal applied to the first electrode of the twenty-fourth transistor T24 can be provided to the gate of the eighteenth transistor T18 in response to the on state of the twenty-fourth transistor T24. Therefore, the on / off state of the eighteenth transistor T18 can be controlled.

[0213] Figure 15 This is another embodiment of the gate driving circuit of the display device according to the present invention. Hereinafter, reference will be made to... Figures 12 to 14 The implementation method is described in Figure 15 The text can be omitted, and the description will be given based on the additional settings.

[0214] Reference Figure 15 The common signal controller 1513 may include a first common control transistor T30 and a second common control transistor T31. The first common control transistor T30 has been referenced... Figure 13 A description has been provided, therefore its detailed description will be omitted.

[0215] In this embodiment, the second common control transistor T31 can be connected to the gate of the seventh transistor T7. The first electrode of the second common control transistor T31 can be connected to the first electrode of the fifth transistor T5 and the second electrode of the ninth transistor T9. The second electrode of the second common control transistor T31 can be connected to the third capacitor CQB and the gate of the seventh transistor T7.

[0216] In this implementation, the second common control transistor T31 can control the provision of the common light-emitting signal EMO. For example, the gate of the second common control transistor T31 can receive the common control signal VGL_C. The second common control transistor T31 can be turned on or off based on the receipt of the common control signal VGL_C. For example, the second common control transistor T31 can be turned on when the common control signal VGL_C is low and can be turned off when the common control signal VGL_C is high. A signal can be provided to the gate of the seventh transistor T7 based on the conduction of the second common control transistor T31, and the seventh transistor T7 can be turned on or off based on the signal provided.

[0217] Figure 16 This is another embodiment of the gate driving circuit of the display device according to the present invention. Hereinafter, reference will be made to... Figures 12 to 15 The implementation method is described in Figure 16 The text can be omitted, and the description will be given based on the additional settings.

[0218] Reference Figure 16 The first mode controller 1611 can correspond to Figure 14The first mode controller 1411. The second mode controller 1612 can correspond to Figure 14 The second mode controller 1412. The common signal controller 1613 can correspond to Figure 12 Common signal controller 1213. For example, common signal controller 1613 may refer to Figure 13 The first common control transistor T30 of the common signal controller 1313 is omitted.

[0219] In one implementation, the first mode controller 1611 may further include a twenty-third transistor T23. The second mode controller 1612 may further include a twenty-fourth transistor T24. The common signal controller 1613 may include a sixth transistor T6, a seventh transistor T7, and a reset transistor TRST. The sixth transistor T6 may be used as a pull-down transistor, and the seventh transistor T7 may be used as a pull-up transistor.

[0220] Figure 17 This is a view illustrating an example of the signal flow of a display device according to an embodiment of the present invention. Specifically, Figure 17 It shows the relationship with Figure 12 Example of signal flow related to the gate drive circuit in the implementation method.

[0221] Reference Figure 17 As a synchronization signal associated with the gate drive circuit, the synchronization signal Vsync can be input at intervals of the first time period P1. The gate start signal VST and the reset signal EQRST can be input to the gate drive circuit at intervals of the first time period P1. The timing of the level change of each of the gate start signal VST and the reset signal EQRST, such as the time when the signal changes from high level to low level or from low level to high level, can be different as shown in the figure.

[0222] The first clock signal ECLK1 and the second clock signal ECLK2 can be input to the gate drive circuit at a constant interval. In an embodiment, at least a portion of the time period corresponding to the high level of the first clock signal ECLK1 can overlap with at least a portion of the time period corresponding to the low level of the second clock signal ECLK2. The length of the overlapping time period can be predetermined.

[0223] In this implementation, the signals from the Q node and QB node can be repeated at intervals corresponding to the first time period P1. According to... Figure 17 The QB node can be low for at least a portion of the time that the Q node is high. The QB node can be high for at least a portion of the time that the Q node is low.

[0224] In one implementation, the first mode signal MOD1 may have a level opposite to that of the second mode signal MOD2. For example, when the first mode signal MOD1 is high, the second mode signal MOD2 may be low. Conversely, when the first mode signal MOD1 is low, the second mode signal MOD2 may be high. In one implementation, the period during which the first mode signal MOD1 is high or the period during which the second mode signal MOD2 is low may include the period during which the display device is driven in the second mode. The period during which the first mode signal MOD1 is low or the period during which the second mode signal MOD2 is high may include the period during which the display device is driven in the first mode.

[0225] In this scenario, the first mode may include a mode that provides light through a light-emitting element at a wider viewing angle than in the second mode. For example, the first mode may include using... Figure 5 Or, the first light-emitting element ED1 of the first light-emitting element 6 emits light in a certain mode. The second mode may include a mode in which light is provided through a second light-emitting element at a narrower viewing angle than in the first mode. For example, the second mode may include using... Figure 5 Or the second light-emitting element ED2 of 6 emits light in a certain mode.

[0226] In this implementation, the first light-emitting signal EM1 can be at a high level when the first mode signal MOD1 is high. At least a portion of the time period of the first light-emitting signal EM1 can be at a low level when the first mode signal MOD1 is low. The second light-emitting signal EM2 can be at a high level when the second mode signal MOD2 is high. At least a portion of the time period of the second light-emitting signal EM2 can be at a low level when the second mode signal MOD2 is low. At least a portion of the time period of the common light-emitting signal EM0 can operate at a low or high level according to the interval of the first time period P1. For example, regardless of the level of the first light-emitting signal EM1 or the second light-emitting signal EM2, the common light-emitting signal EM0 can be provided to the pixel circuit according to the interval of the first time period.

[0227] According to the implementation method, such as Figures 13 to 16 As shown, the gate drive circuit may further include a transistor associated with the control of the common light-emitting signal EM0. For example, the gate drive circuit may include at least one of a first common control transistor T30 and a second common control transistor T31. In this case, a common control signal VGL_C for controlling the first common control transistor T30 and the second common control transistor T31 may be input. Figure 17The common light-emitting signal EM0 can operate at a high or low level based on the input of the common control signal VGL_C. For example, the common light-emitting signal EM0 can be at a high level when the common control signal VGL_C is high. The common light-emitting signal EM0 can be at a low level for at least a portion of the time period when the common control signal VGL_C is low.

[0228] According to an embodiment of the present invention, a gate driving circuit for controlling the driving of pixel circuits in a display device may include: a first mode controller ( Figure 12 First mode controller 1211), the first mode controller responds to a first mode signal (e.g. Figure 12 The first mode signal (MOD1) is received, and the output is based on the first node (e.g., Figure 12 The first emitted signal (e.g., the potential of the Q node) Figure 12 The first luminous signal EM1) or based on the second node (e.g. Figure 12 The second luminescent signal of the potential of the QB node (e.g., the second luminescent signal of the potential of the QB node) Figure 12 The second luminous signal EM2); the second mode controller (e.g. Figure 12 The second mode controller 1212), the second mode controller is responsive to the second mode signal (e.g. Figure 12 The second mode signal (MOD2) is received, and a first emission signal based on the potential of the first node or a second emission signal based on the potential of the second node is output; and a node controller (e.g., Figure 12 The node controller 1201, which uses a start signal (e.g., Figure 12 Gate start signal VST), first clock signal (e.g.) Figure 12 The first clock signal ECLK1) and the second clock signal (e.g. Figure 12 The potential of the first node and the potential of the second node are controlled by at least one of the second clock signals (ECLK2).

[0229] According to some embodiments of the present invention, the first mode controller may include: a first mode control transistor (e.g., connected to a first mode signal line for providing the first mode signal) Figure 12 The fourteenth transistor T14); the first transistor connected to the first voltage line for providing the first value of the voltage (e.g. Figure 12 The eleventh transistor T11); and a second transistor (e.g., connected to a second voltage line for providing a second value higher than the first value). Figure 12 The twelfth transistor (T12).

[0230] According to some embodiments of the present invention, the first mode controller may further include: a third transistor (e.g., a fifteenth transistor T15, a sixteenth transistor T16, and / or a thirteenth transistor T13) for initializing the first mode controller; a first capacitor (e.g., a first-mode pull-up capacitor CQS) connected to the gate of the first transistor; and a second capacitor (e.g., a first-mode pull-up capacitor CQSB) connected to the gate of the second transistor. The first electrode of the first transistor may be connected to the first voltage line, the second electrode of the first transistor may be connected to the second transistor, the first electrode of the second transistor may be connected to the second voltage line, and the second electrode of the second transistor may be connected to the first transistor. The first electrode of the second capacitor may be connected to the first electrode of the second transistor, and the second electrode of the second capacitor may be connected to the gate of the second transistor.

[0231] According to some embodiments of the present invention, the second mode controller may include: connected to a signal for providing a second mode (e.g., Figure 12 The second mode signal line of the second mode signal MOD2) is connected to the second mode control transistor (e.g., the twentieth transistor T20); the fourth transistor (e.g., the fourth transistor connected to the first voltage line for providing the first value) is connected to the second mode control transistor (e.g., the twentieth transistor T20). Figure 12 The seventeenth transistor (T17); and the fifth transistor (e.g., connected to a second voltage line for providing a second value higher than the first value). Figure 12 The eighteenth transistor (T18).

[0232] According to some embodiments of the present invention, the second mode controller may further include: a sixth transistor (e.g., for initializing the second mode controller) Figure 12 The nineteenth transistor T19, the twenty-first transistor T21, and / or the twenty-second transistor T22); and a third capacitor (e.g., connected to the gate of the fourth transistor) Figure 12 The second mode pull-up capacitor (CQP); and the fourth capacitor (e.g., connected to the gate of the fifth transistor). Figure 12 The second-mode pull-up capacitor (CQPB).

[0233] According to some embodiments of the present invention, the first mode controller may be connected to a first light-emitting element (e.g., in the pixel circuit) included in the pixel circuit. Figure 5 Or the first light-emitting element ED1 of 6), the second mode controller can be connected to the second light-emitting element (e.g., ED1) included in the pixel circuit. Figure 5 Or the second light-emitting element ED2 of 6). First lens (e.g. Figure 8 The first lens 510 can be disposed on the first light-emitting element, and the second lens (e.g. Figure 9 The second lens 520 may be disposed on the second light-emitting element. The viewing angle of the area where the first light-emitting element is disposed may correspond to a first value via the first lens, and the viewing angle of the area where the second light-emitting element is disposed may correspond to a second value less than the first value via the second lens.

[0234] According to some embodiments of the present invention, the gate drive circuit may further include a common signal controller (e.g., Figure 12 A common signal controller 1213), the common signal controller being used to output a common light-emitting signal (e.g., based on the potential of the first node and the potential of the second node). Figure 12 The public luminous signal EM0).

[0235] According to some embodiments of the present invention, the starting signal may include at least one light emission signal output from the preamplifier.

[0236] According to some embodiments of the present invention, the gate driving circuit may further include a scan output unit for outputting scan signals.

[0237] The gate driving circuit and display device according to embodiments of the present invention can provide signals for controlling pixel circuits including multiple light-emitting elements.

[0238] A display panel according to an embodiment of the present invention may include: a plurality of pixel circuits; and a gate driving circuit configured to control the driving of the plurality of pixel circuits based on the provision of a first light-emitting signal and a second light-emitting signal to each of the plurality of pixel circuits, wherein the gate driving circuit includes: a first mode controller configured to output a first light-emitting signal based on at least one of the potential of a first node and the potential of a second node to a first output line in response to the reception of a first mode signal; a second mode controller configured to output a second light-emitting signal based on at least one of the potential of the first node and the potential of the second node to a second output line in response to the reception of a second mode signal; and a controller configured to control the potential of the first node and the potential of the second node by using at least one of a start signal, a first clock signal and a second clock signal.

[0239] According to some embodiments of the present invention, a display device may be disposed in at least a portion of a vehicle to provide at least one type of content, and the display device may include: a plurality of pixel circuits; and a gate driving circuit configured to control the driving of the plurality of pixel circuits based on the provision of a first light-emitting signal and a second light-emitting signal to each of the plurality of pixel circuits, wherein the gate driving circuit includes: a first mode controller configured to output a first light-emitting signal based on at least one of the potential of a first node and the potential of a second node to a first output line in response to the reception of a first mode signal; a second mode controller configured to output a second light-emitting signal based on at least one of the potential of the first node and the potential of the second node to a second output line in response to the reception of a second mode signal; and a controller configured to control the potential of the first node and the potential of the second node by using at least one of a start signal, a first clock signal, and a second clock signal.

[0240] Those skilled in the art will readily recognize that the invention described above is not limited to the embodiments and drawings described herein, and various substitutions, modifications, and variations can be made within the scope of the invention without departing from its spirit or scope. Therefore, the scope of the invention is defined by the appended claims, and all variations and modifications derived from the meaning, scope, and equivalent concepts of the claims are intended to fall within the scope of the invention.

Claims

1. A gate driving circuit for controlling the driving of pixel circuits in a display device, the gate driving circuit comprising: A first mode controller is configured to output a first light emission signal based on at least one of the potential of a first node and the potential of a second node to a first output line in response to the reception of a first mode signal. A second mode controller is configured to output a second light emission signal based on at least one of the potential of the first node and the potential of the second node to a second output line in response to the reception of a second mode signal. A node controller that controls the potential of the first node and the potential of the second node by using at least one of a start signal, a first clock signal, and a second clock signal; as well as A common signal controller is configured to output a common light-emitting signal to a third output line based on the potentials of the first node and the second node. The first mode controller, the second mode controller, and the common signal controller are all connected to the first node and are also connected to the second node.

2. The gate driving circuit according to claim 1, wherein the first mode controller comprises: A first transistor is connected between the first output line and a first voltage line for providing a first value of voltage. The second transistor is controlled by the potential of the second node and is connected between the first output line and a second voltage line for providing a second voltage value higher than the first value; as well as A first mode control transistor is connected to a first mode signal line for providing the first mode signal.

3. The gate driving circuit according to claim 2, wherein the first mode controller further comprises: A third transistor, which is controlled by a reset voltage to initialize the first output line of the first mode controller; A first capacitor is connected to the gate of the first transistor; as well as The second capacitor is connected to the gate of the second transistor.

4. The gate driving circuit according to claim 3, wherein the first electrode of the second capacitor is connected to the first electrode of the second transistor, and the second electrode of the second capacitor is connected to the gate of the second transistor.

5. The gate drive circuit according to claim 1, wherein the second mode controller comprises: A second mode control transistor is connected to a second mode signal line for providing a second mode signal; A fourth transistor, the fourth transistor being connected to a first voltage line for providing a first value of voltage; as well as A fifth transistor, which is connected to a second voltage line for providing a second voltage value higher than the first value.

6. The gate drive circuit according to claim 5, wherein the second mode controller further comprises: A sixth transistor, controlled by a reset voltage, initializes the second output line of the second mode controller; A third capacitor is connected to the gate of the fourth transistor; as well as A fourth capacitor is connected to the gate of the fifth transistor.

7. The gate driving circuit according to claim 1, wherein the first mode controller controls a first light-emitting control transistor connected to a first light-emitting element in the pixel circuit, and the second mode controller controls a second light-emitting control transistor connected to a second light-emitting element in the pixel circuit.

8. The gate driving circuit according to claim 7, wherein the first lens is disposed on the first light-emitting element and the second lens is disposed on the second light-emitting element.

9. The gate driving circuit according to claim 8, wherein the viewing angle of the region where the first light-emitting element is disposed corresponds to a first value via the first lens, and the viewing angle of the region where the second light-emitting element is disposed corresponds to a second value less than the first value via the second lens.

10. The gate drive circuit of claim 1, wherein the common signal controller comprises: A seventh transistor, which is controlled based on the potential of the first node and connected to the third output line; as well as The eighth transistor is controlled based on the potential of the second node and is connected to the third output line.

11. The gate drive circuit of claim 1, wherein the start signal includes at least one light emission signal output from the front stage.

12. The gate driving circuit according to claim 1 further includes a scan output unit for outputting a scan signal.

13. The gate driving circuit of claim 1, comprising multiple stages, each stage comprising the first mode controller, the second mode controller and the node controller, wherein the start signal comprises an external start signal and at least one light emission signal output from a previous stage.

14. The gate drive circuit of claim 2, wherein the node controller comprises: A ninth transistor, which is controlled by the second clock signal and connected to a line for providing the start signal; The tenth transistor is controlled by the first clock signal and is connected to the ninth transistor; The eleventh transistor is connected to the tenth transistor and the second voltage line; The twelfth transistor is controlled by the second clock signal and connected to the first voltage line; The thirteenth transistor connected to the second voltage line and the second node; The fourteenth transistor is controlled by the first clock signal and connected to the second node; as well as The fifteenth transistor is connected to the ninth transistor, the tenth transistor, the twelfth transistor, the thirteenth transistor, and the first node.

15. The gate drive circuit of claim 14, wherein the node controller further comprises: The sixteenth transistor is connected to the tenth transistor, the fourteenth transistor, and the fifteenth transistor; as well as A node control capacitor is connected to the fourteenth transistor, the fifteenth transistor, and the sixteenth transistor.

16. The gate drive circuit of claim 14, wherein the fifteenth transistor comprises a dual-gate.

17. The gate drive circuit of claim 10, wherein the common signal controller further comprises: The fifth capacitor connected to the first node; as well as The sixth capacitor connected to the second node.

18. The gate drive circuit of claim 10, wherein the common signal controller further comprises: A reset transistor, which is controlled by a reset voltage and configured to reset the common signal controller.

19. The gate drive circuit of claim 10, wherein the common signal controller further comprises: A first common control transistor, which is controlled by a common control signal and connected to the gate of the seventh transistor.

20. The gate drive circuit of claim 19, wherein the common signal controller further comprises: The second common control transistor is controlled by the common control signal and is connected to the gate of the eighth transistor.

21. The gate driving circuit according to claim 2, wherein the first mode controller further comprises: The seventeenth transistor is controlled by the first mode signal and is connected to the second node and the second transistor.

22. The gate drive circuit of claim 5, wherein the second mode controller further comprises: The eighteenth transistor is controlled by the second mode signal and is connected to the second node and the fifth transistor.

23. A display panel, comprising: Multiple pixel circuits; as well as A gate driving circuit is configured to control the driving of the plurality of pixel circuits based on the provision of a first light-emitting signal and a second light-emitting signal to each of the plurality of pixel circuits. The gate drive circuit includes: A first mode controller is configured to output a first light emission signal based on at least one of the potential of a first node and the potential of a second node to a first output line in response to the reception of a first mode signal. A second mode controller is configured to output a second light emission signal based on at least one of the potential of the first node and the potential of the second node to a second output line in response to the reception of a second mode signal. A controller configured to control the potential of the first node and the potential of the second node by using at least one of a start signal, a first clock signal, and a second clock signal; and A common signal controller is configured to output a common light-emitting signal to a third output line based on the potentials of the first node and the second node. The first mode controller, the second mode controller, and the common signal controller are all connected to the first node and are also connected to the second node.

24. A display device disposed in at least a portion of a vehicle to provide at least one type of content, said display device comprising: Multiple pixel circuits; as well as A gate driving circuit is configured to control the driving of the plurality of pixel circuits based on the provision of a first light-emitting signal and a second light-emitting signal to each of the plurality of pixel circuits. The gate drive circuit includes: A first mode controller is configured to output a first light emission signal based on at least one of the potential of a first node and the potential of a second node to a first output line in response to the reception of a first mode signal. A second mode controller is configured to output a second light emission signal based on at least one of the potential of the first node and the potential of the second node to a second output line in response to the reception of a second mode signal. A controller configured to control the potential of the first node and the potential of the second node by using at least one of a start signal, a first clock signal, and a second clock signal; and A common signal controller is configured to output a common light-emitting signal to a third output line based on the potentials of the first node and the second node. The first mode controller, the second mode controller, and the common signal controller are all connected to the first node and are also connected to the second node.

Images