Storage device and display

Abstract

The embodiment of the present application discloses a storage device and a display. The storage device comprises a signal input end, a signal output end, a latch unit and a control unit. The latch unit is connected between the signal input end and the signal output end. The control unit is connected between the signal input end and the latch unit. The control unit comprises a first transistor, a second transistor and a control switch assembly. The control switch assembly is electrically connected with the first transistor and the second transistor to control the first transistor and the second transistor to be turned on or turned off. The drain current of the first transistor is less than the drain current of the second transistor. The mobility of the second transistor is greater than the mobility of the first transistor. The first transistor and the second transistor are controlled to be turned on or turned off by the control switch assembly. When writing, the high mobility of the second transistor can be used to realize fast writing of the storage device. When storing, the low drain current of the first transistor can be used to realize long storage time of the storage device.

Description

Technical Field

[0001] This application relates to the field of display, specifically to a storage device and a display. Background Technology

[0002] Existing semiconductor memory devices can be broadly classified into two categories: volatile devices and non-volatile devices. Volatile devices lose stored data when power is off, while non-volatile devices retain stored data even when power is off. Volatile devices are further divided into dynamic volatile memory (VTMH) and static volatile memory (SVO). In VTMH, the charge in the capacitor is lost when data is read, so a write operation is required for each read. Furthermore, when the transistor is in the off state, leakage current (cutoff current) flows between the source and drain of the transistor in the memory element. Even when the transistor is not conducting, charge will flow in or out, resulting in a very short data retention period. Therefore, periodic write operations (refresh operations) are necessary. In addition, data stored is lost when power is off, so additional storage devices using magnetic or optical materials are needed to retain data for longer periods.

[0003] Non-volatile memory devices store data by maintaining a charge on a floating gate between the gate electrode and the channel formation region in a transistor. Data can be retained for extended periods, even without power. However, the gate insulating layer in the transistor deteriorates due to tunneling current generated during writing, causing the memory element to lose functionality after a certain number of write operations. To mitigate this problem, methods using complex external currents to even out the number of write operations are employed, but these methods do not fundamentally solve the problem of lifespan decay. Furthermore, injecting and removing charge into the floating gate requires high voltage and takes a long time, resulting in slow write and erase speeds. In other words, existing memory devices cannot guarantee long-term storage while achieving fast writing speeds. Summary of the Invention

[0004] This application provides a storage device and a display that can solve the problem that existing storage devices cannot guarantee long storage time while achieving fast writing.

[0005] This application provides a storage device, including:

[0006] Signal input terminal and signal output terminal;

[0007] A latch unit is connected between the signal input terminal and the signal output terminal, and the latch unit is used for writing and storing data.

[0008] A control unit is connected between the signal input terminal and the latching unit. The control unit includes a first transistor, a second transistor, and a control switch assembly. The first transistor and the second transistor are electrically connected to the latching unit, and the control switch assembly is electrically connected to the first transistor and the second transistor to control the first transistor and the second transistor to be turned on or off. The leakage current of the first transistor is less than that of the second transistor, and the mobility of the second transistor is greater than that of the first transistor.

[0009] Optionally, in some embodiments of this application, the first transistor and the second transistor are connected in series between the signal input terminal and the latching unit, and the control switch assembly includes a first control switch, the input terminal of the first control switch being electrically connected to the input terminal of the first transistor, and the output terminal of the first control switch being electrically connected to the output terminal of the first transistor.

[0010] Optionally, in some embodiments of this application, the control switch assembly further includes a second control switch, the input terminal of which is electrically connected to the input terminal of the second transistor, and the output terminal of which is electrically connected to the output terminal of the second transistor.

[0011] Optionally, in some embodiments of this application, the first transistor and the second transistor are connected in parallel between the signal input terminal and the latching unit, and the control switch assembly includes a third control switch, the input terminal of the third control switch being electrically connected to the signal input terminal, and the output terminal of the third control switch being electrically connected to the input terminal of the first transistor or the input terminal of the second transistor, so as to control the first transistor and the second transistor to be turned on or off.

[0012] Optionally, in some embodiments of this application, the first transistor and the second transistor are connected in parallel between the signal input terminal and the latching unit, and the control switch assembly includes a third control switch. The output terminal of the third control switch is electrically connected to the latching unit, and the input terminal of the third control switch is electrically connected to the output terminal of the first transistor or the output terminal of the second transistor, so as to control the first transistor and the second transistor to be turned on or off.

[0013] Optionally, in some embodiments of this application, the first transistor and the second transistor are connected in parallel between the signal input terminal and the latching unit, and the control switch assembly includes a fourth control switch and a fifth control switch. The fourth control switch is connected in series with the first transistor between the signal input terminal and the latching unit, and the fifth control switch is connected in series with the second transistor between the signal input terminal and the latching unit.

[0014] Optionally, in some embodiments of this application, the first transistor is an oxide transistor; the second transistor is a monocrystalline silicon transistor or a polycrystalline silicon transistor.

[0015] Optionally, in some embodiments of this application, the leakage current of the first transistor is less than or equal to 1*102 -12 A.

[0016] Optionally, in some embodiments of this application, the mobility of the second transistor is greater than or equal to 10 cm⁻¹. 2 / V·s.

[0017] Accordingly, embodiments of this application also provide a display, the display including any of the storage devices described above.

[0018] In this embodiment, the storage device includes a signal input terminal, a signal output terminal, a latch unit, and a control unit. The latch unit is connected between the signal input terminal and the signal output terminal and is used for writing and storing data. The control unit is connected between the signal input terminal and the latch unit and includes a first transistor, a second transistor, and a control switch assembly. The first and second transistors are electrically connected to the latch unit, and the control switch assembly is electrically connected to the first and second transistors to control them to be turned on or off. The leakage current of the first transistor is less than that of the second transistor, and the mobility of the second transistor is greater than that of the first transistor. By simultaneously configuring the first and second transistors in the control unit and using the control switch assembly to control their on / off states, this application enables fast writing of the storage device during writing by utilizing the high mobility of the second transistor, and long storage time during storage by utilizing the low leakage current of the first transistor. This allows the storage device to achieve both fast writing and long storage time. Attached Figure Description

[0019] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0020] Figure 1 This is a schematic diagram of the circuit structure of a storage device provided in an embodiment of this application;

[0021] Figure 2 This is a schematic diagram of the circuit structure of another storage device provided in an embodiment of this application;

[0022] Figure 3 This is a schematic diagram of the circuit structure of another storage device provided in an embodiment of this application;

[0023] Figure 4 This is a schematic diagram of the circuit structure of another storage device provided in an embodiment of this application;

[0024] Figure 5 This is a schematic diagram of the circuit structure of another storage device provided in an embodiment of this application;

[0025] Figure 6 This is a schematic diagram of the structure of a display provided in an embodiment of this application.

[0026] Explanation of reference numerals in the attached figures:

[0027] Detailed Implementation

[0028] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application. In addition, it should be understood that the specific embodiments described herein are only for illustration and explanation of this application and are not intended to limit this application. In this application, unless otherwise stated, directional terms such as "upper" and "lower" generally refer to the upper and lower positions of the device in actual use or operation, specifically the drawing directions in the accompanying drawings; while "inner" and "outer" refer to the outline of the device.

[0029] This application provides a storage device and a display, which will be described in detail below. It should be noted that the order of description of the following embodiments is not intended to limit the preferred order of the embodiments.

[0030] First, embodiments of this application provide a storage device, such as... Figure 1 As shown, the storage device 100 includes a signal input terminal 110 and a signal output terminal 120. By inputting control signals from the signal input terminal 110 and designing the circuit between the signal input terminal 110 and the signal output terminal 120, the storage device 100 can realize the functions of writing, erasing and storing.

[0031] The storage device 100 includes a latch unit 130, which is connected between the signal input terminal 110 and the signal output terminal 120. The latch unit 130 is used for writing and storing data; that is, the latch unit 130 serves as the storage portion of the storage device 100, used to store data written to the storage device 100 in real time. The latch unit 130 is equipped with a latch circuit 131, which is used to cyclically write, store, and erase data. The design of the latch circuit 131 can meet different usage requirements of the storage device 100. The specific structure of the latch circuit 131 can also be designed and adjusted according to the actual usage requirements of the storage device 100; no special limitations are imposed here.

[0032] The storage device 100 includes a control unit 140, which is connected between the signal input terminal 110 and the latch unit 130. That is, after the control signal is input from the signal input terminal 110, it needs to pass through the control unit 140 first, and then be transmitted to the latch unit 130, so as to realize the control unit 140 to control the latch unit 130.

[0033] The control unit 140 includes a first transistor 141, a second transistor 142, and a control switch assembly 143. The first transistor 141 and the second transistor 142 are electrically connected to the latching unit 130, and the control switch assembly 143 is electrically connected to the first transistor 141 and the second transistor 142 to control the first transistor 141 and the second transistor 142 to be turned on or off. The leakage current of the first transistor 141 is less than the leakage current of the second transistor 142, and the mobility of the second transistor 142 is greater than the mobility of the first transistor 141. That is, the first transistor 141 is a low-leakage-current transistor, and the second transistor 142 is a high-mobility transistor.

[0034] During the use of the storage device 100, when data needs to be written or erased, the first transistor 141 is turned off and the second transistor 142 is turned on by the control switch assembly 143, so that the high-mobility second transistor 142 can be used to realize fast writing and erasing of the storage device 100 during the writing and erasing phases; when data needs to be stored, the first transistor 141 is turned on by the control switch assembly 143, so that the first transistor 141 is connected to the circuit and the first transistor 141 is set to the off state. Since the first transistor 141 is a low leakage current type transistor, even if leakage current flows between the source and drain of the first transistor 141 during the storage process, the current flowing is extremely small, thereby helping to improve the storage time of the storage device 100.

[0035] In other words, by controlling the switching component 143 to turn the first transistor 141 and the second transistor 142 on or off, the high mobility of the second transistor 142 can be used to achieve fast writing and erasing of the storage device 100 during the write and erase phases, while the low leakage current of the first transistor 141 can be used to achieve a long storage time of the storage device 100 during the storage phase. Thus, the storage device 100 can achieve the advantage of fast writing and erasing while ensuring a long storage time.

[0036] In this embodiment, the storage device 100 includes a signal input terminal 110, a signal output terminal 120, a latch unit 130, and a control unit 140. The latch unit 130 is connected between the signal input terminal 110 and the signal output terminal 120 and is used for writing and storing data. The control unit 140 is connected between the signal input terminal 110 and the latch unit 130 and includes a first transistor 141, a second transistor 142, and a control switch assembly 143. The control switch assembly 143 is electrically connected to the first transistor 141 and the second transistor 142 to control the first transistor 141 and the second transistor 142 to be turned on or off. The leakage current of the first transistor 141 is less than the leakage current of the second transistor 142, and the mobility of the second transistor 142 is greater than the mobility of the first transistor 141. This application simultaneously sets a first transistor 141 and a second transistor 142 in the control unit 140, and uses a control switch assembly 143 to control the first transistor 141 and the second transistor 142 to be turned on or off. This enables the storage device 100 to be written quickly by utilizing the high mobility of the second transistor 142, and to be stored for a long time by utilizing the low leakage current of the first transistor 141. Thus, the storage device 100 can achieve both fast writing and long storage time.

[0037] Optional, such as Figure 1 and Figure 2As shown, the first transistor 141 and the second transistor 142 are connected in series between the signal input terminal 110 and the latch unit 130. The connection order of the first transistor 141 and the second transistor 142 between the signal input terminal 110 and the latch unit 130 can be adjusted according to the design requirements of the control unit 140. The control switch assembly 143 includes a first control switch 1431. The input terminal of the first control switch 1431 is electrically connected to the input terminal of the first transistor 141, and the output terminal of the first control switch 1431 is electrically connected to the output terminal of the first transistor 141. That is, the first control switch 1431 and the first transistor 141 are connected in parallel to realize the control of turning the first transistor 141 on or off.

[0038] Specifically, such as Figure 1 As shown, during the write and erase phases of the storage device 100, the first control switch 1431 is closed. At this time, a short circuit occurs between the input and output terminals of the first transistor 141. The control signal is transmitted from the first control switch 1431 to the second transistor 142 through the signal input terminal 110, and then to the latch unit 130, so that the storage device 100 can utilize the high mobility of the second transistor 142 to achieve fast write and erase.

[0039] During the storage phase of the storage device 100, the first control switch 1431 is turned off. At this time, the first transistor 141 and the second transistor 142 are connected in series and are in the off state. When the data in the latch unit 130 flows in the form of charge, even if the charge can flow rapidly between the source and drain of the second transistor 142, the flow of charge between the source and drain of the first transistor 141 is minimal due to the small leakage current of the first transistor 141. This allows the storage device 100 to achieve long-term storage by utilizing the low leakage current of the first transistor 141.

[0040] In some embodiments, such as Figure 2 As shown, the control switch assembly 143 also includes a second control switch 1432. The input terminal of the second control switch 1432 is electrically connected to the input terminal of the second transistor 142, and the output terminal of the second control switch 1432 is electrically connected to the output terminal of the second transistor 142. That is, the second control switch 1432 and the second transistor 142 are connected in parallel to realize the control of the second transistor 142 to be turned on or off.

[0041] Specifically, during the write and erase phases of the storage device 100, the first control switch 1431 is closed and the second control switch 1432 is opened. At this time, a short circuit occurs between the input and output terminals of the first transistor 141, and the second transistor 142 can be successfully connected to the circuit. The control signal is transmitted from the first control switch 1431 to the second transistor 142 through the signal input terminal 110, and then to the latch unit 130, so that the storage device 100 can use the high mobility of the second transistor 142 to achieve fast write and erase.

[0042] During the storage phase of the storage device 100, the first control switch 1431 is turned off, and the second control switch 1432 can be selected to be either turned off or closed. If the second control switch 1432 is turned off, the first transistor 141 and the second transistor 142 are connected in series, and their working principle is the same as that in the above embodiment, which will not be described in detail here. If the second control switch 1432 is closed, a short circuit occurs between the input and output terminals of the second transistor 142, and only the first transistor 141 is connected to the circuit. When the data in the latch unit 130 flows in the form of charge, the flow between the source and drain of the first transistor 141 is minimal, so that the storage device 100 can achieve long-term storage by utilizing the low leakage current of the first transistor 141.

[0043] Optional, such as Figure 3 As shown, the first transistor 141 and the second transistor 142 are connected in parallel between the signal input terminal 110 and the latch unit 130. The control switch assembly 143 includes a third control switch 1433. The input terminal of the third control switch 1433 is electrically connected to the signal input terminal 110, and the output terminal of the third control switch 1433 is electrically connected to either the input terminal of the first transistor 141 or the input terminal of the second transistor 142, to control the first transistor 141 and the second transistor 142 to be turned on or off. That is, the output terminal of the third control switch 1433 can be selectively electrically connected to either the input terminal of the first transistor 141 or the input terminal of the second transistor 142, so as to connect the first transistor 141 or the second transistor 142 into the circuit accordingly.

[0044] Specifically, during the write and erase phases of the storage device 100, the output terminal of the third control switch 1433 is electrically connected to the input terminal of the second transistor 142, enabling the second transistor 142 to be smoothly connected to the circuit. The control signal is transmitted from the third control switch 1433 to the second transistor 142 through the signal input terminal 110, and then to the latch unit 130, so that the storage device 100 can utilize the high mobility of the second transistor 142 to achieve fast write and erase.

[0045] During the storage phase of the storage device 100, the output terminal of the third control switch 1433 is electrically connected to the input terminal of the first transistor 141, so that the first transistor 141 can be smoothly connected to the circuit and the first transistor 141 is in the off state. When the data of the latch unit 130 flows in the form of charge, the flow between the source and drain of the first transistor 141 is minimal, so that the storage device 100 can use the low leakage current of the first transistor 141 to achieve long-term storage.

[0046] In some embodiments, such as Figure 4 As shown, the first transistor 141 and the second transistor 142 are connected in parallel between the signal input terminal 110 and the latch unit 130. The control switch assembly 143 includes a third control switch 1433. The output terminal of the third control switch 1433 is electrically connected to the latch unit 130, and the input terminal of the third control switch 1433 is electrically connected to either the output terminal of the first transistor 141 or the output terminal of the second transistor 142, to control the first transistor 141 and the second transistor 142 to be turned on or off. That is, the input terminal of the third control switch 1433 can be selectively connected to either the output terminal of the first transistor 141 or the output terminal of the second transistor 142, so as to connect the first transistor 141 or the second transistor 142 into the circuit accordingly.

[0047] Specifically, during the write and erase phases of the storage device 100, the input terminal of the third control switch 1433 is electrically connected to the output terminal of the second transistor 142, enabling the second transistor 142 to be smoothly connected to the circuit. The control signal is transmitted to the second transistor 142 through the signal input terminal 110, and then transmitted to the latch unit 130 through the third control switch 1433, so that the storage device 100 can utilize the high mobility of the second transistor 142 to achieve fast write and erase.

[0048] During the storage phase of the storage device 100, the input terminal of the third control switch 1433 is electrically connected to the output terminal of the first transistor 141, so that the first transistor 141 can be smoothly connected to the circuit and the first transistor 141 is in the off state. When the data in the latch unit 130 flows in the form of charge, the flow between the source and drain of the first transistor 141 is minimal, so that the storage device 100 can use the low leakage current of the first transistor 141 to achieve long-term storage.

[0049] In other embodiments, such as Figure 5As shown, the first transistor 141 and the second transistor 142 are connected in parallel between the signal input terminal 110 and the latch unit 130. The control switch assembly 143 includes a fourth control switch 1434 and a fifth control switch 1435. The fourth control switch 1434 and the first transistor 141 are connected in series between the signal input terminal 110 and the latch unit 130. The fifth control switch 1435 and the second transistor 142 are connected in series between the signal input terminal 110 and the latch unit 130. The opening and closing of the fourth control switch 1434 and the fifth control switch 1435 can control the conduction and opening of the first transistor 141 and the second transistor 142 respectively, so as to meet the different usage scenarios of the storage device 100.

[0050] Specifically, during the write and erase phases of the storage device 100, the fifth control switch 1435 is closed and the fourth control switch 1434 is opened, allowing the second transistor 142 to be smoothly connected to the circuit. The control signal is transmitted from the fifth control switch 1435 to the second transistor 142 through the signal input terminal 110, and then to the latch unit 130, enabling the storage device 100 to achieve fast write and erase by utilizing the high mobility of the second transistor 142.

[0051] During the storage phase of the storage device 100, the fourth control switch 1434 is closed and the fifth control switch 1435 is opened, so that the first transistor 141 is successfully connected to the circuit and the first transistor 141 is in the off state. When the data in the latch unit 130 flows in the form of charge, the flow between the source and drain of the first transistor 141 is minimal, so that the storage device 100 can use the low leakage current of the first transistor 141 to achieve long-term storage.

[0052] Optionally, in this embodiment, the first transistor 141 can be an oxide transistor, that is, the active layer of the first transistor 141 is an oxide semiconductor material, so as to achieve low leakage current of the first transistor 141. The second transistor 142 can be a monocrystalline silicon transistor or a polycrystalline silicon transistor, that is, the active layer of the second transistor 142 is a monocrystalline silicon or polycrystalline silicon material, so as to achieve high mobility of the second transistor 142.

[0053] The leakage current of the first transistor 141 is less than or equal to 1*10. -12 A, so that when the storage device 100 is in the storage stage, if the data in the latch unit 130 flows in the form of charge, the flow between the source and drain of the first transistor 141 is also minimal, thereby enabling long-term storage of the storage device 100.

[0054] Specifically, in the actual manufacturing process, the leakage current of the first transistor 141 can be designed to be 1*10. -12 A, 8*10-13 A, 5*10 -13 A, 2*10 -13 A or 1*10 -13 The specific value of A can be adjusted according to the actual usage requirements of the storage device 100. It is only necessary to ensure that the storage device 100 can achieve long-term storage by utilizing the low leakage current of the first transistor 141. No special restrictions are imposed here.

[0055] The mobility of the second transistor 142 is greater than or equal to 10 cm⁻¹. 2 / V·s, so that the high mobility of the second transistor 142 enables the storage device 100 to achieve fast writing and erasing during the write and erase phases. In actual manufacturing, the mobility of the second transistor 142 can be designed to be 10 cm⁻¹. 2 / V·s、12cm 2 / V·s、15cm 2 / V·s、18cm 2 / V·s or 20cm 2 The specific value of / V·s can be adjusted according to the actual usage requirements of the storage device 100. It is only necessary to ensure that the storage device 100 can achieve fast writing and erasing by utilizing the high mobility of the second transistor 142. No special restrictions are imposed here.

[0056] Secondly, this application also provides a display, which includes a storage device. The specific structure of the storage device is as described in the above embodiments. Since this display adopts all the technical solutions of all the above embodiments, it has at least all the beneficial effects brought about by the technical solutions of the above embodiments, which will not be described in detail here.

[0057] like Figure 6 As shown, the display 10 may include components such as a processor 200 with one or more processing cores, a storage device 100, a power supply 300, and an input unit 400. Those skilled in the art will understand that... Figure 6 The structure of the display 10 shown does not constitute a limitation on the display 10, and may include more or fewer components than shown, or combine certain components, or have different component arrangements.

[0058] The processor 200 is the control center of the display 10. It connects various parts of the display 10 through various interfaces and lines. By running or executing software programs and / or modules stored in the storage device 100 and calling data stored in the storage device 100, it performs various functions of the display 10 and processes data, thereby controlling the display mode of the display 10.

[0059] The storage device 100 mainly includes a control unit 140 and a latch unit 130. The latch unit 130 serves as the storage portion of the storage device 100, used for real-time storage of data written to the storage device 100. The control unit 140 is used to regulate the control circuitry corresponding to the write / erase phase or the storage phase of the storage device 100, thereby realizing different functions of the latch unit 130. Furthermore, the storage device 100 may include high-speed random access memory and may also include non-volatile memory, such as at least one disk storage device, flash memory device, or other volatile solid-state storage device.

[0060] The display 10 also includes a power supply 300 that supplies power to the various components. The power supply 300 can be logically connected to the processor 200 through a power supply 300 management system, thereby enabling functions such as charging, discharging, and power consumption management through the power supply 300 management system. The power supply 300 may also include one or more DC or AC power supplies 300, a recharging system, a power supply 300 fault detection circuit, a power supply 300 converter or inverter, a power supply 300 status indicator, and other arbitrary components.

[0061] The display 10 may also include an input unit 400, which can be used to receive input digital or character information, and generate keyboard, mouse, joystick, optical, or trackball signal inputs related to user settings and function control. Although not shown, the display 10 may also include a display unit, etc., which will not be described in detail here.

[0062] The above provides a detailed description of a storage device and display provided in the embodiments of this application. Specific examples have been used to illustrate the principles and implementation methods of this application. The description of the above embodiments is only for the purpose of helping to understand the method and core ideas of this application. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of this application. Therefore, the content of this specification should not be construed as a limitation of this application.

Claims

1. A storage device, characterized in that, include: Signal input terminal and signal output terminal; A latch unit is connected between the signal input terminal and the signal output terminal, and the latch unit is used for writing and storing data. A control unit is connected between the signal input terminal and the latching unit. The control unit includes a first transistor, a second transistor, and a control switch assembly. The first transistor and the second transistor are electrically connected to the latching unit, and the control switch assembly is electrically connected to the first transistor and the second transistor to control the first transistor and the second transistor to be turned on or off. The leakage current of the first transistor is less than that of the second transistor, and the mobility of the second transistor is greater than that of the first transistor. The control switch assembly is configured to turn off the first transistor and turn on the second transistor during the write and erase phases, and to turn on the first transistor and turn off the second transistor during the storage phase.

2. The storage device according to claim 1, characterized in that, The first transistor and the second transistor are connected in series between the signal input terminal and the latch unit. The control switch assembly includes a first control switch, the input terminal of the first control switch is electrically connected to the input terminal of the first transistor, and the output terminal of the first control switch is electrically connected to the output terminal of the first transistor.

3. The storage device according to claim 2, characterized in that, The control switch assembly further includes a second control switch, the input terminal of which is electrically connected to the input terminal of the second transistor, and the output terminal of which is electrically connected to the output terminal of the second transistor.

4. The storage device according to claim 1, characterized in that, The first transistor and the second transistor are connected in parallel between the signal input terminal and the latching unit. The control switch assembly includes a third control switch. The input terminal of the third control switch is electrically connected to the signal input terminal, and the output terminal of the third control switch is electrically connected to the input terminal of the first transistor or the input terminal of the second transistor, so as to control the first transistor and the second transistor to be turned on or off.

5. The storage device according to claim 1, characterized in that, The first transistor and the second transistor are connected in parallel between the signal input terminal and the latch unit. The control switch assembly includes a third control switch. The output terminal of the third control switch is electrically connected to the latch unit, and the input terminal of the third control switch is electrically connected to the output terminal of the first transistor or the output terminal of the second transistor, so as to control the first transistor and the second transistor to be turned on or off.

6. The storage device according to claim 1, characterized in that, The first transistor and the second transistor are connected in parallel between the signal input terminal and the latching unit. The control switch assembly includes a fourth control switch and a fifth control switch. The fourth control switch is connected in series with the first transistor between the signal input terminal and the latching unit, and the fifth control switch is connected in series with the second transistor between the signal input terminal and the latching unit.

7. The storage device according to any one of claims 1 to 6, characterized in that, The first transistor is an oxide transistor; the second transistor is a monocrystalline silicon transistor or a polycrystalline silicon transistor.

8. The storage device according to any one of claims 1 to 6, characterized in that, The leakage current of the first transistor is less than or equal to 1*10 -12 A.

9. The storage device according to any one of claims 1 to 6, characterized in that, The mobility of the second transistor is greater than or equal to 10 cm. 2 / V·s.

10. A display, characterized in that, The display includes the storage device according to any one of claims 1 to 9.

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