Memory systems and their operation methods

Abstract

This disclosure may provide a memory system and a method for operating the memory system. The memory controller may include: a latency monitoring component configured to generate information about the number of times over-latency occurs exceeding a preset reference latency, each latency representing the amount of time required from the time a first command is received from an external device to the time a completion response to the first command is transmitted to the external device; and a completion response controller configured to determine a first target latency based on the information about the number of over-latency occurrences, and to provide a completion response to a second command provided from the external device to the external device during a second time period following the first time period.

Description

[0001] Cross-references to related applications

[0002] This patent application claims priority to Korean Patent Application No. 10-2022-0093510, filed on July 27, 2022, the entire disclosure of which is incorporated herein by reference. Technical Field

[0003] The various embodiments of this disclosure generally relate to an electronic device, and more specifically, to a memory system and a method of operating the memory system. Background Technology

[0004] A storage device is a device that stores data under the control of a host device such as a computer, smartphone, or smart tablet. Examples of storage devices, depending on the data storage method, include devices such as hard disk drives (HDDs) that store data on disks, and devices such as solid-state drives (SSDs) or memory cards that store data in semiconductor memory (particularly non-volatile memory).

[0005] A memory system generally comprises a memory device for storing data and a memory controller for controlling the memory device. When a write request for data is received, the memory controller controls the memory device to store the data in the corresponding memory cell area. Furthermore, when a read request for data is received, the memory controller controls the memory device to load the data contained in the corresponding memory cell area. In addition, the memory controller can provide a completion response indicating that the processing of a request from the host has been completed.

[0006] Because memory devices have limited storage space, operations such as wear leveling or garbage collection (GC) can be performed to efficiently utilize the memory. In this scenario, the processing of multiple commands from the host may be delayed. That is, unexpected command processing delays may occur on the host. Therefore, providing a uniform response to command completion increases the likelihood of predictability by the host. Summary of the Invention

[0007] Various embodiments of this disclosure relate to a memory system that provides uniform performance even in a maintenance state, and a method of operating the memory system.

[0008] Embodiments of this disclosure may provide a memory controller. The memory controller may include: a latency monitoring component configured to generate information about the number of times over-latency occurred within a first time period, where each latency represents the amount of time required from the point in time when a first command is received from an external device to the point in time when a completion response to the first command is transmitted to the external device; and a completion response controller configured to determine a first target latency based on the information about the number of over-latency occurrences, and to provide a completion response to a second command provided from the external device to the external device within a second time period following the first time period, after the first target latency has elapsed.

[0009] Embodiments of this disclosure may provide a memory system. The memory system may include: a memory device comprising a plurality of memory blocks; and a memory controller configured to delay a completion response to a second command provided from a host during a second time period following the first time period, based on the number of times an over-delay exceeding a preset reference delay occurs within a first time period, each delay representing the amount of time required from the time the host receives the first command to the memory device to the time the completion response to the first command is provided.

[0010] Embodiments of this disclosure may provide a method for operating a memory controller. The method may include: counting the number of times an over-delay occurs within a first time period, where each delay represents the amount of time required from the time point when a first command is received from an external device to the time point when a completion response to the first command is transmitted to the external device; and delaying the completion response to a second command provided from the external device within a second time period following the first time period, based on a first target delay determined by the number of over-delay occurrences.

[0011] Embodiments of this disclosure may provide a method for operating a memory controller. The method may include: providing a response to a request from a host, where latency is defined as the amount of time between the request and the response; and increasing the latency when the number of over-latency occurrences within a predetermined portion exceeds a threshold, where over-latency is an amount of time exceeding a reference threshold. Attached Figure Description

[0012] Figure 1 This is a diagram illustrating a memory system according to an embodiment of the present disclosure.

[0013] Figure 2 This illustrates an embodiment according to the present disclosure. Figure 1 A diagram of the firmware for the memory controller.

[0014] Figure 3 This is a diagram illustrating the structure and operation of a memory controller according to an embodiment of the present disclosure.

[0015] Figure 4 This is a diagram illustrating parameters determined based on the number of over-delay occurrences according to an embodiment of the present disclosure.

[0016] Figure 5 This illustrates an embodiment according to the present disclosure. Figure 4 A graph showing the relationship between the parameters.

[0017] Figure 6 This is a diagram illustrating a target delay determined based on the number of over-delay occurrences according to an embodiment of the present disclosure.

[0018] Figure 7 It is a graph showing the ratio between the number of over-delay occurrences and the target delay according to an embodiment of the present disclosure.

[0019] Figure 8 This is a diagram illustrating the process of counting the number of times an over-delay occurs beyond a reference delay according to an embodiment of the present disclosure.

[0020] Figure 9 This is a diagram illustrating the process of responding to a command completion in accordance with a target delay according to an embodiment of the present disclosure.

[0021] Figure 10 This is a flowchart illustrating a process of delaying the response to a command completion according to an embodiment of the present disclosure.

[0022] Figure 11 This is a flowchart illustrating the process of periodically calculating the delay and delaying the command completion response according to an embodiment of the present disclosure.

[0023] Figure 12 This is a diagram illustrating a memory controller according to an embodiment of the present disclosure.

[0024] Figure 13 This is a diagram illustrating a memory card system using a storage device according to an embodiment of the present disclosure.

[0025] Figure 14 This is a diagram illustrating an example of a solid-state drive (SSD) system that applies a memory system according to an embodiment of the present disclosure.

[0026] Figure 15 This is a diagram illustrating a user system that applies a memory system according to an embodiment of the present disclosure. Detailed Implementation

[0027] The specific structural or functional descriptions of the embodiments of this disclosure described herein are provided as examples to illustrate embodiments based on the concept of this disclosure. Embodiments based on the concept of this disclosure may be practiced in various forms and should not be construed as limited to the embodiments described herein.

[0028] Figure 1 This is a diagram illustrating a memory system 100 according to an embodiment of the present disclosure.

[0029] Reference Figure 1 The memory system 100 may include a memory device 110 and a memory controller 200.

[0030] The memory system 100 may be a device that stores data under the control of a host 400 such as a mobile phone, smartphone, MP3 player, laptop computer, desktop computer, game console, TV, tablet PC, or in-vehicle infotainment system.

[0031] Depending on the host interface used for communication with host 400, memory system 100 can be manufactured as any of a variety of storage devices. For example, memory system 100 can be implemented as any of the following types of storage devices: solid-state drives (SSDs), multimedia cards such as MMC, embedded MMC (eMMC), size-reduced MMC (RS-MMC), or micro-MMC, secure digital cards such as SD, mini-SD, or micro SD, universal serial bus (USB) storage devices, universal flash memory (UFS) devices, PCMCIA card-type storage devices, peripheral component interconnect (PCI) card-type storage devices, high-speed PCI (PCI-E) card-type storage devices, compact flash memory (CF) cards, smart media cards, and memory sticks.

[0032] The memory system 100 can be manufactured in any of a variety of package types. For example, the memory system 100 can be manufactured in any of the following package types: POP (Package-on-Package), SIP (System-in-Package), SOC (System-on-Chip), MCP (Multi-Chip Package), COB (Chip-on-Board), WFP (Wafer-Level Fabrication Package), and WSP (Wafer-Level Stacked Package).

[0033] Memory device 110 can store data. Memory device 110 can operate under the control of memory controller 200. Memory device 110 may include a memory cell array comprising a plurality of memory cells for storing data. The memory cell array may include a plurality of memory blocks. Each memory block may include a plurality of memory cells. A memory cell may include a plurality of pages. In embodiments, a page may be a unit for storing data in or reading stored data from memory device 110. A memory block may be a unit for erasing data. In embodiments, memory device 110 may take many alternative forms, such as Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM), Generation 4 Low Power Double Data Rate (LPDDR4) SDRAM, Graphics Double Data Rate (GDDR) SDRAM, Low Power DDR (LPDDR), Rambus Dynamic Random Access Memory (RDRAM), NAND Flash Memory, Vertical NAND Flash Memory, NOR Flash Memory, Resistive RAM (RRAM), Phase Change RAM (PRAM), Magnetoresistive RAM (MRAM), Ferroelectric RAM (FRAM), or Spin-Torque RAM (STT-RAM). For ease of description, this specification will describe memory device 110 as NAND flash memory.

[0034] In an embodiment, the memory system 100 may be implemented as a three-dimensional (3D) array structure. This disclosure is applicable not only to flash memory devices where the charge storage layer is formed by conductive floating gates (FGs), but also to charge-fetch flash memory (CTF) devices where the charge storage layer is formed by insulating layers.

[0035] In an embodiment, the memory cell included in the memory device 110 may be implemented as a single-level cell (SLC) capable of storing one data bit. Alternatively, each of the memory cells included in the memory device 110 may be implemented as a multi-level cell (MLC) capable of storing two data bits, a three-level cell (TLC) capable of storing three data bits, or a four-level cell (QLC) capable of storing four data bits.

[0036] Memory device 110 can receive commands and addresses from memory controller 200 and can access a region in the memory cell array selected by the address. That is, memory device 110 can perform an operation corresponding to the command on the region selected by the address. For example, memory device 110 can perform write operations (i.e., programming operations), read operations, and erase operations. During a programming operation, memory device 110 can program data into the region selected by the address. During a read operation, memory device 110 can read data from the region selected by the address. During an erase operation, memory device 110 can erase data stored in the region selected by the address.

[0037] The memory controller 200 can control all operations of the memory system 100.

[0038] When power is applied to the memory system 100, the memory controller 200 can run firmware (FW). In the case that the memory device 110 is a flash memory device, the memory controller 200 can run firmware such as a flash translation layer (FTL) to control communication between the host 400 and the memory device 110.

[0039] In this embodiment, the memory controller 200 can receive data and logical block addresses (LBAs) from the host 400, and can convert the LBAs into physical block addresses (PBAs), which indicate the addresses of memory cells in the memory device 110 containing the data to be stored. Furthermore, the memory controller 200 can store a logical-physical address mapping table configuring the mapping relationship between logical block addresses (LBAs) and physical block addresses (PBAs) in a buffer memory (not shown).

[0040] The memory controller 200 can control the memory device 110 to perform programming, reading, or erasing operations in response to requests from the host 400. During a programming operation, the memory controller 200 can provide a write command, a physical block address (PBA), and data to the memory device 110. During a read operation, the memory controller 200 can provide a read command and a physical block address (PBA) to the memory device 110. During an erasing operation, the memory controller 200 can provide an erase command and a physical block address (PBA) to the memory device 110.

[0041] The memory controller 200 may include a performance controller 210 and an operation controller 220.

[0042] In this embodiment, performance controller 210 can provide a completion response to a command requested by host 400. The command requested by host 400 can be a read command or a write command. When host 400 provides a command, memory controller 200 can control memory device 110 to process the command. When memory controller 200 completes processing the command from host 400, performance controller 210 within the memory controller can provide a command completion response to host 400. Here, performance controller 210 can delay providing the command completion response to host 400.

[0043] In an embodiment, the operation controller 220 can determine the state of the memory device 110. The state of the memory device 110 can be determined based on the number of free blocks among the plurality of memory blocks included in the memory device 110. Such free blocks can be memory blocks among the plurality of memory blocks that do not store data.

[0044] In this embodiment, the operation controller 220 can monitor latency based on the state of the memory device 110. Latency can be the time required from the point in time the host 400 provides a command to the point in time the performance controller 210 provides a completion response to the command. Further, the operation controller 220 can count the number of times over-latency occurs. Over-latency can be a latency longer than a preset reference value. Furthermore, the operation controller 220 can determine whether to delay the command completion response based on the number of over-latency occurrences. The operation controller 220 can provide information about whether to delay the command completion response and the degree of delay to the performance controller 210.

[0045] In some embodiments, memory system 100 may include a buffer memory (not shown). For example, the buffer memory may temporarily store data received from host 400 or data received from memory device 110, or it may temporarily store metadata (e.g., a mapping table) of memory device 110. The buffer memory may include volatile memory such as DRAM, SDRAM, DDR SDRAM, LPDDR SDRAM, and GRAM, or non-volatile memory such as FRAM, ReRAM, STT-MRAM, and PRAM. The buffer memory (not shown) may include a target latency information storage device (not shown). In various embodiments, memory system 200 may not include a buffer memory (not shown). In this case, a volatile memory device located outside memory system 200 may be used as the buffer memory (not shown).

[0046] The host 400 can communicate with the memory system 100 using at least one of the following communication methods: Universal Serial Bus (USB), Serial AT Accessory (SATA), Serial SCSI (SAS), High Speed ​​Chip Interconnect (HSIC), Small Computer System Interface (SCSI), Peripheral Component Interconnect (PCI), High Speed ​​PCI (PCIe), High Speed ​​Non-Volatile Memory (NVMe), Universal Flash Memory (UFS), Secure Digital (SD), Multimedia Card (MMC), Embedded MMC (eMMC), Dual In-line Memory Module (DIMM), Registered DIMM (RDIMM), Low Load DIMM (LRDIMM), and Inter-Integrated Circuit (I2C) communication using System Management Bus (SM-BUS).

[0047] Figure 2 This illustrates an embodiment according to the present disclosure. Figure 1 A diagram of the firmware for the memory controller.

[0048] When power is applied to the memory system, the memory controller 200 can run firmware (FW). In the case that the memory device 110 is a flash memory device, the firmware (FW) may include: a host interface layer (HIL) that controls communication with the host; a flash translation layer (FTL) that controls communication between the host and the memory device 110; and a flash interface layer (FIL) that controls communication with the memory device 110. The flash interface layer (FIL) may be a memory interface.

[0049] In one embodiment, performance controller 210 may be included in the host interface layer (HIL). Performance controller 210 may delay the command completion response to be provided to the host while communicating with the host.

[0050] In an embodiment, the operation controller 220 may be included in a flash translation layer (FTL). When the host provides a logical block address (LBA) and a command, the flash translation layer (FTL) can translate the logical block address into a physical block address and control communication with the memory device 110 to perform operations corresponding to the translated physical block address. Further, a flash interface layer (FIL) can provide an interface between the host and the memory device 110, thereby enabling efficient use of the memory device 110. For example, the flash translation layer (FTL) can translate a logical address received from the host into a physical address used in the memory device 110. Furthermore, the flash translation layer (FTL) can internally generate write commands, addresses, and data without receiving a request from the host, and can transmit write commands, addresses, and data to the memory device 110. For example, the memory controller 200 can provide commands, addresses, and data required to perform background operations such as programming operations for wear leveling and programming operations for garbage collection (GC) to the memory device 110.

[0051] Figure 3 This is a diagram illustrating the structure and operation of a memory controller according to an embodiment of the present disclosure.

[0052] Reference Figure 3 The memory controller 200 may include a status controller 230, a delay monitoring component 240, and a completion response controller 250.

[0053] In this embodiment, the state controller 230 can determine the state of the memory device. The state controller 230 can determine the state of the memory device 110 based on the number of free blocks among the plurality of memory blocks included in the memory device. Such free blocks can be memory blocks among the plurality of memory blocks in the memory device that do not store data. When the number of free blocks is less than a reference value, the state controller 230 can determine the state of the memory device as a maintenance state. The reference value can be a preset value. When the number of free blocks is less than the reference value, a garbage collection (GC) operation can be initiated. Further, the maintenance state can be a state in which garbage collection (GC) is performed to store data. When the state of the memory device is determined, the state controller 230 can provide state information indicating the state of the memory device to the latency monitoring component 240.

[0054] The delay monitoring component 240 can receive status information from the status controller 230. The delay monitoring component 240 can receive status information indicating that the memory device 110 is in a sustaining state. When the memory device is in the sustaining state, the delay monitoring component 240 can measure the delay for a preset time (first time period). The measurement time point and duration can be preset. During this process, the delay monitoring component 240 can count the number of over-delay events, which are delays exceeding a preset reference value. Furthermore, the delay monitoring component 240 can provide information about the number of over-delay events to the completion response controller 250.

[0055] The delay monitoring component 240 can measure the delay over a preset time and provide information about the number of times the delay occurs to the completion response controller 250. The above operation can then be repeated within a preset time (second time period). The preset duration of the second time period can be equal to the preset duration of the first time period. Similarly, the delay monitoring component 240 can repeat the above operation within a third time period. The preset duration of the third time period can be equal to the preset duration of the second time period. The above operation can be repeated within an nth time period, and the preset duration of the nth time period can be equal to the preset duration of the (n-1)th time period. Here, n can be a natural number.

[0056] Unless the memory device is in a sustained state, the delay monitoring component 240 may not perform the operations of measuring delay and counting the number of times over-delay occurs.

[0057] The completion response controller 250 can receive information about the number of times over-delay occurs from the latency monitoring component 240. The completion response controller 250 can determine whether to delay the command completion response to be provided to the host based on the number of over-delay occurrences. Furthermore, the completion response controller 250 can determine the degree of delay in the command completion response to be provided to the host. The degree of delay in the command completion response can be proportional to the number of over-delay occurrences.

[0058] The response controller 250 can receive information about the target delay from the target delay information storage device 120. The target delay can be a delay determined based on the number of times over-delay occurs. Furthermore, the target delay can be a pre-stored value. (Refer to the following...) Figures 4 to 6 Describe the details of the target delay.

[0059] The completion response controller 250 can essentially delay the command completion response to limit performance in the sustain state. The delay measured during this process can be the average delay.

[0060] The completion response controller 250 can determine the target latency based on information about the number of times over-latency has occurred and target latency information. Once the target latency is determined, the level of performance delay required to maintain the target latency can be determined. In an embodiment, when the completion response wait time (the time from when the command is received from the host to when a completion response is provided to the command) is shorter than the target latency, the completion response controller 250 can delay the completion response by the difference between the target latency and the completion response wait time. When the completion response wait time is longer than the target latency, the completion response controller 250 can immediately provide a command completion response to the host.

[0061] Although the target delay information storage device 120 is shown as being located outside the memory controller 200, it can also be located inside the memory control device 200. The target delay information storage device 120 can store parameters determined based on the number of over-delay occurrences. Furthermore, the target delay information storage device 120 can pre-store a target delay determined based on the number of over-delay occurrences. The target delay can be determined based on the parameters determined based on the number of over-delay occurrences. The target delay information storage device 120 can provide the target delay information to the completion response controller 250. The completion response controller 250 can determine the target delay based on the target delay information and the number of over-delay occurrences.

[0062] Figure 4 This is a diagram illustrating parameters determined based on the number of over-delay occurrences according to an embodiment of the present disclosure.

[0063] Reference Figure 4 This allows you to examine the relationships between the parameters used to determine the target delay.

[0064] The parameters used to determine the target latency can be a first weight K1 and a second weight K2. The first weight can be the parameter to be multiplied by the average latency. Furthermore, the second weight can be the parameter to be multiplied by the maximum latency. The average latency can be the latency occurring on average during the maintenance state. The maximum latency can be the latency required to achieve performance corresponding to the minimum performance required by the host request.

[0065] The first and second weights can be determined based on the number of times over-delay occurs. The values ​​of the first and second weights corresponding to the number of over-delay occurrences can be preset values. (Refer to...) Figure 4 In the table, when the number of over-latency occurrences is less than a1, the value of the first weight can be 1, and the value of the second weight can be 0. When the number of over-latency occurrences is less than a1, no additional performance delay may occur.

[0066] When the number of over-delay occurrences is equal to or greater than a1 and less than a2, the first weight to be multiplied by the average delay can be x1. Furthermore, the second weight to be multiplied by the maximum delay can be y1. When the number of over-delay occurrences is equal to or greater than a2 and less than a3, the first weight to be multiplied by the average delay can be x2. Furthermore, the second weight to be multiplied by the maximum delay can be y2. When the number of over-delay occurrences is equal to or greater than a3 and less than a4, the first weight to be multiplied by the average delay can be x3. Furthermore, the second weight to be multiplied by the maximum delay can be y3. When the number of over-delay occurrences is equal to or greater than a4 and less than a5, the first weight to be multiplied by the average delay can be x4. Furthermore, the second weight to be multiplied by the maximum delay can be y4. Similarly, when the number of over-delay occurrences is equal to or greater than a5, the first weight to be multiplied by the average delay can be 0. Furthermore, the second weight to be multiplied by the maximum delay can be 1.

[0067] The value of the first weight can be decreased proportionally to the number of times over-delay occurs. Conversely, the value of the second weight can be increased proportionally to the number of times over-delay occurs. Therefore, the values ​​of the first weight, x1, x2, x3, and x4, can be values ​​from 0 to 1, where the value of x1 can be greater than the value of x4. Similarly, the values ​​of the second weight, y1, y2, y3, and y4, can be values ​​from 0 to 1, where the value of y4 can be greater than the value of y1. Information regarding the first and second weights can be pre-stored in a target delay information storage device.

[0068] For ease of description, although the entire period is described as being roughly divided into six parts based on the number of times over-delay occurs, it will be understood that the number of parts can be changed, and the entire period can be divided into more densely or sparsely set parts based on the number of times over-delay occurs.

[0069] Figure 5 This illustrates an embodiment according to the present disclosure. Figure 4 A graph showing the relationship between the parameters.

[0070] Reference Figure 5 It can check based on Figure 4 The relationship between the first and second weights is described.

[0071] When the number of over-delay occurrences is less than a1, the value of the first weight can be 1, and the value of the second weight can be 0. In this case, the sum of the values ​​of the first weight and the second weight can be 1. Furthermore, when the number of over-delay occurrences is equal to or greater than a1 and less than a2, the value of the first weight can be x1, and the value of the second weight can be y1. In this case, the sum of the values ​​of the first weight and the second weight can be 1. Additionally, when the number of over-delay occurrences is equal to or greater than a2 and less than a3, the value of the first weight can be x2, and the value of the second weight can be y2. In this case, the sum of the values ​​of the first weight and the second weight can be 1. Furthermore, when the number of over-delay occurrences is equal to or greater than a3 and less than a4, the value of the first weight can be x3, and the value of the second weight can be y3. In this case, the sum of the values ​​of the first weight and the second weight can be 1. Furthermore, when the number of over-delay occurrences is equal to or greater than a4 and less than a5, the value of the first weight can be x4, and the value of the second weight can be y4. In this case, the sum of the values ​​of the first weight and the second weight can be 1. Furthermore, when the number of over-delay occurrences is equal to or greater than a5, the value of the first weight can be 0, and the value of the second weight can be 1. In this case, the sum of the values ​​of the first weight and the second weight can be 1.

[0072] As mentioned above, in all parts, the sum of the values ​​of the first weight and the second weight can be "1". Furthermore, as referenced above... Figure 4 The time-division segments can be set more densely or sparsely depending on the number of times the delay occurs.

[0073] Figure 6 This is a diagram illustrating a target delay determined based on the number of over-delay occurrences according to an embodiment of the present disclosure.

[0074] Reference Figure 6 The diagram illustrates the formula and value for the target latency determined based on the number of times overlatency occurs. Overlatency can be represented by the sum of a value obtained by multiplying a first weight by the average latency and a value obtained by multiplying a second weight by the maximum latency. The average latency can be the average of the latency generated in the sustain state. The maximum latency can be the latency generated to achieve the performance corresponding to the minimum performance requested by the host.

[0075] In an embodiment, when the number of over-latency occurrences is between 0 and a1, the value of the first weight can be 1. Further, the value of the second weight can be 0. Therefore, the target latency calculated by adding the value obtained by multiplying the first weight 1 by the average latency to the value obtained by multiplying the second weight 0 by the maximum latency can be the average latency latency_avg.

[0076] In this embodiment, when the number of over-latency occurrences is between a1 and a2, the value of the first weight can be x1. Furthermore, the value of the second weight can be y1. Therefore, the target latency, calculated by adding the value obtained by multiplying the first weight x1 by the average latency to the value obtained by multiplying the second weight y1 by the maximum latency, can be x1*latency_avg + y1*latency_max.

[0077] In this embodiment, when the number of over-latency occurrences is between a2 and a3, the value of the first weight can be x2. Furthermore, the value of the second weight can be y2. Therefore, the target latency, calculated by adding the value obtained by multiplying the first weight x2 by the average latency to the value obtained by multiplying the second weight y2 by the maximum latency, can be x2*latency_avg + y2*latency_max.

[0078] In this embodiment, when the number of over-latency occurrences is between a3 and a4, the value of the first weight can be x3. Furthermore, the value of the second weight can be y3. Therefore, the target latency, calculated by adding the value obtained by multiplying the first weight x3 by the average latency to the value obtained by multiplying the second weight y3 by the maximum latency, can be x3*latency_avg + y3*latency_max.

[0079] In this embodiment, when the number of over-latency occurrences is between a4 and a5, the value of the first weight can be x4. Furthermore, the value of the second weight can be y4. Therefore, the target latency, calculated by adding the value obtained by multiplying the first weight x4 by the average latency to the value obtained by multiplying the second weight y4 by the maximum latency, can be x4*latency_avg + y4*latency_max.

[0080] Similarly, in the embodiment, when the number of over-latency occurrences is equal to or greater than a5, the value of the first weight can be 0. Furthermore, the value of the second weight can be 1. Therefore, the target latency calculated by adding the value obtained by multiplying the first weight 0 by the average latency to the value obtained by multiplying the second weight 1 by the maximum latency can be the maximum latency_max.

[0081] The target delay value can be a predefined value based on the number of times over-delay occurs. For example... Figure 6 As shown, the target delay values ​​can be stored in the form of a table. This table of target delay values ​​can be stored in a target delay information storage device. Although for ease of description, the entire time period is divided into six parts based on the number of delay occurrences, the number of parts can be changed according to settings, and the target delay values ​​corresponding to these parts can also be changed.

[0082] Figure 7It is a graph showing the ratio between the number of over-delay occurrences and the target delay according to an embodiment of the present disclosure.

[0083] Reference Figure 7 The target latency value can be increased proportionally to the number of times overlatency occurs. When the memory device enters a sustaining state, garbage collection (GC) operations can be performed, and the processing of commands provided by the host can be delayed. Therefore, when the memory device enters a sustaining state, a target latency can be set, and the command completion response can be delayed based on the target latency.

[0084] When the number of latency occurrences is less than a1, the target latency can be the average latency `latency_avg`. That is, aside from the average performance limitations that occur in the sustain state, no additional performance limitations may occur. In this case, the memory controller can provide the command completion response to the host based on the average latency `latency_avg`.

[0085] When the number of over-latency occurrences equals or exceeds a1, the target latency can increase proportionally to the number of over-latency occurrences. When the number of over-latency occurrences equals or exceeds a1, the target latency becomes greater than the average latency. In this case, additional performance constraints may arise in order to maintain the latency generated in response to commands provided by the host at the target latency. That is, the moment when the number of over-latency occurrences equals or exceeds a1 may be the trigger point for additional performance constraints (i.e., additional throttling).

[0086] When the number of latency occurrences is equal to or greater than a5, the target latency can be the maximum latency `latency_max`. In this case, additional performance constraints may arise to keep the latency in response to commands provided by the host within the target latency. Since the target latency should not exceed the maximum latency, a maximum performance constraint may also exist. That is, the memory controller can provide the command completion response to the host based on the maximum latency `latency_max`.

[0087] like Figure 7 As shown, for ease of description, although a graph with continuous values ​​has been depicted to indicate the proportional relationship between the target delay and the number of over-delay occurrences, the target delay can be a constant value determined based on the portion corresponding to the number of over-delay occurrences. Furthermore, as referenced above... Figure 7 As described, the target latency can be increased proportionally to the number of times over-latency occurs, rather than being determined based on the number of times over-latency occurs.

[0088] Figure 8 This is a diagram illustrating the process of counting the number of times an over-delay occurs beyond a reference delay according to an embodiment of the present disclosure.

[0089] Reference Figure 8 This illustrates the concept of latency for commands provided within a preset reference time (first time period) and the process of counting the number of over-latency occurrences. When the memory device is in a hold state, the latency monitoring component can measure the latency of commands provided within the reference time. The reference time can have a preset duration. During this process, the number of over-latency occurrences exceeding the reference latency tref can be counted.

[0090] In this embodiment, the host can provide a processing request for command 1 to the memory system. That is, when the host provides command 1 (CMD_1IN), the memory system can process the corresponding command and provide a completion response (COMP_C1OUT) to the host. The time required from the time the host provides command 1 to the time the completion response is provided can be the delay tL1 of command 1. During this process, the delay monitoring component 240 can compare the delay tL1 of command 1 with a reference delay tref. The reference delay tref can be a preset value. Since the value of the delay tL1 of command 1 is greater than the value of the reference delay tref, the delay tL1 of command 1 can be counted as an over-delay.

[0091] While processing command 1, or after receiving a completion response (COMP_C1OUT) for command 1, the host can provide a processing request for command 2 to the memory system. That is, when the host provides command 2 (CMD_2IN), the memory system can process the corresponding command and provide a completion response (COMP_C2OUT) for command 2 to the host. The time required from the time the host provides command 2 to the time the completion response for command 2 is provided can be the delay tL2 of command 2. During this process, the delay monitoring component 240 can compare the delay tL2 of command 2 with a reference delay tref. The value of the reference delay tref to be compared with the delay of command 2 can be equal to the value of the reference delay tref compared with the delay of command 1. Since the value of the delay tL2 of command 2 is greater than the value of the reference delay tref, the delay tL2 of command 2 can be counted as an over-delay.

[0092] While processing command 2, or after receiving a completion response (COMP_C2OUT) for command 2, the host can request the processing of command 3 to the memory system. That is, when the host provides command 3 (CMD_3IN), the memory system can process the corresponding command and provide a completion response (COMP_C3OUT) for command 3 to the host. The time required from the time the host provides command 3 to the time the completion response for command 3 is provided can be the delay tL3 of command 3. During this process, the delay monitoring component can compare the delay tL3 of command 3 with a reference delay tref. The value of the reference delay tref to be compared with the delay of command 3 can be equal to the value of the reference delay tref compared with the delay of command 1. Since the value of the delay tL3 of command 3 is greater than the value of the reference delay tref, the delay tL3 of command 3 can be considered as an over-delay.

[0093] While processing command 3, or after receiving a completion response (COMP_C3OUT) for command 3, the host can provide a request to the memory system to process command 4. That is, when the host provides command 4 (CMD_4IN), the memory system can process the corresponding command and provide a completion response (COMP_C4OUT) for command 4 to the host. The time required from the time the host provides command 4 to the time the completion response for command 4 is provided can be the delay tL4 of command 4. During this process, the delay monitoring component can compare the delay tL4 of command 4 with a reference delay tref. The value of the reference delay tref to be compared with the delay of command 4 can be equal to the value of the reference delay tref compared with the delay of command 1. Since the value of the delay tL4 of command 4 is less than the value of the reference delay tref, the delay tL4 of command 4 can not be counted as an over-delay.

[0094] While processing command 4, or after receiving a completion response (COMP_C4OUT) for command 4, the host can provide a request to the memory system to process command 5. That is, when the host provides command 5 (CMD_5IN), the memory system can process the corresponding command and provide a completion response (COMP_C5OUT) for command 5 to the host. The time required from the time the host provides command 5 to the time the completion response for command 5 is provided can be the delay tL5 of command 5. During this process, the delay monitoring component can compare the delay tL5 of command 5 with a reference delay tref. The value of the reference delay tref to be compared with the delay of command 5 can be equal to the value of the reference delay tref compared with the delay of command 1. Since the value of the delay tL5 of command 5 is greater than the value of the reference delay tref, the delay tL5 of command 5 can be counted as an over-delay.

[0095] Similarly, while processing command 5, or after receiving a completion response (COMP_C5OUT) for command 5, the host can provide a processing request for command 6 to the memory system. That is, when the host provides command 6 (CMD_6IN), the memory system can process the corresponding command and provide a completion response (COMP_C6OUT) for command 6 to the host. The time required from the time the host provides command 6 to the time the completion response for command 6 is provided can be the delay tL6 of command 6. During this process, the delay monitoring component can compare the delay tL6 of command 6 with a reference delay tref. The value of the reference delay tref to be compared with the delay of command 6 can be equal to the value of the reference delay tref compared with the delay of command 1. Since the value of the delay tL6 of command 6 is greater than the value of the reference delay tref, the delay tL6 of command 6 can be counted as an over-delay.

[0096] The latency monitoring component 240 can store information about the number of times (i.e., 5 times) latency occurred during the processing of six commands provided from the host within a reference time (first time period). Furthermore, the latency monitoring component can provide information about the number of times latency occurred within the reference time to the completion response controller. Each of the commands provided from the host can be a read command or a write command.

[0097] The latency monitoring component can monitor the latency of commands provided within a reference time (first time period), and then monitor the latency of commands provided within a reference time (second time period) after the first time period. The latency monitoring process can continue until the memory device is no longer in a sustained state. That is, the latency monitoring component can repeatedly perform the latency monitoring operation when a garbage collection (GC) operation is performed on the memory device. Here, the duration of the next time period can be equal to the duration of the previous time period. Similarly, the latency monitoring component can provide information about the number of times over-latency occurred for each time period to the completion response controller.

[0098] Figure 9 This is a diagram illustrating the process of responding to a command completion in accordance with a target delay according to an embodiment of the present disclosure.

[0099] Reference Figure 9 This illustrates the process of implementing additional performance constraints to meet preset target latency.

[0100] The completion response controller 250 can determine the target delay to be applied in the second time period based on information received from the delay monitoring component regarding the number of over-delay occurrences within the first time period and target delay information received from the target delay information storage device. When the target delay is determined, the completion response controller can provide a completion response according to the target delay control command.

[0101] The completion response controller can delay the provision of the completion response for each command through average performance limits (default throttling) and additional performance limits (additional throttling). When processing of a command provided from the host is complete, the completion response controller can compare the completion response wait time with the target latency. Subsequently, if the target latency is longer than the completion response wait time, the completion response controller can delay the provision of the completion response to the command by the difference between the target latency and the completion response wait time. Alternatively, if the target latency is shorter than the completion response wait time, the completion response controller can immediately provide the completion response to the command to the host without performance throttling. In this case, the average performance limit (i.e., default throttling) can be a performance limit imposed to keep the target latency within the average latency_avg.

[0102] In this embodiment, during a reference time following the first time period (i.e., the second time period), the host may provide a processing request for command 1' to the memory system. That is, when the host provides command 1' (CMD_1'IN), the memory system 100 can process the corresponding command and provide a completion response (COMP_C1'OUT) to the host. The completion response controller may delay the completion response (COMP_C1'OUT) to command 1' such that the delay tL1' of command 1' equals the target delay. In other words, after processing of command 1' is completed, the completion response (COMP_C1'OUT) to command 1' is not immediately provided to the host, and its provision can be delayed through performance limiting (throttling). Even when processing of command 1' is completed, the completion response controller may delay the provision of the completion response to command 1' through average performance limiting (default throttling). Since the target delay is not reached even after default throttling occurs, the completion response controller may implement additional performance limiting (additional throttling). After delaying the completion response to command 1' by the difference between the target delay and the completion response wait time, the completion response to command 1' (COMP_C1'OUT) can be provided to the host. In this case, the delay tL1' of command 1' and the target delay can be equal to each other.

[0103] While processing command 1', or after receiving a completion response (COMP_C1'OUT) for command 1', the host can provide a processing request for command 2' to the memory system. That is, when the host provides command 2' (CMD_2'IN), the memory system can process the corresponding command and provide a completion response (COMP_C2'OUT) for command 2' to the host. The completion response controller can control the completion response (COMP_C2'OUT) for command 2' such that the latency tL2' of command 2' equals the target latency. When processing of command 2' is delayed and the completion response wait time for command 2' is longer than the target latency, the completion response controller can immediately provide a completion response (COMP_C2'OUT) for command 2' to the host without performance limitations. In this case, the latency tL2' of command 2' can be a value greater than the target latency.

[0104] While processing command 2', or after receiving a completion response (COMP_C2'OUT) for command 2', the host can provide a processing request for command 3' to the memory system. That is, when the host provides command 3' (CMD_3'IN), the memory system can process the corresponding command and provide a completion response (COMP_C3'OUT) for command 3' to the host. The completion response controller can delay the completion response (COMP_C3'OUT) for command 3', such that the latency tL3' of command 3' equals the target latency. In other words, after processing command 3' is complete, the completion response (COMP_C3'OUT) for command 3' is not immediately provided to the host, and its provision can be delayed through performance limiting (throttling). Even when processing command 3' is complete, the completion response controller can delay the provision of the completion response for command 3' through average performance limiting (default throttling). Since the target latency is not reached even after default throttling, the completion response controller can implement additional performance constraints (additional throttling). After delaying the completion response to command 3' by the difference between the target latency and the completion response wait time, the completion response to command 3' (COMP_C3'OUT) can be provided to the host. In this case, the latency tL3' of command 3' and the target latency can be equal to each other.

[0105] While processing command 3', or after receiving a completion response (COMP_C3'OUT) for command 3', the host can provide a processing request for command 4' to the memory system. That is, when the host provides command 4' (CMD_4'IN), the memory system can process the corresponding command and provide a completion response (COMP_C4'OUT) for command 4' to the host. However, processing of command 4' may not be completed within the reference time (second period).

[0106] During the process of processing commands provided from the host and providing completion responses to the commands within the reference time (second time period), the latency monitoring component can monitor the latency tL1' to tL3' of commands 1' to 3'. In this process, the latency monitoring component can compare the latency tL1' to tL3' of commands 1' to 3' with a reference latency. The latency monitoring component can compare the reference latency tref with the latency tL1' to tL3' of commands 1' to 3', and can count the number of times over-latency occurs that is greater than the reference latency tref. The reference latency can be equal to the reference latency tref used as the comparison target for the reference time (first time period). Since the latency tL1' to tL3' of commands 1' to 3' is all greater than the reference latency tref, the number of over-latency occurrences within the reference time (second time period) can be 3. The latency monitoring component can provide information about the number of over-latency occurrences within the reference time (second time period) to the completion response controller.

[0107] As the target latency increases, the time required to provide a completion response to a corresponding command may increase. Even if the processing of a command is completed quickly, the completion response controller may not provide a command completion response through default throttling and additional throttling. When the determined target latency value is greater than the reference latency tref value, all latency of commands to be provided in the next time period can be counted as overlatencies. However, the number of commands to be provided can decrease as the target latency increases. When the number of commands to be provided decreases, the number of overlatencies may also decrease. As the number of overlatencies decreases, the target latency can also decrease proportionally. As the target latency decreases, the degree of performance constraint may also decrease. Through the above process, the completion response to a command can be provided to the host according to a certain latency, thereby improving the reliability of the host.

[0108] Figure 10 This is a flowchart illustrating a process of delaying the response to a command completion according to an embodiment of the present disclosure.

[0109] Reference Figure 10 In operation S1001, the memory controller can determine whether the memory device is currently in a sustaining state. The sustaining state can be determined based on the number of free blocks among the multiple memory blocks included in the memory device. Each free block can be a block that does not store data. When the number of free blocks is less than a reference value, a garbage collection (GC) operation can be performed, thereby allowing efficient use of the memory device. In this case, the memory controller can provide status information indicating that the memory device is in a sustaining state.

[0110] In operation S1003, when the memory device is in a sustaining state, the memory controller can count the number of times over-delay occurs. Over-delay can be a delay greater than a preset reference delay tref. The memory controller can count the number of times over-delay occurs within a reference time (the nth time period) and can provide information about the number of over-delay occurrences.

[0111] In operation S1005, the memory controller can determine the target delay based on information about the number of times over-delay has occurred and the target delay information.

[0112] In operation S1007, the memory controller can compare the target delay with the completion response wait time. The completion response wait time can be the time required from the time the host receives the corresponding command to the time before the completion response to the command is provided. The memory controller can compare the target delay with the completion response wait time of a command provided within the reference time (the (n+1)th time period) and can determine whether to delay the completion response to the command.

[0113] In operation S1009, the memory controller 200 can delay the provision of the command completion response to the host based on a comparison between the target delay and the completion response waiting time. When the target delay is longer than the command completion response waiting time, the memory controller can delay the provision of the command completion response by the difference between the target delay and the completion response waiting time. Through this process, the delay of the corresponding command can be equal to the target delay.

[0114] In operation S1011, the memory controller 200 can immediately provide a command completion response to the host based on a comparison between the target delay and the completion response wait time. When the completion response wait time is longer than the target delay, the memory controller can immediately provide a command completion response to the host. Here, the delay of the corresponding command can be equal to or greater than the target delay.

[0115] When the memory device is not in a sustained state, garbage collection (GC) is not performed, allowing commands to be processed without performance limitations (throttling). Therefore, the above process can be omitted when the memory device is not in a sustained state.

[0116] Figure 11 This is a flowchart illustrating the process of periodically calculating the delay and the delayed command completion response according to an embodiment of the present disclosure.

[0117] Reference Figure 11In operation S1101, the memory controller can count the number of times over-delay occurs within the reference time (the nth time period) and calculate a target delay based on the number of over-delay occurrences. The completion response to a command provided within the reference time (the (n+1th time period) can be provided based on the target delay, which is determined according to the number of over-delay occurrences within the reference time (the nth time period).

[0118] In operation S1103, the memory controller may delay providing a completion response to a command provided within a reference time (the (n+1)th time period). This process may include comparing the target delay with the completion response waiting time for each command and providing a command completion response based on the comparison result.

[0119] In operation S1105, the memory controller can count the number of times that the delay of a command provided within the reference time (the (n+1)th time period) exceeds the reference delay tref, and then calculate the target delay. Operations S1103 and S1105 can be executed simultaneously.

[0120] In operation S1107, the memory controller can determine whether the memory device is in a sustaining state. If it is determined that the memory device is not in a sustaining state, no additional throttling is required, and the process can be terminated. On the other hand, if it is determined that the memory device is in a sustaining state, in operation S1109, operations S1101 to S1107 can be repeated during the (n+1)th and (n+2)th time periods. During this process, the durations of the (n+1)th and (n+2)th time periods can be equal to the durations of the (n)th and (n+1)th time periods.

[0121] Figure 12 This is a diagram illustrating a memory controller 1200 according to an embodiment of the present disclosure.

[0122] The memory controller 1200 is coupled to the host and the memory device. In response to a request from the host, the memory controller 1200 can access the memory device. For example, the memory controller 1200 can control write operations, read operations, erase operations, and background operations of the memory device. The memory controller 1200 provides an interface between the memory device and the host. The memory controller 1200 can run firmware for controlling the memory device.

[0123] Reference Figure 12 The memory controller 1200 may include a processor 1210, a memory buffer 1220, an error correction (Error Correction Code: ECC) circuit 1230, a host interface 1240, a buffer control circuit 1250, a memory interface 1260, and a bus 1270.

[0124] Bus 1270 can provide a channel between components of memory controller 1200.

[0125] Processor 1210 can control all operations of memory controller 1200 and execute logical operations. Processor 1210 can communicate with an external host via host interface 1240 and with memory devices via memory interface 1260. Additionally, processor 1210 can communicate with memory buffer 1220 via buffer control circuitry 1250. Processor 1210 can control the operation of the memory system by using memory buffer 1220 as operational memory, cache memory, or buffer memory.

[0126] Processor 1210 can perform the functions of Flash Translation Layer (FTL). Processor 1210 can use FTL to translate Logical Block Address (LBA) provided by the host into Physical Block Address (PBA).

[0127] Processor 1210 can randomize data received from the host. For example, processor 1210 can use a randomization seed to randomize data received from the host. The randomized data can be provided to the memory device as data to be stored and can be written to the memory cell array.

[0128] Processor 1210 can derandomize data received from the memory device during a read operation. For example, processor 1210 can use a derandomization seed to derandomize data received from the memory device. The derandomized data can then be output to the host.

[0129] In an embodiment, processor 1210 may run software or firmware to perform randomization or derandomization operations.

[0130] Memory buffer 1220 can be used as working memory, cache memory, or buffer memory of processor 1210. Memory buffer 1220 can store code and commands executed by processor 1210. Memory buffer 1220 can store data processed by processor 1210. Memory buffer 1220 may include static RAM (SRAM) or dynamic RAM (DRAM).

[0131] Error correction circuit 1230 can perform error correction. Error correction circuit 1230 can perform error correction code (ECC) encoding based on data to be stored in the memory device via memory interface 1260. ECC-encoded data can be transmitted to the memory device via memory interface 1260. Error correction circuit 1230 can perform ECC decoding on data received from the memory device via memory interface 1260. In this example, error correction circuit 1230 can be included as a component of memory interface 1262 within memory interface 1260.

[0132] The buffer control circuit 1250 can control the memory buffer 1220 under the control of the processor 1210.

[0133] The memory interface 1260 can communicate with the memory device under the control of the processor 1210. The memory interface 1260 can transmit and receive commands, addresses, and data to / from the memory device via channels.

[0134] In an embodiment, the memory controller 1200 may not include the memory buffer 1220 and the buffer control circuit 1250.

[0135] In one embodiment, processor 1210 can control the operation of memory controller 1200 using code. Processor 1210 can load code from a non-volatile memory device (e.g., ROM) disposed in memory controller 1200. In another embodiment, processor 1210 can load code from a memory device via memory interface 1260.

[0136] In this embodiment, the bus 1270 of the memory controller 1200 can be divided into a control bus and a data bus. The data bus can transmit data within the memory controller 1200, and the control bus can transmit control information such as commands and addresses within the memory controller 1200. The data bus and the control bus can be separate from each other and can operate independently without interference. The data bus can be connected to the host interface 1240, the buffer control circuit 1250, the error correction circuit 1230, and the memory interface 1260. The control bus can be connected to the host interface 1240, the processor 1210, the buffer control circuit 1250, the memory buffer 1220, and the memory interface 1260.

[0137] Figure 13 This is a diagram illustrating a memory card system 2000 using a storage device according to an embodiment of the present disclosure.

[0138] Reference Figure 13The memory card system 2000 may include a memory controller 2100, a memory device 2200, and a connector 2300. The memory controller 2100 may be configured as described above. Figure 1 The memory controller 200 described is implemented in the same way.

[0139] In an embodiment, the memory controller 2100 may include components such as RAM, a processor, a host interface, a memory interface, and error correction circuitry.

[0140] The memory controller 2100 and the memory device 2200 can be integrated into a single semiconductor device to form a memory card. For example, the memory controller 2100 and the memory device 2200 can be integrated into a single semiconductor device to form memory cards such as PC cards (i.e., PCMCIA), compact flash (CF) cards, smart media cards (SM or SMC), memory sticks, multimedia cards (MMC, RS-MMC, micro MMC, or eMMC), SD cards (SD, mini SD, micro SD, or SDHC), or universal flash memory (UFS).

[0141] Figure 14 This is a diagram illustrating an example of a solid-state drive (SSD) system 3000 that applies a memory system according to an embodiment of the present disclosure.

[0142] Reference Figure 14 The SSD system 3000 includes a host 3100 and an SSD 3200. The SSD 3200 can exchange signals with the host 3100 through a signal connector 3001 and can be powered through a power connector 3002. The SSD 3200 may include an SSD controller 3210, multiple flash memories 3221 to 322n, an auxiliary power supply 3230, and a buffer memory 3240.

[0143] In this embodiment, the SSD controller 3210 can perform the above-mentioned reference. Figure 1 The functions of the memory controller 200 are described.

[0144] SSD controller 3210 can control multiple flash memories 3221 to 322n in response to signals received from host 3100. In an embodiment, signal SIG may include a signal based on the interface between host 3100 and SSD 3200.

[0145] Auxiliary power supply 3230 can be connected to host 3100 via power connector 3002. Auxiliary power supply 3230 can be powered by host 3100 and can be charged. When the power supply from host 3100 is unstable, auxiliary power supply 3230 can supply power to SSD 3200. In embodiments, auxiliary power supply 3230 can be located inside or outside SSD 3200. For example, auxiliary power supply 3230 can be located within the motherboard and can also provide auxiliary power to SSD 3200.

[0146] Buffer memory 3240 can be used as a buffer memory for SSD 3200. For example, buffer memory 3240 can temporarily store data received from host 3100 or data received from multiple flash memories 3221 to 322n, or it can temporarily store metadata (e.g., a mapping table) of flash memories 3221 to 322n. Buffer memory 3240 can include volatile memory such as DRAM, SDRAM, DDR SDRAM, LPDDR SDRAM, and GRAM, or non-volatile memory such as FRAM, ReRAM, STT-MRAM, and PRAM.

[0147] Figure 15 This is a diagram illustrating a user system that applies a memory system according to an embodiment of the present disclosure.

[0148] Reference Figure 15 The user system 4000 may include an application processor 4100, a memory module 4200, a network module 4300, a storage module 4400, and a user interface 4500.

[0149] Application processor 4100 can run components, operating systems (OS), or user programs included in user system 4000. In embodiments, application processor 4100 may include controllers, interfaces, graphics engines, etc., for controlling components included in user system 4000. Application processor 4100 may be configured as a system-on-a-chip (SoC).

[0150] Memory module 4200 can be used as main memory, working memory, buffer memory, or cache memory of user system 4000. Memory module 4200 may include volatile RAM such as DRAM, SDRAM, DDR SDRAM, DDR2 SDRAM, DDR3 SDRAM, LPDDR SDRAM, LPDDR2 SDRAM, and LPDDR3 SDRAM, or non-volatile RAM such as PRAM, ReRAM, MRAM, and FRAM. In embodiments, application processor 4100 and memory module 4200 may be packaged based on a stacked package (POP) and then configured as a single semiconductor package.

[0151] Network module 4300 can communicate with external devices. In embodiments, network module 4300 may support wireless communications such as Code Division Multiple Access (CDMA), Global System for Mobile Communications (GSM), Wideband CDMA (WCDMA), CDMA-2000, Time Division Multiple Access (TDMA), Long Term Evolution (LTE), WiMAX, Wireless LAN (WLAN), UWB, Bluetooth, or Wi-Fi. In embodiments, network module 4300 may be included in application processor 4100.

[0152] Storage module 4400 can store data. For example, storage module 4400 can store data received from application processor 4100. Optionally, storage module 4400 can transfer data stored in storage module 4400 to application processor 4100. In embodiments, storage module 4400 can be implemented as a non-volatile semiconductor memory device such as phase-change RAM (PRAM), magnetic RAM (MRAM), resistive RAM (RRAM), NAND flash memory, NOR flash memory, or NAND flash memory with a three-dimensional (3D) structure. In embodiments, storage module 4400 can be configured as a removable storage medium (removable drive) such as a memory card or an external drive of user system 4000.

[0153] In an embodiment, the storage module 4400 may include a plurality of non-volatile memory devices, each of which may be configured as described above. Figure 1 The memory device 110 described herein operates in the same manner. The memory module 4400 can operate in the same manner as described above. Figure 1 The memory system 100 described operates in the same manner.

[0154] User interface 4500 may include interfaces for inputting data or instructions to application processor 4100 or for outputting data to external devices. In embodiments, user interface 4500 may include user input interfaces such as keyboards, keypads, buttons, touch panels, touchscreens, touchpads, touch balls, cameras, microphones, gyroscope sensors, vibration sensors, and piezoelectric elements. User interface 4500 may include user output interfaces such as liquid crystal displays (LCDs), organic light-emitting diode (OLED) display devices, active-matrix OLED (AMOLED) display devices, LEDs, speakers, and monitors.

[0155] According to this disclosure, a memory system that provides uniform performance even in a maintenance state and a method for operating the memory system are provided.

[0156] Embodiments of this disclosure have been shown in the accompanying drawings and described in the specification. While specific terminology is used herein, it is for the purpose of describing embodiments of this disclosure only. Therefore, this disclosure is not limited to the embodiments described above, and many variations are possible within the spirit and scope of this disclosure. It will be apparent to those skilled in the art that various modifications can be made based on the technical scope of this disclosure in addition to the embodiments and claims disclosed herein. Furthermore, these embodiments can be combined to form other embodiments.

Claims

1. A memory controller, comprising: A latency monitoring component generates information about the number of times over-latency exceeding a preset reference latency occurs within a first time period, where each latency represents the amount of time required from the time point when the first command is received from the external device to the time point when the completion response to the first command is transmitted to the external device. as well as The completion response controller determines a first target delay based on information about the number of times the over-delay occurs, and provides a completion response to the external device for the second command provided from the external device during a second time period following the first time period, after the first target delay has elapsed. The information is determined using the average delay and the maximum delay among the delays within the first time period.

2. The memory controller according to claim 1, further comprising a target delay information storage device, the target delay information storage device storing target delay information corresponding to the number of times the over-delay occurs, and providing the target delay information to the completion response controller.

3. The memory controller according to claim 1, further comprising a state controller, wherein the state controller provides state information indicating that the memory device is in a sustaining state to the delay monitoring component when the number of free blocks included in the memory device is less than a reference value.

4. The memory controller according to claim 2, wherein, The target delay information includes a delay value that increases proportionally to the number of times the over-delay occurs.

5. The memory controller according to claim 4, wherein, The delay value is between the average delay and the maximum delay. The average latency is generated to achieve average performance in a sustaining state, in which the number of free blocks included in the memory device is less than a reference value, and The maximum latency is generated to achieve the minimum performance required for the external device.

6. The memory controller according to claim 1, wherein, Each of the first command and the second command is one of a read command and a write command.

7. The memory controller according to claim 1, wherein, After the first target delay has elapsed, the completion response controller immediately provides a completion response to the second command when the operation corresponding to the second command is completed.

8. A memory system, comprising: A memory device comprising multiple memory blocks; as well as The memory controller, based on the number of times over-delays exceeding a preset reference delay occur within a first time period, delays the completion response to a second command provided by the host during a second time period following the first time period. Each delay represents the amount of time required from the time the host receives the first command for the memory device to the time the completion response to the first command is provided. The delay in responding to the second command is determined by using the average delay within the first time period and the maximum delay among the delays.

9. The memory system according to claim 8, wherein, The memory controller includes: A target delay information storage device stores target delay information corresponding to the number of times the over-delay occurs; The operation controller generates information about the number of times the over-delay has occurred when the number of free blocks among the memory blocks included in the memory device is less than a reference value; and The performance controller selects a first target delay based on information about the number of times the over-delay occurs and the target delay information, and responds to the completion of the second command based on the first target delay.

10. The memory system according to claim 9, wherein, The target delay information includes a delay value that increases proportionally to the number of times the over-delay occurs.

11. The memory system of claim 10, wherein The delay value is between the average delay and the maximum delay. The average latency is generated in a maintenance state to achieve average performance, in which the number of free blocks is less than the reference value, and The maximum latency is generated to achieve the minimum performance required for the host.

12. The memory system according to claim 9, wherein, When the performance controller extends the completion response wait time beyond the first target time, it will allocate an amount corresponding to the difference between the completion response delay for the second command and the first target delay and the completion response wait time. The completion response waiting time is from the time the host receives the second command to the time when the completion response to the second command is to be provided.

13. The memory system according to claim 11, wherein, When the first target delay is shorter than the completion response waiting time, the performance controller immediately provides a completion response to the second command to the host. The completion response waiting time is from the time the host receives the second command to the time when the completion response to the second command is to be provided.

14. The memory system according to claim 8, wherein, Each of the first command and the second command is one of a read command and a write command.

15. A method of operating a memory controller, the method comprising: The number of times the delay exceeds the preset reference delay within the first time period is counted, where each delay represents the amount of time required from the time point when the first command is received from the external device to the time point when the completion response to the first command is transmitted to the external device. as well as Based on a first target delay determined by the number of occurrences of the over-delay, the average delay of the delay within the first time period, and the maximum delay of the delay, the response to the completion of the second command provided from the external device is delayed in a second time period following the first time period.

16. The method according to claim 15, in, The delay in the completion response includes: Compare the first target delay with the response completion waiting time; and When the first target delay is longer than the completion response waiting time, the amount corresponding to the difference between the completion response delay for the second command and the first target delay and the completion response waiting time is calculated, and... The completion response waiting time is from the time the external device receives the second command to the time when the completion response to the second command is to be provided.

17. The method according to claim 15, wherein, Each of the first command and the second command is one of a read command and a write command.

18. The method according to claim 15, wherein, When the number of free blocks in the memory device controlled by the memory controller is less than a reference value, the number of times over-delay occurs during the first time period is counted.

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