Output control interface for static random access memory

Abstract

This invention discloses an output control interface for static random access memory (SRAM). The output control interface includes an SRAM control detector and an SRAM data controller. The SRAM control detector receives control signals input to the SRAM, determines whether the control signals are stable, and outputs an indication signal accordingly. The SRAM data controller receives the indication signal and the SRAM output data signal output by the SRAM control detector, and outputs an output data signal based on the indication signal. Specifically, in response to determining that the control signal is not stable, the SRAM data controller outputs an output data signal with a preset value. In response to determining that the control signal is stable, the SRAM data controller outputs the SRAM output data signal as the output data signal.

Description

Technical Field

[0001] This invention relates to an output control interface and an output control method, and particularly to an output control interface and an output control method for static random access memory. Background Technology

[0002] Static random access memory (SRAM) is widely used in ASIC design. Generally, in SRAM, external circuitry controls read and write operations via control signals. Because SRAM is volatile memory, the data stored in it disappears when power is cut off. Therefore, the data inside the SRAM is unpredictable after the system powers on. Furthermore, during power-on, before the frequency and control signals stabilize, the SRAM output may become unstable, affecting the operation of related circuits.

[0003] In the post-layout simulation stage of integrated circuit design, the aforementioned unexpected outputs are treated as unknown and propagated backward during the simulation process, causing the simulation results to fail. At this stage, debugging usually requires a lot of time to trace the netlist, and after correcting the error, it also requires a long time to re-execute the gate-level simulation, resulting in unnecessary debugging time. Summary of the Invention

[0004] The technical problem to be solved by the present invention is to provide an output control interface and output control method for static random access memory, which addresses the shortcomings of the prior art.

[0005] To address the aforementioned technical problems, one technical solution adopted by the present invention is to provide an output control interface suitable for Static Random Access Memory (SRAM), comprising an SRAM control detector and an SRAM data controller. The SRAM control detector receives a control signal input to the SRAM and is configured to determine whether the control signal is stable, and output an indication signal accordingly. The SRAM data controller is configured to receive the indication signal and an SRAM output data signal output by the SRAM control detector, and output an output data signal based on the indication signal. Specifically, in response to determining that the control signal is not stable, the SRAM control detector outputs the indication signal to indicate that the control signal is not stable, and the SRAM data controller outputs the output data signal having a preset value. Conversely, in response to determining that the control signal is stable, the SRAM control detector outputs the indication signal to indicate that the control signal is stable, and the SRAM data controller outputs the SRAM output data signal as the output data signal.

[0006] To address the aforementioned technical problems, another technical solution adopted by the present invention is to provide an output control method applicable to static random access memory (SRAM), comprising: configuring an SRAM data controller to receive the indication signal and an SRAM output data signal output by the SRAM; configuring an SRAM control detector to receive a control signal input to the SRAM, and determining whether the control signal is stable, and outputting an indication signal accordingly; in response to determining that the control signal is not stable, configuring the SRAM control detector to output the indication signal to indicate that the control signal is not stable, and configuring the SRAM data controller to output the output data signal having a preset value according to the indication signal; and in response to determining that the control signal is stable, the SRAM control detector to output the indication signal to indicate that the control signal is stable, and configuring the SRAM data controller to output the SRAM output data signal as the output data signal according to the indication signal.

[0007] The beneficial effects of the present invention are that the output control interface and output control method for static random access memory provided by the present invention can eliminate the influence of output instability before the SRAM is used through better control methods, and in particular, can reduce unnecessary debugging time in the simulation stage after circuit layout.

[0008] To further understand the features and technical content of this invention, please refer to the following detailed description and accompanying drawings. However, the drawings provided are for reference and illustration only and are not intended to limit the invention. Attached Figure Description

[0009] Figure 1 This is a circuit layout diagram of the output control interface according to an embodiment of the present invention.

[0010] Figure 2 This is a flowchart of an output control method according to an embodiment of the present invention.

[0011] Figure 3 The circuit layout diagram of the output interface is shown for another embodiment of the present invention.

[0012] Figure 4 This is a flowchart of an output control method according to another embodiment of the present invention.

[0013] Figure 5 This is a signal timing diagram of the output control interface according to another embodiment of the present invention.

[0014] Symbol Explanation

[0015] 12: SRAM

[0016] 10: Output control interface

[0017] 100: SRAM Control Detector

[0018] 102: SRAM Data Controller

[0019] clk: First frequency signal

[0020] ctrl_in: Control signal

[0021] data_in: Input data signal

[0022] Sdata_out: SRAM output data signal

[0023] Sind: Indicator signal

[0024] data_out: Output data signal

[0025] resetn: System reset signal

[0026] pon_rstn: Power reset signal

[0027] hclk: Second frequency signal

[0028] T1, T2, T3, T4: Time periods Detailed Implementation

[0029] The following specific embodiments illustrate the implementation of the "output control interface and output control method for static random access memory" disclosed in this invention. Those skilled in the art can understand the advantages and effects of this invention from the content disclosed in this specification. This invention can be implemented or applied through other different specific embodiments, and various details in this specification can also be modified and changed based on different viewpoints and applications without departing from the concept of this invention. Furthermore, the accompanying drawings of this invention are for simple illustrative purposes only and are not depictions of actual dimensions, as stated in advance. The following embodiments will further describe the relevant technical content of this invention in detail, but the disclosed content is not intended to limit the scope of protection of this invention. In addition, the term "or" used herein should be interpreted to include any combination of one or more of the associated listed items, depending on the actual situation.

[0030] Figure 1 This is a circuit layout diagram of the output control interface according to an embodiment of the present invention. (See attached diagram.) Figure 1 As shown, one embodiment of the present invention provides an output control interface 10 suitable for static random access memory (SRAM) 12. The output control interface 10 includes an SRAM control detector 100 and an SRAM data controller 102. In this embodiment, the SRAM 12 may include a storage matrix, an address decoder, and read / write control circuitry. Figure 1 In this paper, SRAM 12 is exemplified as a single-port SRAM, but the present invention does not limit the type of SRAM, nor does it limit the number of reads and writes that can be performed in a single frequency cycle. In other words, in the embodiments of the present invention, for example, a two-port or dual-port SRAM may also be used.

[0031] In a stable system state, SRAM 12 can receive a first frequency signal clk, a control signal ctrl_in, and an input data signal data_in from an external circuit. The control signal ctrl_in can control SRAM 12 (e.g., through a read / write control circuit) to perform read or write operations based on the first frequency signal clk.

[0032] SRAM control detector 100 may include, for example, a finite-state machine (FSM) circuit, receive the control signal ctrl_in input to SRAM 12, and be configured to determine whether the control signal ctrl_in is stable and output an indication signal Sind accordingly.

[0033] The SRAM data controller may include, for example, combinational logic circuitry, which may form a multiplexer configured to receive an indication signal Sind and an SRAM output data signal Sdata_out output by SRAM 12, and output an output data signal data_out according to the indication signal Sind.

[0034] Figure 2 This is a flowchart of the output control method according to an embodiment of the present invention. (See attached document.) Figure 2 As shown, this embodiment of the invention provides an output control method applicable to... Figure 1 The output interface 10 and SRAM 12 are shown. The output control method may include the following steps:

[0035] Step S100: Configure the SRAM data controller to receive the indication signal and the SRAM output data signal.

[0036] Step S101: Configure the SRAM control detector to receive the control signal input to the SRAM.

[0037] Step S102: Determine whether the control signal is stable.

[0038] In step S102, in response to the determination that the control signal is not stable, the output control method proceeds to step S103: configure the SRAM control detector to output an indication signal to indicate that the control signal is not stable, and configure the SRAM data controller to output the output data signal with a preset value according to the indication signal.

[0039] In step S102, in response to the determination that the control signal has stabilized, the output control method proceeds to step S104: configure the SRAM control detector to output an indication signal to indicate that the control signal has stabilized, and configure the SRAM data controller to output the SRAM output data signal as the corresponding output data signal according to the indication signal.

[0040] In some embodiments of the present invention, the SRAM control detector 100 in step S102 can determine whether the control signal has stabilized by detecting whether the first read operation occurs after the write operation in the control signal ctrl_in. Specifically, when the system is powered on but the SRAM 12 is not yet in use, the internal data of the SRAM 12 will be considered an unexpected unknown value. Therefore, the unknown value can be replaced by the output data signal data_out with a preset value output by the SRAM data controller 102. Furthermore, the occurrence of a write operation in the control signal ctrl_in can be considered a sign that the SRAM 12 has begun to be used, and the first read operation following this write operation can be detected. Since the SRAM 12 should output the data written in the aforementioned write operation during the first read operation, the SRAM control detector 100, upon detecting the first read operation, will consider the control signal ctrl_in to be stable and can return to step S104 to control the SRAM data controller 102 to output the SRAM output data signal Sdata_out as the output data signal data_out according to the indication signal Sind.

[0041] Therefore, the above mechanism can prevent the simulation results from failing due to unexpected unknown values ​​output by the SRAM when the system is powered on but SRAM 12 has not yet been used.

[0042] Please refer to further information. Figure 3 This is a circuit layout diagram of the output interface according to another embodiment of the present invention. In another embodiment of the present invention, other unstable factors before the SRAM is used are further considered. For example, before the system is powered on and stabilized, one or more of the first frequency signal clk, the system reset signal resetn, and the control signal ctrl_in input to the SRAM may be in an unstable state; or after the system stabilizes but the SRAM has not yet been used, in addition to the internal data being considered unexpected, one or more of the first frequency signal clk and the control signal ctrl_in input to the SRAM may be in an unstable state. Therefore, as Figure 3 As shown, with Figure 1 The difference is that, Figure 3 The SRAM control detector 100 receives the system reset signal resetn, the first frequency signal clk input to the SRAM 12, the control signal ctrl_in, the power reset signal pon_rstn, and the second frequency signal hclk.

[0043] You can refer to them together. Figure 4 and Figure 5 . Figure 4 This is a flowchart of an output control method according to another embodiment of the present invention. Figure 5 This is a signal timing diagram of the output control interface according to another embodiment of the present invention. Figure 4 As shown, in Figure 3 Under the same architecture, another embodiment of the present invention also provides an output control method, including the following steps:

[0044] Step S400: Configure the SRAM control detector to receive the power reset signal, control signal, system reset signal, first frequency signal, and second frequency signal.

[0045] Step S401: Configure the SRAM control detector to determine whether the system has entered the power-on state based on the power reset signal, and to determine whether a predetermined time has elapsed based on the second frequency signal. For example, such as Figure 5 As shown, during time period T1, the system can be determined to be in power-on state by the power reset signal pon_rstn. Therefore, it is necessary to wait for a predetermined period of time until the system stabilizes before starting to detect the system reset signal resetn, the first frequency signal clk, and the control signal ctrl_in.

[0046] In step S401, in response to determining that the system has entered the power-on state and a predetermined time has elapsed, step S402 is entered: determining whether the system reset signal is stable.

[0047] For example, such as Figure 5As shown, during time period T2, the second frequency signal hclk indicates that a predetermined time has elapsed since the system entered the power-on state. Since the system reset signal resetn and the first frequency signal clk are prerequisites for the normal operation of SRAM 12, it is necessary to first determine whether the system reset signal resetn is stable. If it is not stable, the control signal ctrl_in is not detected. At this time, the contents of SRAM 12 (i.e., its output SRAM output data signal Sdata_out) are considered unpredictable unknown values. Therefore, the final output data signal data_out is replaced with a preset value. It should be noted that in step S402, the stability of the system reset signal resetn can be detected by the second frequency signal hclk. The determination method is to determine whether the system reset signal resetn transitions from an active state to an inactive state and remains so for a predetermined period of time. Furthermore, to ensure that the SRAM control detector 100 has sufficient resolution to determine the stability of the system reset signal resetn, the second frequency signal hclk must have a frequency higher than the first frequency signal clk, making the sampling result of the system reset signal resetn meaningful. It should also be noted that since the first frequency signal clk is provided by the system, the system only operates on the system reset signal resetn after the first frequency signal clk has stabilized. Therefore, if it is determined in step S402 that the system reset signal resetn has stabilized, it indicates that the first frequency signal clk has also stabilized.

[0048] In step S401, in response to determining that the system has not yet entered the power-on state, or has entered the power-on state but has not yet passed the predetermined time, step S401 is repeated.

[0049] In step S402, in response to the determination that the system reset signal is not stable, the output control method proceeds to step S403: configure the SRAM control detector to output an indication signal to indicate that the system reset signal is not stable, and configure the SRAM data controller to output an output data signal with a preset value.

[0050] In step S402, in response to the determination that the system reset signal resetn has stabilized, the output control method can proceed to step S405: configure the SRAM control detector to determine whether the control signal is stable.

[0051] However, preferably, after determining that the system reset signal resetn has stabilized, but before determining whether the control signal ctrl_in is stable, a window period will occur. During this time, the output control method can preemptively enter step S404: configure the SRAM control detector to output an indication signal to instruct the SRAM data controller to output an output data signal with a preset value, to avoid outputting unpredictable unknown values ​​during this window period. At this time, the SRAM control detector 100 synchronously detects whether the control signal ctrl_in has experienced its first read operation after a write operation, to determine whether the control signal ctrl_in is stable. Figure 5 The time period T3 is shown.

[0052] Similar to Figure 2 In the process described above, in step 405, in response to the determination that the control signal is not stable, the output control method proceeds to step S406: configure the SRAM control detector to output an indication signal to indicate that the control signal is not stable, and configure the SRAM data controller to output the output data signal with a preset value according to the indication signal.

[0053] On the other hand, in step S405, in response to determining that the control signal has stabilized, the output control method proceeds to step S407: configuring the SRAM control detector to output an indication signal to indicate that the control signal has stabilized, and configuring the SRAM data controller to output an SRAM output data signal as the output data signal according to the indication signal. For example, such as Figure 5 As shown, since the SRAM control detector 100 detects the first read operation after the write operation of the control signal ctrl_in in time period T3, it means that the control signal ctrl_in and the input data signal data_in have both stabilized and can operate the SRAM 12 normally. Therefore, the SRAM data controller can be instructed by the indicator signal Sind to output the SRAM output data signal Sdata_in as the output data signal according to the indicator signal.

[0054] Beneficial effects of the embodiments

[0055] The beneficial effects of the present invention are that the output control interface and output control method for static random access memory provided by the present invention can eliminate the influence of output instability before the SRAM is used through better control methods, and in particular, can reduce unnecessary debugging time in the simulation stage after circuit layout.

[0056] Although preferred and feasible embodiments of the present invention have been disclosed above, these embodiments are not intended to limit the present invention. Those skilled in the art can make changes to the technical features of the present invention based on the explicit or implicit content of the present invention. All such changes fall within the scope of patent protection sought by the present invention. In other words, the scope of patent protection of the present invention shall be determined by the scope defined in the claims of this application.

Claims

1. An output control interface suitable for static random access memory, characterized in that, The output control interface includes: An SRAM control detector receives control signals input to the SRAM and is configured to determine whether the control signals are stable and output an indication signal accordingly; and The SRAM data controller is configured to receive the indication signal and the SRAM output data signal, and to output an output data signal according to the indication signal. Specifically, in response to determining that the control signal is not stable, the SRAM control detector outputs the indication signal to indicate that the control signal is not stable, and the SRAM data controller correspondingly outputs the output data signal with a preset value. In response to determining that the control signal has stabilized, the SRAM control detector outputs the indication signal to indicate that the control signal has stabilized, and the SRAM data controller correspondingly outputs the SRAM output data signal as the output data signal.

2. The output control interface as described in claim 1, characterized in that, The SRAM-controlled detector includes a finite state machine circuit.

3. The output control interface as described in claim 1, characterized in that, The SRAM data controller includes combinational logic circuitry.

4. The output control interface as described in claim 1, characterized in that, The SRAM control detector determines whether the control signal has stabilized by detecting whether the first read operation occurs after a write operation.

5. The output control interface as described in claim 1, characterized in that, The SRAM control detector further receives a system reset signal and a first frequency signal input to the SRAM, and is configured to determine whether the system reset signal is stable before determining whether the control signal is stable. Specifically, in response to the determination that the system reset signal is not stable, the SRAM control detector outputs the indication signal to indicate that the system reset signal is not stable, and the SRAM data controller correspondingly outputs the output data signal having the preset value. In response to determining that the system reset signal has stabilized, the SRAM control detector further determines whether the control signal is stable and outputs the indication signal accordingly.

6. The output control interface as described in claim 5, characterized in that, After determining that the system reset signal has stabilized, but before determining whether the control signal is stable, the SRAM control detector outputs the indication signal to instruct the SRAM data controller to output the output data signal with the preset value.

7. The output control interface as described in claim 5, characterized in that, The SRAM control detector further receives a second frequency signal and is configured to detect whether the system reset signal is stable via the second frequency signal.

8. The output control interface as described in claim 7, characterized in that, The frequency of the second frequency signal is higher than that of the first frequency signal.

9. The output control interface as described in claim 7, characterized in that, The SRAM control detector is configured to further determine whether the system reset signal is stable after the system enters the power-on state and a predetermined time has elapsed.

10. The output control interface as described in claim 9, characterized in that, The SRAM control detector further receives a power reset signal and is configured to determine whether the system has entered the power-on state based on the power reset signal, and to determine whether the predetermined time has elapsed based on the second frequency signal.

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