Method for determining data read duration, test method, device and storage medium

Abstract

The present disclosure provides a method for determining data reading duration, a test method, an apparatus and a storage medium. The method comprises: under a preset test condition, determining a second offset duration in a wafer test process according to a first offset duration of a chip on a wafer; the first offset duration is an offset duration of a data synchronization signal of the chip on the wafer; and determining a data reading duration of data in the chip on the wafer according to the second offset duration and a preset data reading duration. By using a unified offset duration, i.e., the second offset duration, to read data in all chips in the wafer during the wafer test process, the reliability of data reading during the test process can be improved.

Description

Technical Field

[0001] This disclosure relates to the field of chip design technology, and in particular to a method, test method, apparatus and storage medium for determining data reading duration. Background Technology

[0002] In related technologies, during wafer testing, such as the testing of LPDDR (Low Power Double Data Rate SDRAM) memory chips, the data written to the memory chip is read out at different times due to tolerances in the wafer manufacturing process and different testing conditions. This results in low stability and accuracy during the wafer testing process. Summary of the Invention

[0003] The following is an overview of the subject matter described in detail in this disclosure. This overview is not intended to limit the scope of the claims.

[0004] This disclosure provides a method, test method, apparatus, and storage medium for determining data reading duration.

[0005] According to a first aspect of the present disclosure, a method for determining data reading duration is provided, the method comprising:

[0006] Under preset test conditions, a second offset duration is determined during the wafer testing process based on a first offset duration of the chips on the wafer; the first offset duration is the offset duration of the data synchronization signal of the chips on the wafer.

[0007] The data reading duration of the data in the chip on the wafer is determined based on the second offset duration and the preset data reading duration.

[0008] In some exemplary embodiments, under preset test conditions, determining the second offset duration during wafer testing based on the first offset duration of the chips on the wafer includes:

[0009] Under preset test conditions, the second offset duration during the wafer testing process is determined based on the first offset duration of the first preset number of chips on the wafer.

[0010] In some exemplary embodiments, under preset test conditions, determining the second offset duration during wafer testing based on the first offset duration of a first preset number of chips on the wafer includes:

[0011] The average value of the first offset duration of the first preset number determined under the preset test conditions is determined as the second offset duration in the wafer testing process under the preset test conditions.

[0012] In some exemplary embodiments, under preset test conditions, determining the second offset duration during wafer testing based on the first offset duration of a first preset number of chips on the wafer includes:

[0013] Determine the first offset duration within a preset duration range;

[0014] The average value of the first offset duration is determined as the second offset duration in the wafer testing process under the preset test conditions.

[0015] In some exemplary embodiments, the determination method further includes:

[0016] The preset duration range is determined based on the first offset duration of the first preset number of chips.

[0017] In some exemplary embodiments, the ratio of the first preset number to the total number of chips on the wafer is greater than a preset ratio.

[0018] In some exemplary embodiments, the first preset quantity is the total number of chips on the wafer, or the number of chips obtained after excluding failed chips on the wafer according to preset rules.

[0019] In some exemplary embodiments, the determination method further includes:

[0020] Under the preset test conditions, a second preset number of data write-read tests are performed on the first preset number of chips on the wafer to obtain the first offset duration corresponding to each of the first preset number of chips in the data write-read test.

[0021] In some exemplary embodiments, the second preset quantity is less than or equal to a preset threshold.

[0022] In some exemplary embodiments, determining the data read duration of the data in the chip on the wafer based on the second offset duration and the preset data read duration includes:

[0023] The sum of the second offset duration and the preset data reading duration is determined as the data reading duration of the data in the chip on the wafer.

[0024] According to a second aspect of the present disclosure, a wafer testing method is provided, the method comprising: performing functional testing on the wafer under preset test conditions based on a data readout duration of data in a chip on the wafer determined according to the method provided by an exemplary embodiment of the present disclosure.

[0025] According to a third aspect of the present disclosure, an apparatus for determining data reading duration is provided, the apparatus comprising:

[0026] The first determining module is configured to determine a second offset duration during wafer testing based on a first offset duration of the chip on the wafer under preset test conditions; the first offset duration is the offset duration of the data synchronization signal of the chip on the wafer.

[0027] The second determining module is configured to determine the data reading duration of the data in the chip on the wafer based on the second offset duration and the preset data reading duration.

[0028] In some exemplary embodiments, the first determining module is configured to:

[0029] Under preset test conditions, the second offset duration during the wafer testing process is determined based on the first offset duration of the first preset number of chips on the wafer.

[0030] In some exemplary embodiments, the first determining module is configured to:

[0031] The average value of the first offset duration of the first preset number determined under the preset test conditions is determined as the second offset duration in the wafer testing process under the preset test conditions.

[0032] In some exemplary embodiments, the first determining module is configured to:

[0033] Determine the first offset duration within a preset duration range;

[0034] The average value of the first offset duration is determined as the second offset duration in the wafer testing process under the preset test conditions.

[0035] In some exemplary embodiments, the first determining module is configured to:

[0036] The preset duration range is determined based on the first offset duration of the first preset number of chips.

[0037] In some exemplary embodiments, the ratio of the first preset number to the total number of chips on the wafer is greater than a preset ratio.

[0038] In some exemplary embodiments, the first preset quantity is the total number of chips on the wafer, or the number of chips obtained after excluding failed chips on the wafer according to preset rules.

[0039] In some exemplary embodiments, the determination method further includes a third determination module, configured to:

[0040] Under the preset test conditions, a second preset number of data write-read tests are performed on the first preset number of chips on the wafer to obtain the first offset duration corresponding to each of the first preset number of chips in the data write-read test.

[0041] In some exemplary embodiments, the second preset quantity is less than or equal to a preset threshold.

[0042] In some exemplary embodiments, the second determining module is configured to:

[0043] The sum of the second offset duration and the preset data reading duration is determined as the data reading duration of the data in the chip on the wafer.

[0044] According to a fourth aspect of the present disclosure, a testing apparatus is provided, the apparatus comprising:

[0045] The test module is configured to perform functional tests on the wafer under the preset test conditions, based on the data readout duration of the data in the chip on the wafer determined according to the method described in an exemplary embodiment of this disclosure.

[0046] According to a fifth aspect of the present disclosure, an apparatus for determining data reading duration is provided, the apparatus comprising:

[0047] Processor; and

[0048] A memory storing computer-readable instructions that, when executed by the processor, implement the methods provided in exemplary embodiments of this disclosure.

[0049] According to a sixth aspect of the present disclosure, a computer-readable storage medium is provided having a computer program stored thereon that, when executed by a processor, implements the methods described in the exemplary embodiments of the present disclosure.

[0050] After reading and understanding the accompanying diagrams and detailed descriptions, the other aspects can be understood. Attached Figure Description

[0051] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the present disclosure and, together with the description, serve to explain the principles of these embodiments. In these drawings, similar reference numerals are used to denote similar elements. The drawings described below are some embodiments of the present disclosure, but not all embodiments. Other drawings will be readily available to those skilled in the art based on these drawings without inventive effort.

[0052] Figure 1An exemplary timing diagram is shown when reading data written into a chip during wafer testing.

[0053] Figure 2 This is a flowchart illustrating a method for determining data reading duration according to an exemplary embodiment;

[0054] Figure 3 This is a schematic diagram of the structure of a wafer to be tested provided according to an exemplary embodiment of this disclosure;

[0055] Figure 4 This is a flowchart illustrating a method for determining a second offset duration during wafer testing under preset test conditions, based on a first offset duration of a first preset number of chips on the wafer.

[0056] Figure 5 This is a flowchart illustrating a wafer testing method according to an exemplary embodiment;

[0057] Figure 6 This is a structural block diagram of an apparatus for determining data reading duration according to an exemplary embodiment;

[0058] Figure 7 This is a structural block diagram of a testing apparatus according to an exemplary embodiment;

[0059] Figure 8 This is an apparatus for determining data readout duration and / or wafer testing, according to an exemplary embodiment. Detailed Implementation

[0060] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions in the disclosed embodiments will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the embodiments of this disclosure without creative effort are within the scope of protection of this disclosure. It should be noted that, unless otherwise specified, the embodiments and features in the embodiments of this disclosure can be arbitrarily combined with each other.

[0061] In related technologies, during wafer testing, such as the testing of LPDDR (Low Power Double Data Rate SDRAM) memory chips, the data written to the memory chip and read out can experience a time offset due to tolerances in the wafer manufacturing process and different testing conditions, such as variations in test voltage, temperature, and pulse conditions. For example... Figure 1 As shown, Figure 1An exemplary timing diagram is shown when reading data written to a chip during wafer testing. Figure 1 In this code, CK_c and CK_t represent the clock, COMMAND represents the command, DOS_c and DOS_t represent the data synchronization signal, and DQ represents the data read signal. Due to tolerances in wafer manufacturing processes and variations in test voltages, temperatures, pulses, and other conditions during wafer testing, a time offset tDQSQ will occur between the data synchronization signal and the data read signal on the wafer. This offset tDQSQ varies depending on the test conditions, resulting in poor stability of chip data readout during testing.

[0062] In exemplary embodiments of this disclosure, a method for determining data reading duration is provided, such as... Figure 2 As shown, Figure 2 This is a flowchart illustrating a method for determining data reading duration according to an exemplary embodiment:

[0063] In step S101, under preset test conditions, the second offset duration during the wafer test process is determined based on the first offset duration of the chip on the wafer; the first offset duration is the offset duration of the data synchronization signal of the chip on the wafer.

[0064] In step S102, the data reading time of the data in the chip on the wafer is determined according to the second offset time and the preset data reading time.

[0065] In exemplary embodiments of this disclosure, to address the issue of varying offset durations tDQSQ caused by tolerances in wafer fabrication processes and testing conditions, this disclosure proposes using a uniform offset duration, i.e., a second offset duration, as the data readoff offset duration for data stored within each chip on the wafer during wafer testing. Based on the uniform offset duration, i.e., the second offset duration, and a preset data readoff duration for reading data within the chip, the final data readoff duration for data within the chip during wafer testing is determined. The second offset duration can be determined based on the offset duration of the chips on the wafer, i.e., by using the offset duration of the data synchronization signals of the chips in the wafer, thus determining the offset duration used to read the data synchronization signals from all chips in the wafer.

[0066] The first offset duration is the offset duration of the data synchronization signal on the wafer chip, that is, the time node of the first output data when reading data from the chip during wafer testing. Since different test conditions, such as different test voltages, temperatures, and pulse conditions, will affect the offset duration of the chip's data synchronization signal, different second offset durations are determined based on different preset test conditions to improve the stability of data reading during wafer testing.

[0067] In actual testing, different test temperatures may include, for example, BI (burn-in test) temperatures (e.g., 100-140℃), LT (low temperature test) temperatures (-20~0℃), or HT (high temperature test) temperatures (70-90℃). At different test temperatures, corresponding voltage and pulse conditions are determined, i.e., preset test conditions are established. Under these preset test conditions, a first offset duration for the chip on the wafer is determined. Based on the first offset duration, a second offset duration during wafer testing is determined. Based on the second offset duration and a preset data read duration, the data read duration for the chip on the wafer is determined to improve the stability of data readout during wafer testing.

[0068] In the exemplary embodiments of this disclosure, by using a uniform offset duration, i.e. a second offset duration, under the same test conditions during wafer testing to read data from all chips in the wafer, the reliability of data reading during the testing process can be improved.

[0069] In an exemplary embodiment of this disclosure, when determining the second offset duration based on the first offset duration of the chips on the wafer, the second offset duration can be determined based on the first offset duration of a first preset number of chips on the wafer. Under preset test conditions, determining the second offset duration during wafer testing based on the first offset duration of the chips on the wafer includes:

[0070] Under preset test conditions, the second offset duration during the wafer testing process is determined based on the first offset duration of the first preset number of chips on the wafer.

[0071] like Figure 3 As shown, Figure 3 This is a schematic diagram of the structure of a wafer to be tested provided according to an exemplary embodiment of this disclosure. Figure 3In this example, wafer 100 comprises multiple chips, with each small grid representing one chip, and each chip having a corresponding first offset duration. To determine the second offset duration during wafer testing, a first preset number of chips on the wafer can be selected to determine the first offset duration. The first preset number can be set according to any rule; for example, to ensure the accuracy of the second offset duration determination, the ratio of the first preset number to the total number of chips on the wafer can be greater than a preset ratio. For example, the preset ratio is 0.8. This selection of the number of chips allows for a basic overall assessment of the status of all chips on the wafer and also improves the efficiency of wafer testing.

[0072] In exemplary embodiments of this disclosure, the first preset quantity can be the total number of chips on the wafer, or the number of chips obtained after excluding failed chips on the wafer according to a preset rule. The preset rule can be any rule, for example, the number of chips obtained after excluding abnormal chips on the wafer. The second offset time can be determined more accurately by using the first offset time of all chips on the wafer.

[0073] After obtaining the first offset duration of a first preset number of chips under preset test conditions, the second offset duration for wafer testing can be determined according to any rule. For example, the average of the first offset durations of the first preset number of chips can be taken. Under preset test conditions, the second offset duration during wafer testing is determined based on the first offset duration of the first preset number of chips on the wafer, including:

[0074] The average value of the first offset duration of the first preset quantity determined under the preset test conditions is determined as the second offset duration in the wafer testing process under the preset test conditions.

[0075] In an exemplary embodiment of this disclosure, the average value of a first preset number of first offset durations is used as the second offset duration during wafer testing under preset test conditions. The average value of the first preset number of first offset durations can substantially reflect the offset duration status of all chips on the wafer. Using this as the offset duration of all chips on the wafer during wafer testing under preset test conditions allows for dynamic adjustment of the data reading duration in the chips during wafer testing with the same offset duration, thereby improving the accuracy of data reading in the chips during wafer testing.

[0076] In exemplary embodiments of this disclosure, after obtaining the first offset duration of a first preset number of chips under preset test conditions, a second offset duration for wafer testing can be determined according to any rule. For example, a first offset duration within a preset duration range can be selected, and the average value of the selected first offset durations can be used as the second offset duration during the wafer testing process under the preset test conditions. Figure 4 As shown, Figure 4 This is a flowchart illustrating a method for determining a second offset duration during wafer testing under preset test conditions, based on a first offset duration of a first preset number of chips on the wafer:

[0077] Step S201: Determine the first offset duration within the preset duration range;

[0078] Step S202: The average value of the determined first offset duration is determined as the second offset duration in the wafer testing process under preset test conditions.

[0079] In exemplary embodiments of this disclosure, considering the state of the chips during wafer testing, obviously abnormal offset durations can be removed from the first offset durations of the first preset number of chips, or first offset durations with relatively concentrated values ​​can be selected, or first offset durations including those exceeding a preset proportion can be selected to determine the second offset duration. Therefore, the first offset durations within a preset duration range can be determined, and the average value of the determined first offset durations can be taken as the second offset duration during wafer testing under preset test conditions.

[0080] The preset duration range can be set as needed. For example, the preset duration range can be determined based on the first preset number of first offset durations obtained under preset test conditions. For example, the duration range determined by the first offset duration after removing obviously abnormal offset durations can be used as the preset duration range, or the duration range that includes 90% of the first offset durations obtained under preset test conditions can be used as the preset duration range.

[0081] Under preset test conditions, using the average value of the first offset duration within the preset duration range as the second offset duration can make the determination of the second offset duration more accurate and better meet the test requirements under the preset test conditions.

[0082] Under different preset test conditions, a corresponding second offset duration is determined to better meet the test requirements. This allows for dynamic adjustment of the data reading time in the chip during wafer testing, based on different preset test conditions, thereby further improving the accuracy of data reading in the chip during wafer testing.

[0083] In an embodiment of this disclosure, a method for determining the duration of a first offset is also provided:

[0084] Under preset test conditions, a second preset number of data write-read tests are performed on the first preset number of chips on the wafer to obtain the first offset duration corresponding to each of the first preset number of chips in the data write-read test.

[0085] In an exemplary embodiment of this disclosure, to obtain the first offset duration of a first preset number of chips on the wafer, a second preset number of data write-read tests can be performed on the chips to obtain the first offset duration obtained in the write-read tests. Since the first offset duration is the offset duration of the data synchronization signal of the chips on the wafer, when obtaining the first offset duration, only a small amount of data can be written to the first preset number of chips on the wafer to obtain the corresponding first offset duration during the data read test. Therefore, the second preset number can, for example, be less than a preset threshold. The preset threshold can be set according to actual needs, for example, it can be 5. The small amount of data, i.e., the second preset number, can be 2 to 3 bits.

[0086] During write-read testing, the data read time can be obtained by reading a small amount of data (a second preset quantity). Based on the obtained data read time, the first offset time can be determined, without having to write to the entire memory of the chip, thus saving test time and improving test efficiency.

[0087] In actual testing, this small amount of data can be the data initially read from the chips on the wafer under preset test conditions during wafer testing. Based on this initial data read, a first offset duration corresponding to a first preset number of chips is determined. A second offset duration is then determined based on the first offset duration. Finally, based on the second offset duration and the preset data read duration, the data read duration from the chips on the wafer is determined to improve the stability of data reading during wafer testing.

[0088] In exemplary embodiments of this disclosure, a method for determining the data readout duration of data in a chip on a wafer based on a second offset duration and a preset data readout duration is also provided:

[0089] The sum of the second offset duration and the preset data read duration is determined as the data read duration of the data in the chip on the wafer.

[0090] In the exemplary embodiments of this disclosure, the sum of the second offset duration and the preset number of read durations is used as the data read duration of the chip on the wafer under preset test conditions. This allows for dynamic adjustment of the read duration of data read from the chip during wafer testing, thereby improving the accuracy of data reads from the chip during wafer testing.

[0091] In exemplary embodiments of this disclosure, a wafer testing method is also provided, such as... Figure 5 As shown, Figure 5 This is a flowchart illustrating a wafer testing method according to an exemplary embodiment:

[0092] Step S301: Based on the data read duration determined by the method for determining data read duration proposed in the exemplary embodiments of this disclosure, the wafer is subjected to functional testing under preset test conditions.

[0093] In an exemplary embodiment according to this disclosure, after determining the data readout duration of the data on the chip within the wafer, functional testing can be performed on the wafer based on the determined data readout duration. Since the data readout duration of the data on the chip within the wafer will be affected differently during testing due to varying test conditions, such as different test voltages, temperatures, and pulse conditions, the test conditions for functional testing are the same as the test conditions for the data readout duration. For example, the data readout duration of the data on the chip within the wafer determined under preset test conditions is used to perform functional testing on the wafer under those preset test conditions.

[0094] In actual testing, different test temperatures may include, for example, BI (burn-in test) temperatures (e.g., 100-140℃), LT (low temperature test) temperatures (-20~0℃), or HT (high temperature test) temperatures (70-90℃). At different test temperatures, corresponding voltage and pulse conditions are determined, i.e., preset test conditions are established. Under these preset test conditions, a first offset duration for the chip on the wafer is determined. Based on the first offset duration, a second offset duration is determined during the wafer testing process. Based on the second offset duration and a preset data read duration, the data read duration for the chip on the wafer is determined. Based on the determined data read duration, functional testing is performed on the wafer under the same preset test conditions to improve the accuracy of data reads during functional testing.

[0095] This disclosure exemplarily provides a memory chip access device 600, such as... Figure 6 As shown, Figure 6 This is a structural block diagram of an apparatus for determining data reading duration according to an exemplary embodiment. The apparatus includes:

[0096] The first determining module 601 is configured to determine a second offset duration during wafer testing based on a first offset duration of the chip on the wafer under preset test conditions; the first offset duration is the offset duration of the data synchronization signal of the chip on the wafer.

[0097] The second determining module 602 is configured to determine the data reading duration of the data in the chip on the wafer based on the second offset duration and the preset data reading duration.

[0098] In some exemplary embodiments, the first determining module 601 is configured to:

[0099] Under preset test conditions, the second offset duration during the wafer testing process is determined based on the first offset duration of the first preset number of chips on the wafer.

[0100] In some exemplary embodiments, the first determining module 601 is configured to:

[0101] The average value of the first offset duration of the first preset number determined under the preset test conditions is determined as the second offset duration in the wafer testing process under the preset test conditions.

[0102] In some exemplary embodiments, the first determining module 601 is configured to:

[0103] Determine the first offset duration within the preset test duration range;

[0104] The average value of the first offset duration is determined as the second offset duration in the wafer testing process under the preset test conditions.

[0105] In some exemplary embodiments, the first determining module 601 is configured to:

[0106] The preset duration range is determined based on the first offset duration of the first preset number of chips.

[0107] In some exemplary embodiments, the ratio of the first preset number to the total number of chips on the wafer is greater than a preset ratio.

[0108] In some exemplary embodiments, the first preset number is the total number of chips on the wafer, or the number of chips obtained after excluding failed chips on the wafer according to preset rules.

[0109] In some exemplary embodiments, the determining method further includes a third determining module 603, configured to:

[0110] Under the preset test conditions, a second preset number of data write-read tests are performed on the first preset number of chips on the wafer to obtain the first offset duration corresponding to each of the first preset number of chips in the data write-read test.

[0111] In some exemplary embodiments, the second preset quantity is less than or equal to a preset threshold.

[0112] In some exemplary embodiments, the second determining module 602 is configured to:

[0113] The sum of the second offset duration and the preset data reading duration is determined as the data reading duration of the data in the chip on the wafer.

[0114] This disclosure provides an exemplary testing apparatus, such as... Figure 7 As shown, Figure 7 This is a structural block diagram of a testing apparatus according to an exemplary embodiment, the testing apparatus comprising:

[0115] Test module 701 is configured to perform functional tests on the wafer under the preset test conditions, based on the data read duration determined by the method for determining data read duration provided in the exemplary embodiments of this disclosure, and the data read duration in the chip on the wafer.

[0116] Regarding the apparatus in the above embodiments, the specific manner in which each module performs its operation has been described in detail in the embodiments related to the method, and will not be elaborated upon here.

[0117] Figure 8 This is a block diagram illustrating an apparatus, namely a computer device 800, for determining data read duration and / or wafer testing according to an exemplary embodiment. The apparatus can be the evaluation apparatus or access apparatus described in the exemplary embodiments of this disclosure; for example, the computer device 800 can be provided as a terminal device. (Refer to...) Figure 8 The computer device 800 includes a processor 801, the number of which can be set to one or more as needed. The computer device 800 also includes a memory 802 for storing instructions executable by the processor 801, such as application programs. The number of memories can be set to one or more as needed. The stored application programs can be one or more. The processor 801 is configured to execute instructions to perform the methods described above.

[0118] Those skilled in the art will understand that embodiments of this disclosure can be provided as methods, apparatus (devices), or computer program products. Therefore, this disclosure can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, this disclosure can take the form of a computer program product implemented on one or more computer-usable storage media containing computer-usable program code. Computer storage media include volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information (such as computer-readable instructions, data structures, program modules, or other data), including but not limited to RAM, ROM, EEPROM, flash memory or other memory technologies, CD-ROM, digital versatile disc (DVD) or other optical disc storage, magnetic cartridges, magnetic tape, disk storage or other magnetic storage devices, or any other medium that can be used to store desired information and is accessible by a computer. Furthermore, it is known to those skilled in the art that communication media typically contain computer-readable instructions, data structures, program modules, or other data in modulated data signals such as carrier waves or other transmission mechanisms, and can include any information delivery medium.

[0119] In an exemplary embodiment, a non-transitory computer-readable storage medium including instructions is provided, such as a memory 802 including instructions, which can be executed by a processor 801 of the device 800 to perform the above-described method. For example, the non-transitory computer-readable storage medium may be a ROM, random access memory (RAM), CD-ROM, magnetic tape, floppy disk, and optical data storage device, etc.

[0120] In exemplary embodiments of this disclosure, a computer-readable storage medium is provided having a computer program stored thereon that, when executed by a processor, implements the methods described in exemplary embodiments of this disclosure.

[0121] In an exemplary embodiment of this disclosure, an apparatus for determining data reading duration is provided, the apparatus comprising:

[0122] Processor; and

[0123] A memory storing computer-readable instructions that, when executed by the processor, implement the methods provided in exemplary embodiments of this disclosure.

[0124] This disclosure is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (devices), and computer program products according to embodiments of this disclosure. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create a machine for implementing the flowchart illustrations and / or block diagrams. Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0125] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0126] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0127] In this disclosure, the terms “comprising,” “including,” or any other variations thereof are intended to cover non-exclusive inclusion, such that an article or device that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such an article or device. Without further limitation, an element defined by the phrase “comprising…” does not exclude the presence of additional identical elements in the article or device that includes said element.

[0128] Although preferred embodiments of the present disclosure have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of this disclosure.

[0129] Obviously, those skilled in the art can make various modifications and variations to this disclosure without departing from its spirit and scope. Therefore, if such modifications and variations fall within the scope of the claims of this disclosure and their equivalents, the intent of this disclosure also includes these modifications and variations.

Claims

1. A method for determining data reading duration, characterized in that, The method includes: Under preset test conditions, a second offset duration is determined during the wafer testing process based on a first offset duration of the chips on the wafer; the first offset duration is the offset duration of the data synchronization signal of the chips on the wafer. The data reading duration of the data in the chip on the wafer is determined based on the second offset duration and the preset data reading duration; Among them, under preset test conditions, determining the second offset duration during wafer testing based on the first offset duration of the chip on the wafer includes: Under preset test conditions, the second offset duration during the wafer test process is determined based on the first offset duration of the first preset number of chips on the wafer. Under preset test conditions, determining the second offset duration during wafer testing based on the first offset duration of a first preset number of chips on the wafer includes: Determine the first offset duration within a preset duration range; The average value of the determined first offset duration is determined as the second offset duration in the wafer testing process under the preset test conditions; Based on the second offset duration and the preset data read duration, the data read duration of the data in the chip on the wafer is determined, including: The sum of the second offset duration and the preset data reading duration is determined as the data reading duration of the data in the chip on the wafer.

2. The method according to claim 1, characterized in that, Under preset test conditions, determining the second offset duration during wafer testing based on the first offset duration of a first preset number of chips on the wafer includes: The average value of the first offset duration of the first preset number determined under the preset test conditions is determined as the second offset duration in the wafer testing process under the preset test conditions.

3. The method according to claim 1, characterized in that, The method further includes: The preset duration range is determined based on the first offset duration of the first preset number of chips.

4. The method according to any one of claims 2-3, characterized in that, The ratio of the first preset quantity to the total number of chips on the wafer is greater than the preset ratio.

5. The method according to claim 4, characterized in that, The first preset quantity is the total number of chips on the wafer, or the number of chips obtained after excluding failed chips on the wafer according to preset rules.

6. The method according to claim 1, characterized in that, The method further includes: Under the preset test conditions, a second preset number of data write-read tests are performed on the first preset number of chips on the wafer to obtain the first offset duration corresponding to each of the first preset number of chips in the data write-read test.

7. The method according to claim 6, characterized in that, The second preset quantity is less than or equal to the preset threshold.

8. A testing method, characterized in that, The method includes: performing functional tests on the wafer under the preset test conditions, based on the data readout duration of the chip data on the wafer determined by the method according to any one of claims 1-7.

9. A device for determining the duration of data reading, characterized in that, The device includes: The first determining module is configured to determine a second offset duration during wafer testing based on a first offset duration of the chip on the wafer under preset test conditions; the first offset duration is the offset duration of the data synchronization signal of the chip on the wafer. The second determining module is configured to determine the data reading duration of the data in the chip on the wafer based on the second offset duration and the preset data reading duration; Among them, under preset test conditions, determining the second offset duration during wafer testing based on the first offset duration of the chip on the wafer includes: Under preset test conditions, the second offset duration during the wafer test process is determined based on the first offset duration of the first preset number of chips on the wafer. Under preset test conditions, determining the second offset duration during wafer testing based on the first offset duration of a first preset number of chips on the wafer includes: Determine the first offset duration within a preset duration range; The average value of the determined first offset duration is determined as the second offset duration in the wafer testing process under the preset test conditions; Based on the second offset duration and the preset data read duration, the data read duration of the data in the chip on the wafer is determined, including: The sum of the second offset duration and the preset data reading duration is determined as the data reading duration of the data in the chip on the wafer.

10. A testing apparatus, characterized in that, The device includes: The test module is configured to perform functional tests on the wafer under the preset test conditions, based on the data readout duration of the data in the chip on the wafer as determined by any one of the methods described in claims 1-7.

11. A device for determining the duration of data reading, characterized in that, The device includes: Processor; and A memory storing computer-readable instructions that, when executed by the processor, implement the method according to any one of claims 1 to 8.

12. A computer-readable storage medium having a computer program stored thereon, the computer program, when executed by a processor, implementing the method according to any one of claims 1 to 8.

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