A gallium nitride device preparation method based on gate terminal electric field regulation and device

Abstract

The application discloses a gallium nitride device preparation method based on gate terminal electric field regulation and control and a device, and the method comprises the following steps: sequentially growing a GaN buffer layer and at least two heterojunctions composed of a channel layer and a barrier layer on a substrate layer; preparing a source electrode and a drain electrode on the surface of the top barrier layer; growing a passivation layer on the surface of the source and drain electrodes and the top barrier layer; forming a source-drain electrode corresponding interconnection metal layer hole in the passivation layer; making a gate electrode between the source and drain electrodes and close to the source end; determining auxiliary gate parameters according to the requirement of gate terminal electric field regulation and control, and making an auxiliary gate by etching the passivation layer according to the auxiliary gate parameters; wherein the auxiliary gate parameters include one or more of auxiliary gate position information, auxiliary gate depth, auxiliary gate metal work function and auxiliary gate bias voltage; and preparing a source electrode and a drain electrode corresponding interconnection metal layer. The application can improve the double-peak characteristics and gate control capability of the multi-heterojunction gallium nitride device, and improve the linearity and power.

Description

Technical Field

[0001] This invention belongs to the field of microelectronics technology, specifically relating to a method and device for fabricating gallium nitride devices based on gate-terminated electric field modulation. Background Technology

[0002] Driven by technologies such as 5G and the future 6G, modern wireless communication systems are facing enormous challenges in terms of data transmission rates and system capacity. However, gallium nitride (GaN) devices, with their superior material properties, have emerged and are widely used in high-frequency and high-power applications, offering broad potential for various applications, including but not limited to ultra-high-capacity high-speed mobile communications, high-resolution radar, secure communications, and laser weapons in military and civilian fields.

[0003] To further improve the output power density of gallium nitride (GaN) devices, two or more conductive channels are typically connected in parallel to form a dual-channel or multi-channel structure. This reduces the channel on-resistance, increases the saturation output current, and thus improves the output power density. However, conventional dual-channel or multi-channel structures usually have a large barrier layer thickness, resulting in a large distance between the gate and the underlying conductive channel, leading to poor gate control capability. This can increase the off-state leakage current, lower the breakdown voltage, and limit the device's operating voltage range. Furthermore, a large off-state leakage current usually results in low device efficiency, severely impacting system standby time and power consumption, causing significant energy waste. Simultaneously, the thicker channel layer in a multi-channel structure hinders the coupling between electrons in different channels, causing a pronounced double-peak characteristic in the transconductance profile. This affects transconductance flatness, leading to rapid gain compression, poor intermodulation characteristics, and severe linearity deterioration in millimeter-wave power devices, limiting the application prospects of multi-channel GaN devices in modern wireless communication systems.

[0004] To address the aforementioned issues with dual / multi-channel gallium nitride (GaN) devices, researchers have conducted numerous related technological studies. To overcome the poor gate control capability caused by the thicker barrier layer in multi-channel structures, Josephine Chang et al. proposed a three-dimensional gate structure in 2019 to enhance gate control, achieving a saturated output current of 1.8 A / mm and an output power density of 6 W / mm. However, this technique typically sacrifices the gate width, resulting in an actual gate width larger than the effective gate width, which is not conducive to system integration. Specifically, this technique involves periodically etching the multi-channel barrier layer along the gate width direction, creating a three-dimensional surrounding structure of the gate metal electrodes around the multi-channels. The gate electrodes in this technique mainly consist of a top planar gate and side gate structures. The planar gate enables control of the top channel, while the side gates allow for regulation of the lower channels, thus achieving gate-based switching control of channel carriers. However, this technique often results in an actual gate width smaller than the effective gate width of the device, severely impacting its actual conduction capability. Furthermore, it typically causes significant etching damage during device preparation, introducing serious interface state problems. In addition, the controllability of the sidewall gate heavily depends on the array width of a single cycle of the three-dimensional gate structure. When the width is large, the sidewalls can only control a portion of the carriers on both sides, failing to effectively control the central region far from the sidewalls. Simultaneously, etching releases lattice stress at the heterojunction interface, reducing the two-dimensional electron gas concentration, lowering the device's output current, and severely degrading the output power density. Moreover, the parasitic capacitance formed by the three-dimensional gate structure also limits the device's application frequency.

[0005] To address the issue of poor carrier coupling between channels due to the thicker channel layer in dual-channel structures, Qian Yu et al. used Si doping technology in the channel layer in 2023 to enhance the coupling between the two channels, effectively improving the transconductance flatness of the device. The OIP3 of the device reached 39.3 dBm at 3.6 GHz. However, this technology did not solve the problem of poor gate control capability in dual / multi-channel structures. The low cutoff frequency of the device limited its operating frequency range, making it difficult to meet the application requirements at higher frequency bands. Specifically, this technology primarily involves Si doping the lower barrier layer of a multi-channel structure to reduce the band barrier between channels. This allows carriers from different channels to couple and migrate under a higher electric field, improving the bimodal characteristics of the device's transconductance profile and further enhancing its linearity. However, effective Si doping requires a relatively thick lower barrier layer to ensure effective modulation of the band structure. Furthermore, a high concentration of Si doping may exacerbate carrier scattering in the lower channel, reducing its mobility and limiting the device's saturation output current. Simultaneously, this technology does not effectively address the weak gate electrode control over the lower channel, resulting in poor off-state characteristics of the device.

[0006] Another related technology employs a back barrier structure to improve carrier confinement. This technology enhances the confinement of carriers in the lower channel layer by adding a back barrier structure such as InGaN, thereby improving the off-state characteristics of the device. However, using multiple stacked back barrier structures complicates the material structure of the device and makes the growth process difficult. Furthermore, the back barrier structure may induce conductive channels in the lower buffer layer, causing the source and drain regions to connect under a high electric field, leading to device breakdown and limiting the operating voltage range. Similarly, this technology does not effectively solve the problem of weak gate electrode control over the channel, resulting in poor subthreshold characteristics and limited frequency performance, making it unsuitable for higher frequency applications such as Ka and above. Summary of the Invention

[0007] To address the aforementioned problems in the prior art, this invention provides a method and device for fabricating gallium nitride devices based on gate termination electric field modulation. The technical problem to be solved by this invention is achieved through the following technical solution:

[0008] In a first aspect, embodiments of the present invention provide a method for fabricating gallium nitride devices based on gate termination electric field modulation, the method comprising:

[0009] A GaN buffer layer and at least two heterojunctions consisting of a channel layer and a barrier layer are sequentially grown on the substrate.

[0010] Source and drain electrodes are fabricated on the surface of the last grown top barrier layer;

[0011] A passivation layer is grown on the surface of the source electrode, the drain electrode, and the top barrier layer;

[0012] Interconnect metal layer holes corresponding to the source electrode and the drain electrode are formed in the passivation layer;

[0013] A passivation layer is etched between the source electrode and the drain electrode, near the source electrode, to form a gate electrode;

[0014] The auxiliary gate parameters are determined according to the requirements of gate termination electric field control. Based on the auxiliary gate parameters, the auxiliary gate is fabricated by etching the passivation layer. The auxiliary gate parameters include one or more of the following: auxiliary gate position information, auxiliary gate depth, auxiliary gate metal work function, and auxiliary gate bias voltage. The auxiliary gate position information indicates the positional relationship between the auxiliary gate and the gate electrode. The auxiliary gate depth indicates the position of the barrier layer in contact with the auxiliary gate.

[0015] Based on the location of the interconnect metal layer holes corresponding to the source and drain electrodes, the interconnect metal layers corresponding to the source and drain electrodes are prepared.

[0016] In one embodiment of the present invention, the auxiliary gate position information includes:

[0017] The auxiliary gate is located between the gate electrode and the source electrode, or between the gate electrode and the drain electrode.

[0018] In one embodiment of the present invention, the auxiliary gate position information further includes the distance between the auxiliary gate and the gate electrode.

[0019] In one embodiment of the present invention, the distance between the auxiliary gate and the gate electrode includes 0, such that the auxiliary gate and the gate electrode form an integrated gate.

[0020] In one embodiment of the present invention, the auxiliary gate depth includes:

[0021] The auxiliary gate contacts the surface of the top barrier layer, or the auxiliary gate contacts the surface of the other barrier layers besides the top barrier layer by means of etching grooves.

[0022] In one embodiment of the present invention, the auxiliary gate metal work function includes:

[0023] The same metal work function as the gate electrode, or a different metal work function than the gate electrode.

[0024] In one embodiment of the present invention, the auxiliary gate bias voltage includes:

[0025] The same bias voltage as the gate electrode, or a different bias voltage than the gate electrode.

[0026] In one embodiment of the present invention, the material of the substrate layer includes:

[0027] SiC, Sapphire, Si, GaN.

[0028] In one embodiment of the present invention, the material of any barrier layer includes:

[0029] AlGaN, AlN, InAlN, ScAlN, InAlGaN, and N-plane GaN layers.

[0030] In a second aspect, embodiments of the present invention provide a gallium nitride device, which is fabricated according to the gallium nitride device fabrication method based on gate-terminated electric field modulation described in the first aspect.

[0031] The beneficial effects of this invention are:

[0032] In this embodiment of the invention, auxiliary gate parameters are determined according to the requirements of gate termination electric field control, including one or more of auxiliary gate position information, auxiliary gate depth, auxiliary gate metal work function, and auxiliary gate bias voltage. The auxiliary gate is fabricated according to these parameters, enabling the formation of different auxiliary gate structures and thus different gallium nitride device structures. This effectively improves the problems of poor gate control capability, degraded off-state characteristics, and low operating efficiency in dual / multi-channel structures due to the large distance between the top gate electrode and the carriers in the lower channel layer. Simultaneously, the auxiliary gate structure can effectively flatten the electric field distribution between channels, improving the Rs stability of dual / multi-heterojunction devices under high fields, thereby achieving flattened modulation of the device transconductance profile, improving the obvious double-peak characteristics, and effectively enhancing linearity. This provides a new optimized technical solution for the application of dual / multi-heterojunction gallium nitride devices in the field of high-power, high-linearity microwave communication. Attached Figure Description

[0033] Figure 1 This is a schematic flowchart of a gallium nitride device fabrication method based on gate termination electric field modulation provided in an embodiment of the present invention;

[0034] Figures 2(a) to 2(i) This is a schematic diagram of a process for fabricating a gallium nitride device based on gate terminal electric field modulation, as provided in an embodiment of the present invention.

[0035] Figure 3 This is a schematic diagram of the under-gate electric field of a gallium nitride HEMT with an auxiliary gate structure provided in an embodiment of the present invention.

[0036] Figure 4 This is a schematic diagram of another gallium nitride device structure provided in an embodiment of the present invention;

[0037] Figure 5 This is a schematic diagram of yet another gallium nitride device structure provided in an embodiment of the present invention;

[0038] Figure 6 This is a schematic diagram comparing the transconductance curves of two different gate-type dual-channel gallium nitride devices in an embodiment of the present invention.

[0039] Figure 7 This is a schematic diagram of another gallium nitride device structure provided in an embodiment of the present invention. Detailed Implementation

[0040] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0041] To meet the demands of higher output power applications, GaN HEMT heterojunctions have begun to employ multi-channel structures to reduce channel on-resistance, increase saturation output current, and thus improve output power density. However, for multi-channel devices, the distance from the gate electrode to the underlying channel is significantly affected by the thickness of multiple barrier layers and the channel layer itself. A larger number of channel layers and a thicker barrier layer lead to a greater distance between the gate and the channel, resulting in a lower aspect ratio for the same gate length, reduced gate control capability, and degraded off-state characteristics, leading to increased static power consumption and reduced operating efficiency. Simultaneously, the high barriers between multiple stacked channels hinder carrier coupling, causing the transconductance to exhibit a pronounced double-peak characteristic. This results in high higher-order transconductance, causing severe intermodulation distortion in the output signal, low system transmission efficiency, and limiting the application of dual / multi-channel devices in microwave communications.

[0042] The purpose of this invention is to address the shortcomings of existing dual / multi-channel GaN HEMT devices by proposing a scheme to improve the overall performance of dual / multi-channel GaN HEMT devices through gate termination electric field modulation technology, so as to meet the application requirements of higher output power in modern communication technology.

[0043] In a first aspect, embodiments of the present invention provide a method for fabricating gallium nitride devices based on gate-terminated electric field modulation, such as... Figure 1 As shown, the method may include the following steps:

[0044] S1, GaN buffer layer and at least two heterojunctions consisting of channel layer and barrier layer are grown sequentially on the substrate layer;

[0045] It is understandable that a set of channel layers and barrier layers constitutes a heterojunction, and at least two heterojunctions consisting of channel layers and barrier layers form a dual / multi-channel structure, thereby forming a dual / multi-heterojunction gallium nitride device. The specific number of heterojunctions can be set according to the requirements of gate termination electric field modulation.

[0046] Taking a substrate layer at the bottom and two heterojunctions grown as an example, the structure formed in step S1, from bottom to top, consists of a substrate layer, a GaN buffer layer, a first channel layer, a first barrier layer, a second channel layer, and a second barrier layer. The second barrier layer is the final grown top barrier layer.

[0047] In the embodiments of the present invention, the materials and thicknesses of the substrate layer, channel layer, and barrier layer can be set as needed.

[0048] For example, in one optional embodiment, the material of the substrate layer includes: SiC, sapphire, Si, and GaN.

[0049] In one optional embodiment, the material of the channel layer includes GaN, InGaN, AlGaN, etc.

[0050] In one optional implementation, the material of any barrier layer includes:

[0051] AlGaN, AlN, InAlN, ScAlN, InAlGaN, and N-plane GaN layers.

[0052] The thickness of each channel layer, as well as the variation in Al composition of the barrier layer for AlGaN, AlN, InAlN, ScAlN, and InAlGaN materials, are set according to the requirements of gate termination electric field modulation.

[0053] In this embodiment of the invention, the parameters set according to the requirements of gate termination electric field control are all parameters that can cause changes in the characteristics of dual / multi-channel gallium nitride devices, and can be reasonably set according to performance requirements.

[0054] S2, the source electrode and drain electrode are fabricated on the surface of the last grown top barrier layer;

[0055] Specifically, source and drain patterns are photolithographically etched on the upper surface of the top barrier layer, and source and drain metals are deposited respectively. Then, thermal annealing is performed to form ohmic contacts, resulting in the prepared source and drain electrodes.

[0056] The source and drain electrodes can be made of metals such as Ti / Al / Ni / Au, Ti / Al / Ti / TiN, or Ta / Al / Ti / TiN.

[0057] S3, a passivation layer is grown on the surface of the source electrode, the drain electrode and the top barrier layer;

[0058] The passivation layer protects the barrier layer interface from external contamination and effectively suppresses current collapse. The passivation layer can be made of materials such as SiN or SiO2; its thickness can be adjusted as needed.

[0059] S4, forming interconnect metal layer holes corresponding to the source electrode and drain electrode in the passivation layer;

[0060] Specifically, for the positions of the source and drain electrodes in the passivation layer, the passivation layer is subjected to aperture photolithography to expose the upper surfaces of the source and drain electrodes, forming interconnecting metal layer holes corresponding to the source and drain electrodes. The photolithography can employ contact lithography, stepper lithography, or electron beam lithography, etc.; the etching process can be achieved using F-based (fluorine-based) inductively coupled plasma, and no specific limitations are imposed here.

[0061] S5, etching a passivation layer to form a gate electrode between the source electrode and the drain electrode near the source electrode;

[0062] Specifically, gate pattern photolithography and groove etching are performed on the side near the source end between the source and drain electrodes to expose the top barrier layer on the surface. The obtained structure is then subjected to gate metal evaporation and stripped to obtain the gate electrode.

[0063] The gate electrode can be made of metals with high work functions such as Ni, Pd, Pt, and Au, which creates a gold-semiconductor contact with a large potential barrier difference to suppress gate leakage.

[0064] Fabricating a gate electrode closer to the source electrode between the source and drain electrodes can reduce the parasitic resistance between the gate and source, which is beneficial to improving the frequency characteristics of the device. At the same time, the gate electrode being closer to the source electrode results in a relatively larger gate-drain spacing, which improves the breakdown voltage of the device.

[0065] S6. Determine the auxiliary gate parameters according to the requirements of gate termination electric field control, and fabricate the auxiliary gate by etching the passivation layer according to the auxiliary gate parameters.

[0066] The auxiliary gate parameters include one or more of the following: auxiliary gate position information, auxiliary gate depth, auxiliary gate metal work function, and auxiliary gate bias voltage; the auxiliary gate position information indicates the positional relationship between the auxiliary gate and the gate electrode; the auxiliary gate depth indicates the position of the barrier layer in contact with the auxiliary gate.

[0067] Specifically, this step involves performing auxiliary gate pattern photolithography and groove etching based on the determined auxiliary gate parameters to expose the contact barrier layer surface, followed by auxiliary gate metal evaporation and stripping to obtain the auxiliary gate.

[0068] In one optional implementation, the auxiliary gate position information includes:

[0069] The auxiliary gate is located between the gate electrode and the source electrode, or between the gate electrode and the drain electrode.

[0070] When the auxiliary gate is located between the gate and the source, the source resistance (R) between the gate and the source can be suppressed. s The nonlinear growth of ) is based on the device transconductance and source resistance R s The relationship between G m =G m * / (1+R s ×G m * ), where G m For the transconductance of the device, G m * For the intrinsic transconductance of the device, R s This is the gate-source parasitic resistance of the device, i.e., the source resistance. Based on the above relationship, it can be seen that the modulation R... s After the nonlinear growth, the flatness of the transconductance profile of the device can be effectively improved;

[0071] When the auxiliary gate is between the gate and drain, there is a large non-uniformly distributed peak electric field on the side of the gate electrode near the drain electrode. This can easily cause the device to break down due to excessive local electric field, thus affecting the breakdown voltage of the device. Therefore, the presence of the auxiliary gate can flatten the peak electric field at the gate pin. On the one hand, it can suppress the peak electric field to a certain extent and improve the breakdown voltage of the device. On the other hand, it can alleviate the downward trend of the transconductance peak under high field and improve the linearity of the device.

[0072] In one optional implementation, the auxiliary gate position information further includes the distance between the auxiliary gate and the gate electrode.

[0073] Based on the relative positions of the auxiliary gate and the other electrodes, the following two cases will be explained:

[0074] I. Auxiliary gate between gate and drain

[0075] When the auxiliary gate is located between the gate and drain, its primary function is to modulate the non-uniformly distributed peak electric field at the gate pin, mitigating the degradation of channel carrier mobility under high fields, further suppressing transconductance roll-off, and improving device linearity. Therefore, when the auxiliary gate is far from the gate electrode, its modulating effect weakens, and the improvement in electric field suppression and planarization is not significant. In this case, a closer auxiliary gate to the gate electrode helps improve the device's gate control capability and peak electric field planarization capability, thereby improving transconductance planarity and breakdown voltage, and further enhancing the device's linearity and power characteristics. However, in actual device fabrication, a distance of too close between the auxiliary gate and the gate electrode (<100nm) poses a significant challenge to process implementation capabilities. Therefore, in actual device structure design, process capabilities should be comprehensively considered.

[0076] II. The auxiliary gate is located between the gate and source.

[0077] When the auxiliary gate is located between the gate and the source, the auxiliary gate mainly modulates the parasitic resistance R between the gate and the source. s The nonlinear growth of the auxiliary gate is used to modulate the transconductance profile of the device, thereby improving the linearity of the device. Specifically, when the auxiliary gate is far from the gate electrode, it can quickly regulate the initial velocity of the source carriers, increasing the initial velocity of the device drifting between the source and drain, enhancing the channel conduction capability between the gate and source, and reducing the Rs of the device. This helps to improve the transconductance flatness of the device, thereby improving the linearity of the device. However, at the same time, an excessively far auxiliary gate will weaken the ability to regulate the gate, degrade the off-state characteristics of the device, and thus affect the device's operating efficiency. Therefore, it needs to be set according to the actual requirements.

[0078] In one optional embodiment, the distance between the auxiliary gate and the gate electrode includes 0, such that the auxiliary gate and the gate electrode form an integrated gate.

[0079] In one optional implementation, the auxiliary gate depth includes:

[0080] The auxiliary gate contacts the surface of the top barrier layer, or the auxiliary gate contacts the surface of the other barrier layers besides the top barrier layer by means of etching grooves.

[0081] By increasing the depth of the auxiliary gate, the control capability of the auxiliary gate over the carriers in the underlying channel can be further improved. Specifically, the etching depth of the auxiliary gate can be determined by the following factors:

[0082] I. When the inter-channel distance between dual / multi-heterojunctions is large (>10nm):

[0083] The channel spacing between two / multi-heterojunctions refers to the distance between the channel surfaces formed by two adjacent heterojunctions. When the channel spacing is large, electrons are less likely to transition between heterojunction channel layers. If the auxiliary gate etching depth is too deep, the channel carrier concentration can drop sharply, affecting the device's saturation output current. Therefore, in this case, the groove etching depth of the auxiliary gate should be less than the thickness of the upper heterojunction barrier layer (i.e., the thickness of the top barrier layer). Within the allowable depth range, increasing the etching depth will help the auxiliary gate control the channel carriers, enhance the device's gate control capability, and improve its off-state characteristics.

[0084] II. When the inter-channel distance between dual / multi-heterojunctions is small (≤10nm):

[0085] When the channel spacing is small, because the carriers between the channel layers can undergo mutual transitions, there is a strong coupling effect between the channels. The saturation output current of the device will not be severely degraded due to excessive groove etching depth. Therefore, the groove depth of the auxiliary gate can be extended to the barrier layer of the lower heterojunction (i.e., the remaining barrier layers below the top barrier layer). As the groove etching depth increases, the auxiliary gate's control capability over different heterojunction carriers is enhanced, which helps to improve the gate control capability.

[0086] In one optional implementation, the auxiliary gate metal work function includes:

[0087] The same metal work function as the gate electrode, or a different metal work function than the gate electrode.

[0088] The metal used for the gate electrode can be a Ni / Au stacked metal, etc. The auxiliary gate can be a metal with the same work function as the gate electrode, or it can be a metal stack with different work functions such as Ti / Au, Pt / Au, Ti / Al, Pt / Al.

[0089] For auxiliary gates, metals with different work functions have different depletion effects on channel carriers.

[0090] In one optional implementation, the auxiliary gate bias voltage includes:

[0091] The same bias voltage as the gate electrode, or a different bias voltage than the gate electrode.

[0092] Here, the bias voltage refers to the static bias voltage. By applying a different bias voltage to the auxiliary gate than to the gate electrode, the peak electric field on the side of the gate electrode near the drain electrode can be flattened and dispersed.

[0093] The existence of a dual-gate structure can be equivalent to two common-source transistors for a transistor. Therefore, when the same bias voltage is applied to the auxiliary gate as to the gate electrode, the auxiliary gate can be regarded as a gate field plate structure, which flattens the peak electric field near the gate foot, thus enabling operation at higher bias voltages. This not only benefits the increase of device output power but also suppresses the decreasing trend of carrier saturation velocity at high fields, thereby improving the linearity of the device. On the other hand, when the bias voltage of the auxiliary gate is different from that of the gate electrode, the dual-gate structure is equivalent to two common-source transistors, which can have amplification capability with a greater gain effect on the input signal. Under the same input signal, a greater gain effect means greater output power. At the same time, the transconductance characteristics of the equivalent common-source amplifier transistors can be mutually compensated, so that the transconductance profiles of the dual / multi-heterojunction structure are mutually compensated, and the double-peak characteristic disappears.

[0094] The embodiments of the present invention fabricate auxiliary gates by determining auxiliary gate parameters, thereby forming different auxiliary gate structures and thus different gallium nitride device structures. This enhances the regulation of channel carriers in dual / multi-heterojunction gallium nitride devices, improves the average electron velocity between different channels, and enhances the overall performance of dual / multi-heterojunction gallium nitride devices, including off-state characteristics, breakdown voltage, output power, linearity, and efficiency.

[0095] Specifically, the location of the auxiliary gate, the etching depth of the groove under the auxiliary gate, and the bias voltage all have a significant impact on the linearity and power output characteristics of the device. On the one hand, the auxiliary gate can suppress the peak electric field near the gate electrode, allowing the device to be biased at a higher operating voltage. According to the relationship between output power and operating voltage, expanding the operating voltage range helps to achieve a higher output power characteristic of the device. At the same time, the flattened peak electric field can suppress the decreasing trend of carrier saturation velocity in multi-channel devices under high fields, further slowing down the decrease in transconductance profile. According to the relationship between the key linearity index OIP3 and transconductance, a flat transconductance profile helps to reduce the higher-order transconductance of the device, thereby achieving a larger OIP3 value and improving the linearity of the device. On the other hand, a gallium nitride transistor with an auxiliary gate structure can be equivalent to two common-source transistors. Therefore, the transconductance profile of each transistor can compensate for each other, thereby achieving the purpose of flattening the transconductance profile of the device and achieving greater linearity. In addition, two common-source transistors have a larger power gain, which makes the device have a greater signal amplification capability under the same input power gain, thus further improving the output power of the device.

[0096] The specific details will be analyzed and explained in the following text in conjunction with the corresponding auxiliary gate structure.

[0097] S7. Based on the location of the interconnect metal layer holes corresponding to the source electrode and drain electrode, prepare the interconnect metal layer corresponding to the source electrode and drain electrode.

[0098] Specifically, interconnect metal layers for the source and drain electrodes are fabricated at the locations of the interconnect metal layer holes corresponding to the source and drain electrodes on the passivation layer, thus completing the device fabrication process and obtaining the fabricated gallium nitride device.

[0099] In this embodiment of the invention, auxiliary gate parameters are determined according to the requirements of gate termination electric field control, including one or more of auxiliary gate position information, auxiliary gate depth, auxiliary gate metal work function, and auxiliary gate bias voltage. The auxiliary gate is fabricated according to these parameters, enabling the formation of different auxiliary gate structures and thus different gallium nitride device structures. This effectively improves the problems of poor gate control capability, degraded off-state characteristics, and low operating efficiency in dual / multi-channel structures due to the large distance between the top gate electrode and the carriers in the lower channel layer. Simultaneously, the auxiliary gate structure can effectively flatten the electric field distribution between channels, improving the Rs stability of dual / multi-heterojunction devices under high fields, thereby achieving flattened modulation of the device transconductance profile, improving the obvious double-peak characteristics, and effectively enhancing linearity. This provides a new optimized technical solution for the application of dual / multi-heterojunction gallium nitride devices in the field of high-power, high-linearity microwave communication.

[0100] The method of the present invention will be compared and explained with the prior art below:

[0101] For the fin structure with a three-dimensional gate, the key is the array etching of the barrier layer along the gate width, with an etching depth generally greater than 100 nm. Therefore, this structure results in an actual gate width much larger than the effective gate width, severely limiting the actual amplification capability. Simultaneously, it exhibits large parasitic capacitance, leading to generally poor frequency characteristics. In contrast to the fin structure, the auxiliary gate structure proposed in this invention can apply an additional bias voltage to the auxiliary gate. While achieving enhanced control of channel carriers by the gate electrode, it avoids excessive etching of the barrier layer. The effective gate width matches the actual gate width, resulting in high gain and guaranteed output power. Furthermore, because the peak electric field is suppressed, the operating voltage can be biased to a higher level, further contributing to higher output power.

[0102] The Si doping technique enhances the coupling effect between multi-channel structures. The key to this technique is to dope the barrier layer of the underlying heterojunction during material growth, thereby reducing the barrier height between the conductive channel layers and enhancing the carrier coupling between the channel layers. This improves the bimodal characteristics of the transconductance of dual / multi-heterojunction devices and further enhances the device linearity. However, this technique faces the key problems mentioned in the background section. In contrast, the auxiliary gate structure proposed in this invention can be equivalent to two common-source transistors. The transconductance profiles of each transistor can compensate for each other, thereby improving the transconductance flatness of the device and further effectively enhancing the device linearity.

[0103] The invention employs a back barrier structure to improve carrier confinement, focusing on addressing the problem of poor off-state characteristics caused by the poor gate control capability of multi-channel structures. The back barrier structure is proposed to improve the carrier confinement threshold capability, thereby improving the off-state characteristics of the device. As mentioned above, the auxiliary gate structure proposed in this invention can modulate the peak electric field near the gate foot. By applying different voltage biases to the auxiliary gate, the control effect of the gate electrode on the inter-channel carriers can be enhanced, thereby improving the gate control capability of the device.

[0104] Therefore, compared with the three existing technologies described in the background art, the auxiliary gate structure proposed in this invention has significant performance advantages.

[0105] To facilitate understanding of the embodiments of the present invention, specific embodiments are described below.

[0106] Example 1

[0107] The method for fabricating gallium nitride devices based on gate-terminated electric field modulation provided in this invention may include the following steps:

[0108] Step a1 involves sequentially growing a GaN buffer layer and at least two heterojunctions composed of channel layers and barrier layers on the substrate layer; therefore, the heterojunction in this embodiment of the invention can be a double heterojunction or a multi-heterojunction.

[0109] The substrate material includes: SiC, sapphire, Si, and GaN.

[0110] The material of any barrier layer includes: AlGaN, AlN, InAlN, ScAlN, InAlGaN, and N-plane GaN layers.

[0111] The structure obtained in step a1 is shown in Figure 2(a). For ease of understanding, the channel layer and barrier layer closest to the GaN buffer layer are named the lower channel layer and lower barrier layer, respectively, while the last grown channel layer and barrier layer further away from the GaN buffer layer are named the upper channel layer and upper barrier layer. There are also N heterojunctions between the lower barrier layer and the upper channel layer, where N is a natural number.

[0112] In step a2, source and drain patterns are photolithographically patterned on the upper barrier layer and corresponding source and drain metals are deposited. Then, thermal annealing is performed to form ohmic contacts, thus fabricating the source and drain electrodes. The result is shown in Figure 2(b).

[0113] Step a3: Deposit a passivation layer on the upper barrier layer and on the surfaces of the source and drain electrodes;

[0114] The results are shown in Figure 2(c). The passivation layer can be a dielectric layer such as SiN or SiO2, and its thickness can be 100–200 nm.

[0115] Step a4: Perform hole photolithography and etching at the positions of the source electrode and drain electrode in the passivation layer to form interconnect metal layer holes corresponding to the source electrode and drain electrode.

[0116] The photolithography process can employ contact lithography, stepper lithography, or electron beam lithography, among others; the etching process can be achieved using F-based inductively coupled plasma. The results are shown in Figure 2(d).

[0117] Step a5: Perform gate pattern photolithography and groove etching on the side near the source end between the source and drain electrodes to expose the upper barrier layer on the surface; the result is shown in Figure 2(e).

[0118] Step a6: The obtained structure is subjected to gate metal evaporation and stripped to obtain the gate electrode; the result is shown in Figure 2(f).

[0119] Step a7: Determine the auxiliary gate parameters according to the requirements of gate termination electric field control, and fabricate the auxiliary gate by etching the passivation layer according to the auxiliary gate parameters.

[0120] Among the auxiliary gate parameters, the auxiliary gate position information is that the auxiliary gate is located between the gate electrode and the drain electrode, and the distance between the auxiliary gate and the gate electrode is a preset distance greater than zero; the auxiliary gate depth is the distance at which the auxiliary gate contacts the upper surface of the upper barrier layer; the auxiliary gate work function is that the auxiliary gate uses a different work function than the gate electrode; and the auxiliary gate bias voltage is that the auxiliary gate uses a different bias voltage than the gate electrode. The result is shown in Figure 2(g).

[0121] Step a8: The obtained structure is subjected to auxiliary gate metal evaporation and stripped to obtain the auxiliary gate; the result is shown in Figure 2(h).

[0122] Step a9: Based on the locations of the interconnect metal layer holes corresponding to the source and drain electrodes formed on the passivation layer, the interconnect metal layers corresponding to the source and drain electrodes are fabricated to complete the device fabrication. The results are shown in Figure 2(i).

[0123] In this embodiment of the invention, by applying different bias voltages to the auxiliary gate, the peak electric field near the drain side of the gate can be flattened and dispersed (see [link to invention]). Figure 3 The diagram shows the modulation of the electric field distribution near the gate electrode by the auxiliary gate structure (i.e., the electric field under the gate). For conventional gallium nitride devices with a unipolar gate structure, electrons gradually accelerate and drift towards the drain with a relatively low initial velocity. This results in the maximum electron drift velocity in the channel reaching its maximum near the drain. Therefore, changes in the electric field near the drain can easily cause changes in the kinetic energy of the channel carriers, leading to a severe drain-induced barrier reduction effect. The auxiliary gate structure between the gate and drain can redistribute the electric field in the channel. By applying different bias voltages, the electric field on the gate-drain side can be adjusted, thereby reducing the high electric field effect of the device and improving the gate control capability. On the one hand, it can improve the breakdown voltage of the device and expand the operating voltage range of dual / multi-channel structures. On the other hand, the presence of the auxiliary gate structure enhances the electric field regulation of the carriers in the lower channel, increasing the average electron velocity between different channels, thereby further improving the operating efficiency of multi-channel gallium nitride devices. Figure 3 Chinese V g1 and V g2 These represent the bias voltages of the gate electrode and the auxiliary gate, respectively.

[0124] Example 2

[0125] Using a similar fabrication method to Example 1, another gallium nitride device structure can be fabricated, such as... Figure 4 As shown.

[0126] Compared to Example 1, in Example 2, the auxiliary gate contacts the upper surface of the lower barrier layer, which can further enhance the auxiliary gate's control over the carriers in the lower channel.

[0127] Example 3

[0128] Using a similar fabrication method to Example 1, another gallium nitride device structure can be fabricated, such as... Figure 5 As shown.

[0129] To address the issue of poor device linearity caused by the double-peak transconductance characteristics of dual-channel gallium nitride (HEMT) devices, embodiments of this invention can design an auxiliary gate between the gate and source. By changing the bias voltage on the auxiliary gate structure, electrons at the source end are initially accelerated, thereby reducing the source drive resistance Rs of the device and keeping Rs within a more stable value range. As can be seen from the relationship between transconductance and source-driven electrons, a more stable Rs helps to improve the linearity of the device.

[0130] Furthermore, based on Embodiment 3, a groove can be etched below the auxiliary gate structure, allowing the auxiliary gate to directly contact the upper surface of any lower barrier layer other than the top barrier layer. This further enhances the auxiliary gate's control over the lower channel carriers, which is not illustrated here. This design can compensate for the peaks and valleys of the transconductance in a dual-channel gallium nitride device, achieving flattening of the transconductance profile and thus improving the device's linearity. A schematic diagram of the improved transconductance profile of the dual-channel gallium nitride device is shown below. Figure 6 As shown, Figure 6 This is a schematic diagram comparing the transconductance curves of two different gate-type dual-channel gallium nitride devices in an embodiment of the present invention.

[0131] Example 4

[0132] Using a similar fabrication method to Example 1, another gallium nitride device structure can be fabricated, such as... Figure 7 As shown.

[0133] In this embodiment, the auxiliary gate is designed between the gate and the source, which helps to improve the linearity of the device. The auxiliary gate and the gate electrode form an integrated gate and use the same bias voltage.

[0134] Example 5

[0135] The purpose of this invention is to address the shortcomings of existing dual / multi-channel gallium nitride (GaN) devices, such as poor gate control capability and pronounced transconductance double-peak characteristics. This invention proposes a method for fabricating GaN devices that improves performance through gate termination electric field modulation technology, thereby meeting the application requirements of dual / multi-channel GaN devices in high-power microwave communication. The initial material can be a purchased epitaxial substrate. This epitaxial substrate, from bottom to top, includes a substrate, a GaN buffer layer, and a dual / multi-channel heterojunction structure. Based on this, an implementation method for fabricating GaN devices based on gate termination electric field modulation is provided. This method may include the following steps:

[0136] Step 1: Fabricate the source and drain electrodes on the epitaxial substrate.

[0137] Step 11: Photolithographically etch the source electrode region and drain electrode region on the top barrier layer of the epitaxial substrate:

[0138] Specifically, a double layer of photoresist is coated on the top barrier layer. The sample after coating and spin-coating is placed in a photolithography machine to expose the coated surface. The exposed sample is then placed in a developing solution to remove the photoresist and stripper, forming the photolithographic regions at the source and drain ends.

[0139] Step 12: Evaporate ohmic metal stacks in the photolithographic areas of the source and drain ends:

[0140] Specifically, the photolithographically etched area undergoes plasma treatment to remove residual resist. The sample is then placed in an electron beam evaporation stage, and the vacuum level in the reaction chamber of the electron beam evaporation stage reaches 2 × 10⁻⁶. -6 After Torr, Ti / Al / Ni / Au stacked metals are evaporated on the barrier layers in the source and drain regions and on the photoresist outside the source and drain regions to complete the ohmic metal evaporation.

[0141] The sample after ohmic metal evaporation is stripped to remove the ohmic metal, photoresist and release adhesive outside the source and drain electrodes. The sample is then rinsed with ultrapure water and dried with nitrogen.

[0142] Step 13: The sample after ohmic metal evaporation and stripping is placed in a rapid thermal annealing furnace for annealing treatment, so that the ohmic metal on the barrier layer in the source electrode and drain electrode sinks to the GaN buffer layer, thereby forming an ohmic contact between the ohmic metal and the heterojunction channel.

[0143] Step 2: Photolithographically etch the electrical isolation region of the active region on the top barrier layer, and fabricate the electrical isolation of the active region of the device using inductively coupled plasma (ICP) technology.

[0144] Step 21: Photolithographically lithographically create an electrically isolated region on the top barrier layer:

[0145] First, place the current sample on a hot plate at 210°C and bake for 10 minutes;

[0146] Then, the photoresist is coated and spun at a speed of 3000 rpm, and the current sample is baked on a hot plate at 100°C for 1 minute.

[0147] Finally, the current sample is placed in the lithography machine to expose the photoresist in the electrically isolated area. After exposure, the sample is placed in the developer to remove the photoresist in the electrically isolated area, and then rinsed with ultrapure water and dried with nitrogen.

[0148] Step 22: Etch an electrically isolated region on the top barrier layer:

[0149] First, the barrier layer and buffer layer of the electrically isolated region are etched sequentially using the ICP process to achieve mesa isolation of the active region, with a total etching depth of 130nm.

[0150] Finally, the current sample is sequentially placed in acetone solution, stripping solution, acetone solution and ethanol solution for cleaning to remove the photoresist outside the electrically isolated area, then rinsed with ultrapure water and dried with nitrogen.

[0151] Step 3: On the source electrode, drain electrode and the barrier layer of the active region, a passivation layer structure is grown using chemical vapor deposition processes such as PECVD, LPCVD or PEALD. The structure can be composed of dielectric layers such as SiN or SiO2.

[0152] Step 4: Photolithographically pattern the metal interconnection openings of the source and drain electrodes on the passivation layer, and use ICP process to etch away the passivation layer of the interconnection openings to form interconnection metal layer holes.

[0153] Step 41: Photolithographically etch the metal interconnect opening area on the passivation layer:

[0154] First, place the current sample on a hot plate at 200°C and bake for 5 minutes;

[0155] Then, the photoresist is coated and spun at a speed of 3500 rpm, and the sample is baked on a hot plate at 90°C for 1 minute.

[0156] Next, the current sample is placed in a lithography machine to expose the photoresist in the metal interconnect opening area;

[0157] Finally, the exposed sample is placed in the developer to remove the photoresist in the interconnect opening area, and then rinsed with ultrapure water and dried with nitrogen.

[0158] Step 42: Using ICP etching, under the conditions of CF4 and O2 as reaction gases, 10mTorr reaction chamber pressure, and 100W and 10W RF power of the upper and lower electrodes, respectively, the passivation layer in the interconnect opening area is removed.

[0159] Step 5: Photolithography of the gate electrode pattern and etching of the passivation layer in the gate region.

[0160] Step 51: Define the gate region using electron beam lithography.

[0161] First, place the current sample on a hot plate at 210°C and bake for 10 minutes to remove moisture from the sample surface;

[0162] Then, electron beam photoresist is applied. The electron beam photoresist can be polymethyl methacrylate (PMMA), ZEP520, AR-P6200.09, etc., which have high resolution and low sensitivity. The spin-spinning speed is 3000 rad / min to 5000 rad / min. After that, the sample is placed on a hot plate at 200°C and baked for 5 minutes.

[0163] Finally, the spun-coated substrate sample is exposed, developed, and fixed to form submicron fine grids of 20–100 nm in the first electron beam photoresist layer. Specifically, electron beam exposure can be performed using an NB5 lithography machine with an exposure dose of 7 C / m. 2 PMMA can be developed using a developer solution of methyl isobutyl ketone (MIBK):isopropanol (IPA) = 1:3, or AR-6200.09 can be developed using AR600-546.

[0164] Step 52: Use ICP etching process to etch the passivation layer trench in the gate region.

[0165] The passivation layer of the gate region was removed using an ICP etching process with CF4 and O2 plasmas, and RF power and bias power of 70W / 5W. Finally, the sample was sequentially cleaned in acetone solution, stripping solution, acetone solution, and ethanol solution to remove the photoresist outside the electrically isolated region. The sample was then rinsed with ultrapure water and dried with nitrogen.

[0166] Step 6: Fabrication of the gate electrode.

[0167] Step 61: Perform gate cap lithography using a stepper lithography machine.

[0168] First, place the current sample on a hot plate at 200°C and bake for 5 minutes;

[0169] Then, the release adhesive was applied and spun onto the passivation layer on the wafer surface, with a spun adhesive thickness of 0.35 μm, and the sample was baked on a hot plate at 200°C for 5 min.

[0170] Next, photoresist was coated and spin-coated onto the release agent, with a spin-coating thickness of 0.77 μm, and the sample was baked on a hot plate at 90°C for 1 min.

[0171] Afterwards, the sample with the completed coating and spin coating is placed in a photolithography machine to expose the photoresist in the gate electrode area;

[0172] Finally, the exposed sample is placed in the developer to remove the photoresist and stripper in the gate electrode area, and then rinsed with ultrapure water and dried with nitrogen.

[0173] Step 62: Evaporate the gate electrode on the barrier layer within the gate electrode region and on the photoresist outside the gate electrode region:

[0174] First, the sample with the photolithographic pattern of the gate electrode is placed in a plasma resist remover for bottom film treatment, which takes 5 minutes.

[0175] Then, the sample is placed in the electron beam evaporation stage, and the vacuum degree of the reaction chamber of the electron beam evaporation stage reaches 2×10⁻⁶. -6 After Torr, gate metal is evaporated on the barrier layer in the gate electrode region and on the photoresist outside the gate electrode region. This gate metal is a Ni / Au stacked metal, and the higher work function of Ni can effectively reduce gate leakage.

[0176] Finally, the sample after the gate metal evaporation is completed is stripped to remove the gate metal, photoresist and release adhesive outside the gate electrode area. The sample is then rinsed with ultrapure water and dried with nitrogen to form the gate electrode.

[0177] Step 7, auxiliary gate fabrication.

[0178] Step 71: Define the auxiliary gate using electron beam lithography.

[0179] First, place the current sample on a hot plate at 210°C and bake for 10 minutes to remove moisture from the sample surface;

[0180] Then, electron beam photoresist is applied. The electron beam photoresist can be polymethyl methacrylate (PMMA), ZEP520, AR-P6200.09, etc., which have high resolution and low sensitivity. The spin-coating speed is ~2000 rad / min and the spin-coating thickness is about 700 nm. After that, the sample is placed on a hot plate at 200℃ and baked for 5 min.

[0181] Finally, the spun-coated substrate sample is exposed, developed, and fixed to form submicron lines of 20–100 nm in the electron beam photoresist layer. Specifically, electron beam exposure can be performed using an NB5 lithography machine with an exposure dose of 7 C / m. 2 PMMA can be developed using a developer solution of methyl isobutyl ketone (MIBK):isopropanol (IPA) = 1:3, or AR-6200.09 can be developed using AR600-546.

[0182] Step 72: Use ICP etching process to etch the passivation layer trench in the gate region.

[0183] The passivation layer in the gate region was removed using an ICP etching process with CF4 and O2 plasmas, and the RF power and bias power were 70W and 5W respectively. Finally, the wafer with electron beam photoresist after surface etching was purged with nitrogen.

[0184] Step 73: Evaporate the auxiliary gate on the electron beam photoresist in the auxiliary gate region and outside the auxiliary gate region;

[0185] The sample obtained in step 72 is placed in an electron beam evaporation stage, and the vacuum level in the reaction chamber of the electron beam evaporation stage is allowed to reach 2 × 10⁻⁶. -6 After Torr, an auxiliary gate metal is evaporated on the barrier layer in the gate electrode region and the photoresist outside the gate electrode region. This auxiliary gate metal can be a Ni / Au stacked metal, or a metal stack with different work functions such as Ti / Au, Pt / Au, Ti / Al, and Pt / Al. Different work function structures are used to control the multi-channel carriers.

[0186] Finally, the sample with the auxiliary gate metal evaporated was stripped to remove the metal and photoresist outside the auxiliary gate region. The sample was then rinsed with ultrapure water and dried with nitrogen to form the auxiliary gate.

[0187] Step 8: Photolithographically pattern the metal interconnect layer region on the source and drain electrodes of the metal interconnect opening region and the passivation layer without opening etching, and fabricate the metal interconnect layer using electron beam evaporation process.

[0188] Step 81: Photolithographically etch a metal interconnect layer on the source and drain electrodes in the metal interconnect opening region and on the passivation layer without openings.

[0189] First, place the sample with the completed metal interconnect opening etching on a hot plate at 200°C and bake for 5 minutes;

[0190] Then, the release adhesive was applied and spun on the source and drain electrodes in the metal interconnect opening area and the passivation layer without opening etching. The spun adhesive thickness was 0.35 μm, and the sample was baked on a hot plate at 200°C for 5 min.

[0191] Next, photoresist was coated and spin-coated onto the release agent, with a spin-coating thickness of 0.77 μm, and the sample was baked on a hot plate at 90°C for 1 min.

[0192] Finally, the sample with the completed coating and spin coating is placed in the photolithography machine to expose the photoresist in the metal interconnect area. Then, the exposed sample is placed in the developer to remove the photoresist and stripper in the metal interconnect area, and then rinsed with ultrapure water and dried with nitrogen.

[0193] Step 82: Evaporate the metal interconnect layer on the electrodes and passivation layer within the metal interconnect region and on the photoresist outside the metal interconnect region:

[0194] First, the sample with the metal interconnect area is placed in a plasma desizing machine for bottom film treatment, which takes 5 minutes.

[0195] Then, the sample is placed in the electron beam evaporation stage, and the vacuum degree of the reaction chamber of the electron beam evaporation stage reaches 2×10⁻⁶. -6 After Torr, interconnect metal is evaporated on the electrodes and passivation layer in the metal interconnect region and on the photoresist outside the metal interconnect region to form a metal interconnect layer. This metal interconnect layer is a metal stack structure consisting of two layers, Ti and Au, arranged from bottom to top, to bring out the electrodes.

[0196] Finally, the sample with the interconnect metal evaporated is stripped to remove the metal, photoresist and release adhesive outside the metal interconnect layer, and the sample is rinsed with ultrapure water and dried with nitrogen to complete the device fabrication.

[0197] Secondly, corresponding to the method embodiment of the first aspect, the present invention also provides a gallium nitride device, which is prepared according to the gallium nitride device fabrication method based on gate terminal electric field modulation described in the first aspect.

[0198] Specifically, the formed gallium nitride device includes, from bottom to top, a substrate layer, a GaN buffer layer, and at least two heterojunctions composed of channel layers and barrier layers; source electrodes and drain electrodes are provided at both ends of the upper surface of the top barrier layer; corresponding metal interconnect layers are provided on the source electrodes and drain electrodes; a gate electrode is provided on the side of the source electrode between the source and drain electrodes, and an auxiliary gate is provided near the gate electrode; and passivation layers are provided on the top barrier layer, the source electrode, and the drain electrode.

[0199] The auxiliary gate can be located between the gate electrode and the source electrode, or between the gate electrode and the drain electrode. The distance between the auxiliary gate and the gate electrode can be greater than or equal to zero. The auxiliary gate can contact the upper surface of the top barrier layer, or it can contact the surfaces of other barrier layers besides the top barrier layer by etching grooves. The auxiliary gate can use the same work function as the gate electrode, or it can use a different work function. The auxiliary gate can use the same bias voltage as the gate electrode, or it can use a different bias voltage. The specific auxiliary gate structure can be designed and implemented by determining the auxiliary gate parameters according to the gate termination electric field control requirements corresponding to the actual application needs.

[0200] The embodiments of this invention can induce changes in the characteristics of dual / multi-channel gallium nitride devices by altering key parameters such as auxiliary gate parameters, the number of channels in a multi-channel structure (i.e., the specific number of heterojunctions), the thickness of each channel layer, and the variation in Al composition of the barrier layer for AlGaN, AlN, InAlN, ScAlN, and InAlGaN materials. In practical design, a suitable auxiliary gate structure can be selected according to different requirements to improve the overall device performance. For gallium nitride device structures formed by various auxiliary gate structures, please refer to the relevant content in the first aspect; they will not be repeated here.

[0201] In this embodiment of the invention, the structure of the gallium nitride (GaN) device is designed based on the requirements of gate terminal electric field control, and the auxiliary gate parameters include one or more of the following: auxiliary gate position information, auxiliary gate depth, auxiliary gate metal work function, and auxiliary gate bias voltage. By fabricating the auxiliary gate according to these parameters, different auxiliary gate structures can be formed, thus creating different GaN device structures. This effectively improves the problems of poor gate control capability, degraded off-state characteristics, and low operating efficiency in dual / multi-channel structures due to the large distance between the top gate electrode and the carriers in the lower channel layer. Simultaneously, the auxiliary gate structure can effectively flatten the electric field distribution between channels, improve the Rs stability of dual / multi-heterojunction devices under high fields, thereby achieving flattened modulation of the transconductance profile, improving the obvious double-peak characteristics, and effectively enhancing linearity. This provides a new optimized technical solution for the application of dual / multi-heterojunction GaN devices in high-power, high-linearity microwave communication.

[0202] The above description is merely a preferred embodiment of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention are included within the scope of protection of the present invention.

Claims

1. A method for fabricating gallium nitride devices based on gate-terminated electric field modulation, characterized in that, include: A GaN buffer layer and at least two heterojunctions consisting of a channel layer and a barrier layer are sequentially grown on the substrate. Source and drain electrodes are fabricated on the surface of the last grown top barrier layer; A passivation layer is grown on the surface of the source electrode, the drain electrode, and the top barrier layer; Interconnect metal layer holes corresponding to the source electrode and the drain electrode are formed in the passivation layer; A passivation layer is etched between the source electrode and the drain electrode, near the source electrode, to form a gate electrode; The auxiliary gate parameters are determined according to the requirements of gate termination electric field control. Based on the auxiliary gate parameters, the auxiliary gate is fabricated by etching the passivation layer. The auxiliary gate parameters include one or more of the following: auxiliary gate position information, auxiliary gate depth, auxiliary gate metal work function, and auxiliary gate bias voltage. The auxiliary gate position information indicates the positional relationship between the auxiliary gate and the gate electrode. The auxiliary gate depth indicates the position of the barrier layer in contact with the auxiliary gate. Based on the location of the interconnect metal layer holes corresponding to the source and drain electrodes, the interconnect metal layers corresponding to the source and drain electrodes are prepared.

2. The method for fabricating gallium nitride devices based on gate-terminated electric field modulation according to claim 1, characterized in that, The auxiliary gate position information includes: The auxiliary gate is located between the gate electrode and the source electrode, or between the gate electrode and the drain electrode.

3. The method for fabricating gallium nitride devices based on gate-terminated electric field modulation according to claim 2, characterized in that, The auxiliary gate position information also includes the distance between the auxiliary gate and the gate electrode.

4. The method for fabricating gallium nitride devices based on gate-terminated electric field modulation according to claim 3, characterized in that, The distance between the auxiliary gate and the gate electrode includes 0, such that the auxiliary gate and the gate electrode form an integrated gate.

5. The method for fabricating gallium nitride devices based on gate-terminated electric field modulation according to claim 1, characterized in that, The auxiliary gate depth includes: The auxiliary gate contacts the surface of the top barrier layer, or the auxiliary gate contacts the surface of the other barrier layers besides the top barrier layer by means of etching grooves.

6. The method for fabricating gallium nitride devices based on gate termination electric field modulation according to claim 1, characterized in that, The auxiliary gate metal work function includes: The same metal work function as the gate electrode, or a different metal work function than the gate electrode.

7. The method for fabricating gallium nitride devices based on gate termination electric field modulation according to claim 1, characterized in that, The auxiliary gate bias voltage includes: The same bias voltage as the gate electrode, or a different bias voltage than the gate electrode.

8. The method for fabricating gallium nitride devices based on gate termination electric field modulation according to claim 1, characterized in that, The material of any barrier layer includes: AlGaN, AlN, InAlN, ScAlN, InAlGaN, and N-plane GaN layers.

9. A gallium nitride device, characterized in that, The gallium nitride device is prepared according to the method for fabricating gallium nitride based on gate termination electric field modulation according to any one of claims 1 to 8.

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