Semiconductor test structure and method of forming same, test result analysis system

Abstract

The present disclosure relates to the field of semiconductor technology, and relates to a semiconductor test structure, a forming method thereof and a test result analysis system. The forming method comprises the following steps: providing a substrate; forming an isolation layer on the substrate; forming a capacitor structure on a surface of the isolation layer away from the substrate, the capacitor structure comprising a lower electrode layer, a capacitor dielectric layer and an upper electrode layer which are sequentially stacked in a direction perpendicular to the substrate; forming a first lead and a second lead on a side of the capacitor structure away from the substrate, the first lead being in contact with the lower electrode layer, the second lead being in contact with the upper electrode layer, and the first lead and the second lead not overlapping in orthographic projection on the substrate; and forming a first test pad and a second test pad arranged at intervals on a side of the isolation layer away from the substrate, the first test pad being in contact with the first lead, and the second test pad being in contact with the second lead. The forming method can accelerate the development progress of the capacitor and improve the accuracy of the test result.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and more specifically, to a semiconductor test structure, a method for forming the same, and a test result analysis system. Background Technology

[0002] Dynamic Random Access Memory (DRAM) is widely used in mobile devices such as mobile phones and tablets due to its advantages such as small size, high integration, and high transfer speed. Capacitors, as the core component of DRAM, are mainly used to store electrical charge.

[0003] In the DRAM manufacturing process, transistors are usually formed before capacitors are formed. To test the capacitors, transistors must be manufactured first, then capacitors, and then the capacitors must be tested. However, the transistor manufacturing process accounts for more than half of the entire process cycle, which makes the capacitor testing cycle long, the capacitor development progress slow, and the test structure is easily affected by other structures, resulting in low accuracy of test results.

[0004] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of this disclosure, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0005] In view of this, the present disclosure provides a semiconductor test structure and its formation method, as well as a test result analysis system, which can accelerate the progress of capacitor research and development and improve the accuracy of test results.

[0006] According to one aspect of this disclosure, a method for forming a semiconductor test structure is provided, comprising:

[0007] Provide substrate;

[0008] An isolation layer is formed on the substrate;

[0009] A capacitor structure is formed on the surface of the isolation layer away from the substrate. The capacitor structure includes a lower electrode layer, a capacitor dielectric layer, and an upper electrode layer that are stacked sequentially along a direction perpendicular to the substrate.

[0010] A first lead and a second lead are formed on the side of the capacitor structure away from the substrate. The first lead is in contact with the lower electrode layer, and the second lead is in contact with the upper electrode layer. The orthographic projections of the first lead and the second lead on the substrate do not overlap.

[0011] A first test pad and a second test pad are formed at intervals on the side of the isolation layer away from the substrate. The first test pad is in contact with the first lead, and the second test pad is in contact with the second lead.

[0012] In one exemplary embodiment of this disclosure, the forming method further includes:

[0013] A plurality of capacitor structures are formed on the surface of the isolation layer away from the substrate, each capacitor structure having a corresponding first lead and a second lead; in a direction parallel to the substrate, the areas of the upper electrode layers of at least some of the capacitor structures are not equal.

[0014] In one exemplary embodiment of this disclosure, the areas of the upper electrode layers of each capacitor structure are not equal in a direction parallel to the substrate.

[0015] In one exemplary embodiment of this disclosure, the capacitor structures are arranged side by side, and in a direction parallel to the substrate, the area of ​​the upper electrode layer in each capacitor structure increases or decreases sequentially.

[0016] In one exemplary embodiment of this disclosure, the orthographic projection of the first lead onto the substrate covers the perimeter of the orthographic projection of the lower electrode layer onto the substrate.

[0017] In one exemplary embodiment of this disclosure, a capacitor structure is formed on the surface of the isolation layer away from the substrate. The capacitor structure includes a lower electrode layer, a capacitor dielectric layer, and an upper electrode layer sequentially stacked along a direction perpendicular to the substrate, comprising:

[0018] A lower electrode material layer, a capacitor dielectric material layer, and an upper electrode material layer are sequentially formed on the side of the isolation layer away from the substrate.

[0019] The capacitor dielectric material layer and the upper electrode material layer are etched to form the capacitor dielectric layer and the upper electrode layer;

[0020] A photoresist layer is formed covering the upper electrode layer and the lower electrode material layer adjacent to the capacitor dielectric layer, wherein the orthographic projection of the photoresist layer on the substrate is within the orthographic projection of the lower electrode material layer on the substrate;

[0021] Remove the lower electrode material layer that is not covered by the photoresist layer to form the lower electrode layer.

[0022] In one exemplary embodiment of this disclosure, a first lead and a second lead are formed on the side of the capacitor structure away from the substrate. The first lead is in contact with the lower electrode layer, and the second lead is in contact with the upper electrode layer. The orthographic projections of the first lead and the second lead on the substrate do not overlap.

[0023] An insulating layer is formed covering the capacitor structure;

[0024] A mask layer is formed on the surface of the insulating layer;

[0025] The insulating layer is patterned using the mask layer as a mask to form a first contact hole exposing the lower electrode layer and a second contact hole exposing the upper electrode layer in the insulating layer. The orthographic projection of the first contact hole on the substrate does not overlap with the orthographic projection of the upper electrode layer on the substrate, and the orthographic projection of the second contact hole on the substrate is within the orthographic projection of the upper electrode layer on the substrate.

[0026] Conductive material is filled into the first contact hole and the second contact hole respectively to form a first lead in the first contact hole and a second lead in the second contact hole.

[0027] In one exemplary embodiment of this disclosure, etching is performed on the capacitor dielectric material layer and the upper electrode material layer to form the capacitor dielectric layer and the upper electrode layer, including:

[0028] A first photoresist layer is formed on the surface of the upper electrode material layer, and the orthographic projection of the first photoresist layer on the substrate is within the orthographic projection of the lower electrode material layer on the substrate;

[0029] Using the lower electrode material layer as an etching stop layer and the first photoresist layer as a photoresist, photolithography is performed on the capacitor dielectric material layer and the upper electrode material layer to form the capacitor dielectric layer and the upper electrode layer.

[0030] In one exemplary embodiment of this disclosure, the insulating layer is patterned using the mask layer as a mask to form a first contact hole exposing the lower electrode layer and a second contact hole exposing the upper electrode layer in the insulating layer, including:

[0031] A second photoresist layer is formed on the surface of the mask layer. The second photoresist layer includes a first developing area and a second developing area. The orthographic projection of the first developing area on the substrate does not overlap with the orthographic projection of the upper electrode layer on the substrate. The orthographic projection of the second developing area on the substrate is within the orthographic projection of the upper electrode layer on the substrate.

[0032] The mask layer and the insulating layer are etched in the first developing area and the second developing area to form a first contact hole exposing the lower electrode layer and a second contact hole exposing the upper electrode layer.

[0033] According to one aspect of this disclosure, a semiconductor test structure is provided, comprising:

[0034] Substrate;

[0035] An isolation layer is formed on the substrate;

[0036] A capacitor structure is formed on the surface of the isolation layer away from the substrate, the capacitor structure comprising a lower electrode layer, a capacitor dielectric layer and an upper electrode layer stacked sequentially along a direction perpendicular to the substrate;

[0037] A first lead and a second lead are formed on the side of the capacitor structure away from the substrate. The first lead is in contact with the lower electrode layer, and the second lead is in contact with the upper electrode layer. The orthographic projections of the first lead and the second lead on the substrate do not overlap.

[0038] A first test pad and a second test pad are arranged at intervals on the side of the isolation layer away from the substrate. The first test pad is in contact with the first lead, and the second test pad is in contact with the second lead.

[0039] In one exemplary embodiment of this disclosure, there are multiple capacitor structures, each formed on the surface of the isolation layer away from the substrate, and each capacitor structure has a corresponding first lead and a second lead; in a direction parallel to the substrate, the areas of the upper electrode layers of at least some of the capacitor structures are not equal.

[0040] In one exemplary embodiment of this disclosure, the areas of the upper electrode layers of each capacitor structure are not equal in a direction parallel to the substrate.

[0041] In one exemplary embodiment of this disclosure, the capacitor structures are arranged side by side, and in a direction parallel to the substrate, the area of ​​the upper electrode layer in each capacitor structure increases or decreases sequentially.

[0042] In one exemplary embodiment of this disclosure, the orthographic projection of the first lead onto the substrate covers the perimeter of the orthographic projection of the lower electrode layer onto the substrate.

[0043] According to one aspect of this disclosure, a test result analysis system is provided, comprising:

[0044] A data import component is used to import test data of any of the semiconductor test structures described above; the test data includes the area of ​​the upper electrode layer of each capacitor structure and the storage capacity corresponding to each capacitor structure.

[0045] A data generation component is used to generate test analysis results based on the area of ​​the upper electrode layer of each capacitor structure and the corresponding storage capacity of each capacitor structure.

[0046] The semiconductor test structure and its formation method disclosed herein can directly form a planar capacitor structure on a substrate. The lower electrode layer of the capacitor structure is connected to a first test pad via a first lead, and the upper electrode layer of the capacitor structure is connected to a second test pad via a second lead. The capacitor structure is then tested by inserting test probes onto the first and second test pads. In this process, on the one hand, there is no need to wait for transistor fabrication before capacitor fabrication and testing, which shortens the capacitor testing cycle and accelerates capacitor development. On the other hand, there is no need to fabricate a high aspect ratio aperture structure, eliminating the influence of the aperture formation process on the test results. Simultaneously, since the capacitor structure is directly fabricated on the substrate, and there are no other structures (e.g., transistors) on the substrate, the influence of other structures on the capacitor test results is eliminated, making the test results more accurate and improving the accuracy of the test results. Furthermore, by setting an isolation layer between the capacitor structure and the substrate, and thus preventing impurities inside the substrate from diffusing into the capacitor structure, the influence of impurities in the substrate on the capacitor structure test results can be eliminated, further improving the accuracy of the test results.

[0047] The test result analysis system disclosed herein can generate test analysis results based on the area of ​​the upper electrode layer of each capacitor structure and the storage capacity of each capacitor structure. It can clearly show the relationship between the area of ​​the capacitor structure and the storage capacity of the capacitor structure. A monitoring board can be made based on the test analysis results. During the research and development process, the process stability of the capacitor dielectric layer can be monitored through the monitoring board. So that when the storage capacity of the capacitor structure obtained by testing changes during the process, the change in the storage capacity of the capacitor structure can be quickly checked based on the test analysis results to see if it is due to the change in the material of the capacitor dielectric layer or the change in the key dimensions of the capacitor structure, which can accelerate the research and development progress.

[0048] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0049] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. It is obvious that the drawings described below are merely some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0050] Figure 1 This is a schematic diagram of DRAM in related technologies;

[0051] Figure 2 This is a flowchart of a method for forming a semiconductor test structure according to an embodiment of the present disclosure;

[0052] Figure 3 This is a schematic diagram of the structure after step S130 is completed in the embodiment of this disclosure;

[0053] Figure 4 This is a flowchart of step S130 in the embodiment of this disclosure;

[0054] Figure 5 This is a flowchart of step S220 in the embodiment of this disclosure;

[0055] Figure 6 This is a schematic diagram of the structure after step S2210 is completed in the embodiment of this disclosure;

[0056] Figure 7 This is a schematic diagram of the structure after step S2220 is completed in the embodiment of this disclosure;

[0057] Figure 8 This is a schematic diagram of the structure after step S230 is completed in the embodiment of this disclosure;

[0058] Figure 9 This is a schematic diagram of the structure after step S240 is completed in the embodiment of this disclosure;

[0059] Figure 10 This is a top view of the photoresist layer in the embodiment of this disclosure;

[0060] Figure 11 This is a top view of the first photoresist layer in the embodiment of this disclosure;

[0061] Figure 12 This is a flowchart of step S140 in the embodiment of this disclosure;

[0062] Figure 13 This is a schematic diagram of the structure after step S310 is completed in the embodiment of this disclosure;

[0063] Figure 14 This is a schematic diagram of the structure after step S320 is completed in the embodiment of this disclosure;

[0064] Figure 15 This is a schematic diagram of the structure after step S330 is completed in the embodiment of this disclosure;

[0065] Figure 16 This is a schematic diagram of the structure after step S3310 is completed in the embodiment of this disclosure;

[0066] Figure 17 This is a schematic diagram of the structure after step S340 is completed in the embodiment of this disclosure;

[0067] Figure 18 This is a schematic diagram of the conductive material layer in an embodiment of this disclosure;

[0068] Figure 19 This is a schematic diagram of the third photoresist layer in the embodiments of this disclosure;

[0069] Figure 20 This is a schematic diagram of the third photoresist layer when forming multiple capacitor structures in the embodiments of this disclosure;

[0070] Figure 21 This is a schematic diagram of the structure after step S150 is completed in the embodiment of this disclosure;

[0071] Figure 22 This is a schematic diagram of a photomask formed when multiple first test pads and multiple second test pads are formed in the embodiments of this disclosure;

[0072] Figure 23 This is a schematic diagram of the superposition of photomasks in the embodiments of this disclosure.

[0073] Explanation of reference numerals in the attached figures:

[0074] 100. Transistor; 200. Capacitor structure 3; 1. Substrate; 2. Isolation layer; 3. Capacitor structure; 31. Lower electrode layer; 310. Lower electrode material layer; 32. Capacitor dielectric layer; 320. Capacitor dielectric material layer; 33. Upper electrode layer; 330. Upper electrode material layer; 41. First lead; 411. First contact hole; 42. Second lead; 421. Second contact hole; 51. First test pad; 52. Second test pad; 300. Photoresist layer; 400. Insulating layer; 500. Mask layer; 600. Conductive material layer; 700. First photoresist layer; 800. Second photoresist layer; 801. First developing area; 802. Second developing area; 900. Third photoresist layer. Detailed Implementation

[0075] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the embodiments set forth herein; rather, they are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the exemplary embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and therefore detailed descriptions of them will be omitted. Furthermore, the drawings are merely illustrative of this disclosure and are not necessarily drawn to scale.

[0076] Although relative terms such as "up" and "down" are used in this specification to describe the relative relationship of one component of an icon to another, these terms are used only for convenience, such as according to the orientation of the examples shown in the accompanying drawings. It is understood that if the device of the icon is flipped upside down, the component described as "up" will become the component described as "down." When a structure is "up" of another structure, it may mean that the structure is integrally formed on the other structure, or that the structure is "directly" mounted on the other structure, or that the structure is "indirectly" mounted on the other structure through another structure.

[0077] The terms “a,” “one,” “the,” “the,” and “at least one” are used to indicate the presence of one or more elements / components / etc.; the terms “including” and “having” are used to indicate an open-ended inclusion and to mean that there may be other elements / components / etc. in addition to the listed elements / components / etc.; the terms “first” and “second” are used only as markers and are not a limitation on the number of objects.

[0078] like Figure 1 As shown, Dynamic Random Access Memory (DRAM) typically includes transistors 100 and capacitor structures 200. In DRAM manufacturing, transistors 100 are usually manufactured first, followed by capacitor structures 200. Therefore, the transistor 100 fabrication process consumes a significant portion of the time during the testing of capacitor structures 200, resulting in a longer testing cycle and slower development progress. Furthermore, during capacitor structure 200 testing, the test structure is susceptible to interference from transistors 100, leading to lower test accuracy. Additionally, during product manufacturing, the storage capacity of capacitor structures 200 is typically increased by increasing their surface area. This involves forming high aspect ratio apertures on the substrate, within which capacitor structures 200 are formed. However, due to limitations in the fabrication process, the critical dimensions of the formed apertures contain errors, and incomplete etching of the apertures can easily occur. All of these factors significantly interfere with the test results of capacitor structures 200, resulting in low accuracy.

[0079] Based on this, the present disclosure provides a method for forming a semiconductor test structure to solve the above-mentioned technical problems. Figure 2 A flowchart illustrating a method for forming a semiconductor test structure according to an embodiment of this disclosure is shown. See also... Figure 2 As shown, the forming method may include steps S110-S150, wherein:

[0080] Step S110: Provide a substrate;

[0081] Step S120: An isolation layer is formed on the substrate;

[0082] Step S130: A capacitor structure is formed on the surface of the isolation layer away from the substrate. The capacitor structure includes a lower electrode layer, a capacitor dielectric layer, and an upper electrode layer that are stacked sequentially along a direction perpendicular to the substrate.

[0083] Step S140: A first lead and a second lead are formed on the side of the capacitor structure away from the substrate. The first lead is in contact with the lower electrode layer, and the second lead is in contact with the upper electrode layer. The orthographic projections of the first lead and the second lead on the substrate do not overlap.

[0084] In step S150, a first test pad and a second test pad are formed at intervals on the side of the isolation layer away from the substrate. The first test pad is in contact with the first lead, and the second test pad is in contact with the second lead.

[0085] The method for forming a semiconductor test structure disclosed herein can directly form a planar capacitor structure on a substrate. The lower electrode layer of the capacitor structure is connected to a first test pad via a first lead, and the upper electrode layer of the capacitor structure is connected to a second test pad via a second lead. The capacitor structure is then tested by inserting test probes onto the first and second test pads respectively. In this process, on the one hand, there is no need to wait for transistor fabrication before capacitor fabrication and testing, which shortens the capacitor testing cycle and accelerates capacitor development. On the other hand, there is no need to fabricate a high aspect ratio aperture structure, eliminating the influence of the aperture formation process on the test results. Simultaneously, since the capacitor structure is directly fabricated on the substrate, which has no other structures (e.g., transistors), the influence of other structures on the capacitor test results is eliminated, making the test results more accurate and improving the accuracy of the test results. Furthermore, by setting an isolation layer between the capacitor structure and the substrate, and thus preventing impurities from the substrate from diffusing into the capacitor structure, the influence of impurities in the substrate on the capacitor structure test results can be eliminated, further improving the accuracy of the test results.

[0086] The steps of the method for forming a semiconductor test structure according to the present disclosure will be described in detail below:

[0087] like Figure 2 As shown, in step S110, a substrate is provided.

[0088] like Figure 3 As shown, substrate 1 can be a flat plate structure, which can be rectangular, circular, elliptical, polygonal or irregular in shape, and its material can be silicon or other semiconductor materials. No special restrictions are made on the shape and material of substrate 1 here.

[0089] like Figure 2 As shown, in step S120, an isolation layer is formed on the substrate.

[0090] In one exemplary embodiment of this disclosure, the isolation layer may be located on the surface of the substrate, and the isolation layer can separate the substrate from other film layers to prevent impurities in the substrate from diffusing into other film layers, thereby helping to ensure the stability of the device.

[0091] The isolation layer 2 can be a thin film or a coating formed on the surface of the substrate 1, and there is no particular limitation. In one embodiment, the isolation layer 2 can be formed on the surface of the substrate 1 by chemical vapor deposition, physical vapor deposition, atomic layer deposition, thermal evaporation, vacuum evaporation or magnetron sputtering, etc. Of course, the isolation layer 2 can also be formed by other methods, and there is no particular limitation.

[0092] The material of the insulating layer 2 can be an insulating material, such as silicon dioxide, a high-k dielectric material, or other dielectric materials, or any combination thereof. The thickness of the insulating layer 2 can be set according to actual needs.

[0093] like Figure 2 As shown, in step S130, a capacitor structure is formed on the surface of the isolation layer away from the substrate. The capacitor structure includes a lower electrode layer, a capacitor dielectric layer, and an upper electrode layer that are stacked sequentially along a direction perpendicular to the substrate.

[0094] In one exemplary embodiment of this disclosure, the capacitor structure 3 may be a planar capacitor. The capacitor structure 3 may include a stacked lower electrode layer 31, a capacitor dielectric layer 32, and an upper electrode layer 33. The lower electrode layer 31 may be located on the surface of the isolation layer 2, the capacitor dielectric layer 32 may be located on the surface of the lower electrode layer 31, and the upper electrode layer 33 may be located on the surface of the capacitor dielectric layer 32. The area of ​​the upper electrode layer 33 may be equal to the area of ​​the capacitor dielectric layer 32. The area of ​​the upper electrode layer 33 may be equal to or unequal to the area of ​​the lower electrode layer 31, and no special limitation is made here.

[0095] In one embodiment, the lower electrode layer 31 may be circular, elliptical, rectangular, or irregular in shape, and the upper electrode layer 33 may be circular, elliptical, rectangular, or irregular in shape. The shape of the capacitor dielectric layer 32 may be the same as that of the upper electrode layer 33, and the shape of the upper electrode layer 33 may be the same as or different from that of the lower electrode layer 31; no special limitation is made here.

[0096] In one exemplary embodiment of this disclosure, there may be multiple capacitor structures 3, and multiple capacitor structures 3 may be formed on the surface of the isolation layer 2 away from the substrate 1. The manufacturing process of each capacitor structure 3 is the same, and multiple capacitor structures 3 can be formed by the same capacitor structure 3 forming process.

[0097] For example, the number of capacitor structures 3 can be 12 to 48, such as 12, 24, 36 or 48. Of course, the number of capacitor structures 3 can also be other numbers. No special limitation is made on the number of capacitor structures 3 here.

[0098] It should be noted that the number of capacitor structures 3 can be set according to the number of test pins of the test equipment in the subsequent testing process. For example, if the test equipment includes 24 test pins and 2 test pins are needed to test each capacitor structure 3, then the number of capacitor structures 3 can be 12; if the test equipment includes 48 test pins and 2 test pins are needed to test each capacitor structure 3, then the number of capacitor structures 3 can be 24; if the test equipment includes 72 test pins and 2 test pins are needed to test each capacitor structure 3, then the number of capacitor structures 3 can be 36; if the test equipment includes 96 test pins and 2 test pins are needed to test each capacitor structure 3, then the number of capacitor structures 3 can be 48. Of course, the number of test pins of the test equipment can also be other, and correspondingly, the number of capacitor structures 3 can also be other, which will not be listed here.

[0099] In one embodiment, in a direction parallel to the substrate 1, at least some of the capacitor structures 3 have unequal areas of their upper electrode layers 3. Multiple capacitor structures 3 with unequal areas can be fabricated simultaneously, allowing for subsequent analysis based on the area of ​​the capacitor structures 3 and the storage capacity of the capacitor structures 3 with different areas obtained from testing. For example, the number of capacitor structures 3 can be 48, with 36 of them having unequal areas of their upper electrode layers 33; or, the number of capacitor structures 3 can be 36, with 24 of them having unequal areas of their upper electrode layers 33; or, the number of capacitor structures 3 can be 24, with 12 of them having unequal areas of their upper electrode layers 33.

[0100] In one exemplary embodiment of this disclosure, the area of ​​the lower electrode layer 31 in each capacitor structure 3 is equal. Taking the shape of the lower electrode layer 31 as an example, the area of ​​the lower electrode layer 31 in each capacitor structure 3 can be 35um*286.76um.

[0101] In some embodiments of this disclosure, the area of ​​the lower electrode layer 31 in each capacitor structure 3 is equal in the direction parallel to the substrate 1, and the area of ​​the upper electrode layer 33 in each capacitor structure 3 is unequal. By testing the electrical performance of capacitor structures 3 with unequal upper electrode layer 33 areas, test analysis results can be generated based on the area of ​​the upper electrode layer 33 and the storage capacity of each capacitor structure 3. The relationship between the area of ​​the capacitor structure 3 and the storage capacity of the capacitor structure 3 can be clearly seen from the test analysis results. A monitoring board can also be fabricated based on the test analysis results. During the research and development process, the process stability of the capacitor dielectric layer 32 can be monitored through the monitoring board. When the storage capacity of the capacitor structure 3 obtained during the process changes, the test analysis results can be used to quickly check whether the change in the storage capacity of the capacitor structure 3 is due to a change in the material of the capacitor dielectric layer 32 or a change in the critical dimensions of the capacitor structure 3, thereby accelerating the research and development progress.

[0102] In one embodiment, each capacitor structure 3 can be arranged side by side on the surface of the isolation layer 2, and in the direction parallel to the substrate 1, the area of ​​the upper electrode layer 33 in each capacitor structure 3 can be increased or decreased sequentially. In this way, the relationship between the capacitor area and the capacitor storage capacity can be clearly seen in the subsequent testing process, which helps to reduce the difficulty of data analysis.

[0103] The following section uses the manufacture of capacitor structure 3 as an example to explain in detail the process of manufacturing capacitor structure 3:

[0104] In one exemplary embodiment of this disclosure, a capacitor structure 3 is formed on the surface of the isolation layer 2 away from the substrate 1. The capacitor structure 3 includes a lower electrode layer 31, a capacitor dielectric layer 32, and an upper electrode layer 33 sequentially stacked along a direction perpendicular to the substrate 1 (i.e., step S130). This may include steps S210-S240, as follows: Figure 4 As shown, where:

[0105] Step S210: A lower electrode material layer, a capacitor dielectric material layer, and an upper electrode material layer are sequentially formed on the side of the isolation layer away from the substrate.

[0106] In one embodiment, a lower electrode material layer 310, a capacitor dielectric material layer 320, and an upper electrode material layer 330 may be sequentially formed on the surface of the isolation layer 2. For example, the lower electrode material layer 310 may be formed on the surface of the isolation layer 2, the capacitor dielectric material layer 320 may be formed on the surface of the lower electrode material layer 310, and the upper electrode material layer 330 may be formed on the surface of the capacitor dielectric material layer 320. For ease of fabrication, the lower electrode material layer 310, the capacitor dielectric material layer 320, and the upper electrode material layer 330 may all be flush with both ends of the isolation layer 2, that is, the orthographic projection of the lower electrode material layer 310, the orthographic projection of the capacitor dielectric material layer 320, and the orthographic projection of the upper electrode material layer 330 on the substrate 1 may all coincide with the orthographic projection of the isolation layer 2 on the substrate 1.

[0107] For example, the lower electrode material layer 310, the capacitor dielectric material layer 320, and the upper electrode material layer 330 can be sequentially formed on the surface of the isolation layer 2 by means of vacuum evaporation, magnetron sputtering, thermal evaporation, chemical vapor deposition, physical vapor deposition, or atomic layer deposition. Of course, the lower electrode material layer 310, the capacitor dielectric material layer 320, and the upper electrode material layer 330 can also be formed by other processes. No special limitation is made here on the formation method of the lower electrode material layer 310, the capacitor dielectric material layer 320, and the upper electrode material layer 330.

[0108] The material of the lower electrode material layer 310 can be titanium, titanium nitride, tungsten, or germanium-silicon, or a combination of any two of the above materials. Of course, other materials suitable as electrodes can also be used; no special limitations are placed on the material and formation process of the lower electrode material layer 310. The capacitor dielectric material layer 320 can be a single-layer film structure composed of the same material, or a mixed film structure composed of film layers of different materials. For example, it can include materials with a high dielectric constant, such as alumina, hafnium oxide, lanthanum oxide, titanium oxide, zirconium oxide, tantalum oxide, niobium oxide, strontium oxide, silicon nitride, or mixtures thereof. Other materials are also possible, and will not be listed here. The material of the upper electrode material layer 330 can be titanium, titanium nitride, tungsten, or germanium-silicon, or a combination of any two of the above materials. Of course, other materials suitable as electrodes can also be used; no special limitations are placed on the material of the upper electrode material layer 330.

[0109] It should be noted that the material of the upper electrode material layer 330 can be the same as or different from the material of the lower electrode material layer 310, and no special limitation is made here. For example, the materials of both the upper electrode material layer 330 and the lower electrode material layer 310 can be a combination of titanium nitride and germanium silicon; or the material of the upper electrode material layer 330 can be titanium nitride and the material of the lower electrode material layer 310 can be tungsten; or the material of the upper electrode material layer 330 can be tungsten and the material of the lower electrode material layer 310 can be titanium nitride.

[0110] Step S220: Etch the capacitor dielectric material layer and the upper electrode material layer to form the capacitor dielectric layer and the upper electrode layer.

[0111] In one exemplary embodiment of this disclosure, the area of ​​the upper electrode layer 33 may be smaller than the area of ​​the lower electrode material layer 310, and the area of ​​the capacitor dielectric layer 32 may be equal to the area of ​​the upper electrode layer 33. The capacitor dielectric layer 320 and the upper electrode material layer 330 can be etched by photolithography to form the capacitor dielectric layer 32 and the upper electrode layer 33.

[0112] In one exemplary embodiment of this disclosure, etching the capacitor dielectric material layer 320 and the upper electrode material layer 330 to form the capacitor dielectric layer 32 and the upper electrode layer 33 (i.e., step S220) may include steps S2210 and S2220, as follows: Figure 5 As shown, where:

[0113] Step S2210: A first photoresist layer is formed on the surface of the upper electrode material layer, and the orthographic projection of the first photoresist layer on the substrate is within the orthographic projection of the lower electrode material layer on the substrate.

[0114] A photolithography layer can be formed on the surface of the upper electrode material layer 330 by spin coating or other methods. The material of the photolithography layer can be positive or negative photoresist, without special limitation. For ease of processing, the photolithography layer can cover the entire surface of the upper electrode material layer 330, and a portion of the photolithography layer can be removed to form a first photoresist layer 700. The area of ​​the first photoresist layer 700 can be smaller than the area of ​​the lower electrode material layer 310, and the orthogonal projection of the first photoresist layer 700 onto the substrate 1 can lie within the orthogonal projection of the lower electrode material layer 310 onto the substrate 1. In the direction parallel to the substrate 1, the first photoresist layer 700 can be circular, elliptical, fan-shaped, rectangular, or irregular in shape. Of course, the first photoresist layer 700 can also be other shapes, which will not be listed here. The structure after step S2210 in this embodiment is as follows: Figure 6 As shown.

[0115] Step S2220: Using the lower electrode material layer as an etching stop layer and the first photoresist layer as a photoresist, photolithography is performed on the capacitor dielectric material layer and the upper electrode material layer to form the capacitor dielectric layer and the upper electrode layer.

[0116] The upper electrode material layer 330 and the capacitor dielectric material layer 320 that do not overlap with the first photoresist layer 700 in the direction perpendicular to the substrate 1 can be removed, thereby forming the capacitor dielectric layer 32 and the upper electrode layer 33. For example, the lower electrode material layer 310 can be used as an etching stop layer to perform anisotropic etching on the upper electrode material layer 330 and the capacitor dielectric material layer 320 that do not overlap with the first photoresist layer 700 in the direction perpendicular to the substrate 1. In this process, the first photoresist layer 700 can be used as a photoresist, thereby retaining the upper electrode material layer 330 and the capacitor dielectric material layer 320 that overlap with the first photoresist layer 700 in the direction perpendicular to the substrate 1. That is, the upper electrode material layer 330 and the capacitor dielectric layer 320 directly below the first photoresist layer 700 are retained. After etching, the upper electrode material layer 330 located directly below the first photoresist layer 700 can be defined as the upper electrode layer 33, and the capacitor dielectric material layer 320 located directly below the first photoresist layer 700 can be defined as the capacitor dielectric layer 32.

[0117] It should be noted that after etching, the first photoresist layer 700 can be removed by ashing or other processes, thereby exposing the upper electrode layer 33 formed by etching. The structure after step S2220 in this embodiment is as follows: Figure 7 As shown.

[0118] Step S230: A photoresist layer is formed covering the upper electrode layer and the lower electrode material layer adjacent to the capacitor dielectric layer, wherein the orthographic projection of the photoresist layer on the substrate is within the orthographic projection of the lower electrode material layer on the substrate.

[0119] A photoresist layer can be formed on the surfaces of the upper electrode layer 33 and the lower electrode material layer 310 by spin coating or other methods. The material of the photoresist layer can be positive or negative photoresist, without special limitation. For ease of fabrication, the photoresist layer can cover the entire surface of the structure formed by the upper electrode layer 33, the capacitor dielectric layer 32, and the lower electrode material layer 310. That is, the photoresist layer can cover the surface of the upper electrode layer 33, the sidewalls of the capacitor dielectric layer 32, and the surface of the structure in the lower electrode material layer 310 not covered by the capacitor dielectric layer 32. Part of the photoresist layer can be removed to form a photoresist layer 300. The area of ​​the photoresist layer 300 can be larger than the area of ​​the upper electrode layer 33 and smaller than the area of ​​the lower electrode material layer 310. The orthogonal projection of the upper electrode layer 33 on the substrate 1 can be within the orthogonal projection of the photoresist layer 300 on the substrate 1, and the orthogonal projection of the photoresist layer 300 on the substrate 1 can be within the orthogonal projection of the lower electrode material layer 310 on the substrate 1.

[0120] In the direction parallel to the substrate 1, the photoresist layer 300 can be circular, elliptical, fan-shaped, rectangular, or irregular in shape. Of course, the photoresist layer 300 can also be other shapes, which will not be listed here. The structure after step S230 in this embodiment is as follows: Figure 8 As shown.

[0121] Step S240: Remove the lower electrode material layer not covered by the photoresist layer to form the lower electrode layer.

[0122] The lower electrode material layer 310 can be etched to form the lower electrode layer 31. For example, the lower electrode material layer 310 that does not overlap with the photoresist layer 300 in the direction perpendicular to the substrate 1 can be removed to form the lower electrode layer 31. For example, the lower electrode material layer 310 that does not overlap with the photoresist layer 300 in the direction perpendicular to the substrate 1 can be anisotropically etched using the isolation layer 2 as an etch stop layer. In this process, the photoresist layer 300 can be used as a photoresist, and the lower electrode material layer 310 that overlaps with the photoresist layer 300 in the direction perpendicular to the substrate 1 can be retained. That is, the lower electrode material layer 310 directly below the photoresist layer 300 can be retained. After etching, the lower electrode material layer 310 located directly below the photoresist layer 300 can be defined as the lower electrode layer 31.

[0123] It should be noted that after etching, the photoresist layer 300 can be removed by ashing or other processes, thereby exposing the surface of the upper electrode layer 33, the sidewalls of the capacitor dielectric layer 32, and the surfaces of the lower electrode layer 31 not covered by the capacitor dielectric layer 32. At this time, the area of ​​the upper electrode layer 33 is smaller than the area of ​​the lower electrode layer 31. The structure after step S240 in this embodiment is as follows. Figure 9 As shown.

[0124] It should be noted that when multiple capacitor structures 3 have their lower electrode layers 31 formed using the same patterning process, the shape of the photoresist layer 300 can be as follows: Figure 10 As shown, with Figure 10 The photoresist layer 300 is formed by etching the lower electrode material layer 310 using a photomask, resulting in multiple lower electrode layers 31 with equal areas. When forming multiple upper electrode layers 33 of capacitor structures 3 using the same patterning process, the shape of the first photoresist layer 700 can be as follows: Figure 11 As shown, in Figure 11 The area of ​​each region of the photomask increases sequentially from left to right, with... Figure 11 The photoresist layer 300 is formed by etching the upper electrode material layer 330 and the capacitor dielectric material layer 320 with a photomask, which can form multiple upper electrode layers 33 with different areas, and the area of ​​each upper electrode layer 33 increases from left to right.

[0125] For example, in the direction parallel to the substrate 1, the area of ​​the upper electrode layer 33 of each capacitor structure 3 can be 10um*10um, 20um*20um, 25um*62um, 25um*63um, 25um*155um, and 25um*252um from left to right.

[0126] like Figure 2 As shown, in step S140, a first lead and a second lead are formed on the side of the capacitor structure away from the substrate. The first lead is in contact with the lower electrode layer, and the second lead is in contact with the upper electrode layer. The orthographic projections of the first lead and the second lead on the substrate do not overlap.

[0127] Both the first lead 41 and the second lead 42 can be made of conductive material. The lower electrode layer 31 and the upper electrode layer 33 can be electrically led out through the first lead 41 and the second lead 42 respectively, so that test voltage can be applied to the lower electrode layer 31 and the upper electrode layer 33 of the capacitor structure 3 through the first lead 41 and the second lead 42, thereby completing the electrical performance test of the capacitor structure 3.

[0128] It should be noted that when there are multiple capacitor structures 3, each capacitor structure 3 may have a corresponding first lead 41 and second lead 42.

[0129] The process of forming the first lead 41 and the second lead 42 corresponding to a capacitor structure 3 will be explained in detail below:

[0130] In one exemplary embodiment of this disclosure, a first lead 41 and a second lead 42 are formed on the side of the capacitor structure 3 away from the substrate 1. The first lead 41 is in contact with the lower electrode layer 31, and the second lead 42 is in contact with the upper electrode layer 33. The orthographic projections of the first lead 41 and the second lead 42 on the substrate 1 do not overlap (i.e., step S140). This may include steps S310-S340, as follows: Figure 12 As shown, where:

[0131] Step S310: Form an insulating layer covering the capacitor structure.

[0132] In one exemplary embodiment of this disclosure, the insulating layer 400 may cover the surface of the capacitor structure 3, and may simultaneously cover the surface of the isolation layer 2 that is not covered by the lower electrode layer 31, and the end of the insulating layer 400 may be flush with the end of the isolation layer 2.

[0133] The insulating layer 400 can be a thin film formed on the surface of the capacitor structure 3, the lower electrode layer 31, and the upper electrode layer 33, or it can be a coating formed on the surface of the capacitor structure 3, the lower electrode layer 31, and the upper electrode layer 33; no particular limitation is made here. In one embodiment, the insulating layer 400 can be formed on the surface of the capacitor structure 3, the lower electrode layer 31, and the upper electrode layer 33 by means of chemical vapor deposition, physical vapor deposition, atomic layer deposition, thermal evaporation, vacuum evaporation, or magnetron sputtering. Of course, the insulating layer 400 can also be formed by other means; no particular limitation is made here.

[0134] The insulating layer 400 can be made of insulating materials, such as silicon dioxide, high-k dielectric materials, or other dielectric materials, or any combination thereof. The thickness of the insulating layer 400 can be set according to actual needs. The structure after step S310 in this embodiment is as follows: Figure 13 As shown.

[0135] Step S320: A mask layer is formed on the surface of the insulating layer.

[0136] For example, a mask layer 500 can be formed on the surface of the insulating layer 400. The mask layer 500 can be a single-layer film or a composite film composed of multiple film layers. There is no special limitation on the number of thin film layers in the mask layer 500. When it is a multi-layer film, the materials of adjacent film layers can be different.

[0137] The mask layer 500 can be an anti-reflective coating, and its material can be an insulating material. For example, its material can be silicon, silicon nitride, silicon oxide, or carbide, etc. The specific material can be selected according to the design and requirements of the subsequent photolithography process. In one embodiment, the mask layer 500 can have a low dielectric constant and a certain hardness, which can reduce the coupling with the substrate 1 while meeting the requirements of the subsequent etching process. For example, its material can be carbon-doped silicon nitride. The structure after step S320 in this embodiment is as follows: Figure 14 As shown.

[0138] Step S330: Pattern the insulating layer using the mask layer as a mask to form a first contact hole exposing the lower electrode layer and a second contact hole exposing the upper electrode layer in the insulating layer. The orthographic projection of the first contact hole on the substrate does not overlap with the orthographic projection of the upper electrode layer on the substrate, and the orthographic projection of the second contact hole on the substrate is within the orthographic projection of the upper electrode layer on the substrate.

[0139] A first contact hole 411 and a second contact hole 421 can be formed in the insulating layer 400 by etching. The first contact hole 411 can expose the lower electrode layer 31. The first contact hole 411 can be a circular hole, an elliptical hole, a rectangular hole, an annular hole, or other shaped hole structure. There is no special limitation on the shape of the first contact hole 411, as long as it can expose the lower electrode layer 31.

[0140] In one embodiment, the orthographic projection of the first contact hole 411 on the substrate 1 and the orthographic projection of the lower electrode layer 31 on the substrate 1 at least partially overlap, and the orthographic projection of the first contact hole 411 on the substrate 1 does not overlap with the orthographic projection of the upper electrode layer 33 on the substrate 1. Preferably, the first contact hole 411 may be annular, and its orthographic projection on the substrate 1 may cover the circumference of the edge of the orthographic projection of the lower electrode layer 31 on the substrate 1, that is, the first contact hole 411 may expose the circumference of the edge of the lower electrode layer 31.

[0141] The orthographic projection of the second contact hole 421 on the substrate 1 does not overlap with the orthographic projection of the first contact hole 411 on the substrate 1, and the orthographic projection of the second contact hole 421 on the substrate 1 is within the orthographic projection of the upper electrode layer 33 on the substrate 1. The first contact hole 411 and the second contact hole 421 are isolated by an insulating layer 400, thereby preventing the first lead 41 formed in the first contact hole 411 from being short-circuited with the second lead 42 formed in the second contact hole 421.

[0142] The second contact hole 421 can expose the upper electrode layer 33. The second contact hole 421 can be a circular hole, an elliptical hole, a rectangular hole, or other shaped hole structure. The shape of the second contact hole 421 is not specifically limited here, as long as it exposes the upper electrode layer 33. The structure after step S330 in this embodiment is as follows: Figure 15 As shown.

[0143] In one exemplary embodiment of this disclosure, the insulating layer 400 is patterned using the mask layer 500 as a mask to form a first contact hole 411 exposing the lower electrode layer 31 and a second contact hole 421 exposing the upper electrode layer 33 in the insulating layer 400 (i.e., step S330). This may include steps S3310 and S3320, wherein:

[0144] Step S3310: A second photoresist layer is formed on the surface of the mask layer. The second photoresist layer includes a first developing area and a second developing area. The orthographic projection of the first developing area on the substrate does not overlap with the orthographic projection of the upper electrode layer on the substrate. The orthographic projection of the second developing area on the substrate is within the orthographic projection of the upper electrode layer on the substrate.

[0145] A second photoresist layer 800 can be formed on the surface of the mask layer 500 by spin coating or other methods. The material of the second photoresist layer 800 can be positive or negative photoresist, without special limitation. For ease of processing, the second photoresist layer 800 can cover the entire surface of the mask layer 500. A mask can be used to expose and develop the second photoresist layer 800 to form a first developing region 801 and a second developing region 802 in the second photoresist layer 800; wherein:

[0146] The first developing area 801 may be circular, elliptical, rectangular, annular, or other shapes, and no special limitation is made on the shape of the first developing area 801 here. The orthographic projection of the first developing area 801 on the substrate 1 and the orthographic projection of the lower electrode layer 31 on the substrate 1 overlap at least partially, and the orthographic projection of the first developing area 801 on the substrate 1 and the orthographic projection of the upper electrode layer 33 on the substrate 1 do not overlap.

[0147] The second developing area 802 can be circular, elliptical, rectangular, or other shapes; no special limitation is made to the shape of the second developing area 802 here. The orthographic projection of the second developing area 802 on the substrate 1 does not overlap with the orthographic projection of the first contact hole 411 on the substrate 1, and the orthographic projection of the second developing area 802 on the substrate 1 is within the orthographic projection of the upper electrode layer 33 on the substrate 1. The structure after step S3310 in this embodiment is as follows: Figure 16 As shown.

[0148] Step S3320: Etch the mask layer and the insulating layer in the first developing area and the second developing area to form a first contact hole exposing the lower electrode layer and a second contact hole exposing the upper electrode layer.

[0149] The insulating layer 400 can be etched by a dry etching process using a mask layer 500 as a mask, in the first developing area 801 and the second developing area 802, thereby forming a first contact hole 411 that exposes the lower electrode layer 31 and a second contact hole 421 that exposes the upper electrode layer 33.

[0150] The etching gases used in dry etching may include SF6 and CF2. x It contains at least one gas selected from Cl2 or Ar. For example, it may include Ar, and may also include SF6 or CF2. x Or at least one of the gases, such as Cl2.

[0151] It should be noted that after forming the first contact hole 411 and the second contact hole 421, there is no need to remove the mask layer 500. For example, the remaining mask layer 500 can be retained, and the surface of the test structure can be protected by the mask layer 500 to avoid damage to the surface of the test structure. In addition, the compressive stress of the mask layer 500 can balance the tensile stress in the insulating layer 400, so that the test structure can achieve stress balance.

[0152] Step S340: Fill the first contact hole and the second contact hole with conductive material to form a first lead in the first contact hole and a second lead in the second contact hole.

[0153] Conductive materials can be filled into the first contact hole 411 and the second contact hole 421 by means of electroplating, vacuum evaporation, magnetron sputtering, chemical vapor deposition, physical vapor deposition, atomic layer deposition, or thermal evaporation. Alternatively, other methods can be used to fill the first contact hole 411 and the second contact hole 421 with conductive materials, thereby forming a first lead 41 in the first contact hole 411 and a second lead 42 in the second contact hole 421, so that the lower electrode layer 31 and the upper electrode layer 33 can be electrically led out through the first lead 41 and the second lead 42, respectively. The structure after step S340 in this embodiment is as follows: Figure 17 As shown.

[0154] It should be noted that when the first contact hole 411 is annular and its orthogonal projection on the substrate 1 covers the edge of the orthogonal projection of the lower electrode layer 31 on the substrate 1, the first lead 41 can also be annular. The orthogonal projection of the first lead 41 on the substrate 1 can cover the edge of the orthogonal projection of the lower electrode layer 31 on the substrate 1, thereby enabling a uniform electric field distribution during subsequent electrical performance testing of the capacitor structure 3 and ensuring the accuracy of the test structure.

[0155] In one exemplary embodiment of this disclosure, the conductive material may be a metallic material, such as tungsten or titanium nitride, or other materials with good conductivity, which will not be listed here.

[0156] In some embodiments of this disclosure, such as Figure 18 As shown, during the filling of conductive material, for ease of process, conductive material can be deposited simultaneously on the surface of mask layer 500, thereby forming conductive material layer 600 on the surface of mask layer 500. When the conductive material fills the first contact hole 411 and the second contact hole 421, the deposition stops. At this time, the conductive material in the first contact hole 411 and the conductive material in the second contact hole 421 are connected together through conductive material layer 600. The conductive material layer 600 on the surface of mask layer 500 can be etched by a patterning process (e.g., photolithography) to disconnect the first lead 41 in the first contact hole 411 and the second lead 42 in the second contact hole 421.

[0157] For example, such as Figure 19As shown, a third photoresist layer 900 can be formed on the surface of the conductive material layer 600. The third photoresist layer 900 is exposed and developed to form a developing area. The developing area can be located between the first contact hole 411 and the second contact hole 421, and the developing area can be annularly surrounding the outer circumference of the first contact hole 411. When the second contact hole 421 is annular, the annularity of the developing area can be located within the annularity of the second contact hole 421. The orthographic projection of the third photoresist layer 900 on the substrate 1 at least partially overlaps with the orthographic projection of the first lead 41 on the substrate 1. At the same time, the orthographic projection of the third photoresist layer 900 on the substrate 1 at least partially overlaps with the orthographic projection of the second lead 42 on the substrate 1.

[0158] It should be noted that when forming the first lead 41 and second lead 42 corresponding to multiple capacitor structures 3 through the same patterning process, the shape of the third photoresist layer 900 can be as follows: Figure 20 As shown, with Figure 20 The third photoresist layer 900 is formed by etching the conductive material layer 600 with a photomask, which can form multiple first leads 41 that are respectively connected to the lower electrode layer 31 of each capacitor structure 3 and multiple second leads 42 that are respectively connected to the upper electrode layer 33 of each capacitor structure 3.

[0159] like Figure 2 As shown, in step S150, a first test pad and a second test pad are formed at intervals on the side of the isolation layer away from the substrate. The first test pad is in contact with the first lead, and the second test pad is in contact with the second lead.

[0160] Each capacitor structure 3 can be provided with a first test pad 51 and a second test pad 52. Both the first test pad 51 and the second test pad 52 can be made of conductive material. Each first test pad 51 and each second test pad 52 can be located on both sides of the corresponding capacitor structure 3. The first test pad 51 and the second test pad 52 can be connected to the first lead 41 and the second lead 42 corresponding to the capacitor structure 3, respectively, so that the test voltage can be transmitted to the lower electrode layer 31 and the upper electrode layer 33 of the capacitor structure 3 through the first test pad 51 and the second test pad 52, so as to complete the electrical performance test of the capacitor structure 3.

[0161] In some embodiments of this disclosure, the first test pad 51 and the second test pad 52 may be formed on the surface of the isolation layer 2 and may be arranged at intervals on the surface of the isolation layer 2; the first test pad 51 and the second test pad 52 may also be formed on the surface of the insulating layer 400 and may be arranged at intervals on the surface of the insulating layer 400; the first test pad 51 and the second test pad 52 may also be formed on the surface of the mask layer 500 and may be arranged at intervals on the surface of the mask layer 500; of course, the first test pad 51 and the second test pad 52 may also be formed on the surface of other film layers on the side of the isolation layer 2 away from the substrate 1. The specific positions of the first test pad 51 and the second test pad 52 are not specifically limited here, as long as the first test pad 51 and the second test pad 52 can be connected to the first lead 41 and the second lead 42 respectively and can transmit the test voltage to the first lead 41 and the second lead 42.

[0162] For example, the first test pad 51 and the second test pad 52 can be formed on the side of the isolation layer 2 away from the substrate 1 by means of vacuum evaporation, magnetron sputtering, chemical vapor deposition, physical vapor deposition, atomic layer deposition or thermal evaporation. Of course, the first test pad 51 and the second test pad 52 can also be formed by other means. No special limitation is made here on the formation method of the first test pad 51 and the second test pad 52.

[0163] The material of the first test pad 51 can be a metallic material, such as tungsten or titanium nitride. Of course, it can also be other materials with good conductivity, which will not be listed here. In some embodiments, the materials of the first test pad 51 and the second test pad 52 can be the same or different, and no special limitation is made here. For example, the materials of the first test pad 51 and the second test pad 52 can be the same. For example, both the first test pad 51 and the second test pad 52 can be made of tungsten, or both the first test pad 51 and the second test pad 52 can be made of titanium nitride, or one of the first test pad 51 and the second test pad 52 can be made of tungsten and the other of titanium nitride.

[0164] Each capacitor structure 3, together with its corresponding first lead 41, second lead 42, first test pad 51, and second test pad 52, constitutes a test unit. The spacing between each test unit can be set according to the spacing of the pins in the test equipment, and is not specifically limited here. The structure after step S150 in this embodiment is as follows: Figure 21 As shown.

[0165] It should be noted that when forming multiple capacitor structures 3 corresponding to the first test pad 51 and the second test pad 52 through the same patterning process, the following can be used: Figure 22 The light mask shown is used to Figure 22The photoresist layer 300 is formed by etching a metal material layer with a photomask to form multiple first test pads 51 that are respectively connected to the first lead 41 of each capacitor structure 3 and multiple second test pads 52 that are respectively connected to the second lead 42 of each capacitor structure 3.

[0166] In each patterning process, the photomask used to form the lower electrode layer 31, the photomask used to form the upper electrode layer 33, the photomask used to form the first lead 41 and the second lead 42, and the photomask used to form the first test pad 51 and the second test pad 52 are stacked together as follows: Figure 23 As shown in the figure, the photomask area between two adjacent test units can be used for alignment, which can minimize alignment errors as much as possible.

[0167] During the test, two test probes in the test equipment can be placed on the first test pad 51 and the second test pad 52 respectively to complete the test of the capacitor structure 3. The semiconductor test structure disclosed herein has high test sensitivity and can detect weak ferroelectric or antiferroelectric effect signals present in the capacitor structure 3.

[0168] It should be noted that although the steps of the method for forming the semiconductor test structure in this disclosure are described in a specific order in the accompanying drawings, this does not require or imply that these steps must be performed in that specific order, or that all the steps shown must be performed to achieve the desired result. Additional or alternative steps may be omitted, multiple steps may be combined into one step, and / or one step may be broken down into multiple steps.

[0169] This disclosure also provides a semiconductor testing structure, such as... Figure 17 and Figure 21 As shown, the semiconductor test structure may include a substrate 1, an isolation layer 2, a capacitor structure 3, a first lead 41 and a second lead 42, and a first test pad 51 and a second test pad 52, wherein:

[0170] The isolation layer 2 can be formed on the substrate 1;

[0171] The capacitor structure 3 can be formed on the surface of the isolation layer 2 away from the substrate 1. The capacitor structure 3 may include a lower electrode layer 31, a capacitor dielectric layer 32 and an upper electrode layer 33 stacked sequentially along a direction perpendicular to the substrate 1.

[0172] The first lead 41 and the second lead 42 can be formed on the side of the capacitor structure 3 away from the substrate 1. The first lead 41 is in contact with the lower electrode layer 31, and the second lead 42 is in contact with the upper electrode layer 33. The orthographic projections of the first lead 41 and the second lead 42 on the substrate 1 do not overlap.

[0173] The first test pad 51 and the second test pad 52 can be arranged at intervals on the side of the isolation layer 2 away from the substrate 1. The first test pad 51 is in contact with the first lead 41, and the second test pad 52 is in contact with the second lead 42.

[0174] The semiconductor test structure disclosed herein can directly form a planar capacitor structure 3 on a substrate 1. The lower electrode layer 31 of the capacitor structure 3 can be connected to the first test pad 51 via a first lead 41, and the upper electrode layer 33 of the capacitor structure 3 can be connected to the second test pad 52 via a second lead 42. The capacitor structure 3 can be tested by inserting test probes onto the first test pad 51 and the second test pad 52. In the above process, on the one hand, there is no need to wait for the transistor to be fabricated before the capacitor is fabricated and tested, which can shorten the capacitor testing cycle and accelerate the capacitor R&D progress; on the other hand, there is no need to manufacture a hole structure with a high aspect ratio, which can eliminate the influence of the hole structure formation process on the test results; at the same time, since the capacitor structure 3 is directly fabricated on the substrate 1, and there are no other structures (e.g., transistors) on the substrate 1, the influence of other structures on the capacitor test results can be eliminated, making the test results more accurate and improving the accuracy of the test results; in addition, by setting an isolation layer 2 between the capacitor structure 3 and the substrate 1, the impurities inside the substrate 1 can be blocked from diffusing into the capacitor structure 3, which can eliminate the influence of impurities in the substrate 1 on the test results of the capacitor structure 3, further improving the accuracy of the test results.

[0175] The specific details of the semiconductor test structure in the embodiments of this disclosure are described in detail below:

[0176] like Figure 3 As shown, substrate 1 can be a flat plate structure, which can be rectangular, circular, elliptical, polygonal or irregular in shape, and its material can be silicon or other semiconductor materials. No special restrictions are made on the shape and material of substrate 1 here.

[0177] The isolation layer 2 can be located on the surface of the substrate 1. The isolation layer 2 can separate the substrate 1 from other film layers to prevent impurities in the substrate 1 from diffusing into other film layers, which helps to ensure the stability of the device.

[0178] The isolation layer 2 can be a thin film or a coating formed on the surface of the substrate 1, without any particular limitation. The material of the isolation layer 2 can be an insulating material, such as silicon dioxide, a high-k dielectric material, or other dielectric materials, or any combination thereof. The thickness of the isolation layer 2 can be set according to actual needs.

[0179] The capacitor structure 3 can be a planar capacitor. The capacitor structure 3 can include a stacked lower electrode layer 31, a capacitor dielectric layer 32, and an upper electrode layer 33. The lower electrode layer 31 can be located on the surface of the isolation layer 2, the capacitor dielectric layer 32 can be located on the surface of the lower electrode layer 31, and the upper electrode layer 33 can be located on the surface of the capacitor dielectric layer 32. The area of ​​the upper electrode layer 33 can be equal to the area of ​​the capacitor dielectric layer 32. The area of ​​the upper electrode layer 33 and the area of ​​the lower electrode layer 31 can be equal or unequal, which is not specifically limited here.

[0180] In one embodiment, the lower electrode layer 31 may be circular, elliptical, rectangular, or irregular in shape, and the upper electrode layer 33 may be circular, elliptical, rectangular, or irregular in shape. The shape of the capacitor dielectric layer 32 may be the same as that of the upper electrode layer 33, and the shape of the upper electrode layer 33 may be the same as or different from that of the lower electrode layer 31; no special limitation is made here.

[0181] The material of the upper electrode layer 33 can be a material with good conductivity. For example, it may include titanium, titanium nitride, tungsten, or germanium silicon, or a combination of any two of the above materials. Preferably, the material of the upper electrode layer 33 can be a combination of titanium nitride and germanium silicon. The material of the lower electrode layer 31 can also be a material with good conductivity. It can be the same as the material of the upper electrode layer 33 or a different material, without special limitation. Preferably, the material of the lower electrode layer 31 is the same as the material of the upper electrode layer 33. For example, both the material of the lower electrode layer 31 and the material of the upper electrode layer 33 are a combination of titanium nitride and germanium silicon. The material of the capacitor dielectric layer 32 can be a material with a high dielectric constant. For example, it can be alumina, hafnium oxide, lanthanum oxide, titanium oxide, zirconium oxide, tantalum oxide, niobium oxide, strontium oxide, silicon nitride, or a mixture thereof. Of course, it can also be other materials, which will not be listed here.

[0182] In one exemplary embodiment of this disclosure, there may be multiple capacitor structures 3, and multiple capacitor structures 3 may be formed on the surface of the isolation layer 2 away from the substrate 1. The manufacturing process of each capacitor structure 3 is the same, and multiple capacitor structures 3 can be formed by the same capacitor structure 3 forming process.

[0183] For example, the number of capacitor structures 3 can be 12 to 48, such as 12, 24, 36 or 48. Of course, the number of capacitor structures 3 can also be other numbers. No special limitation is made on the number of capacitor structures 3 here.

[0184] It should be noted that the number of capacitor structures 3 can be set according to the number of test pins of the test equipment in the subsequent testing process. For example, if the test equipment includes 24 test pins and 2 test pins are needed to test each capacitor structure 3, then the number of capacitor structures 3 can be 12; if the test equipment includes 48 test pins and 2 test pins are needed to test each capacitor structure 3, then the number of capacitor structures 3 can be 24; if the test equipment includes 72 test pins and 2 test pins are needed to test each capacitor structure 3, then the number of capacitor structures 3 can be 36; if the test equipment includes 96 test pins and 2 test pins are needed to test each capacitor structure 3, then the number of capacitor structures 3 can be 48. Of course, the number of test pins of the test equipment can also be other, and correspondingly, the number of capacitor structures 3 can also be other, which will not be listed here.

[0185] In one embodiment, in a direction parallel to the substrate 1, at least some of the capacitor structures 3 have unequal areas of their upper electrode layers 3. Multiple capacitor structures 3 with unequal areas can be fabricated simultaneously, allowing for subsequent analysis based on the area of ​​the capacitor structures 3 and the storage capacity of the capacitor structures 3 with different areas obtained from testing. For example, the number of capacitor structures 3 can be 48, with 36 of them having unequal areas of their upper electrode layers 33; or, the number of capacitor structures 3 can be 36, with 24 of them having unequal areas of their upper electrode layers 33; or, the number of capacitor structures 3 can be 24, with 12 of them having unequal areas of their upper electrode layers 33.

[0186] In one exemplary embodiment of this disclosure, the area of ​​the lower electrode layer 31 in each capacitor structure 3 is equal. Taking the shape of the lower electrode layer 31 as an example, the area of ​​the lower electrode layer 31 in each capacitor structure 3 can be 35um*286.76um.

[0187] In some embodiments of this disclosure, the area of ​​the lower electrode layer 31 in each capacitor structure 3 is equal in the direction parallel to the substrate 1, and the area of ​​the upper electrode layer 33 in each capacitor structure 3 is unequal. By testing the electrical performance of capacitor structures 3 with unequal upper electrode layer 33 areas, more effective data can be obtained, which can enrich the database for subsequent data analysis, improve the accuracy of data analysis, and thus quickly eliminate the influence of parasitic capacitance on the capacitance size in subsequent analysis.

[0188] In one embodiment, the capacitor structures 3 can be arranged side-by-side on the surface of the isolation layer 2, and in the direction parallel to the substrate 1, the area of ​​the upper electrode layer 33 in each capacitor structure 3 can be sequentially increased or decreased. This allows for a clearer understanding of the relationship between the capacitor area and its storage capacity during subsequent testing, helping to reduce the difficulty of data analysis. Furthermore, after testing, a curve showing the relationship between the area of ​​the capacitor structure 3 and its storage capacity can be plotted based on the test results, enabling the rapid elimination of abnormal data based on this curve.

[0189] For example, in the direction parallel to the substrate 1, the area of ​​the upper electrode layer 33 of each capacitor structure 3 can be 10um*10um, 20um*20um, 25um*62um, 25um*63um, 25um*155um, and 25um*252um from left to right.

[0190] Both the first lead 41 and the second lead 42 can be made of conductive material. The lower electrode layer 31 and the upper electrode layer 33 can be electrically led out through the first lead 41 and the second lead 42 respectively, so that test voltage can be applied to the lower electrode layer 31 and the upper electrode layer 33 of the capacitor structure 3 through the first lead 41 and the second lead 42, thereby completing the electrical performance test of the capacitor structure 3.

[0191] The first lead 41 and its cross-section can be circular, elliptical, rectangular, annular, or other shapes. No particular limitation is made to the shape of the first lead 41. Preferably, the cross-section of the first lead 41 can be annular, and the orthographic projection of the first lead 41 on the substrate 1 can cover the edge of the orthographic projection of the lower electrode layer 31 on the substrate 1. This allows for a uniform electric field distribution during subsequent electrical performance testing of the capacitor structure 3, ensuring the accuracy of the test structure.

[0192] The material of the first lead 41 can be a metallic material, such as tungsten or titanium nitride. Of course, it can also be other materials with good conductivity, which will not be listed here.

[0193] The second lead 42 and its cross-section can be circular, elliptical, rectangular, or other shapes. No special limitation is made on the shape of the second lead 42. The material of the second lead 42 can be a metallic material, such as tungsten or titanium nitride. Of course, it can also be other materials with good conductivity, which will not be listed here.

[0194] In some embodiments, the material of the second lead 42 may be the same as or different from the material of the first lead 41, without special limitation. For example, the second lead 42 and the first lead 41 may be made of the same material, which may both be tungsten.

[0195] It should be noted that when there are multiple capacitor structures 3, each capacitor structure 3 may have a corresponding first lead 41 and second lead 42.

[0196] Each capacitor structure 3 can be equipped with a first test pad 51 and a second test pad 52. Both the first test pad 51 and the second test pad 52 can be made of conductive material, such as... Figure 21 As shown, each first test pad 51 and each second test pad 52 can be located on both sides of the corresponding capacitor structure 3. The first test pad 51 and the second test pad 52 can be connected to the first lead 41 and the second lead 42 corresponding to the capacitor structure 3, respectively, so that the test voltage can be transmitted to the lower electrode layer 31 and the upper electrode layer 33 of the capacitor structure 3 through the first test pad 51 and the second test pad 52, respectively, so as to complete the electrical performance test of the capacitor structure 3.

[0197] In some embodiments of this disclosure, the first test pad 51 and the second test pad 52 may be formed on the surface of the isolation layer 2 and may be arranged at intervals on the surface of the isolation layer 2; the first test pad 51 and the second test pad 52 may also be formed on the surface of the insulating layer 400 and may be arranged at intervals on the surface of the insulating layer 400; the first test pad 51 and the second test pad 52 may also be formed on the surface of the mask layer 500 and may be arranged at intervals on the surface of the mask layer 500; of course, the first test pad 51 and the second test pad 52 may also be formed on the surface of other film layers on the side of the isolation layer 2 away from the substrate 1. The specific positions of the first test pad 51 and the second test pad 52 are not specifically limited here, as long as the first test pad 51 and the second test pad 52 can be connected to the first lead 41 and the second lead 42 respectively and can transmit the test voltage to the first lead 41 and the second lead 42.

[0198] The material of the first test pad 51 can be a metallic material, such as tungsten or titanium nitride. Of course, it can also be other materials with good conductivity, which will not be listed here. In some embodiments, the materials of the first test pad 51 and the second test pad 52 can be the same or different, and no special limitation is made here. For example, the materials of the first test pad 51 and the second test pad 52 can be the same. For example, both the first test pad 51 and the second test pad 52 can be made of tungsten, or both the first test pad 51 and the second test pad 52 can be made of titanium nitride, or one of the first test pad 51 and the second test pad 52 can be made of tungsten and the other of titanium nitride.

[0199] Each capacitor structure 3 and its corresponding first lead 41, second lead 42, first test pad 51 and second test pad 52 together constitute a test unit. The spacing between each test unit can be set according to the spacing of the pin cards in the test equipment, and no special limitation is made here.

[0200] During the test, two test probes in the test equipment can be placed on the first test pad 51 and the second test pad 52 respectively to complete the test of the capacitor structure 3. The semiconductor test structure disclosed herein has high test sensitivity and can detect weak ferroelectric or antiferroelectric effect signals present in the capacitor structure 3.

[0201] This disclosure also provides a test result analysis system, which can be used to analyze weak ferroelectric and antiferroelectric effect signals, the area of ​​the upper electrode layer 33 of the capacitor structure 3, and the storage capacity of each capacitor structure 3 in the semiconductor test structure of any of the above embodiments. The analysis system includes a data import component and a data generation component, wherein:

[0202] The data import component can be used to import test data of the semiconductor test structures in some of the above embodiments; the test data includes the area of ​​the upper electrode layer 33 of each capacitor structure 3 and the storage capacity corresponding to each capacitor structure 3.

[0203] The data generation component can be used to generate test analysis results based on the area of ​​the upper electrode layer 33 of each capacitor structure 3 and the corresponding storage capacity of each capacitor structure 3.

[0204] The test result analysis system disclosed herein can generate test analysis results based on the area of ​​the upper electrode layer 33 of each capacitor structure 3 and the storage capacity of each capacitor structure 3. It can clearly show the relationship between the area of ​​the capacitor structure 3 and the storage capacity of the capacitor structure. A monitoring board can be made based on the test analysis results. During the research and development process, the process stability of the capacitor dielectric layer 32 can be monitored through the monitoring board. So that when the storage capacity of the capacitor structure 3 obtained by testing changes during the process, the change in storage capacity of the capacitor structure 3 can be quickly checked based on the test analysis results to see if it is due to a change in the material of the capacitor dielectric layer 3 or a change in the key dimensions of the capacitor structure 3, which can accelerate the research and development progress.

[0205] In one exemplary embodiment of this disclosure, electrical performance tests can be performed on the semiconductor test structure to obtain test data. This test data may include the area of ​​the upper electrode layer 33 of each capacitor structure 3 and the corresponding storage capacity of each capacitor structure 3. The test data can be imported into a test result analysis system via a data import component for data analysis. In one embodiment, the data import component can be a data interface, which can be a hardware interface or a software calling program; no special limitation is made here. Of course, other forms of data import components are also possible, as long as they can import test data into the test analysis system. No special limitation is made here regarding the specific type of data import component.

[0206] The data generation component can import test data from within the data import component and generate test analysis results based on the test data. For example, the test data generation component can generate a graph showing the relationship between the area of ​​the upper electrode layer 33 and the corresponding storage capacity. During the R&D process, researchers can quickly eliminate abnormal data based on this graph. Alternatively, the area of ​​the upper electrode layer 33 and the corresponding storage capacity can be plotted in a table. In subsequent R&D, the table can be consulted to determine if there are any data anomalies.

[0207] For example, when the graph showing the relationship between the capacitor's storage capacity and the area of ​​the capacitor's upper electrode layer 33 is a straight line, the test data can be quickly determined to be normal by checking the graph during subsequent research and development. For instance, if the storage capacity and area of ​​the upper electrode layer 33 of a certain capacitor structure 3 are obtained through subsequent testing, these values ​​can be compared with the aforementioned graph. If the data matches the graph, the test data for the capacitor structure 3 is considered authentic and reliable; if the data deviates, the test data for the capacitor structure 3 is considered problematic and unreliable.

[0208] It should be noted that the data analysis system disclosed herein can also be used to analyze the relationship between the dielectric constant of the material of the capacitor dielectric layer 32 and the change in the capacitor's storage capacity. The analysis principle is similar to the analysis process of the relationship between the change in capacitor area and storage capacity, so it will not be described in detail here.

[0209] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the appended claims.

Claims

1. A method for forming a semiconductor test structure, characterized in that, include: Provide substrate; An isolation layer is formed on the substrate; A capacitor structure is formed on the surface of the isolation layer away from the substrate. The capacitor structure includes a lower electrode layer, a capacitor dielectric layer, and an upper electrode layer that are stacked sequentially along a direction perpendicular to the substrate. A first lead and a second lead are formed on the side of the capacitor structure away from the substrate. The first lead is in contact with the lower electrode layer, and the second lead is in contact with the upper electrode layer. The orthographic projections of the first lead and the second lead on the substrate do not overlap. A first test pad and a second test pad are formed at intervals on the side of the isolation layer away from the substrate. The first test pad is in contact with the first lead, and the second test pad is in contact with the second lead. The forming method further includes: A plurality of capacitor structures are formed on the surface of the isolation layer away from the substrate, each capacitor structure having a corresponding first lead and a second lead; in a direction parallel to the substrate, the areas of the upper electrode layers of at least some of the capacitor structures are not equal.

2. The forming method according to claim 1, characterized in that, In a direction parallel to the substrate, the areas of the upper electrode layers of each capacitor structure are not equal.

3. The forming method according to claim 2, characterized in that, The capacitor structures are arranged side by side, and in a direction parallel to the substrate, the area of ​​the upper electrode layer in each capacitor structure increases or decreases sequentially.

4. The forming method according to claim 1, characterized in that, The orthographic projection of the first lead onto the substrate covers the circumference of the orthographic projection of the lower electrode layer onto the substrate.

5. The forming method according to any one of claims 1-4, characterized in that, A capacitor structure is formed on the surface of the isolation layer away from the substrate. The capacitor structure includes a lower electrode layer, a capacitor dielectric layer, and an upper electrode layer stacked sequentially along a direction perpendicular to the substrate. A lower electrode material layer, a capacitor dielectric material layer, and an upper electrode material layer are sequentially formed on the side of the isolation layer away from the substrate. The capacitor dielectric material layer and the upper electrode material layer are etched to form the capacitor dielectric layer and the upper electrode layer; A photoresist layer is formed covering the upper electrode layer and the lower electrode material layer adjacent to the capacitor dielectric layer, wherein the orthographic projection of the photoresist layer on the substrate is within the orthographic projection of the lower electrode material layer on the substrate; Remove the lower electrode material layer that is not covered by the photoresist layer to form the lower electrode layer.

6. The forming method according to any one of claims 1-4, characterized in that, A first lead and a second lead are formed on the side of the capacitor structure away from the substrate. The first lead is in contact with the lower electrode layer, and the second lead is in contact with the upper electrode layer. The orthographic projections of the first lead and the second lead on the substrate do not overlap. An insulating layer is formed covering the capacitor structure; A mask layer is formed on the surface of the insulating layer; The insulating layer is patterned using the mask layer as a mask to form a first contact hole exposing the lower electrode layer and a second contact hole exposing the upper electrode layer in the insulating layer. The orthographic projection of the first contact hole on the substrate does not overlap with the orthographic projection of the upper electrode layer on the substrate, and the orthographic projection of the second contact hole on the substrate is within the orthographic projection of the upper electrode layer on the substrate. Conductive material is filled into the first contact hole and the second contact hole respectively to form a first lead in the first contact hole and a second lead in the second contact hole.

7. The forming method according to claim 5, characterized in that, Etching the capacitor dielectric material layer and the upper electrode material layer to form the capacitor dielectric layer and the upper electrode layer includes: A first photoresist layer is formed on the surface of the upper electrode material layer, and the orthographic projection of the first photoresist layer on the substrate is within the orthographic projection of the lower electrode material layer on the substrate; Using the lower electrode material layer as an etching stop layer and the first photoresist layer as a photoresist, photolithography is performed on the capacitor dielectric material layer and the upper electrode material layer to form the capacitor dielectric layer and the upper electrode layer.

8. The forming method according to claim 6, characterized in that, Patterning the insulating layer using the mask layer as a mask to form a first contact hole exposing the lower electrode layer and a second contact hole exposing the upper electrode layer in the insulating layer includes: A second photoresist layer is formed on the surface of the mask layer. The second photoresist layer includes a first developing area and a second developing area. The orthographic projection of the first developing area on the substrate does not overlap with the orthographic projection of the upper electrode layer on the substrate. The orthographic projection of the second developing area on the substrate is within the orthographic projection of the upper electrode layer on the substrate. The mask layer and the insulating layer are etched in the first developing area and the second developing area to form a first contact hole exposing the lower electrode layer and a second contact hole exposing the upper electrode layer.

9. A semiconductor testing structure, characterized in that, include: Substrate; An isolation layer is formed on the substrate; A capacitor structure is formed on the surface of the isolation layer away from the substrate, the capacitor structure comprising a lower electrode layer, a capacitor dielectric layer and an upper electrode layer stacked sequentially along a direction perpendicular to the substrate; A first lead and a second lead are formed on the side of the capacitor structure away from the substrate. The first lead is in contact with the lower electrode layer, and the second lead is in contact with the upper electrode layer. The orthographic projections of the first lead and the second lead on the substrate do not overlap. A first test pad and a second test pad are arranged at intervals on the side of the isolation layer away from the substrate. The first test pad is in contact with the first lead, and the second test pad is in contact with the second lead. The number of capacitor structures is multiple, and each capacitor structure is formed on the surface of the isolation layer away from the substrate. Each capacitor structure has a corresponding first lead and a second lead. In a direction parallel to the substrate, the areas of the upper electrode layers of at least some of the capacitor structures are not equal.

10. The test structure according to claim 9, characterized in that, In a direction parallel to the substrate, the areas of the upper electrode layers of each capacitor structure are not equal.

11. The test structure according to claim 10, characterized in that, The capacitor structures are arranged side by side, and in a direction parallel to the substrate, the area of ​​the upper electrode layer in each capacitor structure increases or decreases sequentially.

12. The test structure according to claim 9, characterized in that, The orthographic projection of the first lead onto the substrate covers the circumference of the orthographic projection of the lower electrode layer onto the substrate.

13. A test result analysis system, characterized in that, include: A data import component is used to import test data of the semiconductor test structure described in claim 9; The test data includes the area of ​​the upper electrode layer of each capacitor structure and the storage capacity corresponding to each capacitor structure. A data generation component is used to generate test analysis results based on the area of ​​the upper electrode layer of each capacitor structure and the corresponding storage capacity of each capacitor structure.

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