A method for measuring epitaxial drift in infrared measurements

Abstract

This invention relates to an infrared method for testing epitaxial drift. An overlay tester is used to measure the overlay offset A between a reference alignment mark (4) and an epitaxial alignment mark (3), where A = (a1 - a2) / 2, a1 is the distance between the left boundary of the epitaxial alignment mark (3) and the left boundary of the reference alignment mark (4), and a2 is the distance between the right boundary of the epitaxial alignment mark (3) and the right and left boundaries of the reference alignment mark (4). An infrared overlay detector is used to measure the overlay offset B between the reference alignment mark (4) and the back alignment mark (2), where B = (b1 - b2) / 2, b1 is the distance between the left boundary of the back alignment mark (2) and the left boundary of the reference alignment mark (4), and b2 is the distance between the right boundary of the back alignment mark (2) and the right and left boundaries of the reference alignment mark (4). The epitaxial drift is equal to |A - B|. The advantage of this invention is that it enables non-destructive testing of epitaxial drift, significantly improving testing efficiency.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing technology, specifically to a method for testing epitaxial drift in the field of epitaxial technology within semiconductor manufacturing. Background Technology

[0002] Epitaxial growth is the process of arranging atoms (or molecules) of a certain substance in a regular and directional manner on a substrate surface under specific conditions. The resulting epitaxial layer is a silicon single-crystal layer that corresponds to the crystal structure of the substrate. In the manufacturing process of bipolar integrated circuits, the growth of the epitaxial layer introduces the problem of "buried layer drift." This drift can cause the buried layer to collide with isolation trenches. If this happens, even if adjacent isolation islands are completed under normal isolation process conditions, the N+ buried layer is unlikely to be penetrated by the isolated P+ layer. Since buried layer drift can lead to product failure in actual processes, it is necessary to study the amount of drift and then correct for it in the planar layout design.

[0003] Common methods for testing epitaxial drift include the grinding and staining method and the patch method. This paper proposes a method to measure epitaxial drift by measuring the registration offset between the epitaxial layer and the buried layer.

[0004] The abrasion staining method involves cutting a piece of the sample with the buried layer from the original sample, keeping both sides parallel and perpendicular to the main reference plane, attaching it to a measuring block with a known angle, grinding it, and then etching the ground surface for 2–3 seconds. The pattern displacement of the buried layer region is then measured under an interference microscope. This measurement method is destructive, and the wafer being measured cannot be reused.

[0005] For example, the Chinese patent "Method for Testing the Drift of Epitaxial Pattern" (patent number CN101325168A) uses slicing and staining methods to measure the offset of the epitaxial pattern; "Method for Measuring the Drift of Embedded Pattern after Epitaxial Growth" (patent number CN102788556A) divides the embedded pattern into a protected area and an unprotected area, and obtains the epitaxial drift by measuring the displacement data of the protected area and the unprotected area. Summary of the Invention

[0006] The purpose of this invention is to provide a method for testing epitaxial drift. This method involves double-sided registration, measuring the registration offset on the epitaxial layer and the offset of the back reference pattern. The difference between the registration offset on the epitaxial layer and the registration offset of the back reference pattern is the epitaxial drift, thereby achieving non-destructive measurement of epitaxial drift.

[0007] The technical solution adopted in this invention is as follows: A method for measuring epitaxial drift in infrared imaging, characterized by the following steps: S1. Take a P-type silicon wafer; S2. A first silicon dioxide layer is grown on the surface of a P-type silicon using a thermal oxidation method. The thickness of the first silicon dioxide layer is 0.3 μm. S3. A pre-alignment mark is formed on the surface of the first silicon dioxide layer using photolithography and etching processes. The mark has a size of 20μm × 20μm and a depth of 0.3μm. S4. An oxidation process is used to grow a second silicon dioxide layer on the surface of the first silicon dioxide layer, thereby forming a front alignment mark on the P-type silicon wafer below the pre-alignment mark. The mark has a size of 20μm×20μm and a depth of 0.2μm. S5. A back alignment mark is formed on the back side of a P-type silicon wafer using double-sided photolithography and etching processes, so that the center coordinates of the front alignment mark and the back alignment mark are consistent. The back alignment mark has a size of 30μm×30μm and a marking depth of 2μm. S6. Use a wet etching process to remove the two silicon dioxide layers on the surface of the P-type silicon wafer, aligning the front side with mark 1; S7. An epitaxial single-crystal silicon layer with a thickness of 10 μm is grown on the front side of the wafer, and an epitaxial alignment mark is formed after epitaxy. The epitaxial alignment mark is formed above the alignment mark. Due to epitaxial drift, the epitaxial alignment mark does not overlap with the front alignment mark. S8. A reference alignment mark is formed on the epitaxial layer using photolithography. The mark has a size of 25μm×25μm and a depth of 1μm. The reference alignment mark and the epitaxial alignment mark are interleaved. S9. Epitaxial drift test: First, the overlay offset A between the reference alignment mark and the extension alignment mark is measured using an overlay tester. A = (a1-a2) / 2, where a1 is the distance between the left boundary of the extension alignment mark and the left boundary of the reference alignment mark, and a2 is the distance between the right boundary of the extension alignment mark and the right and left boundaries of the reference alignment mark. Then, the overlay offset B between the reference alignment mark and the back alignment mark is measured using a red overlay engraving detector. B = (b1-b2) / 2, where b1 is the distance between the left boundary of the back alignment mark and the left boundary of the reference alignment mark, and b2 is the distance between the right boundary of the back alignment mark and the right and left boundaries of the reference alignment mark. The epitaxial drift is equal to |AB|.

[0008] The advantage of this invention is that it enables non-destructive testing of epitaxial drift, significantly improving testing efficiency. Attached Figure Description

[0009] Figure 1 — Figure 7 This is a flowchart of the process preparation for an infrared method for measuring epitaxial drift according to the present invention. Implementation

[0010] The following figure, in conjunction with the accompanying drawings, illustrates the specific embodiments of the present invention, including the following steps: S1. As Figure 1 As shown, P is selected with a resistivity of (8~13) Ω·cm. <111> Silicon wafer 5; S 2. As Figure 1 As shown, a first silicon dioxide layer 6 with a thickness of 0.3 μm is grown on the surface of a P-type silicon wafer 5 using a thermal oxidation method; S 3. For example Figure 1 As shown, a pre-alignment mark 1a is formed on the first silicon dioxide surface using photolithography and etching processes. The mark size is 20μm × 20μm, and the mark depth is 0.3μm. The specific steps include: Spin-coat a layer of photoresist on the silicon dioxide surface → form a 20μm×20μm window using photomask A → use an etching process to clean the silicon dioxide inside the window → after removing the photoresist, a pre-alignment mark 1a is formed on the silicon dioxide surface; S 4. For example Figure 2 As shown, an oxidation process is used to grow a second silicon dioxide layer 7 on the wafer surface (i.e., the first silicon dioxide layer). Because the growth rates of the silicon on the P-type silicon wafer and the oxide layer on the silicon dioxide are different, the thickness of the P-type substrate silicon (i.e., the P-type silicon wafer) 5 consumed is also inconsistent, thus forming an oxide layer mark 1b with a size of 20μm×20μm and a depth of 0.2μm at the pre-alignment mark 1a position of the P-type substrate silicon 5. S 5. For example Figure 3 As shown, a back alignment mark 2 is formed on the back side of a P-type silicon wafer 5 using double-sided photolithography and etching processes. The mark is 30μm×30μm in size and 2μm in depth. The back alignment mark 2 is formed by transferring the alignment mark 1 to the back side of the wafer using double-sided photolithography. Without considering alignment deviation, the center coordinates of the two marks are consistent.

[0011] The specific steps for photolithography back-side alignment mark 2 include: Front spin coating with photoresist for protection → Back spin coating with photoresist → Forming a 30μm×30μm window on the back of wafer 5 using photomask B → Etching the silicon dioxide inside the window clean using an etching process → Etching the silicon inside the window using an etching process → Forming alignment mark 2 on the back of the wafer after removing the photoresist. S 6. For example Figure 4 As shown, a wet etching process was used to remove the silicon dioxide from the surface of wafer 5 before epitaxy. Figure 2 The oxide layer marker 1b formed due to inconsistent silicon thickness was also removed, leaving... Figure 4 Align the front side with mark 1, with dimensions of 20μm × 20μm and a depth of 0.2μm; S 7. For example Figure 5As shown, a single-crystal silicon epitaxial layer 8 is grown on the front side of wafer 5 to form an alignment mark 3 after epitaxy. The epitaxial thickness is 10μm. Mark 3 is formed above mark 1. Due to epitaxial drift, mark 3 and mark 1 do not completely overlap. S 8. For example Figure 6 As shown, alignment marks 4 are formed on the epitaxial layer 8 using photolithography. The marks have a size of 25μm × 25μm and a depth of 1μm. The specific steps include: Spin-coating photoresist on the front → Using photomask C, alignment mark 4 is formed on the photoresist. Alignment mark 4 and alignment mark 3 are interleaved. S9. Epitaxial Drift Test: First, use an overlay tester to measure the overlay offset A between alignment mark 4 and alignment mark 3 formed after epitaxy. A = (a1-a2) / 2, and the positions of a1 and a2 are shown in […]. Figure 6 Identify the location; a1: Distance between the left boundary of marker 3 and the left boundary of marker 4; a2: Distance between the right boundary of marker 3 and the right and left boundaries of marker 4; Then, the overlay offset B between alignment mark 4 and alignment mark 2 is measured using a red overlay engraving detector. B = (b1-b2) / 2, and the positions of b1 and b2 are shown in [reference]. Figure 7 Identify the location. b1: Distance between the left boundary of marker 2 and the left boundary of marker 4; b2: Distance between the right boundary of marker 2 and the right and left boundaries of marker 4; The epitaxial drift is equal to |AB|.

[0012] The methods described in this invention are not limited to the embodiments described in the specific implementation. Those skilled in the art can make many possible variations and modifications to the technical solutions of this invention using the methods and techniques described above, or modify them into equivalent embodiments with equivalent changes, without departing from the scope of the technical solution of this invention. Therefore, any simple modifications, equivalent substitutions, equivalent changes, and modifications made to the above embodiments based on the technical essence of this invention, without departing from the content of the technical solution of this invention, still fall within the protection scope of the technical solution of this invention.

Claims

1. A method for measuring epitaxial drift using infrared technology, characterized in that... Includes the following steps: S1. Take a P-type silicon wafer (5); S2. A first silicon dioxide layer (6) is grown on the surface of a P-type silicon by thermal oxidation, the thickness of the first silicon dioxide layer being 0.3 μm; S3. A pre-alignment mark (1a) is formed on the surface of the first silicon dioxide layer using photolithography and etching processes. The mark has a size of 20μm × 20μm and a depth of 0.3μm. S4. An oxidation process is used to grow a second silicon dioxide layer (7) on the surface of the first silicon dioxide layer, thereby forming a front alignment mark (1) on the P-type silicon wafer (5) below the pre-alignment mark (1a). The mark has a size of 20μm×20μm and a depth of 0.2μm. S5. A back alignment mark (2) is formed on the back side of a P-type silicon wafer using double-sided photolithography and etching processes, so that the center coordinates of the front alignment mark (1) and the back alignment mark (2) are consistent. The size of the back alignment mark is 30μm×30μm and the marking depth is 2μm. S6. Use a wet etching process to etch away the two layers of silicon dioxide on the surface of the P-type silicon wafer, leaving a front alignment mark (1). S7. An epitaxial single-crystal silicon layer (8) is grown on the front side of the wafer. The thickness of the epitaxial layer is 10 μm, and an epitaxial alignment mark (3) is formed after epitaxy. The epitaxial alignment mark (3) is formed above the front alignment mark (1). Due to epitaxial drift, the epitaxial alignment mark (3) and the front alignment mark (1) do not overlap. S8. A reference alignment mark (4) is formed on the epitaxial single crystal silicon layer (8) using photolithography. The mark has a size of 25μm×25μm and a depth of 1μm. The reference alignment mark (4) and the epitaxial alignment mark (3) are interleaved. S9. Epitaxial drift test: First, the overlay offset A between the reference alignment mark (4) and the extension alignment mark (3) is measured using an overlay tester. A = (a1-a2) / 2, where a1 is the distance between the left boundary of the extension alignment mark (3) and the left boundary of the reference alignment mark (4), and a2 is the distance between the right boundary of the extension alignment mark (3) and the right and left boundaries of the reference alignment mark (4). Then, the overlay offset B between the reference alignment mark (4) and the back alignment mark (2) is measured using a red overlay engraving detector. B = (b1-b2) / 2, where b1 is the distance between the left boundary of the back alignment mark (2) and the left boundary of the reference alignment mark (4), and b2 is the distance between the right boundary of the back alignment mark (2) and the right and left boundaries of the reference alignment mark (4). The epitaxial drift is equal to |AB|.

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