Capacitor device and method of forming the same

Abstract

A capacitor device and a method for forming the same, wherein the structure comprises: each layer of the first metal layer is located between the second metal layers of adjacent layers, the first metal layer comprises a plurality of first electrode layers and a plurality of second electrode layers, the plurality of first electrode layers and the plurality of second electrode layers are arranged parallel to the first direction and along the second direction respectively, each first electrode layer is located between adjacent second electrode layers, each of the second metal layers comprises a plurality of third electrode layers and a plurality of fourth electrode layers, the plurality of third electrode layers and the plurality of fourth electrode layers are arranged along the second direction and parallel to the first direction respectively, and each third electrode layer is located between adjacent fourth electrode layers, a plurality of first conductive plugs electrically connect the plurality of first electrode layers and the plurality of third electrode layers, and a plurality of second conductive plugs electrically connect the plurality of second electrode layers and the plurality of fourth electrode layers, which is conducive to improving the quality factor of the capacitor device and improving the performance of the capacitor device.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing, and in particular to a capacitor and a method for forming the same. Background Technology

[0002] In semiconductor integrated circuits, integrated capacitors fabricated on the same chip as transistor circuits are widely used. They mainly come in two forms: metal-insulator-metal (MIM) capacitors and metal-oxide-metal (MOM) capacitors. MIM capacitors use upper and lower metal layers as capacitor plates. Fabricating MIM capacitors generally requires additional photolithography layers, and the breakdown voltage of the capacitor dielectric layer and the capacitance size are inherently contradictory. Furthermore, planar capacitors typically require a large area, which is detrimental to device integration. MOM capacitors, on the other hand, use a combination of finger structures and stacked layers to fabricate larger capacitance values ​​in a relatively smaller area. In addition, MOM capacitors do not require additional photoresist layers and masks, making the fabrication process simpler and less expensive than that of MIM capacitors.

[0003] However, as device dimensions continue to shrink, MOM capacitors are limited by the spacing between metal lines, preventing them from achieving high capacitance density and resulting in poor stability. Therefore, existing MOM capacitor technology needs further improvement. Summary of the Invention

[0004] The technical problem solved by the present invention is to provide a capacitor device and a method for forming the same, so as to improve the performance of semiconductor structures.

[0005] To solve the above-mentioned technical problems, the present invention provides a capacitor device, comprising: a substrate, the substrate including a main region and a connection region located around and adjacent to the main region; a plurality of first metal layers and a plurality of second metal layers stacked on the main region and the connection region, each first metal layer being located between adjacent second metal layers, each first metal layer including a plurality of first electrode layers and a plurality of second electrode layers, the plurality of first electrode layers and the plurality of second electrode layers being arranged parallel to a first direction and along a second direction, the plurality of first electrode layers and the plurality of second electrode layers being arranged in an interdigitated manner, each first electrode layer being located between adjacent second electrode layers. Each of the second metal layers includes a plurality of third electrode layers and a plurality of fourth electrode layers, wherein the plurality of third electrode layers and the plurality of fourth electrode layers are respectively arranged in a second direction and along a first direction, the plurality of third electrode layers and the plurality of fourth electrode layers are arranged in an interdigitated manner, and each third electrode layer is located between adjacent fourth electrode layers; a plurality of first conductive plugs are provided on the first electrode layer located on the connection region, the plurality of first conductive plugs electrically connecting the plurality of first electrode layers and the plurality of third electrode layers; a plurality of second conductive plugs are provided on the second electrode layer located on the connection region, the plurality of second conductive plugs electrically connecting the plurality of second electrode layers and the plurality of fourth electrode layers.

[0006] Optionally, the first electrode layer and the third electrode layer of the adjacent layer have overlapping first projection areas on the connection area; the second electrode layer and the fourth electrode layer of the adjacent layer have overlapping second projection areas on the connection area.

[0007] Optionally, the configuration includes: the plurality of first conductive plugs located on the first projection area, and the plurality of third electrode layers located on the plurality of first conductive plugs; the plurality of second conductive plugs located on the second projection area, and the plurality of fourth electrode layers located on the plurality of second conductive plugs.

[0008] Optionally, it further includes: a first lead-out terminal, which is electrically connected to the plurality of first electrode layers and the plurality of third electrode layers; and a second lead-out terminal, which is electrically connected to the plurality of second electrode layers and the plurality of fourth electrode layers.

[0009] Optionally, the number of the plurality of first metal layers is greater than or equal to 2 layers; the number of the plurality of second metal layers is greater than or equal to 2 layers.

[0010] Optionally, along the second direction, the distance between adjacent first electrode layers and second electrode layers ranges from 10 nm to 1 μm; along the first direction, the distance between adjacent third electrode layers and fourth electrode layers ranges from 10 nm to 5 μm; along the second direction, the width of the first electrode layer ranges from 30 nm to 1 μm, and the width of the second electrode layer ranges from 30 nm to 1 μm; along the first direction, the width of the third electrode layer ranges from 30 nm to 1 μm, and the width of the fourth electrode layer ranges from 30 nm to 1 μm.

[0011] Accordingly, the present invention also provides a method for forming a capacitor, comprising: providing a substrate, the substrate including a main region and a connection region located around and adjacent to the main region; forming a plurality of first metal layers and a plurality of second metal layers stacked on the main region and the connection region, each first metal layer being located between adjacent second metal layers, each first metal layer including a plurality of first electrode layers and a plurality of second electrode layers, the plurality of first electrode layers and the plurality of second electrode layers being respectively parallel to a first direction and arranged along a second direction, the plurality of first electrode layers and the plurality of second electrode layers being arranged in an interdigitated manner, each first electrode layer being located between adjacent second electrode layers, each second metal layer including a plurality of third electrode layers and a plurality of fourth electrode layers, the plurality of third electrode layers and the plurality of fourth electrode layers being respectively arranged in a second direction and arranged along a first direction, the plurality of third electrode layers and the plurality of fourth electrode layers being arranged in an interdigitated manner, each third electrode layer being located between adjacent fourth electrode layers, the plurality of first electrode layers and the plurality of third electrode layers located on the connection region being electrically connected, and the plurality of second electrode layers and the plurality of fourth electrode layers located on the connection region being electrically connected.

[0012] Optionally, the first electrode layer and the third electrode layer of the adjacent layer have overlapping first projection areas on the connection area; the second electrode layer and the fourth electrode layer of the adjacent layer have overlapping second projection areas on the connection area.

[0013] Optionally, it further includes: forming a plurality of first conductive plugs, the plurality of first conductive plugs being located on the first projection area, and the plurality of third electrode layers being located on the plurality of first conductive plugs; forming a plurality of second conductive plugs, the plurality of second conductive plugs being located on the second projection area, and the plurality of fourth electrode layers being located on the plurality of second conductive plugs.

[0014] Optionally, a first lead and a second lead are also formed, wherein the first lead is electrically connected to the plurality of first electrode layers and the plurality of third electrode layers, and the second lead is electrically connected to the plurality of second electrode layers and the plurality of fourth electrode layers.

[0015] Optionally, the number of the plurality of first metal layers is greater than or equal to 2 layers; the number of the plurality of second metal layers is greater than or equal to 2 layers.

[0016] Optionally, along the second direction, the distance between adjacent first electrode layers and second electrode layers ranges from 10 nm to 1 μm; along the first direction, the distance between adjacent third electrode layers and fourth electrode layers ranges from 10 nm to 5 μm; along the second direction, the width of the first electrode layer ranges from 30 nm to 1 μm, and the width of the second electrode layer ranges from 30 nm to 1 μm; along the first direction, the width of the third electrode layer ranges from 30 nm to 1 μm, and the width of the fourth electrode layer ranges from 30 nm to 1 μm.

[0017] Compared with the prior art, the technical solution of the embodiments of the present invention has the following beneficial effects:

[0018] In the capacitor device provided by the present invention, the plurality of first electrode layers and the plurality of third electrode layers located on the connection area are electrically connected, and the plurality of second electrode layers and the plurality of third electrode layers located on the connection area are electrically connected. Since the connection area is located around the main body area, the first electrode layers and the third electrode layers of adjacent layers are electrically interconnected from both ends. In the equivalent circuit, this is equivalent to the first electrode layers and the third electrode layers being connected in parallel. In the high-frequency band of the capacitor, due to the correlation between resistance and capacitance, the smaller the resistance value, the lower the radio frequency signal loss, and the smaller the decrease in device capacitance value with frequency, which is beneficial to improving capacitance density. Similarly, in the equivalent circuit, the second electrode layer and the fourth electrode layer are connected in parallel, which is beneficial to improving capacitance density. In addition, the reduction of the equivalent resistance value of the capacitor is beneficial to improving the quality factor Q of the capacitor device, thereby improving the overall performance of the capacitor device.

[0019] In the method for forming a capacitor provided by the present invention, the plurality of first electrode layers and the plurality of third electrode layers located on the connection region are electrically connected, and the plurality of second electrode layers and the plurality of fourth electrode layers located on the connection region are electrically connected. Since the connection region is located around the main body region, the first electrode layers and third electrode layers of adjacent layers are electrically interconnected from both ends. In the equivalent circuit, this is equivalent to the first electrode layers and third electrode layers being connected in parallel, which reduces the equivalent resistance value of the capacitor electrode layers. In the high-frequency band of the capacitor, due to the correlation between resistance and capacitance, the smaller the resistance value, the lower the radio frequency signal loss, and the smaller the decrease in device capacitance value with frequency, which is beneficial to improving capacitance density. Similarly, in the equivalent circuit, the second electrode layers and fourth electrode layers are connected in parallel, which is beneficial to improving capacitance density. In addition, the reduction of the equivalent resistance value of the capacitor is beneficial to improving the quality factor Q of the capacitor, thus improving the overall performance of the capacitor. Attached Figure Description

[0020] Figures 1 to 3 This is a structural schematic diagram of a capacitor device;

[0021] Figures 4 to 7 This is a schematic diagram of the structure corresponding to each step in the capacitor device forming method of the present invention. Detailed Implementation

[0022] It should be noted that the terms "surface" and "on" in this specification are used to describe the relative spatial position and are not limited to whether there is direct contact.

[0023] As described in the background section, the performance of capacitors in the prior art needs improvement. A capacitor will now be described and analyzed in conjunction with this example.

[0024] Figures 1 to 3 This is a schematic diagram of the structure of a capacitor.

[0025] Please refer to Figures 1 to 3 , Figure 1 yes Figure 2 and Figure 3 A top-view structural diagram. Figure 2 yes Figure 1 A schematic diagram of the cross-sectional structure along the DD1 direction. Figure 3 yes Figure 1A cross-sectional view along the EE1 direction is shown in the diagram. The capacitor structure includes: a substrate 100; several first metal layers and several second metal layers stacked on the substrate 100, with each first metal layer located between adjacent second metal layers. Each first metal layer includes several first electrode layers 110 and several second electrode layers 111, which are arranged parallel to a first direction X and along a second direction Y. Each first electrode layer 110 is located between adjacent second electrode layers 111. Each second metal layer includes several third electrode layers 120 and several fourth electrode layers 121, which are arranged along the second direction Y and along the first direction X, with each third electrode layer 120 located between adjacent fourth electrode layers 121. Between; a plurality of first conductive plugs 130 located on the first side region I and the second side region II adjacent to the second metal layer, the plurality of first conductive plugs 130 electrically connecting the first electrode layer 110 and the third electrode layer 120; a plurality of second conductive plugs 140 located on the third side region III and the fourth side region IV adjacent to the second metal layer, the third side region III being opposite to the first side region I, the fourth side region IV being opposite to the second side region II, the plurality of second conductive plugs 140 electrically connecting the second electrode layer 111 and the fourth electrode layer 121; a first lead-out terminal P1 and a second lead-out terminal P2 located on both sides of the uppermost second metal layer and parallel to the second direction Y, the first lead-out terminal P1 being connected to the middle part of the first region I, and the second lead-out terminal P2 being connected to the middle part of the third region III.

[0026] In the aforementioned MOM capacitor structure, to increase capacitance density, the thickness of the insulating layer between metal layers can be reduced, or a high-k dielectric layer can be used as the insulating layer to achieve high-density capacitance. However, these two methods are incompatible with other devices, which hinders the promotion of production technology.

[0027] To address the aforementioned problems, this invention provides a capacitor and its forming method. A plurality of first electrode layers and a plurality of third electrode layers located on the connection region are electrically connected, as are a plurality of second electrode layers and a plurality of fourth electrode layers located on the connection region. Since the connection region is located around the main body region, adjacent first and third electrode layers are electrically interconnected from their ends. In the equivalent circuit, this is equivalent to the first and third electrode layers being connected in parallel, reducing the equivalent resistance of the capacitor electrode layers. In the high-frequency band of the capacitor, due to the correlation between resistance and capacitance, a smaller resistance value results in lower RF signal loss, and the capacitance value decreases less with frequency, which is beneficial for increasing capacitance density. Similarly, in the equivalent circuit, the parallel connection between the second and fourth electrode layers is beneficial for increasing capacitance density. Furthermore, the reduction in the equivalent resistance value of the capacitor helps improve the quality factor Q of the capacitor, thus improving the overall performance of the capacitor.

[0028] To make the above-mentioned objectives, features and beneficial effects of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0029] Figures 4 to 7 This is a schematic diagram of the structure corresponding to each step in the capacitor device forming method of the present invention.

[0030] Please refer to Figure 4 A substrate 200 is provided, the substrate 200 including a main region I and a connection region II located around and adjacent to the main region I.

[0031] The connection area II is used to subsequently locate the connection point of the electrical connection between the first electrode layer and the third electrode layer, as well as the connection point of the electrical connection between the second electrode layer and the fourth electrode layer.

[0032] In this embodiment, the substrate 200 includes a substrate (not shown in the figure), a device layer (not shown in the figure) on the substrate, and a dielectric layer (not shown in the figure) on the surface of the substrate and the device layer. The device layer includes an isolation structure (not shown in the figure) and a device structure (not shown in the figure) located within the isolation structure. The device structure includes transistors, diodes, triodes, capacitors, inductors, or conductive structures, etc.

[0033] Please refer to Figures 5 to 7 , Figure 5 This is a top-down structural diagram. Figure 6 for Figure 5 A schematic diagram of the cross-sectional structure along the MM1 direction. Figure 7 yes Figure 5A cross-sectional structural diagram along the NN1 direction shows that a plurality of first metal layers and a plurality of second metal layers are stacked on the main body region I and the connecting region II. Each first metal layer is located between adjacent second metal layers. Each first metal layer includes a plurality of first electrode layers 201 and a plurality of second electrode layers 202. The plurality of first electrode layers 201 and the plurality of second electrode layers 202 are arranged parallel to a first direction X and along a second direction Y, respectively. The plurality of first electrode layers 201 and the plurality of second electrode layers 202 are arranged in an interdigitated manner, with each first electrode layer 201 located between adjacent second electrode layers 202. Each of the second metal layers includes a plurality of third electrode layers 203 and a plurality of fourth electrode layers 204. The plurality of third electrode layers 203 and the plurality of fourth electrode layers 204 are respectively arranged in a second direction Y and along a first direction X. The plurality of third electrode layers 203 and the plurality of fourth electrode layers 204 are arranged in an interdigitated manner. Each third electrode layer 203 is located between adjacent fourth electrode layers 204. The plurality of first electrode layers 201 and the plurality of third electrode layers 203 located on the connection region II are electrically connected. The plurality of second electrode layers 202 and the plurality of fourth electrode layers 204 located on the connection region II are electrically connected.

[0034] At this point, the plurality of first electrode layers 201 and the plurality of third electrode layers 203 located on the connection area II are electrically connected, and the plurality of second electrode layers 202 and the plurality of fourth electrode layers 204 located on the connection area II are electrically connected. Since the connection area II is located around the main body area I, the first electrode layers 201 and third electrode layers 203 of adjacent layers are electrically interconnected from both ends. In the equivalent circuit, this is equivalent to the first electrode layers 201 and third electrode layers 203 being connected in parallel, which reduces the equivalent resistance value of the capacitor electrode layers. In the high-frequency band of the capacitor, due to the correlation between resistance and capacitance, the smaller the resistance value, the lower the RF signal loss, and the smaller the decrease in device capacitance value with frequency, which is beneficial to improving capacitance density. Similarly, in the equivalent circuit, the second electrode layers 202 and fourth electrode layers 204 are connected in parallel, which is beneficial to improving capacitance density. In addition, the reduction of the equivalent resistance value of the capacitor is beneficial to improving the quality factor Q of the capacitor device, thereby improving the overall performance of the capacitor device.

[0035] In this embodiment, the first electrode layer 201 and the adjacent third electrode layer 203 have overlapping first projection areas on the connection region II; the second electrode layer 202 and the adjacent fourth electrode layer 204 have overlapping second projection areas on the connection region II.

[0036] In this embodiment, a plurality of first conductive plugs 301 and a plurality of second conductive plugs 302 are also formed. The plurality of first conductive plugs 301 are located on the first projection area, the plurality of third electrode layers 203 are located on the plurality of first conductive plugs 301, the plurality of second conductive plugs 302 are located on the second projection area, and the plurality of fourth electrode layers 204 are located on the plurality of second conductive plugs 302.

[0037] In this embodiment, a first lead-out terminal 401 and a second lead-out terminal 402 are also formed. The first lead-out terminal 401 is electrically connected to the plurality of first electrode layers 201 and the plurality of third electrode layers 203, and the second lead-out terminal 402 is electrically connected to the plurality of second electrode layers 202 and the plurality of fourth electrode layers 204.

[0038] In this embodiment, the first lead-out terminal 401 and the second lead-out terminal 402 are located on the top of the first metal layer. In other embodiments, the first lead-out terminal 401 and the second lead-out terminal 402 can be located on any other metal layer.

[0039] The number of the plurality of first metal layers is greater than or equal to two; the number of the plurality of second metal layers is greater than or equal to two. In this embodiment, the number of the plurality of first metal layers is four; the number of the plurality of second metal layers is four.

[0040] In this embodiment, along the second direction Y, the distance between adjacent first electrode layers 201 and second electrode layers 202 ranges from 10 nm to 1 μm; along the first direction X, the distance between adjacent third electrode layers 203 and fourth electrode layers 204 ranges from 10 nm to 5 μm; along the second direction Y, the width of the first electrode layer 201 ranges from 30 nm to 1 μm, and the width of the second electrode layer 202 ranges from 30 nm to 1 μm; along the first direction X, the width of the third electrode layer 203 ranges from 30 nm to 1 μm, and the width of the fourth electrode layer 204 ranges from 30 nm to 1 μm.

[0041] Accordingly, embodiments of the present invention also provide a capacitor device formed by the above method; please refer to further details. Figures 5 to 7The system includes: a substrate 200, the substrate 200 including a main region I and a connection region II located around and adjacent to the main region I; a plurality of first metal layers and a plurality of second metal layers stacked on the main region I and the connection region II, each first metal layer being located between adjacent second metal layers, each first metal layer including a plurality of first electrode layers 201 and a plurality of second electrode layers 202, the plurality of first electrode layers 201 and the plurality of second electrode layers 202 being arranged parallel to a first direction X and along a second direction Y, the plurality of first electrode layers 201 and the plurality of second electrode layers 202 being arranged in an interdigitated manner, each first electrode layer 201 being located between adjacent second electrode layers 202, and each second metal layer including a plurality of third electrode layers 203 and A plurality of fourth electrode layers 204, wherein the plurality of third electrode layers 203 and the plurality of fourth electrode layers 204 are respectively arranged in a second direction Y and along a first direction X, the plurality of third electrode layers 203 and the plurality of fourth electrode layers 204 are arranged in an interdigitated manner, and each third electrode layer 203 is located between adjacent fourth electrode layers 204; a plurality of first conductive plugs 301 are provided on the first electrode layer 201 located on the connection region II, the plurality of first conductive plugs 301 electrically connecting the plurality of first electrode layers 201 and the plurality of third electrode layers 203; a plurality of second conductive plugs 302 are provided on the second electrode layer 202 located on the connection region II, the plurality of second conductive plugs 302 electrically connecting the plurality of second electrode layers 202 and the plurality of fourth electrode layers 204.

[0042] At this point, the plurality of first electrode layers 201 and the plurality of third electrode layers 203 located on the connection area II are electrically connected, and the plurality of second electrode layers 202 and the plurality of fourth electrode layers 204 located on the connection area II are electrically connected. Since the connection area II is located around the main body area I, the first electrode layers 201 and third electrode layers 203 of adjacent layers are electrically interconnected from both ends. In the equivalent circuit, this is equivalent to the first electrode layers 201 and third electrode layers 203 being connected in parallel, which reduces the equivalent resistance value of the capacitor electrode layers. In the high-frequency band of the capacitor, due to the correlation between resistance and capacitance, the smaller the resistance value, the lower the RF signal loss, and the smaller the decrease in device capacitance value with frequency, which is beneficial to improving capacitance density. Similarly, in the equivalent circuit, the second electrode layers 202 and fourth electrode layers 204 are connected in parallel, which is beneficial to improving capacitance density. In addition, the reduction of the equivalent resistance value of the capacitor is beneficial to improving the quality factor Q of the capacitor device, thereby improving the overall performance of the capacitor device.

[0043] In this embodiment, the first electrode layer 201 and the adjacent third electrode layer 203 have overlapping first projection areas on the connection region II; the second electrode layer 202 and the adjacent fourth electrode layer 204 have overlapping second projection areas on the connection region II.

[0044] In this embodiment, the capacitor structure includes: a plurality of first conductive plugs 301 located on the first projection area, and a plurality of third electrode layers 203 located on the plurality of first conductive plugs 301; a plurality of second conductive plugs 302 located on the second projection area II, and a plurality of fourth electrode layers 204 located on the plurality of second conductive plugs 302.

[0045] In this embodiment, it further includes: a first lead-out terminal 401, which is electrically connected to the plurality of first electrode layers 201 and the plurality of third electrode layers 203; and a second lead-out terminal 402, which is electrically connected to the plurality of second electrode layers 202 and the plurality of fourth electrode layers 204.

[0046] The number of the plurality of first metal layers is greater than or equal to two; the number of the plurality of second metal layers is greater than or equal to two. In this embodiment, the number of the plurality of first metal layers is four; the number of the plurality of second metal layers is four.

[0047] In this embodiment, along the second direction Y, the distance between adjacent first electrode layers 201 and second electrode layers 202 ranges from 10 nm to 1 μm; along the first direction X, the distance between adjacent third electrode layers 203 and fourth electrode layers 204 ranges from 10 nm to 5 μm; along the second direction Y, the width of the first electrode layer 201 ranges from 30 nm to 1 μm, and the width of the second electrode layer 202 ranges from 30 nm to 1 μm; along the first direction X, the width of the third electrode layer 203 ranges from 30 nm to 1 μm, and the width of the fourth electrode layer 204 ranges from 30 nm to 1 μm.

[0048] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A capacitor component, characterized in that, include: A substrate, the substrate including a main region and a connection region located around and adjacent to the main region; A plurality of first metal layers and a plurality of second metal layers are stacked on the main body area and the connection area. Each first metal layer is located between the second metal layers of adjacent layers. Each first metal layer includes a plurality of first electrode layers and a plurality of second electrode layers. The plurality of first electrode layers and the plurality of second electrode layers are respectively parallel to a first direction and arranged along a second direction. The plurality of first electrode layers and the plurality of second electrode layers are arranged in an interdigitated manner. Each first electrode layer is located between adjacent second electrode layers. Each second metal layer includes a plurality of third electrode layers and a plurality of fourth electrode layers. The plurality of third electrode layers and the plurality of fourth electrode layers are respectively arranged in a second direction and arranged along a first direction. The plurality of third electrode layers and the plurality of fourth electrode layers are arranged in an interdigitated manner. Each third electrode layer is located between adjacent fourth electrode layers. The first electrode layer located on the connection area has a plurality of first conductive plugs, which electrically connect the plurality of first electrode layers and the plurality of third electrode layers. The second electrode layer located on the connection area has a plurality of second conductive plugs, which electrically connect the plurality of second electrode layers and the plurality of fourth electrode layers.

2. The capacitor as described in claim 1, characterized in that, The first electrode layer and the third electrode layer of the adjacent layer have overlapping first projection areas on the connection area; the second electrode layer and the fourth electrode layer of the adjacent layer have overlapping second projection areas on the connection area.

3. The capacitor as described in claim 2, characterized in that, include: The plurality of first conductive plugs are located on the first projection area, and the plurality of third electrode layers are located on the plurality of first conductive plugs; The plurality of second conductive plugs are located on the second projection area, and the plurality of fourth electrode layers are located on the plurality of second conductive plugs.

4. The capacitor as claimed in claim 1, characterized in that, Also includes: The first lead-out terminal, the The first lead is electrically connected to the plurality of first electrode layers and the plurality of third electrode layers; the second lead is electrically connected to the plurality of second electrode layers and the plurality of fourth electrode layers.

5. The capacitor as claimed in claim 1, characterized in that, The number of the plurality of first metal layers is greater than or equal to 2; the number of the plurality of second metal layers is greater than or equal to 2.

6. The capacitor as claimed in claim 1, characterized in that, Along the second direction, the distance between adjacent first and second electrode layers ranges from 10 nm to 1 μm; along the first direction, the distance between adjacent third and fourth electrode layers ranges from 10 nm to 5 μm; along the second direction, the width of the first electrode layer ranges from 30 nm to 1 μm, and the width of the second electrode layer ranges from 30 nm to 1 μm; along the first direction, the width of the third electrode layer ranges from 30 nm to 1 μm, and the width of the fourth electrode layer ranges from 30 nm to 1 μm.

7. A method for forming a capacitor element, characterized in that, include: A substrate is provided, the substrate including a body region and a connection region located around and adjacent to the body region; A plurality of first metal layers and a plurality of second metal layers are stacked on the main body region and the connection region. Each first metal layer is located between adjacent second metal layers. Each first metal layer includes a plurality of first electrode layers and a plurality of second electrode layers. The plurality of first electrode layers and the plurality of second electrode layers are respectively parallel to a first direction and arranged along a second direction. The plurality of first electrode layers and the plurality of second electrode layers are arranged in an interdigitated manner. Each first electrode layer is located between adjacent second electrode layers. Each second metal layer includes a plurality of third electrode layers and a plurality of fourth electrode layers. The plurality of third electrode layers and the plurality of fourth electrode layers are respectively arranged in a second direction and along a first direction. The plurality of third electrode layers and the plurality of fourth electrode layers are arranged in an interdigitated manner. Each third electrode layer is located between adjacent fourth electrode layers. The plurality of first electrode layers and the plurality of third electrode layers located on the connection region are electrically connected. The plurality of second electrode layers and the plurality of fourth electrode layers located on the connection region are also electrically connected.

8. The method for forming a capacitor element as described in claim 7, characterized in that, The first electrode layer and the third electrode layer of the adjacent layer have overlapping first projection areas on the connection area; the second electrode layer and the fourth electrode layer of the adjacent layer have overlapping second projection areas on the connection area.

9. The method for forming a capacitor element as described in claim 8, characterized in that, Also includes: A plurality of first conductive plugs are formed, the plurality of first conductive plugs being located on the first projection area, and the plurality of third electrode layers being located on the plurality of first conductive plugs; A plurality of second conductive plugs are formed, the plurality of second conductive plugs being located on the second projection area, and the plurality of fourth electrode layers being located on the plurality of second conductive plugs.

10. The method for forming a capacitor element as claimed in claim 7, characterized in that, It also forms a first lead and a second lead, the first lead being electrically connected to the plurality of first electrode layers and the plurality of third electrode layers, and the second lead being electrically connected to the plurality of second electrode layers and the plurality of fourth electrode layers.

11. The method for forming a capacitor element as described in claim 7, characterized in that, The number of the plurality of first metal layers is greater than or equal to 2; the number of the plurality of second metal layers is greater than or equal to 2.

12. The method for forming a capacitor element as described in claim 7, characterized in that, Along the second direction, the distance between adjacent first and second electrode layers ranges from 10 nm to 1 μm; along the first direction, the distance between adjacent third and fourth electrode layers ranges from 10 nm to 5 μm; along the second direction, the width of the first electrode layer ranges from 30 nm to 1 μm, and the width of the second electrode layer ranges from 30 nm to 1 μm; along the first direction, the width of the third electrode layer ranges from 30 nm to 1 μm, and the width of the fourth electrode layer ranges from 30 nm to 1 μm.

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